2 * Copyright (c) 2014 The FreeBSD Foundation
5 * This software was developed by Semihalf under
6 * the sponsorship of the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/types.h>
37 #include <sys/systm.h>
39 #include <machine/armreg.h>
40 #include <machine/cpu.h>
41 #include <machine/debug_monitor.h>
42 #include <machine/kdb.h>
45 #include <ddb/db_sym.h>
48 DBG_TYPE_BREAKPOINT = 0,
49 DBG_TYPE_WATCHPOINT = 1,
52 static int dbg_watchpoint_num;
53 static int dbg_breakpoint_num;
54 static int dbg_ref_count_mde[MAXCPU];
55 static int dbg_ref_count_kde[MAXCPU];
57 /* Watchpoints/breakpoints control register bitfields */
58 #define DBG_WATCH_CTRL_LEN_1 (0x1 << 5)
59 #define DBG_WATCH_CTRL_LEN_2 (0x3 << 5)
60 #define DBG_WATCH_CTRL_LEN_4 (0xf << 5)
61 #define DBG_WATCH_CTRL_LEN_8 (0xff << 5)
62 #define DBG_WATCH_CTRL_LEN_MASK(x) ((x) & (0xff << 5))
63 #define DBG_WATCH_CTRL_EXEC (0x0 << 3)
64 #define DBG_WATCH_CTRL_LOAD (0x1 << 3)
65 #define DBG_WATCH_CTRL_STORE (0x2 << 3)
66 #define DBG_WATCH_CTRL_ACCESS_MASK(x) ((x) & (0x3 << 3))
68 /* Common for breakpoint and watchpoint */
69 #define DBG_WB_CTRL_EL1 (0x1 << 1)
70 #define DBG_WB_CTRL_EL0 (0x2 << 1)
71 #define DBG_WB_CTRL_ELX_MASK(x) ((x) & (0x3 << 1))
72 #define DBG_WB_CTRL_E (0x1 << 0)
74 #define DBG_REG_BASE_BVR 0
75 #define DBG_REG_BASE_BCR (DBG_REG_BASE_BVR + 16)
76 #define DBG_REG_BASE_WVR (DBG_REG_BASE_BCR + 16)
77 #define DBG_REG_BASE_WCR (DBG_REG_BASE_WVR + 16)
79 /* Watchpoint/breakpoint helpers */
80 #define DBG_WB_WVR "wvr"
81 #define DBG_WB_WCR "wcr"
82 #define DBG_WB_BVR "bvr"
83 #define DBG_WB_BCR "bcr"
85 #define DBG_WB_READ(reg, num, val) do { \
86 __asm __volatile("mrs %0, dbg" reg #num "_el1" : "=r" (val)); \
89 #define DBG_WB_WRITE(reg, num, val) do { \
90 __asm __volatile("msr dbg" reg #num "_el1, %0" :: "r" (val)); \
93 #define READ_WB_REG_CASE(reg, num, offset, val) \
94 case (num + offset): \
95 DBG_WB_READ(reg, num, val); \
98 #define WRITE_WB_REG_CASE(reg, num, offset, val) \
99 case (num + offset): \
100 DBG_WB_WRITE(reg, num, val); \
103 #define SWITCH_CASES_READ_WB_REG(reg, offset, val) \
104 READ_WB_REG_CASE(reg, 0, offset, val); \
105 READ_WB_REG_CASE(reg, 1, offset, val); \
106 READ_WB_REG_CASE(reg, 2, offset, val); \
107 READ_WB_REG_CASE(reg, 3, offset, val); \
108 READ_WB_REG_CASE(reg, 4, offset, val); \
109 READ_WB_REG_CASE(reg, 5, offset, val); \
110 READ_WB_REG_CASE(reg, 6, offset, val); \
111 READ_WB_REG_CASE(reg, 7, offset, val); \
112 READ_WB_REG_CASE(reg, 8, offset, val); \
113 READ_WB_REG_CASE(reg, 9, offset, val); \
114 READ_WB_REG_CASE(reg, 10, offset, val); \
115 READ_WB_REG_CASE(reg, 11, offset, val); \
116 READ_WB_REG_CASE(reg, 12, offset, val); \
117 READ_WB_REG_CASE(reg, 13, offset, val); \
118 READ_WB_REG_CASE(reg, 14, offset, val); \
119 READ_WB_REG_CASE(reg, 15, offset, val)
121 #define SWITCH_CASES_WRITE_WB_REG(reg, offset, val) \
122 WRITE_WB_REG_CASE(reg, 0, offset, val); \
123 WRITE_WB_REG_CASE(reg, 1, offset, val); \
124 WRITE_WB_REG_CASE(reg, 2, offset, val); \
125 WRITE_WB_REG_CASE(reg, 3, offset, val); \
126 WRITE_WB_REG_CASE(reg, 4, offset, val); \
127 WRITE_WB_REG_CASE(reg, 5, offset, val); \
128 WRITE_WB_REG_CASE(reg, 6, offset, val); \
129 WRITE_WB_REG_CASE(reg, 7, offset, val); \
130 WRITE_WB_REG_CASE(reg, 8, offset, val); \
131 WRITE_WB_REG_CASE(reg, 9, offset, val); \
132 WRITE_WB_REG_CASE(reg, 10, offset, val); \
133 WRITE_WB_REG_CASE(reg, 11, offset, val); \
134 WRITE_WB_REG_CASE(reg, 12, offset, val); \
135 WRITE_WB_REG_CASE(reg, 13, offset, val); \
136 WRITE_WB_REG_CASE(reg, 14, offset, val); \
137 WRITE_WB_REG_CASE(reg, 15, offset, val)
140 dbg_wb_read_reg(int reg, int n)
145 SWITCH_CASES_READ_WB_REG(DBG_WB_WVR, DBG_REG_BASE_WVR, val);
146 SWITCH_CASES_READ_WB_REG(DBG_WB_WCR, DBG_REG_BASE_WCR, val);
147 SWITCH_CASES_READ_WB_REG(DBG_WB_BVR, DBG_REG_BASE_BVR, val);
148 SWITCH_CASES_READ_WB_REG(DBG_WB_BCR, DBG_REG_BASE_BCR, val);
150 db_printf("trying to read from wrong debug register %d\n", n);
157 dbg_wb_write_reg(int reg, int n, uint64_t val)
160 SWITCH_CASES_WRITE_WB_REG(DBG_WB_WVR, DBG_REG_BASE_WVR, val);
161 SWITCH_CASES_WRITE_WB_REG(DBG_WB_WCR, DBG_REG_BASE_WCR, val);
162 SWITCH_CASES_WRITE_WB_REG(DBG_WB_BVR, DBG_REG_BASE_BVR, val);
163 SWITCH_CASES_WRITE_WB_REG(DBG_WB_BCR, DBG_REG_BASE_BCR, val);
165 db_printf("trying to write to wrong debug register %d\n", n);
171 kdb_cpu_set_singlestep(void)
174 kdb_frame->tf_spsr |= DBG_SPSR_SS;
175 WRITE_SPECIALREG(MDSCR_EL1, READ_SPECIALREG(MDSCR_EL1) |
176 DBG_MDSCR_SS | DBG_MDSCR_KDE);
179 * Disable breakpoints and watchpoints, e.g. stepping
180 * over watched instruction will trigger break exception instead of
181 * single-step exception and locks CPU on that instruction for ever.
183 if (dbg_ref_count_mde[PCPU_GET(cpuid)] > 0) {
184 WRITE_SPECIALREG(MDSCR_EL1,
185 READ_SPECIALREG(MDSCR_EL1) & ~DBG_MDSCR_MDE);
190 kdb_cpu_clear_singlestep(void)
193 WRITE_SPECIALREG(MDSCR_EL1, READ_SPECIALREG(MDSCR_EL1) &
194 ~(DBG_MDSCR_SS | DBG_MDSCR_KDE));
196 /* Restore breakpoints and watchpoints */
197 if (dbg_ref_count_mde[PCPU_GET(cpuid)] > 0) {
198 WRITE_SPECIALREG(MDSCR_EL1,
199 READ_SPECIALREG(MDSCR_EL1) | DBG_MDSCR_MDE);
202 if (dbg_ref_count_kde[PCPU_GET(cpuid)] > 0) {
203 WRITE_SPECIALREG(MDSCR_EL1,
204 READ_SPECIALREG(MDSCR_EL1) | DBG_MDSCR_KDE);
209 dbg_watchtype_str(uint32_t type)
212 case DBG_WATCH_CTRL_EXEC:
214 case DBG_WATCH_CTRL_STORE:
216 case DBG_WATCH_CTRL_LOAD:
218 case DBG_WATCH_CTRL_LOAD | DBG_WATCH_CTRL_STORE:
219 return ("read/write");
226 dbg_watchtype_len(uint32_t len)
229 case DBG_WATCH_CTRL_LEN_1:
231 case DBG_WATCH_CTRL_LEN_2:
233 case DBG_WATCH_CTRL_LEN_4:
235 case DBG_WATCH_CTRL_LEN_8:
243 dbg_show_watchpoint(void)
245 uint32_t wcr, len, type;
249 db_printf("\nhardware watchpoints:\n");
250 db_printf(" watch status type len address symbol\n");
251 db_printf(" ----- -------- ---------- --- ------------------ ------------------\n");
252 for (i = 0; i < dbg_watchpoint_num; i++) {
253 wcr = dbg_wb_read_reg(DBG_REG_BASE_WCR, i);
254 if ((wcr & DBG_WB_CTRL_E) != 0) {
255 type = DBG_WATCH_CTRL_ACCESS_MASK(wcr);
256 len = DBG_WATCH_CTRL_LEN_MASK(wcr);
257 addr = dbg_wb_read_reg(DBG_REG_BASE_WVR, i);
258 db_printf(" %-5d %-8s %10s %3d 0x%16lx ",
259 i, "enabled", dbg_watchtype_str(type),
260 dbg_watchtype_len(len), addr);
261 db_printsym((db_addr_t)addr, DB_STGY_ANY);
264 db_printf(" %-5d disabled\n", i);
271 dbg_find_free_slot(enum dbg_t type)
276 case DBG_TYPE_BREAKPOINT:
277 max = dbg_breakpoint_num;
278 reg = DBG_REG_BASE_BCR;
281 case DBG_TYPE_WATCHPOINT:
282 max = dbg_watchpoint_num;
283 reg = DBG_REG_BASE_WCR;
286 db_printf("Unsupported debug type\n");
290 for (i = 0; i < max; i++) {
291 if ((dbg_wb_read_reg(reg, i) & DBG_WB_CTRL_E) == 0)
299 dbg_find_slot(enum dbg_t type, db_expr_t addr)
301 u_int max, reg_addr, reg_ctrl, i;
304 case DBG_TYPE_BREAKPOINT:
305 max = dbg_breakpoint_num;
306 reg_addr = DBG_REG_BASE_BVR;
307 reg_ctrl = DBG_REG_BASE_BCR;
309 case DBG_TYPE_WATCHPOINT:
310 max = dbg_watchpoint_num;
311 reg_addr = DBG_REG_BASE_WVR;
312 reg_ctrl = DBG_REG_BASE_WCR;
315 db_printf("Unsupported debug type\n");
319 for (i = 0; i < max; i++) {
320 if ((dbg_wb_read_reg(reg_addr, i) == addr) &&
321 ((dbg_wb_read_reg(reg_ctrl, i) & DBG_WB_CTRL_E) != 0))
329 dbg_enable_monitor(enum dbg_el_t el)
331 uint64_t reg_mdcr = 0;
334 * There is no need to have debug monitor on permanently, thus we are
335 * refcounting and turn it on only if any of CPU is going to use that.
337 if (atomic_fetchadd_int(&dbg_ref_count_mde[PCPU_GET(cpuid)], 1) == 0)
338 reg_mdcr = DBG_MDSCR_MDE;
340 if ((el == DBG_FROM_EL1) &&
341 atomic_fetchadd_int(&dbg_ref_count_kde[PCPU_GET(cpuid)], 1) == 0)
342 reg_mdcr |= DBG_MDSCR_KDE;
345 WRITE_SPECIALREG(MDSCR_EL1, READ_SPECIALREG(MDSCR_EL1) | reg_mdcr);
349 dbg_disable_monitor(enum dbg_el_t el)
351 uint64_t reg_mdcr = 0;
353 if (atomic_fetchadd_int(&dbg_ref_count_mde[PCPU_GET(cpuid)], -1) == 1)
354 reg_mdcr = DBG_MDSCR_MDE;
356 if ((el == DBG_FROM_EL1) &&
357 atomic_fetchadd_int(&dbg_ref_count_kde[PCPU_GET(cpuid)], -1) == 1)
358 reg_mdcr |= DBG_MDSCR_KDE;
361 WRITE_SPECIALREG(MDSCR_EL1, READ_SPECIALREG(MDSCR_EL1) & ~reg_mdcr);
365 dbg_setup_watchpoint(db_expr_t addr, db_expr_t size, enum dbg_el_t el,
366 enum dbg_access_t access)
368 uint64_t wcr_size, wcr_priv, wcr_access;
371 i = dbg_find_free_slot(DBG_TYPE_WATCHPOINT);
373 db_printf("Can not find slot for watchpoint, max %d"
374 " watchpoints supported\n", dbg_watchpoint_num);
380 wcr_size = DBG_WATCH_CTRL_LEN_1;
383 wcr_size = DBG_WATCH_CTRL_LEN_2;
386 wcr_size = DBG_WATCH_CTRL_LEN_4;
389 wcr_size = DBG_WATCH_CTRL_LEN_8;
392 db_printf("Unsupported address size for watchpoint\n");
398 wcr_priv = DBG_WB_CTRL_EL0;
401 wcr_priv = DBG_WB_CTRL_EL1;
404 db_printf("Unsupported exception level for watchpoint\n");
409 case HW_BREAKPOINT_X:
410 wcr_access = DBG_WATCH_CTRL_EXEC;
412 case HW_BREAKPOINT_R:
413 wcr_access = DBG_WATCH_CTRL_LOAD;
415 case HW_BREAKPOINT_W:
416 wcr_access = DBG_WATCH_CTRL_STORE;
418 case HW_BREAKPOINT_RW:
419 wcr_access = DBG_WATCH_CTRL_LOAD | DBG_WATCH_CTRL_STORE;
422 db_printf("Unsupported exception level for watchpoint\n");
426 dbg_wb_write_reg(DBG_REG_BASE_WVR, i, addr);
427 dbg_wb_write_reg(DBG_REG_BASE_WCR, i, wcr_size | wcr_access | wcr_priv |
429 dbg_enable_monitor(el);
434 dbg_remove_watchpoint(db_expr_t addr, db_expr_t size, enum dbg_el_t el)
438 i = dbg_find_slot(DBG_TYPE_WATCHPOINT, addr);
440 db_printf("Can not find watchpoint for address 0%lx\n", addr);
444 dbg_wb_write_reg(DBG_REG_BASE_WCR, i, 0);
445 dbg_disable_monitor(el);
450 dbg_monitor_init(void)
455 WRITE_SPECIALREG(OSLAR_EL1, 0);
457 /* Find out many breakpoints and watchpoints we can use */
458 dbg_watchpoint_num = ((READ_SPECIALREG(ID_AA64DFR0_EL1) >> 20) & 0xf) + 1;
459 dbg_breakpoint_num = ((READ_SPECIALREG(ID_AA64DFR0_EL1) >> 12) & 0xf) + 1;
461 if (bootverbose && PCPU_GET(cpuid) == 0) {
462 db_printf("%d watchpoints and %d breakpoints supported\n",
463 dbg_watchpoint_num, dbg_breakpoint_num);
467 * We have limited number of {watch,break}points, each consists of
469 * - wcr/bcr regsiter configurates corresponding {watch,break}point
471 * - wvr/bvr register keeps address we are hunting for
473 * Reset all breakpoints and watchpoints.
475 for (i = 0; i < dbg_watchpoint_num; ++i) {
476 dbg_wb_write_reg(DBG_REG_BASE_WCR, i, 0);
477 dbg_wb_write_reg(DBG_REG_BASE_WVR, i, 0);
480 for (i = 0; i < dbg_breakpoint_num; ++i) {
481 dbg_wb_write_reg(DBG_REG_BASE_BCR, i, 0);
482 dbg_wb_write_reg(DBG_REG_BASE_BVR, i, 0);