2 * Copyright (c) 2014 Andrew Turner
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <machine/asm.h>
29 #include <machine/armreg.h>
30 __FBSDID("$FreeBSD$");
36 .macro save_registers el
41 sub sp, sp, #(TF_SIZE + 16)
42 stp x29, x30, [sp, #(TF_SIZE)]
43 stp x28, x29, [sp, #(TF_X + 28 * 8)]
44 stp x26, x27, [sp, #(TF_X + 26 * 8)]
45 stp x24, x25, [sp, #(TF_X + 24 * 8)]
46 stp x22, x23, [sp, #(TF_X + 22 * 8)]
47 stp x20, x21, [sp, #(TF_X + 20 * 8)]
48 stp x18, x19, [sp, #(TF_X + 18 * 8)]
49 stp x16, x17, [sp, #(TF_X + 16 * 8)]
50 stp x14, x15, [sp, #(TF_X + 14 * 8)]
51 stp x12, x13, [sp, #(TF_X + 12 * 8)]
52 stp x10, x11, [sp, #(TF_X + 10 * 8)]
53 stp x8, x9, [sp, #(TF_X + 8 * 8)]
54 stp x6, x7, [sp, #(TF_X + 6 * 8)]
55 stp x4, x5, [sp, #(TF_X + 4 * 8)]
56 stp x2, x3, [sp, #(TF_X + 2 * 8)]
57 stp x0, x1, [sp, #(TF_X + 0 * 8)]
64 str x10, [sp, #(TF_ELR)]
65 stp w11, w12, [sp, #(TF_SPSR)]
66 stp x18, lr, [sp, #(TF_SP)]
68 add x29, sp, #(TF_SIZE)
70 /* Apply the SSBD (CVE-2018-3639) workaround if needed */
71 ldr x1, [x18, #PC_SSBD]
79 .macro restore_registers el
83 * Disable interrupts, x18 may change in the interrupt exception
84 * handler. For EL0 exceptions, do_ast already did this.
88 /* Remove the SSBD (CVE-2018-3639) workaround if needed */
89 ldr x1, [x18, #PC_SSBD]
95 ldp x18, lr, [sp, #(TF_SP)]
96 ldp x10, x11, [sp, #(TF_ELR)]
102 ldp x0, x1, [sp, #(TF_X + 0 * 8)]
103 ldp x2, x3, [sp, #(TF_X + 2 * 8)]
104 ldp x4, x5, [sp, #(TF_X + 4 * 8)]
105 ldp x6, x7, [sp, #(TF_X + 6 * 8)]
106 ldp x8, x9, [sp, #(TF_X + 8 * 8)]
107 ldp x10, x11, [sp, #(TF_X + 10 * 8)]
108 ldp x12, x13, [sp, #(TF_X + 12 * 8)]
109 ldp x14, x15, [sp, #(TF_X + 14 * 8)]
110 ldp x16, x17, [sp, #(TF_X + 16 * 8)]
113 * We only restore the callee saved registers when returning to
114 * userland as they may have been updated by a system call or signal.
116 ldp x18, x19, [sp, #(TF_X + 18 * 8)]
117 ldp x20, x21, [sp, #(TF_X + 20 * 8)]
118 ldp x22, x23, [sp, #(TF_X + 22 * 8)]
119 ldp x24, x25, [sp, #(TF_X + 24 * 8)]
120 ldp x26, x27, [sp, #(TF_X + 26 * 8)]
121 ldp x28, x29, [sp, #(TF_X + 28 * 8)]
123 ldr x29, [sp, #(TF_X + 29 * 8)]
126 add sp, sp, #(TF_SIZE + 16)
135 /* Make sure the IRQs are enabled before calling ast() */
138 /* Disable interrupts */
141 /* Read the current thread flags */
142 ldr x1, [x18, #PC_CURTHREAD] /* Load curthread */
143 ldr x2, [x1, #TD_FLAGS]
145 /* Check if we have either bits set */
146 mov x3, #((TDF_ASTPENDING|TDF_NEEDRESCHED) >> 8)
151 /* Restore interrupts */
158 /* Re-check for new ast scheduled */
163 ENTRY(handle_el1h_sync)
165 ldr x0, [x18, #PC_CURTHREAD]
170 END(handle_el1h_sync)
172 ENTRY(handle_el1h_irq)
180 ENTRY(handle_el0_sync)
182 ldr x0, [x18, #PC_CURTHREAD]
184 str x1, [x0, #TD_FRAME]
191 ENTRY(handle_el0_irq)
207 ENTRY(handle_empty_exception)
210 1: bl unhandled_exception
212 END(handle_unhandled_exception)
216 b handle_empty_exception
225 .globl exception_vectors
227 vempty /* Synchronous EL1t */
228 vempty /* IRQ EL1t */
229 vempty /* FIQ EL1t */
230 vempty /* Error EL1t */
232 vector el1h_sync /* Synchronous EL1h */
233 vector el1h_irq /* IRQ EL1h */
234 vempty /* FIQ EL1h */
235 vector serror /* Error EL1h */
237 vector el0_sync /* Synchronous 64-bit EL0 */
238 vector el0_irq /* IRQ 64-bit EL0 */
239 vempty /* FIQ 64-bit EL0 */
240 vector serror /* Error 64-bit EL0 */
242 vector el0_sync /* Synchronous 32-bit EL0 */
243 vector el0_irq /* IRQ 32-bit EL0 */
244 vempty /* FIQ 32-bit EL0 */
245 vector serror /* Error 32-bit EL0 */