2 * Copyright (c) 2015-2016 The FreeBSD Foundation
5 * This software was developed by Andrew Turner under
6 * the sponsorship of the FreeBSD Foundation.
8 * This software was developed by Semihalf under
9 * the sponsorship of the FreeBSD Foundation.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include "opt_platform.h"
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/bitstring.h>
42 #include <sys/kernel.h>
44 #include <sys/malloc.h>
45 #include <sys/module.h>
49 #include <sys/cpuset.h>
51 #include <sys/mutex.h>
57 #include <machine/bus.h>
58 #include <machine/cpu.h>
59 #include <machine/intr.h>
62 #include <dev/ofw/ofw_bus_subr.h>
67 #include "gic_v3_reg.h"
68 #include "gic_v3_var.h"
70 static bus_read_ivar_t gic_v3_read_ivar;
72 static pic_disable_intr_t gic_v3_disable_intr;
73 static pic_enable_intr_t gic_v3_enable_intr;
74 static pic_map_intr_t gic_v3_map_intr;
75 static pic_setup_intr_t gic_v3_setup_intr;
76 static pic_teardown_intr_t gic_v3_teardown_intr;
77 static pic_post_filter_t gic_v3_post_filter;
78 static pic_post_ithread_t gic_v3_post_ithread;
79 static pic_pre_ithread_t gic_v3_pre_ithread;
80 static pic_bind_intr_t gic_v3_bind_intr;
82 static pic_init_secondary_t gic_v3_init_secondary;
83 static pic_ipi_send_t gic_v3_ipi_send;
84 static pic_ipi_setup_t gic_v3_ipi_setup;
87 static u_int gic_irq_cpu;
89 static u_int sgi_to_ipi[GIC_LAST_SGI - GIC_FIRST_SGI + 1];
90 static u_int sgi_first_unused = GIC_FIRST_SGI;
93 static device_method_t gic_v3_methods[] = {
94 /* Device interface */
95 DEVMETHOD(device_detach, gic_v3_detach),
98 DEVMETHOD(bus_read_ivar, gic_v3_read_ivar),
100 /* Interrupt controller interface */
101 DEVMETHOD(pic_disable_intr, gic_v3_disable_intr),
102 DEVMETHOD(pic_enable_intr, gic_v3_enable_intr),
103 DEVMETHOD(pic_map_intr, gic_v3_map_intr),
104 DEVMETHOD(pic_setup_intr, gic_v3_setup_intr),
105 DEVMETHOD(pic_teardown_intr, gic_v3_teardown_intr),
106 DEVMETHOD(pic_post_filter, gic_v3_post_filter),
107 DEVMETHOD(pic_post_ithread, gic_v3_post_ithread),
108 DEVMETHOD(pic_pre_ithread, gic_v3_pre_ithread),
110 DEVMETHOD(pic_bind_intr, gic_v3_bind_intr),
111 DEVMETHOD(pic_init_secondary, gic_v3_init_secondary),
112 DEVMETHOD(pic_ipi_send, gic_v3_ipi_send),
113 DEVMETHOD(pic_ipi_setup, gic_v3_ipi_setup),
120 DEFINE_CLASS_0(gic, gic_v3_driver, gic_v3_methods,
121 sizeof(struct gic_v3_softc));
124 * Driver-specific definitions.
126 MALLOC_DEFINE(M_GIC_V3, "GICv3", GIC_V3_DEVSTR);
129 * Helper functions and definitions.
131 /* Destination registers, either Distributor or Re-Distributor */
137 struct gic_v3_irqsrc {
138 struct intr_irqsrc gi_isrc;
140 enum intr_polarity gi_pol;
141 enum intr_trigger gi_trig;
144 /* Helper routines starting with gic_v3_ */
145 static int gic_v3_dist_init(struct gic_v3_softc *);
146 static int gic_v3_redist_alloc(struct gic_v3_softc *);
147 static int gic_v3_redist_find(struct gic_v3_softc *);
148 static int gic_v3_redist_init(struct gic_v3_softc *);
149 static int gic_v3_cpu_init(struct gic_v3_softc *);
150 static void gic_v3_wait_for_rwp(struct gic_v3_softc *, enum gic_v3_xdist);
152 /* A sequence of init functions for primary (boot) CPU */
153 typedef int (*gic_v3_initseq_t) (struct gic_v3_softc *);
154 /* Primary CPU initialization sequence */
155 static gic_v3_initseq_t gic_v3_primary_init[] = {
164 /* Secondary CPU initialization sequence */
165 static gic_v3_initseq_t gic_v3_secondary_init[] = {
173 gic_r_read_4(device_t dev, bus_size_t offset)
175 struct gic_v3_softc *sc;
177 sc = device_get_softc(dev);
178 return (bus_read_4(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset));
182 gic_r_read_8(device_t dev, bus_size_t offset)
184 struct gic_v3_softc *sc;
186 sc = device_get_softc(dev);
187 return (bus_read_8(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset));
191 gic_r_write_4(device_t dev, bus_size_t offset, uint32_t val)
193 struct gic_v3_softc *sc;
195 sc = device_get_softc(dev);
196 bus_write_4(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset, val);
200 gic_r_write_8(device_t dev, bus_size_t offset, uint64_t val)
202 struct gic_v3_softc *sc;
204 sc = device_get_softc(dev);
205 bus_write_8(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset, val);
212 gic_v3_attach(device_t dev)
214 struct gic_v3_softc *sc;
215 gic_v3_initseq_t *init_func;
223 sc = device_get_softc(dev);
224 sc->gic_registered = FALSE;
228 /* Initialize mutex */
229 mtx_init(&sc->gic_mtx, "GICv3 lock", NULL, MTX_SPIN);
232 * Allocate array of struct resource.
233 * One entry for Distributor and all remaining for Re-Distributor.
235 sc->gic_res = malloc(
236 sizeof(*sc->gic_res) * (sc->gic_redists.nregions + 1),
239 /* Now allocate corresponding resources */
240 for (i = 0, rid = 0; i < (sc->gic_redists.nregions + 1); i++, rid++) {
241 sc->gic_res[rid] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
243 if (sc->gic_res[rid] == NULL)
248 * Distributor interface
250 sc->gic_dist = sc->gic_res[0];
253 * Re-Dristributor interface
255 /* Allocate space under region descriptions */
256 sc->gic_redists.regions = malloc(
257 sizeof(*sc->gic_redists.regions) * sc->gic_redists.nregions,
260 /* Fill-up bus_space information for each region. */
261 for (i = 0, rid = 1; i < sc->gic_redists.nregions; i++, rid++)
262 sc->gic_redists.regions[i] = sc->gic_res[rid];
264 /* Get the number of supported SPI interrupts */
265 typer = gic_d_read(sc, 4, GICD_TYPER);
266 sc->gic_nirqs = GICD_TYPER_I_NUM(typer);
267 if (sc->gic_nirqs > GIC_I_NUM_MAX)
268 sc->gic_nirqs = GIC_I_NUM_MAX;
270 sc->gic_irqs = malloc(sizeof(*sc->gic_irqs) * sc->gic_nirqs,
271 M_GIC_V3, M_WAITOK | M_ZERO);
272 name = device_get_nameunit(dev);
273 for (irq = 0; irq < sc->gic_nirqs; irq++) {
274 struct intr_irqsrc *isrc;
276 sc->gic_irqs[irq].gi_irq = irq;
277 sc->gic_irqs[irq].gi_pol = INTR_POLARITY_CONFORM;
278 sc->gic_irqs[irq].gi_trig = INTR_TRIGGER_CONFORM;
280 isrc = &sc->gic_irqs[irq].gi_isrc;
281 if (irq <= GIC_LAST_SGI) {
282 err = intr_isrc_register(isrc, sc->dev,
283 INTR_ISRCF_IPI, "%s,i%u", name, irq - GIC_FIRST_SGI);
284 } else if (irq <= GIC_LAST_PPI) {
285 err = intr_isrc_register(isrc, sc->dev,
286 INTR_ISRCF_PPI, "%s,p%u", name, irq - GIC_FIRST_PPI);
288 err = intr_isrc_register(isrc, sc->dev, 0,
289 "%s,s%u", name, irq - GIC_FIRST_SPI);
292 /* XXX call intr_isrc_deregister() */
293 free(sc->gic_irqs, M_DEVBUF);
298 /* Get the number of supported interrupt identifier bits */
299 sc->gic_idbits = GICD_TYPER_IDBITS(typer);
302 device_printf(dev, "SPIs: %u, IDs: %u\n",
303 sc->gic_nirqs, (1 << sc->gic_idbits) - 1);
306 /* Train init sequence for boot CPU */
307 for (init_func = gic_v3_primary_init; *init_func != NULL; init_func++) {
308 err = (*init_func)(sc);
317 gic_v3_detach(device_t dev)
319 struct gic_v3_softc *sc;
323 sc = device_get_softc(dev);
325 if (device_is_attached(dev)) {
327 * XXX: We should probably deregister PIC
329 if (sc->gic_registered)
330 panic("Trying to detach registered PIC");
332 for (rid = 0; rid < (sc->gic_redists.nregions + 1); rid++)
333 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->gic_res[rid]);
335 for (i = 0; i < mp_ncpus; i++)
336 free(sc->gic_redists.pcpu[i], M_GIC_V3);
338 free(sc->gic_res, M_GIC_V3);
339 free(sc->gic_redists.regions, M_GIC_V3);
345 gic_v3_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
347 struct gic_v3_softc *sc;
349 sc = device_get_softc(dev);
352 case GICV3_IVAR_NIRQS:
353 *result = sc->gic_nirqs;
355 case GICV3_IVAR_REDIST_VADDR:
356 *result = (uintptr_t)rman_get_virtual(
357 sc->gic_redists.pcpu[PCPU_GET(cpuid)]);
365 arm_gic_v3_intr(void *arg)
367 struct gic_v3_softc *sc = arg;
368 struct gic_v3_irqsrc *gi;
369 struct intr_pic *pic;
371 struct trapframe *tf;
378 if (CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1) {
380 * Hardware: Cavium ThunderX
381 * Chip revision: Pass 1.0 (early version)
382 * Pass 1.1 (production)
383 * ERRATUM: 22978, 23154
386 "nop;nop;nop;nop;nop;nop;nop;nop; \n"
387 "mrs %0, ICC_IAR1_EL1 \n"
388 "nop;nop;nop;nop; \n"
390 : "=&r" (active_irq));
392 active_irq = gic_icc_read(IAR1);
395 if (active_irq >= GIC_FIRST_LPI) {
396 intr_child_irq_handler(pic, active_irq);
400 if (__predict_false(active_irq >= sc->gic_nirqs))
401 return (FILTER_HANDLED);
403 tf = curthread->td_intr_frame;
404 gi = &sc->gic_irqs[active_irq];
405 if (active_irq <= GIC_LAST_SGI) {
406 /* Call EOI for all IPI before dispatch. */
407 gic_icc_write(EOIR1, (uint64_t)active_irq);
409 intr_ipi_dispatch(sgi_to_ipi[gi->gi_irq], tf);
411 device_printf(sc->dev, "SGI %u on UP system detected\n",
412 active_irq - GIC_FIRST_SGI);
414 } else if (active_irq >= GIC_FIRST_PPI &&
415 active_irq <= GIC_LAST_SPI) {
416 if (gi->gi_pol == INTR_TRIGGER_EDGE)
417 gic_icc_write(EOIR1, gi->gi_irq);
419 if (intr_isrc_dispatch(&gi->gi_isrc, tf) != 0) {
420 if (gi->gi_pol != INTR_TRIGGER_EDGE)
421 gic_icc_write(EOIR1, gi->gi_irq);
422 gic_v3_disable_intr(sc->dev, &gi->gi_isrc);
423 device_printf(sc->dev,
424 "Stray irq %lu disabled\n", active_irq);
432 gic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp,
433 enum intr_polarity *polp, enum intr_trigger *trigp)
441 * The 1st cell is the interrupt type:
444 * The 2nd cell contains the interrupt number:
447 * The 3rd cell is the flags, encoded as follows:
448 * bits[3:0] trigger type and level flags
450 * 2 = edge triggered (PPI only)
451 * 4 = level-sensitive
452 * 8 = level-sensitive (PPI only)
456 irq = GIC_FIRST_SPI + cells[1];
457 /* SPI irq is checked later. */
460 irq = GIC_FIRST_PPI + cells[1];
461 if (irq > GIC_LAST_PPI) {
462 device_printf(dev, "unsupported PPI interrupt "
463 "number %u\n", cells[1]);
468 device_printf(dev, "unsupported interrupt type "
469 "configuration %u\n", cells[0]);
473 switch (cells[2] & 0xf) {
475 *trigp = INTR_TRIGGER_EDGE;
476 *polp = INTR_POLARITY_HIGH;
479 *trigp = INTR_TRIGGER_EDGE;
480 *polp = INTR_POLARITY_LOW;
483 *trigp = INTR_TRIGGER_LEVEL;
484 *polp = INTR_POLARITY_HIGH;
487 *trigp = INTR_TRIGGER_LEVEL;
488 *polp = INTR_POLARITY_LOW;
491 device_printf(dev, "unsupported trigger/polarity "
492 "configuration 0x%02x\n", cells[2]);
496 /* Check the interrupt is valid */
497 if (irq >= GIC_FIRST_SPI && *polp != INTR_POLARITY_HIGH)
506 do_gic_v3_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp,
507 enum intr_polarity *polp, enum intr_trigger *trigp)
509 struct gic_v3_softc *sc;
510 enum intr_polarity pol;
511 enum intr_trigger trig;
513 struct intr_map_data_fdt *daf;
517 sc = device_get_softc(dev);
519 switch (data->type) {
521 case INTR_MAP_DATA_FDT:
522 daf = (struct intr_map_data_fdt *)data;
523 if (gic_map_fdt(dev, daf->ncells, daf->cells, &irq, &pol,
532 if (irq >= sc->gic_nirqs)
535 case INTR_POLARITY_CONFORM:
536 case INTR_POLARITY_LOW:
537 case INTR_POLARITY_HIGH:
543 case INTR_TRIGGER_CONFORM:
544 case INTR_TRIGGER_EDGE:
545 case INTR_TRIGGER_LEVEL:
560 gic_v3_map_intr(device_t dev, struct intr_map_data *data,
561 struct intr_irqsrc **isrcp)
563 struct gic_v3_softc *sc;
567 error = do_gic_v3_map_intr(dev, data, &irq, NULL, NULL);
569 sc = device_get_softc(dev);
570 *isrcp = GIC_INTR_ISRC(sc, irq);
576 gic_v3_setup_intr(device_t dev, struct intr_irqsrc *isrc,
577 struct resource *res, struct intr_map_data *data)
579 struct gic_v3_softc *sc = device_get_softc(dev);
580 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
581 enum intr_trigger trig;
582 enum intr_polarity pol;
590 error = do_gic_v3_map_intr(dev, data, &irq, &pol, &trig);
594 if (gi->gi_irq != irq || pol == INTR_POLARITY_CONFORM ||
595 trig == INTR_TRIGGER_CONFORM)
598 /* Compare config if this is not first setup. */
599 if (isrc->isrc_handlers != 0) {
600 if (pol != gi->gi_pol || trig != gi->gi_trig)
610 * XXX - In case that per CPU interrupt is going to be enabled in time
611 * when SMP is already started, we need some IPI call which
612 * enables it on others CPUs. Further, it's more complicated as
613 * pic_enable_source() and pic_disable_source() should act on
614 * per CPU basis only. Thus, it should be solved here somehow.
616 if (isrc->isrc_flags & INTR_ISRCF_PPI)
617 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
619 if (irq >= GIC_FIRST_PPI && irq <= GIC_LAST_SPI) {
620 mtx_lock_spin(&sc->gic_mtx);
622 /* Set the trigger and polarity */
623 if (irq <= GIC_LAST_PPI)
624 reg = gic_r_read(sc, 4,
625 GICR_SGI_BASE_SIZE + GICD_ICFGR(irq));
627 reg = gic_d_read(sc, 4, GICD_ICFGR(irq));
628 if (trig == INTR_TRIGGER_LEVEL)
629 reg &= ~(2 << ((irq % 16) * 2));
631 reg |= 2 << ((irq % 16) * 2);
633 if (irq <= GIC_LAST_PPI) {
635 GICR_SGI_BASE_SIZE + GICD_ICFGR(irq), reg);
636 gic_v3_wait_for_rwp(sc, REDIST);
638 gic_d_write(sc, 4, GICD_ICFGR(irq), reg);
639 gic_v3_wait_for_rwp(sc, DIST);
642 mtx_unlock_spin(&sc->gic_mtx);
644 gic_v3_bind_intr(dev, isrc);
651 gic_v3_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
652 struct resource *res, struct intr_map_data *data)
654 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
656 if (isrc->isrc_handlers == 0) {
657 gi->gi_pol = INTR_POLARITY_CONFORM;
658 gi->gi_trig = INTR_TRIGGER_CONFORM;
665 gic_v3_disable_intr(device_t dev, struct intr_irqsrc *isrc)
667 struct gic_v3_softc *sc;
668 struct gic_v3_irqsrc *gi;
671 sc = device_get_softc(dev);
672 gi = (struct gic_v3_irqsrc *)isrc;
675 if (irq <= GIC_LAST_PPI) {
676 /* SGIs and PPIs in corresponding Re-Distributor */
677 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ICENABLER(irq),
679 gic_v3_wait_for_rwp(sc, REDIST);
680 } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) {
681 /* SPIs in distributor */
682 gic_d_write(sc, 4, GICD_ICENABLER(irq), GICD_I_MASK(irq));
683 gic_v3_wait_for_rwp(sc, DIST);
685 panic("%s: Unsupported IRQ %u", __func__, irq);
689 gic_v3_enable_intr(device_t dev, struct intr_irqsrc *isrc)
691 struct gic_v3_softc *sc;
692 struct gic_v3_irqsrc *gi;
695 sc = device_get_softc(dev);
696 gi = (struct gic_v3_irqsrc *)isrc;
699 if (irq <= GIC_LAST_PPI) {
700 /* SGIs and PPIs in corresponding Re-Distributor */
701 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ISENABLER(irq),
703 gic_v3_wait_for_rwp(sc, REDIST);
704 } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) {
705 /* SPIs in distributor */
706 gic_d_write(sc, 4, GICD_ISENABLER(irq), GICD_I_MASK(irq));
707 gic_v3_wait_for_rwp(sc, DIST);
709 panic("%s: Unsupported IRQ %u", __func__, irq);
713 gic_v3_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
715 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
717 gic_v3_disable_intr(dev, isrc);
718 gic_icc_write(EOIR1, gi->gi_irq);
722 gic_v3_post_ithread(device_t dev, struct intr_irqsrc *isrc)
725 gic_v3_enable_intr(dev, isrc);
729 gic_v3_post_filter(device_t dev, struct intr_irqsrc *isrc)
731 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
733 if (gi->gi_pol == INTR_TRIGGER_EDGE)
736 gic_icc_write(EOIR1, gi->gi_irq);
740 gic_v3_bind_intr(device_t dev, struct intr_irqsrc *isrc)
742 struct gic_v3_softc *sc;
743 struct gic_v3_irqsrc *gi;
746 gi = (struct gic_v3_irqsrc *)isrc;
747 if (gi->gi_irq <= GIC_LAST_PPI)
750 KASSERT(gi->gi_irq >= GIC_FIRST_SPI && gi->gi_irq <= GIC_LAST_SPI,
751 ("%s: Attempting to bind an invalid IRQ", __func__));
753 sc = device_get_softc(dev);
755 if (CPU_EMPTY(&isrc->isrc_cpu)) {
756 gic_irq_cpu = intr_irq_next_cpu(gic_irq_cpu, &all_cpus);
757 CPU_SETOF(gic_irq_cpu, &isrc->isrc_cpu);
758 gic_d_write(sc, 4, GICD_IROUTER(gi->gi_irq),
759 CPU_AFFINITY(gic_irq_cpu));
762 * We can only bind to a single CPU so select
763 * the first CPU found.
765 cpu = CPU_FFS(&isrc->isrc_cpu) - 1;
766 gic_d_write(sc, 4, GICD_IROUTER(gi->gi_irq), CPU_AFFINITY(cpu));
774 gic_v3_init_secondary(device_t dev)
777 struct gic_v3_softc *sc;
778 gic_v3_initseq_t *init_func;
779 struct intr_irqsrc *isrc;
783 sc = device_get_softc(dev);
784 cpu = PCPU_GET(cpuid);
786 /* Train init sequence for boot CPU */
787 for (init_func = gic_v3_secondary_init; *init_func != NULL;
789 err = (*init_func)(sc);
792 "Could not initialize GIC for CPU%u\n", cpu);
797 /* Unmask attached SGI interrupts. */
798 for (irq = GIC_FIRST_SGI; irq <= GIC_LAST_SGI; irq++) {
799 isrc = GIC_INTR_ISRC(sc, irq);
800 if (intr_isrc_init_on_cpu(isrc, cpu))
801 gic_v3_enable_intr(dev, isrc);
804 /* Unmask attached PPI interrupts. */
805 for (irq = GIC_FIRST_PPI; irq <= GIC_LAST_PPI; irq++) {
806 isrc = GIC_INTR_ISRC(sc, irq);
807 if (intr_isrc_init_on_cpu(isrc, cpu))
808 gic_v3_enable_intr(dev, isrc);
811 for (i = 0; i < sc->gic_nchildren; i++) {
812 child = sc->gic_children[i];
813 PIC_INIT_SECONDARY(child);
818 gic_v3_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus,
821 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
822 uint64_t aff, val, irq;
825 #define GIC_AFF_MASK (CPU_AFF3_MASK | CPU_AFF2_MASK | CPU_AFF1_MASK)
826 #define GIC_AFFINITY(i) (CPU_AFFINITY(i) & GIC_AFF_MASK)
827 aff = GIC_AFFINITY(0);
831 /* Iterate through all CPUs in set */
832 for (i = 0; i < mp_ncpus; i++) {
833 /* Move to the next affinity group */
834 if (aff != GIC_AFFINITY(i)) {
837 gic_icc_write(SGI1R, val);
840 aff = GIC_AFFINITY(i);
843 /* Send the IPI to this cpu */
844 if (CPU_ISSET(i, &cpus)) {
845 #define ICC_SGI1R_AFFINITY(aff) \
846 (((uint64_t)CPU_AFF3(aff) << ICC_SGI1R_EL1_AFF3_SHIFT) | \
847 ((uint64_t)CPU_AFF2(aff) << ICC_SGI1R_EL1_AFF2_SHIFT) | \
848 ((uint64_t)CPU_AFF1(aff) << ICC_SGI1R_EL1_AFF1_SHIFT))
849 /* Set the affinity when the first at this level */
851 val = ICC_SGI1R_AFFINITY(aff) |
852 irq << ICC_SGI1R_EL1_SGIID_SHIFT;
853 /* Set the bit to send the IPI to te CPU */
854 val |= 1 << CPU_AFF0(CPU_AFFINITY(i));
858 /* Send the IPI to the last cpu affinity group */
860 gic_icc_write(SGI1R, val);
866 gic_v3_ipi_setup(device_t dev, u_int ipi, struct intr_irqsrc **isrcp)
868 struct intr_irqsrc *isrc;
869 struct gic_v3_softc *sc = device_get_softc(dev);
871 if (sgi_first_unused > GIC_LAST_SGI)
874 isrc = GIC_INTR_ISRC(sc, sgi_first_unused);
875 sgi_to_ipi[sgi_first_unused++] = ipi;
877 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
888 gic_v3_wait_for_rwp(struct gic_v3_softc *sc, enum gic_v3_xdist xdist)
890 struct resource *res;
892 size_t us_left = 1000000;
894 cpuid = PCPU_GET(cpuid);
901 res = sc->gic_redists.pcpu[cpuid];
904 KASSERT(0, ("%s: Attempt to wait for unknown RWP", __func__));
908 while ((bus_read_4(res, GICD_CTLR) & GICD_CTLR_RWP) != 0) {
911 panic("GICD Register write pending for too long");
917 gic_v3_cpu_priority(uint64_t mask)
920 /* Set prority mask */
921 gic_icc_write(PMR, mask & ICC_PMR_EL1_PRIO_MASK);
925 gic_v3_cpu_enable_sre(struct gic_v3_softc *sc)
930 cpuid = PCPU_GET(cpuid);
932 * Set the SRE bit to enable access to GIC CPU interface
933 * via system registers.
935 sre = READ_SPECIALREG(icc_sre_el1);
936 sre |= ICC_SRE_EL1_SRE;
937 WRITE_SPECIALREG(icc_sre_el1, sre);
940 * Now ensure that the bit is set.
942 sre = READ_SPECIALREG(icc_sre_el1);
943 if ((sre & ICC_SRE_EL1_SRE) == 0) {
944 /* We are done. This was disabled in EL2 */
945 device_printf(sc->dev, "ERROR: CPU%u cannot enable CPU interface "
946 "via system registers\n", cpuid);
948 } else if (bootverbose) {
949 device_printf(sc->dev,
950 "CPU%u enabled CPU interface via system registers\n",
958 gic_v3_cpu_init(struct gic_v3_softc *sc)
962 /* Enable access to CPU interface via system registers */
963 err = gic_v3_cpu_enable_sre(sc);
966 /* Priority mask to minimum - accept all interrupts */
967 gic_v3_cpu_priority(GIC_PRIORITY_MIN);
968 /* Disable EOI mode */
969 gic_icc_clear(CTLR, ICC_CTLR_EL1_EOIMODE);
970 /* Enable group 1 (insecure) interrups */
971 gic_icc_set(IGRPEN1, ICC_IGRPEN0_EL1_EN);
978 gic_v3_dist_init(struct gic_v3_softc *sc)
984 * 1. Disable the Distributor
986 gic_d_write(sc, 4, GICD_CTLR, 0);
987 gic_v3_wait_for_rwp(sc, DIST);
990 * 2. Configure the Distributor
992 /* Set all global interrupts to be level triggered, active low. */
993 for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ICFGRn)
994 gic_d_write(sc, 4, GICD_ICFGR(i), 0x00000000);
996 /* Set priority to all shared interrupts */
997 for (i = GIC_FIRST_SPI;
998 i < sc->gic_nirqs; i += GICD_I_PER_IPRIORITYn) {
999 /* Set highest priority */
1000 gic_d_write(sc, 4, GICD_IPRIORITYR(i), GIC_PRIORITY_MAX);
1004 * Disable all interrupts. Leave PPI and SGIs as they are enabled in
1005 * Re-Distributor registers.
1007 for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ISENABLERn)
1008 gic_d_write(sc, 4, GICD_ICENABLER(i), 0xFFFFFFFF);
1010 gic_v3_wait_for_rwp(sc, DIST);
1013 * 3. Enable Distributor
1015 /* Enable Distributor with ARE, Group 1 */
1016 gic_d_write(sc, 4, GICD_CTLR, GICD_CTLR_ARE_NS | GICD_CTLR_G1A |
1020 * 4. Route all interrupts to boot CPU.
1022 aff = CPU_AFFINITY(0);
1023 for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i++)
1024 gic_d_write(sc, 4, GICD_IROUTER(i), aff);
1029 /* Re-Distributor */
1031 gic_v3_redist_alloc(struct gic_v3_softc *sc)
1035 /* Allocate struct resource for all CPU's Re-Distributor registers */
1036 for (cpuid = 0; cpuid < mp_ncpus; cpuid++)
1037 if (CPU_ISSET(cpuid, &all_cpus) != 0)
1038 sc->gic_redists.pcpu[cpuid] =
1039 malloc(sizeof(*sc->gic_redists.pcpu[0]),
1040 M_GIC_V3, M_WAITOK);
1042 sc->gic_redists.pcpu[cpuid] = NULL;
1047 gic_v3_redist_find(struct gic_v3_softc *sc)
1049 struct resource r_res;
1050 bus_space_handle_t r_bsh;
1057 cpuid = PCPU_GET(cpuid);
1059 aff = CPU_AFFINITY(cpuid);
1060 /* Affinity in format for comparison with typer */
1061 aff = (CPU_AFF3(aff) << 24) | (CPU_AFF2(aff) << 16) |
1062 (CPU_AFF1(aff) << 8) | CPU_AFF0(aff);
1065 device_printf(sc->dev,
1066 "Start searching for Re-Distributor\n");
1068 /* Iterate through Re-Distributor regions */
1069 for (i = 0; i < sc->gic_redists.nregions; i++) {
1070 /* Take a copy of the region's resource */
1071 r_res = *sc->gic_redists.regions[i];
1072 r_bsh = rman_get_bushandle(&r_res);
1074 pidr2 = bus_read_4(&r_res, GICR_PIDR2);
1075 switch (pidr2 & GICR_PIDR2_ARCH_MASK) {
1076 case GICR_PIDR2_ARCH_GICv3: /* fall through */
1077 case GICR_PIDR2_ARCH_GICv4:
1080 device_printf(sc->dev,
1081 "No Re-Distributor found for CPU%u\n", cpuid);
1086 typer = bus_read_8(&r_res, GICR_TYPER);
1087 if ((typer >> GICR_TYPER_AFF_SHIFT) == aff) {
1088 KASSERT(sc->gic_redists.pcpu[cpuid] != NULL,
1089 ("Invalid pointer to per-CPU redistributor"));
1090 /* Copy res contents to its final destination */
1091 *sc->gic_redists.pcpu[cpuid] = r_res;
1093 device_printf(sc->dev,
1094 "CPU%u Re-Distributor has been found\n",
1100 r_bsh += (GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);
1101 if ((typer & GICR_TYPER_VLPIS) != 0) {
1103 (GICR_VLPI_BASE_SIZE + GICR_RESERVED_SIZE);
1106 rman_set_bushandle(&r_res, r_bsh);
1107 } while ((typer & GICR_TYPER_LAST) == 0);
1110 device_printf(sc->dev, "No Re-Distributor found for CPU%u\n", cpuid);
1115 gic_v3_redist_wake(struct gic_v3_softc *sc)
1118 size_t us_left = 1000000;
1120 waker = gic_r_read(sc, 4, GICR_WAKER);
1121 /* Wake up Re-Distributor for this CPU */
1122 waker &= ~GICR_WAKER_PS;
1123 gic_r_write(sc, 4, GICR_WAKER, waker);
1125 * When clearing ProcessorSleep bit it is required to wait for
1126 * ChildrenAsleep to become zero following the processor power-on.
1128 while ((gic_r_read(sc, 4, GICR_WAKER) & GICR_WAKER_CA) != 0) {
1130 if (us_left-- == 0) {
1131 panic("Could not wake Re-Distributor for CPU%u",
1137 device_printf(sc->dev, "CPU%u Re-Distributor woke up\n",
1145 gic_v3_redist_init(struct gic_v3_softc *sc)
1150 err = gic_v3_redist_find(sc);
1154 err = gic_v3_redist_wake(sc);
1159 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ICENABLER0,
1160 GICR_I_ENABLER_PPI_MASK);
1162 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ISENABLER0,
1163 GICR_I_ENABLER_SGI_MASK);
1165 /* Set priority for SGIs and PPIs */
1166 for (i = 0; i <= GIC_LAST_PPI; i += GICR_I_PER_IPRIORITYn) {
1167 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_IPRIORITYR(i),
1171 gic_v3_wait_for_rwp(sc, REDIST);