sys/arm64/arm64/gic_v3.c

   1 /*-
   2  * Copyright (c) 2015-2016 The FreeBSD Foundation
   3  *
   4  * This software was developed by Andrew Turner under
   5  * the sponsorship of the FreeBSD Foundation.
   6  *
   7  * This software was developed by Semihalf under
   8  * the sponsorship of the FreeBSD Foundation.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  */
  31
  32 #include "opt_acpi.h"
  33 #include "opt_platform.h"
  34
  35 #include <sys/cdefs.h>
  36 __FBSDID("$FreeBSD$");
  37
  38 #include <sys/param.h>
  39 #include <sys/systm.h>
  40 #include <sys/bitstring.h>
  41 #include <sys/bus.h>
  42 #include <sys/kernel.h>
  43 #include <sys/ktr.h>
  44 #include <sys/malloc.h>
  45 #include <sys/module.h>
  46 #include <sys/rman.h>
  47 #include <sys/pcpu.h>
  48 #include <sys/proc.h>
  49 #include <sys/cpuset.h>
  50 #include <sys/lock.h>
  51 #include <sys/mutex.h>
  52 #include <sys/smp.h>
  53 #include <sys/interrupt.h>
  54
  55 #include <vm/vm.h>
  56 #include <vm/pmap.h>
  57
  58 #include <machine/bus.h>
  59 #include <machine/cpu.h>
  60 #include <machine/intr.h>
  61
  62 #ifdef FDT
  63 #include <dev/fdt/fdt_intr.h>
  64 #include <dev/ofw/ofw_bus_subr.h>
  65 #endif
  66
  67 #ifdef DEV_ACPI
  68 #include <contrib/dev/acpica/include/acpi.h>
  69 #include <dev/acpica/acpivar.h>
  70 #endif
  71
  72 #include "pic_if.h"
  73 #include "msi_if.h"
  74
  75 #include <arm/arm/gic_common.h>
  76 #include "gic_v3_reg.h"
  77 #include "gic_v3_var.h"
  78
  79 static bus_get_domain_t gic_v3_get_domain;
  80 static bus_read_ivar_t gic_v3_read_ivar;
  81
  82 static pic_disable_intr_t gic_v3_disable_intr;
  83 static pic_enable_intr_t gic_v3_enable_intr;
  84 static pic_map_intr_t gic_v3_map_intr;
  85 static pic_setup_intr_t gic_v3_setup_intr;
  86 static pic_teardown_intr_t gic_v3_teardown_intr;
  87 static pic_post_filter_t gic_v3_post_filter;
  88 static pic_post_ithread_t gic_v3_post_ithread;
  89 static pic_pre_ithread_t gic_v3_pre_ithread;
  90 static pic_bind_intr_t gic_v3_bind_intr;
  91 #ifdef SMP
  92 static pic_init_secondary_t gic_v3_init_secondary;
  93 static pic_ipi_send_t gic_v3_ipi_send;
  94 static pic_ipi_setup_t gic_v3_ipi_setup;
  95 #endif
  96
  97 static msi_alloc_msi_t gic_v3_alloc_msi;
  98 static msi_release_msi_t gic_v3_release_msi;
  99 static msi_alloc_msix_t gic_v3_alloc_msix;
 100 static msi_release_msix_t gic_v3_release_msix;
 101 static msi_map_msi_t gic_v3_map_msi;
 102
 103 static u_int gic_irq_cpu;
 104 #ifdef SMP
 105 static u_int sgi_to_ipi[GIC_LAST_SGI - GIC_FIRST_SGI + 1];
 106 static u_int sgi_first_unused = GIC_FIRST_SGI;
 107 #endif
 108
 109 static device_method_t gic_v3_methods[] = {
 110         /* Device interface */
 111         DEVMETHOD(device_detach,        gic_v3_detach),
 112
 113         /* Bus interface */
 114         DEVMETHOD(bus_get_domain,       gic_v3_get_domain),
 115         DEVMETHOD(bus_read_ivar,        gic_v3_read_ivar),
 116
 117         /* Interrupt controller interface */
 118         DEVMETHOD(pic_disable_intr,     gic_v3_disable_intr),
 119         DEVMETHOD(pic_enable_intr,      gic_v3_enable_intr),
 120         DEVMETHOD(pic_map_intr,         gic_v3_map_intr),
 121         DEVMETHOD(pic_setup_intr,       gic_v3_setup_intr),
 122         DEVMETHOD(pic_teardown_intr,    gic_v3_teardown_intr),
 123         DEVMETHOD(pic_post_filter,      gic_v3_post_filter),
 124         DEVMETHOD(pic_post_ithread,     gic_v3_post_ithread),
 125         DEVMETHOD(pic_pre_ithread,      gic_v3_pre_ithread),
 126 #ifdef SMP
 127         DEVMETHOD(pic_bind_intr,        gic_v3_bind_intr),
 128         DEVMETHOD(pic_init_secondary,   gic_v3_init_secondary),
 129         DEVMETHOD(pic_ipi_send,         gic_v3_ipi_send),
 130         DEVMETHOD(pic_ipi_setup,        gic_v3_ipi_setup),
 131 #endif
 132
 133         /* MSI/MSI-X */
 134         DEVMETHOD(msi_alloc_msi,        gic_v3_alloc_msi),
 135         DEVMETHOD(msi_release_msi,      gic_v3_release_msi),
 136         DEVMETHOD(msi_alloc_msix,       gic_v3_alloc_msix),
 137         DEVMETHOD(msi_release_msix,     gic_v3_release_msix),
 138         DEVMETHOD(msi_map_msi,          gic_v3_map_msi),
 139
 140         /* End */
 141         DEVMETHOD_END
 142 };
 143
 144 DEFINE_CLASS_0(gic, gic_v3_driver, gic_v3_methods,
 145     sizeof(struct gic_v3_softc));
 146
 147 /*
 148  * Driver-specific definitions.
 149  */
 150 MALLOC_DEFINE(M_GIC_V3, "GICv3", GIC_V3_DEVSTR);
 151
 152 /*
 153  * Helper functions and definitions.
 154  */
 155 /* Destination registers, either Distributor or Re-Distributor */
 156 enum gic_v3_xdist {
 157         DIST = 0,
 158         REDIST,
 159 };
 160
 161 struct gic_v3_irqsrc {
 162         struct intr_irqsrc      gi_isrc;
 163         uint32_t                gi_irq;
 164         enum intr_polarity      gi_pol;
 165         enum intr_trigger       gi_trig;
 166 #define GI_FLAG_MSI             (1 << 1) /* This interrupt source should only */
 167                                          /* be used for MSI/MSI-X interrupts */
 168 #define GI_FLAG_MSI_USED        (1 << 2) /* This irq is already allocated */
 169                                          /* for a MSI/MSI-X interrupt */
 170         u_int                   gi_flags;
 171 };
 172
 173 /* Helper routines starting with gic_v3_ */
 174 static int gic_v3_dist_init(struct gic_v3_softc *);
 175 static int gic_v3_redist_alloc(struct gic_v3_softc *);
 176 static int gic_v3_redist_find(struct gic_v3_softc *);
 177 static int gic_v3_redist_init(struct gic_v3_softc *);
 178 static int gic_v3_cpu_init(struct gic_v3_softc *);
 179 static void gic_v3_wait_for_rwp(struct gic_v3_softc *, enum gic_v3_xdist);
 180
 181 /* A sequence of init functions for primary (boot) CPU */
 182 typedef int (*gic_v3_initseq_t) (struct gic_v3_softc *);
 183 /* Primary CPU initialization sequence */
 184 static gic_v3_initseq_t gic_v3_primary_init[] = {
 185         gic_v3_dist_init,
 186         gic_v3_redist_alloc,
 187         gic_v3_redist_init,
 188         gic_v3_cpu_init,
 189         NULL
 190 };
 191
 192 #ifdef SMP
 193 /* Secondary CPU initialization sequence */
 194 static gic_v3_initseq_t gic_v3_secondary_init[] = {
 195         gic_v3_redist_init,
 196         gic_v3_cpu_init,
 197         NULL
 198 };
 199 #endif
 200
 201 uint32_t
 202 gic_r_read_4(device_t dev, bus_size_t offset)
 203 {
 204         struct gic_v3_softc *sc;
 205         struct resource *rdist;
 206
 207         sc = device_get_softc(dev);
 208         rdist = &sc->gic_redists.pcpu[PCPU_GET(cpuid)]->res;
 209         return (bus_read_4(rdist, offset));
 210 }
 211
 212 uint64_t
 213 gic_r_read_8(device_t dev, bus_size_t offset)
 214 {
 215         struct gic_v3_softc *sc;
 216         struct resource *rdist;
 217
 218         sc = device_get_softc(dev);
 219         rdist = &sc->gic_redists.pcpu[PCPU_GET(cpuid)]->res;
 220         return (bus_read_8(rdist, offset));
 221 }
 222
 223 void
 224 gic_r_write_4(device_t dev, bus_size_t offset, uint32_t val)
 225 {
 226         struct gic_v3_softc *sc;
 227         struct resource *rdist;
 228
 229         sc = device_get_softc(dev);
 230         rdist = &sc->gic_redists.pcpu[PCPU_GET(cpuid)]->res;
 231         bus_write_4(rdist, offset, val);
 232 }
 233
 234 void
 235 gic_r_write_8(device_t dev, bus_size_t offset, uint64_t val)
 236 {
 237         struct gic_v3_softc *sc;
 238         struct resource *rdist;
 239
 240         sc = device_get_softc(dev);
 241         rdist = &sc->gic_redists.pcpu[PCPU_GET(cpuid)]->res;
 242         bus_write_8(rdist, offset, val);
 243 }
 244
 245 /*
 246  * Device interface.
 247  */
 248 int
 249 gic_v3_attach(device_t dev)
 250 {
 251         struct gic_v3_softc *sc;
 252         gic_v3_initseq_t *init_func;
 253         uint32_t typer;
 254         int rid;
 255         int err;
 256         size_t i;
 257         u_int irq;
 258         const char *name;
 259
 260         sc = device_get_softc(dev);
 261         sc->gic_registered = FALSE;
 262         sc->dev = dev;
 263         err = 0;
 264
 265         /* Initialize mutex */
 266         mtx_init(&sc->gic_mtx, "GICv3 lock", NULL, MTX_SPIN);
 267
 268         /*
 269          * Allocate array of struct resource.
 270          * One entry for Distributor and all remaining for Re-Distributor.
 271          */
 272         sc->gic_res = malloc(
 273             sizeof(*sc->gic_res) * (sc->gic_redists.nregions + 1),
 274             M_GIC_V3, M_WAITOK);
 275
 276         /* Now allocate corresponding resources */
 277         for (i = 0, rid = 0; i < (sc->gic_redists.nregions + 1); i++, rid++) {
 278                 sc->gic_res[rid] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 279                     &rid, RF_ACTIVE);
 280                 if (sc->gic_res[rid] == NULL)
 281                         return (ENXIO);
 282         }
 283
 284         /*
 285          * Distributor interface
 286          */
 287         sc->gic_dist = sc->gic_res[0];
 288
 289         /*
 290          * Re-Dristributor interface
 291          */
 292         /* Allocate space under region descriptions */
 293         sc->gic_redists.regions = malloc(
 294             sizeof(*sc->gic_redists.regions) * sc->gic_redists.nregions,
 295             M_GIC_V3, M_WAITOK);
 296
 297         /* Fill-up bus_space information for each region. */
 298         for (i = 0, rid = 1; i < sc->gic_redists.nregions; i++, rid++)
 299                 sc->gic_redists.regions[i] = sc->gic_res[rid];
 300
 301         /* Get the number of supported SPI interrupts */
 302         typer = gic_d_read(sc, 4, GICD_TYPER);
 303         sc->gic_nirqs = GICD_TYPER_I_NUM(typer);
 304         if (sc->gic_nirqs > GIC_I_NUM_MAX)
 305                 sc->gic_nirqs = GIC_I_NUM_MAX;
 306
 307         sc->gic_irqs = malloc(sizeof(*sc->gic_irqs) * sc->gic_nirqs,
 308             M_GIC_V3, M_WAITOK | M_ZERO);
 309         name = device_get_nameunit(dev);
 310         for (irq = 0; irq < sc->gic_nirqs; irq++) {
 311                 struct intr_irqsrc *isrc;
 312
 313                 sc->gic_irqs[irq].gi_irq = irq;
 314                 sc->gic_irqs[irq].gi_pol = INTR_POLARITY_CONFORM;
 315                 sc->gic_irqs[irq].gi_trig = INTR_TRIGGER_CONFORM;
 316
 317                 isrc = &sc->gic_irqs[irq].gi_isrc;
 318                 if (irq <= GIC_LAST_SGI) {
 319                         err = intr_isrc_register(isrc, sc->dev,
 320                             INTR_ISRCF_IPI, "%s,i%u", name, irq - GIC_FIRST_SGI);
 321                 } else if (irq <= GIC_LAST_PPI) {
 322                         err = intr_isrc_register(isrc, sc->dev,
 323                             INTR_ISRCF_PPI, "%s,p%u", name, irq - GIC_FIRST_PPI);
 324                 } else {
 325                         err = intr_isrc_register(isrc, sc->dev, 0,
 326                             "%s,s%u", name, irq - GIC_FIRST_SPI);
 327                 }
 328                 if (err != 0) {
 329                         /* XXX call intr_isrc_deregister() */
 330                         free(sc->gic_irqs, M_DEVBUF);
 331                         return (err);
 332                 }
 333         }
 334
 335         if (sc->gic_mbi_start > 0) {
 336                 /* Reserve these interrupts for MSI/MSI-X use */
 337                 for (irq = sc->gic_mbi_start; irq <= sc->gic_mbi_end; irq++) {
 338                         sc->gic_irqs[irq].gi_pol = INTR_POLARITY_HIGH;
 339                         sc->gic_irqs[irq].gi_trig = INTR_TRIGGER_EDGE;
 340                         sc->gic_irqs[irq].gi_flags |= GI_FLAG_MSI;
 341                 }
 342
 343                 mtx_init(&sc->gic_mbi_mtx, "GICv3 mbi lock", NULL, MTX_DEF);
 344
 345                 if (bootverbose) {
 346                         device_printf(dev, "using spi %u to %u\n", sc->gic_mbi_start,
 347                                         sc->gic_mbi_end);
 348                 }
 349         }
 350
 351         /*
 352          * Read the Peripheral ID2 register. This is an implementation
 353          * defined register, but seems to be implemented in all GICv3
 354          * parts and Linux expects it to be there.
 355          */
 356         sc->gic_pidr2 = gic_d_read(sc, 4, GICD_PIDR2);
 357
 358         /* Get the number of supported interrupt identifier bits */
 359         sc->gic_idbits = GICD_TYPER_IDBITS(typer);
 360
 361         if (bootverbose) {
 362                 device_printf(dev, "SPIs: %u, IDs: %u\n",
 363                     sc->gic_nirqs, (1 << sc->gic_idbits) - 1);
 364         }
 365
 366         /* Train init sequence for boot CPU */
 367         for (init_func = gic_v3_primary_init; *init_func != NULL; init_func++) {
 368                 err = (*init_func)(sc);
 369                 if (err != 0)
 370                         return (err);
 371         }
 372
 373         return (0);
 374 }
 375
 376 int
 377 gic_v3_detach(device_t dev)
 378 {
 379         struct gic_v3_softc *sc;
 380         size_t i;
 381         int rid;
 382
 383         sc = device_get_softc(dev);
 384
 385         if (device_is_attached(dev)) {
 386                 /*
 387                  * XXX: We should probably deregister PIC
 388                  */
 389                 if (sc->gic_registered)
 390                         panic("Trying to detach registered PIC");
 391         }
 392         for (rid = 0; rid < (sc->gic_redists.nregions + 1); rid++)
 393                 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->gic_res[rid]);
 394
 395         for (i = 0; i <= mp_maxid; i++)
 396                 free(sc->gic_redists.pcpu[i], M_GIC_V3);
 397
 398         free(sc->gic_res, M_GIC_V3);
 399         free(sc->gic_redists.regions, M_GIC_V3);
 400
 401         return (0);
 402 }
 403
 404 static int
 405 gic_v3_get_domain(device_t dev, device_t child, int *domain)
 406 {
 407         struct gic_v3_devinfo *di;
 408
 409         di = device_get_ivars(child);
 410         if (di->gic_domain < 0)
 411                 return (ENOENT);
 412
 413         *domain = di->gic_domain;
 414         return (0);
 415 }
 416
 417 static int
 418 gic_v3_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
 419 {
 420         struct gic_v3_softc *sc;
 421
 422         sc = device_get_softc(dev);
 423
 424         switch (which) {
 425         case GICV3_IVAR_NIRQS:
 426                 *result = (intr_nirq - sc->gic_nirqs) / sc->gic_nchildren;
 427                 return (0);
 428         case GICV3_IVAR_REDIST:
 429                 *result = (uintptr_t)sc->gic_redists.pcpu[PCPU_GET(cpuid)];
 430                 return (0);
 431         case GIC_IVAR_HW_REV:
 432                 KASSERT(
 433                     GICR_PIDR2_ARCH(sc->gic_pidr2) == GICR_PIDR2_ARCH_GICv3 ||
 434                     GICR_PIDR2_ARCH(sc->gic_pidr2) == GICR_PIDR2_ARCH_GICv4,
 435                     ("gic_v3_read_ivar: Invalid GIC architecture: %d (%.08X)",
 436                      GICR_PIDR2_ARCH(sc->gic_pidr2), sc->gic_pidr2));
 437                 *result = GICR_PIDR2_ARCH(sc->gic_pidr2);
 438                 return (0);
 439         case GIC_IVAR_BUS:
 440                 KASSERT(sc->gic_bus != GIC_BUS_UNKNOWN,
 441                     ("gic_v3_read_ivar: Unknown bus type"));
 442                 KASSERT(sc->gic_bus <= GIC_BUS_MAX,
 443                     ("gic_v3_read_ivar: Invalid bus type %u", sc->gic_bus));
 444                 *result = sc->gic_bus;
 445                 return (0);
 446         }
 447
 448         return (ENOENT);
 449 }
 450
 451 int
 452 arm_gic_v3_intr(void *arg)
 453 {
 454         struct gic_v3_softc *sc = arg;
 455         struct gic_v3_irqsrc *gi;
 456         struct intr_pic *pic;
 457         uint64_t active_irq;
 458         struct trapframe *tf;
 459
 460         pic = sc->gic_pic;
 461
 462         while (1) {
 463                 if (CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1) {
 464                         /*
 465                          * Hardware:            Cavium ThunderX
 466                          * Chip revision:       Pass 1.0 (early version)
 467                          *                      Pass 1.1 (production)
 468                          * ERRATUM:             22978, 23154
 469                          */
 470                         __asm __volatile(
 471                             "nop;nop;nop;nop;nop;nop;nop;nop;   \n"
 472                             "mrs %0, ICC_IAR1_EL1               \n"
 473                             "nop;nop;nop;nop;                   \n"
 474                             "dsb sy                             \n"
 475                             : "=&r" (active_irq));
 476                 } else {
 477                         active_irq = gic_icc_read(IAR1);
 478                 }
 479
 480                 if (active_irq >= GIC_FIRST_LPI) {
 481                         intr_child_irq_handler(pic, active_irq);
 482                         continue;
 483                 }
 484
 485                 if (__predict_false(active_irq >= sc->gic_nirqs))
 486                         return (FILTER_HANDLED);
 487
 488                 tf = curthread->td_intr_frame;
 489                 gi = &sc->gic_irqs[active_irq];
 490                 if (active_irq <= GIC_LAST_SGI) {
 491                         /* Call EOI for all IPI before dispatch. */
 492                         gic_icc_write(EOIR1, (uint64_t)active_irq);
 493 #ifdef SMP
 494                         intr_ipi_dispatch(sgi_to_ipi[gi->gi_irq], tf);
 495 #else
 496                         device_printf(sc->dev, "SGI %ju on UP system detected\n",
 497                             (uintmax_t)(active_irq - GIC_FIRST_SGI));
 498 #endif
 499                 } else if (active_irq >= GIC_FIRST_PPI &&
 500                     active_irq <= GIC_LAST_SPI) {
 501                         if (gi->gi_trig == INTR_TRIGGER_EDGE)
 502                                 gic_icc_write(EOIR1, gi->gi_irq);
 503
 504                         if (intr_isrc_dispatch(&gi->gi_isrc, tf) != 0) {
 505                                 if (gi->gi_trig != INTR_TRIGGER_EDGE)
 506                                         gic_icc_write(EOIR1, gi->gi_irq);
 507                                 gic_v3_disable_intr(sc->dev, &gi->gi_isrc);
 508                                 device_printf(sc->dev,
 509                                     "Stray irq %lu disabled\n", active_irq);
 510                         }
 511                 }
 512         }
 513 }
 514
 515 #ifdef FDT
 516 static int
 517 gic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp,
 518     enum intr_polarity *polp, enum intr_trigger *trigp)
 519 {
 520         u_int irq;
 521
 522         if (ncells < 3)
 523                 return (EINVAL);
 524
 525         /*
 526          * The 1st cell is the interrupt type:
 527          *      0 = SPI
 528          *      1 = PPI
 529          * The 2nd cell contains the interrupt number:
 530          *      [0 - 987] for SPI
 531          *      [0 -  15] for PPI
 532          * The 3rd cell is the flags, encoded as follows:
 533          *   bits[3:0] trigger type and level flags
 534          *      1 = edge triggered
 535          *      2 = edge triggered (PPI only)
 536          *      4 = level-sensitive
 537          *      8 = level-sensitive (PPI only)
 538          */
 539         switch (cells[0]) {
 540         case 0:
 541                 irq = GIC_FIRST_SPI + cells[1];
 542                 /* SPI irq is checked later. */
 543                 break;
 544         case 1:
 545                 irq = GIC_FIRST_PPI + cells[1];
 546                 if (irq > GIC_LAST_PPI) {
 547                         device_printf(dev, "unsupported PPI interrupt "
 548                             "number %u\n", cells[1]);
 549                         return (EINVAL);
 550                 }
 551                 break;
 552         default:
 553                 device_printf(dev, "unsupported interrupt type "
 554                     "configuration %u\n", cells[0]);
 555                 return (EINVAL);
 556         }
 557
 558         switch (cells[2] & FDT_INTR_MASK) {
 559         case FDT_INTR_EDGE_RISING:
 560                 *trigp = INTR_TRIGGER_EDGE;
 561                 *polp = INTR_POLARITY_HIGH;
 562                 break;
 563         case FDT_INTR_EDGE_FALLING:
 564                 *trigp = INTR_TRIGGER_EDGE;
 565                 *polp = INTR_POLARITY_LOW;
 566                 break;
 567         case FDT_INTR_LEVEL_HIGH:
 568                 *trigp = INTR_TRIGGER_LEVEL;
 569                 *polp = INTR_POLARITY_HIGH;
 570                 break;
 571         case FDT_INTR_LEVEL_LOW:
 572                 *trigp = INTR_TRIGGER_LEVEL;
 573                 *polp = INTR_POLARITY_LOW;
 574                 break;
 575         default:
 576                 device_printf(dev, "unsupported trigger/polarity "
 577                     "configuration 0x%02x\n", cells[2]);
 578                 return (EINVAL);
 579         }
 580
 581         /* Check the interrupt is valid */
 582         if (irq >= GIC_FIRST_SPI && *polp != INTR_POLARITY_HIGH)
 583                 return (EINVAL);
 584
 585         *irqp = irq;
 586         return (0);
 587 }
 588 #endif
 589
 590 static int
 591 gic_map_msi(device_t dev, struct intr_map_data_msi *msi_data, u_int *irqp,
 592     enum intr_polarity *polp, enum intr_trigger *trigp)
 593 {
 594         struct gic_v3_irqsrc *gi;
 595
 596         /* SPI-mapped MSI */
 597         gi = (struct gic_v3_irqsrc *)msi_data->isrc;
 598         if (gi == NULL)
 599                 return (ENXIO);
 600
 601         *irqp = gi->gi_irq;
 602
 603         /* MSI/MSI-X interrupts are always edge triggered with high polarity */
 604         *polp = INTR_POLARITY_HIGH;
 605         *trigp = INTR_TRIGGER_EDGE;
 606
 607         return (0);
 608 }
 609
 610 static int
 611 do_gic_v3_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp,
 612     enum intr_polarity *polp, enum intr_trigger *trigp)
 613 {
 614         struct gic_v3_softc *sc;
 615         enum intr_polarity pol;
 616         enum intr_trigger trig;
 617         struct intr_map_data_msi *dam;
 618 #ifdef FDT
 619         struct intr_map_data_fdt *daf;
 620 #endif
 621 #ifdef DEV_ACPI
 622         struct intr_map_data_acpi *daa;
 623 #endif
 624         u_int irq;
 625
 626         sc = device_get_softc(dev);
 627
 628         switch (data->type) {
 629 #ifdef FDT
 630         case INTR_MAP_DATA_FDT:
 631                 daf = (struct intr_map_data_fdt *)data;
 632                 if (gic_map_fdt(dev, daf->ncells, daf->cells, &irq, &pol,
 633                     &trig) != 0)
 634                         return (EINVAL);
 635                 break;
 636 #endif
 637 #ifdef DEV_ACPI
 638         case INTR_MAP_DATA_ACPI:
 639                 daa = (struct intr_map_data_acpi *)data;
 640                 irq = daa->irq;
 641                 pol = daa->pol;
 642                 trig = daa->trig;
 643                 break;
 644 #endif
 645         case INTR_MAP_DATA_MSI:
 646                 /* SPI-mapped MSI */
 647                 dam = (struct intr_map_data_msi *)data;
 648                 if (gic_map_msi(dev, dam, &irq, &pol, &trig) != 0)
 649                         return (EINVAL);
 650                 break;
 651         default:
 652                 return (EINVAL);
 653         }
 654
 655         if (irq >= sc->gic_nirqs)
 656                 return (EINVAL);
 657         switch (pol) {
 658         case INTR_POLARITY_CONFORM:
 659         case INTR_POLARITY_LOW:
 660         case INTR_POLARITY_HIGH:
 661                 break;
 662         default:
 663                 return (EINVAL);
 664         }
 665         switch (trig) {
 666         case INTR_TRIGGER_CONFORM:
 667         case INTR_TRIGGER_EDGE:
 668         case INTR_TRIGGER_LEVEL:
 669                 break;
 670         default:
 671                 return (EINVAL);
 672         }
 673
 674         *irqp = irq;
 675         if (polp != NULL)
 676                 *polp = pol;
 677         if (trigp != NULL)
 678                 *trigp = trig;
 679         return (0);
 680 }
 681
 682 static int
 683 gic_v3_map_intr(device_t dev, struct intr_map_data *data,
 684     struct intr_irqsrc **isrcp)
 685 {
 686         struct gic_v3_softc *sc;
 687         int error;
 688         u_int irq;
 689
 690         error = do_gic_v3_map_intr(dev, data, &irq, NULL, NULL);
 691         if (error == 0) {
 692                 sc = device_get_softc(dev);
 693                 *isrcp = GIC_INTR_ISRC(sc, irq);
 694         }
 695         return (error);
 696 }
 697
 698 static int
 699 gic_v3_setup_intr(device_t dev, struct intr_irqsrc *isrc,
 700     struct resource *res, struct intr_map_data *data)
 701 {
 702         struct gic_v3_softc *sc = device_get_softc(dev);
 703         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 704         enum intr_trigger trig;
 705         enum intr_polarity pol;
 706         uint32_t reg;
 707         u_int irq;
 708         int error;
 709
 710         if (data == NULL)
 711                 return (ENOTSUP);
 712
 713         error = do_gic_v3_map_intr(dev, data, &irq, &pol, &trig);
 714         if (error != 0)
 715                 return (error);
 716
 717         if (gi->gi_irq != irq || pol == INTR_POLARITY_CONFORM ||
 718             trig == INTR_TRIGGER_CONFORM)
 719                 return (EINVAL);
 720
 721         /* Compare config if this is not first setup. */
 722         if (isrc->isrc_handlers != 0) {
 723                 if (pol != gi->gi_pol || trig != gi->gi_trig)
 724                         return (EINVAL);
 725                 else
 726                         return (0);
 727         }
 728
 729         /* For MSI/MSI-X we should have already configured these */
 730         if ((gi->gi_flags & GI_FLAG_MSI) == 0) {
 731                 gi->gi_pol = pol;
 732                 gi->gi_trig = trig;
 733         }
 734
 735         /*
 736          * XXX - In case that per CPU interrupt is going to be enabled in time
 737          *       when SMP is already started, we need some IPI call which
 738          *       enables it on others CPUs. Further, it's more complicated as
 739          *       pic_enable_source() and pic_disable_source() should act on
 740          *       per CPU basis only. Thus, it should be solved here somehow.
 741          */
 742         if (isrc->isrc_flags & INTR_ISRCF_PPI)
 743                 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
 744
 745         if (irq >= GIC_FIRST_PPI && irq <= GIC_LAST_SPI) {
 746                 mtx_lock_spin(&sc->gic_mtx);
 747
 748                 /* Set the trigger and polarity */
 749                 if (irq <= GIC_LAST_PPI)
 750                         reg = gic_r_read(sc, 4,
 751                             GICR_SGI_BASE_SIZE + GICD_ICFGR(irq));
 752                 else
 753                         reg = gic_d_read(sc, 4, GICD_ICFGR(irq));
 754                 if (trig == INTR_TRIGGER_LEVEL)
 755                         reg &= ~(2 << ((irq % 16) * 2));
 756                 else
 757                         reg |= 2 << ((irq % 16) * 2);
 758
 759                 if (irq <= GIC_LAST_PPI) {
 760                         gic_r_write(sc, 4,
 761                             GICR_SGI_BASE_SIZE + GICD_ICFGR(irq), reg);
 762                         gic_v3_wait_for_rwp(sc, REDIST);
 763                 } else {
 764                         gic_d_write(sc, 4, GICD_ICFGR(irq), reg);
 765                         gic_v3_wait_for_rwp(sc, DIST);
 766                 }
 767
 768                 mtx_unlock_spin(&sc->gic_mtx);
 769
 770                 gic_v3_bind_intr(dev, isrc);
 771         }
 772
 773         return (0);
 774 }
 775
 776 static int
 777 gic_v3_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
 778     struct resource *res, struct intr_map_data *data)
 779 {
 780         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 781
 782         if (isrc->isrc_handlers == 0 && (gi->gi_flags & GI_FLAG_MSI) == 0) {
 783                 gi->gi_pol = INTR_POLARITY_CONFORM;
 784                 gi->gi_trig = INTR_TRIGGER_CONFORM;
 785         }
 786
 787         return (0);
 788 }
 789
 790 static void
 791 gic_v3_disable_intr(device_t dev, struct intr_irqsrc *isrc)
 792 {
 793         struct gic_v3_softc *sc;
 794         struct gic_v3_irqsrc *gi;
 795         u_int irq;
 796
 797         sc = device_get_softc(dev);
 798         gi = (struct gic_v3_irqsrc *)isrc;
 799         irq = gi->gi_irq;
 800
 801         if (irq <= GIC_LAST_PPI) {
 802                 /* SGIs and PPIs in corresponding Re-Distributor */
 803                 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ICENABLER(irq),
 804                     GICD_I_MASK(irq));
 805                 gic_v3_wait_for_rwp(sc, REDIST);
 806         } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) {
 807                 /* SPIs in distributor */
 808                 gic_d_write(sc, 4, GICD_ICENABLER(irq), GICD_I_MASK(irq));
 809                 gic_v3_wait_for_rwp(sc, DIST);
 810         } else
 811                 panic("%s: Unsupported IRQ %u", __func__, irq);
 812 }
 813
 814 static void
 815 gic_v3_enable_intr(device_t dev, struct intr_irqsrc *isrc)
 816 {
 817         struct gic_v3_softc *sc;
 818         struct gic_v3_irqsrc *gi;
 819         u_int irq;
 820
 821         sc = device_get_softc(dev);
 822         gi = (struct gic_v3_irqsrc *)isrc;
 823         irq = gi->gi_irq;
 824
 825         if (irq <= GIC_LAST_PPI) {
 826                 /* SGIs and PPIs in corresponding Re-Distributor */
 827                 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ISENABLER(irq),
 828                     GICD_I_MASK(irq));
 829                 gic_v3_wait_for_rwp(sc, REDIST);
 830         } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) {
 831                 /* SPIs in distributor */
 832                 gic_d_write(sc, 4, GICD_ISENABLER(irq), GICD_I_MASK(irq));
 833                 gic_v3_wait_for_rwp(sc, DIST);
 834         } else
 835                 panic("%s: Unsupported IRQ %u", __func__, irq);
 836 }
 837
 838 static void
 839 gic_v3_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
 840 {
 841         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 842
 843         gic_v3_disable_intr(dev, isrc);
 844         gic_icc_write(EOIR1, gi->gi_irq);
 845 }
 846
 847 static void
 848 gic_v3_post_ithread(device_t dev, struct intr_irqsrc *isrc)
 849 {
 850
 851         gic_v3_enable_intr(dev, isrc);
 852 }
 853
 854 static void
 855 gic_v3_post_filter(device_t dev, struct intr_irqsrc *isrc)
 856 {
 857         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 858
 859         if (gi->gi_trig == INTR_TRIGGER_EDGE)
 860                 return;
 861
 862         gic_icc_write(EOIR1, gi->gi_irq);
 863 }
 864
 865 static int
 866 gic_v3_bind_intr(device_t dev, struct intr_irqsrc *isrc)
 867 {
 868         struct gic_v3_softc *sc;
 869         struct gic_v3_irqsrc *gi;
 870         int cpu;
 871
 872         gi = (struct gic_v3_irqsrc *)isrc;
 873         if (gi->gi_irq <= GIC_LAST_PPI)
 874                 return (EINVAL);
 875
 876         KASSERT(gi->gi_irq >= GIC_FIRST_SPI && gi->gi_irq <= GIC_LAST_SPI,
 877             ("%s: Attempting to bind an invalid IRQ", __func__));
 878
 879         sc = device_get_softc(dev);
 880
 881         if (CPU_EMPTY(&isrc->isrc_cpu)) {
 882                 gic_irq_cpu = intr_irq_next_cpu(gic_irq_cpu, &all_cpus);
 883                 CPU_SETOF(gic_irq_cpu, &isrc->isrc_cpu);
 884                 gic_d_write(sc, 8, GICD_IROUTER(gi->gi_irq),
 885                     CPU_AFFINITY(gic_irq_cpu));
 886         } else {
 887                 /*
 888                  * We can only bind to a single CPU so select
 889                  * the first CPU found.
 890                  */
 891                 cpu = CPU_FFS(&isrc->isrc_cpu) - 1;
 892                 gic_d_write(sc, 8, GICD_IROUTER(gi->gi_irq), CPU_AFFINITY(cpu));
 893         }
 894
 895         return (0);
 896 }
 897
 898 #ifdef SMP
 899 static void
 900 gic_v3_init_secondary(device_t dev)
 901 {
 902         device_t child;
 903         struct gic_v3_softc *sc;
 904         gic_v3_initseq_t *init_func;
 905         struct intr_irqsrc *isrc;
 906         u_int cpu, irq;
 907         int err, i;
 908
 909         sc = device_get_softc(dev);
 910         cpu = PCPU_GET(cpuid);
 911
 912         /* Train init sequence for boot CPU */
 913         for (init_func = gic_v3_secondary_init; *init_func != NULL;
 914             init_func++) {
 915                 err = (*init_func)(sc);
 916                 if (err != 0) {
 917                         device_printf(dev,
 918                             "Could not initialize GIC for CPU%u\n", cpu);
 919                         return;
 920                 }
 921         }
 922
 923         /* Unmask attached SGI interrupts. */
 924         for (irq = GIC_FIRST_SGI; irq <= GIC_LAST_SGI; irq++) {
 925                 isrc = GIC_INTR_ISRC(sc, irq);
 926                 if (intr_isrc_init_on_cpu(isrc, cpu))
 927                         gic_v3_enable_intr(dev, isrc);
 928         }
 929
 930         /* Unmask attached PPI interrupts. */
 931         for (irq = GIC_FIRST_PPI; irq <= GIC_LAST_PPI; irq++) {
 932                 isrc = GIC_INTR_ISRC(sc, irq);
 933                 if (intr_isrc_init_on_cpu(isrc, cpu))
 934                         gic_v3_enable_intr(dev, isrc);
 935         }
 936
 937         for (i = 0; i < sc->gic_nchildren; i++) {
 938                 child = sc->gic_children[i];
 939                 PIC_INIT_SECONDARY(child);
 940         }
 941 }
 942
 943 static void
 944 gic_v3_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus,
 945     u_int ipi)
 946 {
 947         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 948         uint64_t aff, val, irq;
 949         int i;
 950
 951 #define GIC_AFF_MASK    (CPU_AFF3_MASK | CPU_AFF2_MASK | CPU_AFF1_MASK)
 952 #define GIC_AFFINITY(i) (CPU_AFFINITY(i) & GIC_AFF_MASK)
 953         aff = GIC_AFFINITY(0);
 954         irq = gi->gi_irq;
 955         val = 0;
 956
 957         /* Iterate through all CPUs in set */
 958         for (i = 0; i <= mp_maxid; i++) {
 959                 /* Move to the next affinity group */
 960                 if (aff != GIC_AFFINITY(i)) {
 961                         /* Send the IPI */
 962                         if (val != 0) {
 963                                 gic_icc_write(SGI1R, val);
 964                                 val = 0;
 965                         }
 966                         aff = GIC_AFFINITY(i);
 967                 }
 968
 969                 /* Send the IPI to this cpu */
 970                 if (CPU_ISSET(i, &cpus)) {
 971 #define ICC_SGI1R_AFFINITY(aff)                                 \
 972     (((uint64_t)CPU_AFF3(aff) << ICC_SGI1R_EL1_AFF3_SHIFT) |    \
 973      ((uint64_t)CPU_AFF2(aff) << ICC_SGI1R_EL1_AFF2_SHIFT) |    \
 974      ((uint64_t)CPU_AFF1(aff) << ICC_SGI1R_EL1_AFF1_SHIFT))
 975                         /* Set the affinity when the first at this level */
 976                         if (val == 0)
 977                                 val = ICC_SGI1R_AFFINITY(aff) |
 978                                     irq << ICC_SGI1R_EL1_SGIID_SHIFT;
 979                         /* Set the bit to send the IPI to te CPU */
 980                         val |= 1 << CPU_AFF0(CPU_AFFINITY(i));
 981                 }
 982         }
 983
 984         /* Send the IPI to the last cpu affinity group */
 985         if (val != 0)
 986                 gic_icc_write(SGI1R, val);
 987 #undef GIC_AFF_MASK
 988 #undef GIC_AFFINITY
 989 }
 990
 991 static int
 992 gic_v3_ipi_setup(device_t dev, u_int ipi, struct intr_irqsrc **isrcp)
 993 {
 994         struct intr_irqsrc *isrc;
 995         struct gic_v3_softc *sc = device_get_softc(dev);
 996
 997         if (sgi_first_unused > GIC_LAST_SGI)
 998                 return (ENOSPC);
 999
1000         isrc = GIC_INTR_ISRC(sc, sgi_first_unused);
1001         sgi_to_ipi[sgi_first_unused++] = ipi;
1002
1003         CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
1004
1005         *isrcp = isrc;
1006         return (0);
1007 }
1008 #endif /* SMP */
1009
1010 /*
1011  * Helper routines
1012  */
1013 static void
1014 gic_v3_wait_for_rwp(struct gic_v3_softc *sc, enum gic_v3_xdist xdist)
1015 {
1016         struct resource *res;
1017         u_int cpuid;
1018         size_t us_left = 1000000;
1019
1020         cpuid = PCPU_GET(cpuid);
1021
1022         switch (xdist) {
1023         case DIST:
1024                 res = sc->gic_dist;
1025                 break;
1026         case REDIST:
1027                 res = &sc->gic_redists.pcpu[cpuid]->res;
1028                 break;
1029         default:
1030                 KASSERT(0, ("%s: Attempt to wait for unknown RWP", __func__));
1031                 return;
1032         }
1033
1034         while ((bus_read_4(res, GICD_CTLR) & GICD_CTLR_RWP) != 0) {
1035                 DELAY(1);
1036                 if (us_left-- == 0)
1037                         panic("GICD Register write pending for too long");
1038         }
1039 }
1040
1041 /* CPU interface. */
1042 static __inline void
1043 gic_v3_cpu_priority(uint64_t mask)
1044 {
1045
1046         /* Set prority mask */
1047         gic_icc_write(PMR, mask & ICC_PMR_EL1_PRIO_MASK);
1048 }
1049
1050 static int
1051 gic_v3_cpu_enable_sre(struct gic_v3_softc *sc)
1052 {
1053         uint64_t sre;
1054         u_int cpuid;
1055
1056         cpuid = PCPU_GET(cpuid);
1057         /*
1058          * Set the SRE bit to enable access to GIC CPU interface
1059          * via system registers.
1060          */
1061         sre = READ_SPECIALREG(icc_sre_el1);
1062         sre |= ICC_SRE_EL1_SRE;
1063         WRITE_SPECIALREG(icc_sre_el1, sre);
1064         isb();
1065         /*
1066          * Now ensure that the bit is set.
1067          */
1068         sre = READ_SPECIALREG(icc_sre_el1);
1069         if ((sre & ICC_SRE_EL1_SRE) == 0) {
1070                 /* We are done. This was disabled in EL2 */
1071                 device_printf(sc->dev, "ERROR: CPU%u cannot enable CPU interface "
1072                     "via system registers\n", cpuid);
1073                 return (ENXIO);
1074         } else if (bootverbose) {
1075                 device_printf(sc->dev,
1076                     "CPU%u enabled CPU interface via system registers\n",
1077                     cpuid);
1078         }
1079
1080         return (0);
1081 }
1082
1083 static int
1084 gic_v3_cpu_init(struct gic_v3_softc *sc)
1085 {
1086         int err;
1087
1088         /* Enable access to CPU interface via system registers */
1089         err = gic_v3_cpu_enable_sre(sc);
1090         if (err != 0)
1091                 return (err);
1092         /* Priority mask to minimum - accept all interrupts */
1093         gic_v3_cpu_priority(GIC_PRIORITY_MIN);
1094         /* Disable EOI mode */
1095         gic_icc_clear(CTLR, ICC_CTLR_EL1_EOIMODE);
1096         /* Enable group 1 (insecure) interrups */
1097         gic_icc_set(IGRPEN1, ICC_IGRPEN0_EL1_EN);
1098
1099         return (0);
1100 }
1101
1102 /* Distributor */
1103 static int
1104 gic_v3_dist_init(struct gic_v3_softc *sc)
1105 {
1106         uint64_t aff;
1107         u_int i;
1108
1109         /*
1110          * 1. Disable the Distributor
1111          */
1112         gic_d_write(sc, 4, GICD_CTLR, 0);
1113         gic_v3_wait_for_rwp(sc, DIST);
1114
1115         /*
1116          * 2. Configure the Distributor
1117          */
1118         /* Set all SPIs to be Group 1 Non-secure */
1119         for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_IGROUPRn)
1120                 gic_d_write(sc, 4, GICD_IGROUPR(i), 0xFFFFFFFF);
1121
1122         /* Set all global interrupts to be level triggered, active low. */
1123         for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ICFGRn)
1124                 gic_d_write(sc, 4, GICD_ICFGR(i), 0x00000000);
1125
1126         /* Set priority to all shared interrupts */
1127         for (i = GIC_FIRST_SPI;
1128             i < sc->gic_nirqs; i += GICD_I_PER_IPRIORITYn) {
1129                 /* Set highest priority */
1130                 gic_d_write(sc, 4, GICD_IPRIORITYR(i), GIC_PRIORITY_MAX);
1131         }
1132
1133         /*
1134          * Disable all interrupts. Leave PPI and SGIs as they are enabled in
1135          * Re-Distributor registers.
1136          */
1137         for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ISENABLERn)
1138                 gic_d_write(sc, 4, GICD_ICENABLER(i), 0xFFFFFFFF);
1139
1140         gic_v3_wait_for_rwp(sc, DIST);
1141
1142         /*
1143          * 3. Enable Distributor
1144          */
1145         /* Enable Distributor with ARE, Group 1 */
1146         gic_d_write(sc, 4, GICD_CTLR, GICD_CTLR_ARE_NS | GICD_CTLR_G1A |
1147             GICD_CTLR_G1);
1148
1149         /*
1150          * 4. Route all interrupts to boot CPU.
1151          */
1152         aff = CPU_AFFINITY(0);
1153         for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i++)
1154                 gic_d_write(sc, 8, GICD_IROUTER(i), aff);
1155
1156         return (0);
1157 }
1158
1159 /* Re-Distributor */
1160 static int
1161 gic_v3_redist_alloc(struct gic_v3_softc *sc)
1162 {
1163         u_int cpuid;
1164
1165         /* Allocate struct resource for all CPU's Re-Distributor registers */
1166         for (cpuid = 0; cpuid <= mp_maxid; cpuid++)
1167                 if (CPU_ISSET(cpuid, &all_cpus) != 0)
1168                         sc->gic_redists.pcpu[cpuid] =
1169                                 malloc(sizeof(*sc->gic_redists.pcpu[0]),
1170                                     M_GIC_V3, M_WAITOK);
1171                 else
1172                         sc->gic_redists.pcpu[cpuid] = NULL;
1173         return (0);
1174 }
1175
1176 static int
1177 gic_v3_redist_find(struct gic_v3_softc *sc)
1178 {
1179         struct resource r_res;
1180         bus_space_handle_t r_bsh;
1181         uint64_t aff;
1182         uint64_t typer;
1183         uint32_t pidr2;
1184         u_int cpuid;
1185         size_t i;
1186
1187         cpuid = PCPU_GET(cpuid);
1188
1189         aff = CPU_AFFINITY(cpuid);
1190         /* Affinity in format for comparison with typer */
1191         aff = (CPU_AFF3(aff) << 24) | (CPU_AFF2(aff) << 16) |
1192             (CPU_AFF1(aff) << 8) | CPU_AFF0(aff);
1193
1194         if (bootverbose) {
1195                 device_printf(sc->dev,
1196                     "Start searching for Re-Distributor\n");
1197         }
1198         /* Iterate through Re-Distributor regions */
1199         for (i = 0; i < sc->gic_redists.nregions; i++) {
1200                 /* Take a copy of the region's resource */
1201                 r_res = *sc->gic_redists.regions[i];
1202                 r_bsh = rman_get_bushandle(&r_res);
1203
1204                 pidr2 = bus_read_4(&r_res, GICR_PIDR2);
1205                 switch (GICR_PIDR2_ARCH(pidr2)) {
1206                 case GICR_PIDR2_ARCH_GICv3: /* fall through */
1207                 case GICR_PIDR2_ARCH_GICv4:
1208                         break;
1209                 default:
1210                         device_printf(sc->dev,
1211                             "No Re-Distributor found for CPU%u\n", cpuid);
1212                         return (ENODEV);
1213                 }
1214
1215                 do {
1216                         typer = bus_read_8(&r_res, GICR_TYPER);
1217                         if ((typer >> GICR_TYPER_AFF_SHIFT) == aff) {
1218                                 KASSERT(sc->gic_redists.pcpu[cpuid] != NULL,
1219                                     ("Invalid pointer to per-CPU redistributor"));
1220                                 /* Copy res contents to its final destination */
1221                                 sc->gic_redists.pcpu[cpuid]->res = r_res;
1222                                 sc->gic_redists.pcpu[cpuid]->lpi_enabled = false;
1223                                 if (bootverbose) {
1224                                         device_printf(sc->dev,
1225                                             "CPU%u Re-Distributor has been found\n",
1226                                             cpuid);
1227                                 }
1228                                 return (0);
1229                         }
1230
1231                         r_bsh += (GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);
1232                         if ((typer & GICR_TYPER_VLPIS) != 0) {
1233                                 r_bsh +=
1234                                     (GICR_VLPI_BASE_SIZE + GICR_RESERVED_SIZE);
1235                         }
1236
1237                         rman_set_bushandle(&r_res, r_bsh);
1238                 } while ((typer & GICR_TYPER_LAST) == 0);
1239         }
1240
1241         device_printf(sc->dev, "No Re-Distributor found for CPU%u\n", cpuid);
1242         return (ENXIO);
1243 }
1244
1245 static int
1246 gic_v3_redist_wake(struct gic_v3_softc *sc)
1247 {
1248         uint32_t waker;
1249         size_t us_left = 1000000;
1250
1251         waker = gic_r_read(sc, 4, GICR_WAKER);
1252         /* Wake up Re-Distributor for this CPU */
1253         waker &= ~GICR_WAKER_PS;
1254         gic_r_write(sc, 4, GICR_WAKER, waker);
1255         /*
1256          * When clearing ProcessorSleep bit it is required to wait for
1257          * ChildrenAsleep to become zero following the processor power-on.
1258          */
1259         while ((gic_r_read(sc, 4, GICR_WAKER) & GICR_WAKER_CA) != 0) {
1260                 DELAY(1);
1261                 if (us_left-- == 0) {
1262                         panic("Could not wake Re-Distributor for CPU%u",
1263                             PCPU_GET(cpuid));
1264                 }
1265         }
1266
1267         if (bootverbose) {
1268                 device_printf(sc->dev, "CPU%u Re-Distributor woke up\n",
1269                     PCPU_GET(cpuid));
1270         }
1271
1272         return (0);
1273 }
1274
1275 static int
1276 gic_v3_redist_init(struct gic_v3_softc *sc)
1277 {
1278         int err;
1279         size_t i;
1280
1281         err = gic_v3_redist_find(sc);
1282         if (err != 0)
1283                 return (err);
1284
1285         err = gic_v3_redist_wake(sc);
1286         if (err != 0)
1287                 return (err);
1288
1289         /* Configure SGIs and PPIs to be Group1 Non-secure */
1290         gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_IGROUPR0,
1291             0xFFFFFFFF);
1292
1293         /* Disable SPIs */
1294         gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ICENABLER0,
1295             GICR_I_ENABLER_PPI_MASK);
1296         /* Enable SGIs */
1297         gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ISENABLER0,
1298             GICR_I_ENABLER_SGI_MASK);
1299
1300         /* Set priority for SGIs and PPIs */
1301         for (i = 0; i <= GIC_LAST_PPI; i += GICR_I_PER_IPRIORITYn) {
1302                 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_IPRIORITYR(i),
1303                     GIC_PRIORITY_MAX);
1304         }
1305
1306         gic_v3_wait_for_rwp(sc, REDIST);
1307
1308         return (0);
1309 }
1310
1311 /*
1312  * SPI-mapped Message Based Interrupts -- a GICv3 MSI/MSI-X controller.
1313  */
1314
1315 static int
1316 gic_v3_alloc_msi(device_t dev, device_t child, int count, int maxcount,
1317     device_t *pic, struct intr_irqsrc **srcs)
1318 {
1319         struct gic_v3_softc *sc;
1320         int i, irq, end_irq;
1321         bool found;
1322
1323         KASSERT(powerof2(count), ("%s: bad count", __func__));
1324         KASSERT(powerof2(maxcount), ("%s: bad maxcount", __func__));
1325
1326         sc = device_get_softc(dev);
1327
1328         mtx_lock(&sc->gic_mbi_mtx);
1329
1330         found = false;
1331         for (irq = sc->gic_mbi_start; irq < sc->gic_mbi_end; irq++) {
1332                 /* Start on an aligned interrupt */
1333                 if ((irq & (maxcount - 1)) != 0)
1334                         continue;
1335
1336                 /* Assume we found a valid range until shown otherwise */
1337                 found = true;
1338
1339                 /* Check this range is valid */
1340                 for (end_irq = irq; end_irq != irq + count; end_irq++) {
1341                         /* No free interrupts */
1342                         if (end_irq == sc->gic_mbi_end) {
1343                                 found = false;
1344                                 break;
1345                         }
1346
1347                         KASSERT((sc->gic_irqs[end_irq].gi_flags & GI_FLAG_MSI)!= 0,
1348                             ("%s: Non-MSI interrupt found", __func__));
1349
1350                         /* This is already used */
1351                         if ((sc->gic_irqs[end_irq].gi_flags & GI_FLAG_MSI_USED) ==
1352                             GI_FLAG_MSI_USED) {
1353                                 found = false;
1354                                 break;
1355                         }
1356                 }
1357                 if (found)
1358                         break;
1359         }
1360
1361         /* Not enough interrupts were found */
1362         if (!found || irq == sc->gic_mbi_end) {
1363                 mtx_unlock(&sc->gic_mbi_mtx);
1364                 return (ENXIO);
1365         }
1366
1367         for (i = 0; i < count; i++) {
1368                 /* Mark the interrupt as used */
1369                 sc->gic_irqs[irq + i].gi_flags |= GI_FLAG_MSI_USED;
1370         }
1371         mtx_unlock(&sc->gic_mbi_mtx);
1372
1373         for (i = 0; i < count; i++)
1374                 srcs[i] = (struct intr_irqsrc *)&sc->gic_irqs[irq + i];
1375         *pic = dev;
1376
1377         return (0);
1378 }
1379
1380 static int
1381 gic_v3_release_msi(device_t dev, device_t child, int count,
1382     struct intr_irqsrc **isrc)
1383 {
1384         struct gic_v3_softc *sc;
1385         struct gic_v3_irqsrc *gi;
1386         int i;
1387
1388         sc = device_get_softc(dev);
1389
1390         mtx_lock(&sc->gic_mbi_mtx);
1391         for (i = 0; i < count; i++) {
1392                 gi = (struct gic_v3_irqsrc *)isrc[i];
1393
1394                 KASSERT((gi->gi_flags & GI_FLAG_MSI_USED) == GI_FLAG_MSI_USED,
1395                     ("%s: Trying to release an unused MSI-X interrupt",
1396                     __func__));
1397
1398                 gi->gi_flags &= ~GI_FLAG_MSI_USED;
1399         }
1400         mtx_unlock(&sc->gic_mbi_mtx);
1401
1402         return (0);
1403 }
1404
1405 static int
1406 gic_v3_alloc_msix(device_t dev, device_t child, device_t *pic,
1407     struct intr_irqsrc **isrcp)
1408 {
1409         struct gic_v3_softc *sc;
1410         int irq;
1411
1412         sc = device_get_softc(dev);
1413
1414         mtx_lock(&sc->gic_mbi_mtx);
1415         /* Find an unused interrupt */
1416         for (irq = sc->gic_mbi_start; irq < sc->gic_mbi_end; irq++) {
1417                 KASSERT((sc->gic_irqs[irq].gi_flags & GI_FLAG_MSI) != 0,
1418                     ("%s: Non-MSI interrupt found", __func__));
1419                 if ((sc->gic_irqs[irq].gi_flags & GI_FLAG_MSI_USED) == 0)
1420                         break;
1421         }
1422         /* No free interrupt was found */
1423         if (irq == sc->gic_mbi_end) {
1424                 mtx_unlock(&sc->gic_mbi_mtx);
1425                 return (ENXIO);
1426         }
1427
1428         /* Mark the interrupt as used */
1429         sc->gic_irqs[irq].gi_flags |= GI_FLAG_MSI_USED;
1430         mtx_unlock(&sc->gic_mbi_mtx);
1431
1432         *isrcp = (struct intr_irqsrc *)&sc->gic_irqs[irq];
1433         *pic = dev;
1434
1435         return (0);
1436 }
1437
1438 static int
1439 gic_v3_release_msix(device_t dev, device_t child, struct intr_irqsrc *isrc)
1440 {
1441         struct gic_v3_softc *sc;
1442         struct gic_v3_irqsrc *gi;
1443
1444         sc = device_get_softc(dev);
1445         gi = (struct gic_v3_irqsrc *)isrc;
1446
1447         KASSERT((gi->gi_flags & GI_FLAG_MSI_USED) == GI_FLAG_MSI_USED,
1448             ("%s: Trying to release an unused MSI-X interrupt", __func__));
1449
1450         mtx_lock(&sc->gic_mbi_mtx);
1451         gi->gi_flags &= ~GI_FLAG_MSI_USED;
1452         mtx_unlock(&sc->gic_mbi_mtx);
1453
1454         return (0);
1455 }
1456
1457 static int
1458 gic_v3_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc,
1459     uint64_t *addr, uint32_t *data)
1460 {
1461         struct gic_v3_softc *sc = device_get_softc(dev);
1462         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
1463
1464         *addr = vtophys(rman_get_virtual(sc->gic_dist)) + GICD_SETSPI_NSR;
1465         *data = gi->gi_irq;
1466
1467         return (0);
1468 }