sys/arm64/arm64/gic_v3.c

   1 /*-
   2  * Copyright (c) 2015-2016 The FreeBSD Foundation
   3  *
   4  * This software was developed by Andrew Turner under
   5  * the sponsorship of the FreeBSD Foundation.
   6  *
   7  * This software was developed by Semihalf under
   8  * the sponsorship of the FreeBSD Foundation.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  */
  31
  32 #include "opt_acpi.h"
  33 #include "opt_platform.h"
  34
  35 #include <sys/cdefs.h>
  36 __FBSDID("$FreeBSD$");
  37
  38 #include <sys/param.h>
  39 #include <sys/systm.h>
  40 #include <sys/bitstring.h>
  41 #include <sys/bus.h>
  42 #include <sys/kernel.h>
  43 #include <sys/ktr.h>
  44 #include <sys/malloc.h>
  45 #include <sys/module.h>
  46 #include <sys/rman.h>
  47 #include <sys/pcpu.h>
  48 #include <sys/proc.h>
  49 #include <sys/cpuset.h>
  50 #include <sys/lock.h>
  51 #include <sys/mutex.h>
  52 #include <sys/smp.h>
  53 #include <sys/interrupt.h>
  54
  55 #include <vm/vm.h>
  56 #include <vm/pmap.h>
  57
  58 #include <machine/bus.h>
  59 #include <machine/cpu.h>
  60 #include <machine/intr.h>
  61
  62 #ifdef FDT
  63 #include <dev/fdt/fdt_intr.h>
  64 #include <dev/ofw/ofw_bus_subr.h>
  65 #endif
  66
  67 #ifdef DEV_ACPI
  68 #include <contrib/dev/acpica/include/acpi.h>
  69 #include <dev/acpica/acpivar.h>
  70 #endif
  71
  72 #include "pic_if.h"
  73 #include "msi_if.h"
  74
  75 #include <arm/arm/gic_common.h>
  76 #include "gic_v3_reg.h"
  77 #include "gic_v3_var.h"
  78
  79 static bus_print_child_t gic_v3_print_child;
  80 static bus_get_domain_t gic_v3_get_domain;
  81 static bus_read_ivar_t gic_v3_read_ivar;
  82
  83 static pic_disable_intr_t gic_v3_disable_intr;
  84 static pic_enable_intr_t gic_v3_enable_intr;
  85 static pic_map_intr_t gic_v3_map_intr;
  86 static pic_setup_intr_t gic_v3_setup_intr;
  87 static pic_teardown_intr_t gic_v3_teardown_intr;
  88 static pic_post_filter_t gic_v3_post_filter;
  89 static pic_post_ithread_t gic_v3_post_ithread;
  90 static pic_pre_ithread_t gic_v3_pre_ithread;
  91 static pic_bind_intr_t gic_v3_bind_intr;
  92 #ifdef SMP
  93 static pic_init_secondary_t gic_v3_init_secondary;
  94 static pic_ipi_send_t gic_v3_ipi_send;
  95 static pic_ipi_setup_t gic_v3_ipi_setup;
  96 #endif
  97
  98 static msi_alloc_msi_t gic_v3_alloc_msi;
  99 static msi_release_msi_t gic_v3_release_msi;
 100 static msi_alloc_msix_t gic_v3_alloc_msix;
 101 static msi_release_msix_t gic_v3_release_msix;
 102 static msi_map_msi_t gic_v3_map_msi;
 103
 104 static u_int gic_irq_cpu;
 105 #ifdef SMP
 106 static u_int sgi_to_ipi[GIC_LAST_SGI - GIC_FIRST_SGI + 1];
 107 static u_int sgi_first_unused = GIC_FIRST_SGI;
 108 #endif
 109
 110 static device_method_t gic_v3_methods[] = {
 111         /* Device interface */
 112         DEVMETHOD(device_detach,        gic_v3_detach),
 113
 114         /* Bus interface */
 115         DEVMETHOD(bus_print_child,      gic_v3_print_child),
 116         DEVMETHOD(bus_get_domain,       gic_v3_get_domain),
 117         DEVMETHOD(bus_read_ivar,        gic_v3_read_ivar),
 118
 119         /* Interrupt controller interface */
 120         DEVMETHOD(pic_disable_intr,     gic_v3_disable_intr),
 121         DEVMETHOD(pic_enable_intr,      gic_v3_enable_intr),
 122         DEVMETHOD(pic_map_intr,         gic_v3_map_intr),
 123         DEVMETHOD(pic_setup_intr,       gic_v3_setup_intr),
 124         DEVMETHOD(pic_teardown_intr,    gic_v3_teardown_intr),
 125         DEVMETHOD(pic_post_filter,      gic_v3_post_filter),
 126         DEVMETHOD(pic_post_ithread,     gic_v3_post_ithread),
 127         DEVMETHOD(pic_pre_ithread,      gic_v3_pre_ithread),
 128 #ifdef SMP
 129         DEVMETHOD(pic_bind_intr,        gic_v3_bind_intr),
 130         DEVMETHOD(pic_init_secondary,   gic_v3_init_secondary),
 131         DEVMETHOD(pic_ipi_send,         gic_v3_ipi_send),
 132         DEVMETHOD(pic_ipi_setup,        gic_v3_ipi_setup),
 133 #endif
 134
 135         /* MSI/MSI-X */
 136         DEVMETHOD(msi_alloc_msi,        gic_v3_alloc_msi),
 137         DEVMETHOD(msi_release_msi,      gic_v3_release_msi),
 138         DEVMETHOD(msi_alloc_msix,       gic_v3_alloc_msix),
 139         DEVMETHOD(msi_release_msix,     gic_v3_release_msix),
 140         DEVMETHOD(msi_map_msi,          gic_v3_map_msi),
 141
 142         /* End */
 143         DEVMETHOD_END
 144 };
 145
 146 DEFINE_CLASS_0(gic, gic_v3_driver, gic_v3_methods,
 147     sizeof(struct gic_v3_softc));
 148
 149 /*
 150  * Driver-specific definitions.
 151  */
 152 MALLOC_DEFINE(M_GIC_V3, "GICv3", GIC_V3_DEVSTR);
 153
 154 /*
 155  * Helper functions and definitions.
 156  */
 157 /* Destination registers, either Distributor or Re-Distributor */
 158 enum gic_v3_xdist {
 159         DIST = 0,
 160         REDIST,
 161 };
 162
 163 struct gic_v3_irqsrc {
 164         struct intr_irqsrc      gi_isrc;
 165         uint32_t                gi_irq;
 166         enum intr_polarity      gi_pol;
 167         enum intr_trigger       gi_trig;
 168 #define GI_FLAG_MSI             (1 << 1) /* This interrupt source should only */
 169                                          /* be used for MSI/MSI-X interrupts */
 170 #define GI_FLAG_MSI_USED        (1 << 2) /* This irq is already allocated */
 171                                          /* for a MSI/MSI-X interrupt */
 172         u_int                   gi_flags;
 173 };
 174
 175 /* Helper routines starting with gic_v3_ */
 176 static int gic_v3_dist_init(struct gic_v3_softc *);
 177 static int gic_v3_redist_alloc(struct gic_v3_softc *);
 178 static int gic_v3_redist_find(struct gic_v3_softc *);
 179 static int gic_v3_redist_init(struct gic_v3_softc *);
 180 static int gic_v3_cpu_init(struct gic_v3_softc *);
 181 static void gic_v3_wait_for_rwp(struct gic_v3_softc *, enum gic_v3_xdist);
 182
 183 /* A sequence of init functions for primary (boot) CPU */
 184 typedef int (*gic_v3_initseq_t) (struct gic_v3_softc *);
 185 /* Primary CPU initialization sequence */
 186 static gic_v3_initseq_t gic_v3_primary_init[] = {
 187         gic_v3_dist_init,
 188         gic_v3_redist_alloc,
 189         gic_v3_redist_init,
 190         gic_v3_cpu_init,
 191         NULL
 192 };
 193
 194 #ifdef SMP
 195 /* Secondary CPU initialization sequence */
 196 static gic_v3_initseq_t gic_v3_secondary_init[] = {
 197         gic_v3_redist_init,
 198         gic_v3_cpu_init,
 199         NULL
 200 };
 201 #endif
 202
 203 uint32_t
 204 gic_r_read_4(device_t dev, bus_size_t offset)
 205 {
 206         struct gic_v3_softc *sc;
 207         struct resource *rdist;
 208
 209         sc = device_get_softc(dev);
 210         rdist = &sc->gic_redists.pcpu[PCPU_GET(cpuid)]->res;
 211         return (bus_read_4(rdist, offset));
 212 }
 213
 214 uint64_t
 215 gic_r_read_8(device_t dev, bus_size_t offset)
 216 {
 217         struct gic_v3_softc *sc;
 218         struct resource *rdist;
 219
 220         sc = device_get_softc(dev);
 221         rdist = &sc->gic_redists.pcpu[PCPU_GET(cpuid)]->res;
 222         return (bus_read_8(rdist, offset));
 223 }
 224
 225 void
 226 gic_r_write_4(device_t dev, bus_size_t offset, uint32_t val)
 227 {
 228         struct gic_v3_softc *sc;
 229         struct resource *rdist;
 230
 231         sc = device_get_softc(dev);
 232         rdist = &sc->gic_redists.pcpu[PCPU_GET(cpuid)]->res;
 233         bus_write_4(rdist, offset, val);
 234 }
 235
 236 void
 237 gic_r_write_8(device_t dev, bus_size_t offset, uint64_t val)
 238 {
 239         struct gic_v3_softc *sc;
 240         struct resource *rdist;
 241
 242         sc = device_get_softc(dev);
 243         rdist = &sc->gic_redists.pcpu[PCPU_GET(cpuid)]->res;
 244         bus_write_8(rdist, offset, val);
 245 }
 246
 247 /*
 248  * Device interface.
 249  */
 250 int
 251 gic_v3_attach(device_t dev)
 252 {
 253         struct gic_v3_softc *sc;
 254         gic_v3_initseq_t *init_func;
 255         uint32_t typer;
 256         int rid;
 257         int err;
 258         size_t i;
 259         u_int irq;
 260         const char *name;
 261
 262         sc = device_get_softc(dev);
 263         sc->gic_registered = FALSE;
 264         sc->dev = dev;
 265         err = 0;
 266
 267         /* Initialize mutex */
 268         mtx_init(&sc->gic_mtx, "GICv3 lock", NULL, MTX_SPIN);
 269
 270         /*
 271          * Allocate array of struct resource.
 272          * One entry for Distributor and all remaining for Re-Distributor.
 273          */
 274         sc->gic_res = malloc(
 275             sizeof(*sc->gic_res) * (sc->gic_redists.nregions + 1),
 276             M_GIC_V3, M_WAITOK);
 277
 278         /* Now allocate corresponding resources */
 279         for (i = 0, rid = 0; i < (sc->gic_redists.nregions + 1); i++, rid++) {
 280                 sc->gic_res[rid] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 281                     &rid, RF_ACTIVE);
 282                 if (sc->gic_res[rid] == NULL)
 283                         return (ENXIO);
 284         }
 285
 286         /*
 287          * Distributor interface
 288          */
 289         sc->gic_dist = sc->gic_res[0];
 290
 291         /*
 292          * Re-Dristributor interface
 293          */
 294         /* Allocate space under region descriptions */
 295         sc->gic_redists.regions = malloc(
 296             sizeof(*sc->gic_redists.regions) * sc->gic_redists.nregions,
 297             M_GIC_V3, M_WAITOK);
 298
 299         /* Fill-up bus_space information for each region. */
 300         for (i = 0, rid = 1; i < sc->gic_redists.nregions; i++, rid++)
 301                 sc->gic_redists.regions[i] = sc->gic_res[rid];
 302
 303         /* Get the number of supported SPI interrupts */
 304         typer = gic_d_read(sc, 4, GICD_TYPER);
 305         sc->gic_nirqs = GICD_TYPER_I_NUM(typer);
 306         if (sc->gic_nirqs > GIC_I_NUM_MAX)
 307                 sc->gic_nirqs = GIC_I_NUM_MAX;
 308
 309         sc->gic_irqs = malloc(sizeof(*sc->gic_irqs) * sc->gic_nirqs,
 310             M_GIC_V3, M_WAITOK | M_ZERO);
 311         name = device_get_nameunit(dev);
 312         for (irq = 0; irq < sc->gic_nirqs; irq++) {
 313                 struct intr_irqsrc *isrc;
 314
 315                 sc->gic_irqs[irq].gi_irq = irq;
 316                 sc->gic_irqs[irq].gi_pol = INTR_POLARITY_CONFORM;
 317                 sc->gic_irqs[irq].gi_trig = INTR_TRIGGER_CONFORM;
 318
 319                 isrc = &sc->gic_irqs[irq].gi_isrc;
 320                 if (irq <= GIC_LAST_SGI) {
 321                         err = intr_isrc_register(isrc, sc->dev,
 322                             INTR_ISRCF_IPI, "%s,i%u", name, irq - GIC_FIRST_SGI);
 323                 } else if (irq <= GIC_LAST_PPI) {
 324                         err = intr_isrc_register(isrc, sc->dev,
 325                             INTR_ISRCF_PPI, "%s,p%u", name, irq - GIC_FIRST_PPI);
 326                 } else {
 327                         err = intr_isrc_register(isrc, sc->dev, 0,
 328                             "%s,s%u", name, irq - GIC_FIRST_SPI);
 329                 }
 330                 if (err != 0) {
 331                         /* XXX call intr_isrc_deregister() */
 332                         free(sc->gic_irqs, M_DEVBUF);
 333                         return (err);
 334                 }
 335         }
 336
 337         if (sc->gic_mbi_start > 0) {
 338                 /* Reserve these interrupts for MSI/MSI-X use */
 339                 for (irq = sc->gic_mbi_start; irq <= sc->gic_mbi_end; irq++) {
 340                         sc->gic_irqs[irq].gi_pol = INTR_POLARITY_HIGH;
 341                         sc->gic_irqs[irq].gi_trig = INTR_TRIGGER_EDGE;
 342                         sc->gic_irqs[irq].gi_flags |= GI_FLAG_MSI;
 343                 }
 344
 345                 mtx_init(&sc->gic_mbi_mtx, "GICv3 mbi lock", NULL, MTX_DEF);
 346
 347                 if (bootverbose) {
 348                         device_printf(dev, "using spi %u to %u\n", sc->gic_mbi_start,
 349                                         sc->gic_mbi_end);
 350                 }
 351         }
 352
 353         /*
 354          * Read the Peripheral ID2 register. This is an implementation
 355          * defined register, but seems to be implemented in all GICv3
 356          * parts and Linux expects it to be there.
 357          */
 358         sc->gic_pidr2 = gic_d_read(sc, 4, GICD_PIDR2);
 359
 360         /* Get the number of supported interrupt identifier bits */
 361         sc->gic_idbits = GICD_TYPER_IDBITS(typer);
 362
 363         if (bootverbose) {
 364                 device_printf(dev, "SPIs: %u, IDs: %u\n",
 365                     sc->gic_nirqs, (1 << sc->gic_idbits) - 1);
 366         }
 367
 368         /* Train init sequence for boot CPU */
 369         for (init_func = gic_v3_primary_init; *init_func != NULL; init_func++) {
 370                 err = (*init_func)(sc);
 371                 if (err != 0)
 372                         return (err);
 373         }
 374
 375         return (0);
 376 }
 377
 378 int
 379 gic_v3_detach(device_t dev)
 380 {
 381         struct gic_v3_softc *sc;
 382         size_t i;
 383         int rid;
 384
 385         sc = device_get_softc(dev);
 386
 387         if (device_is_attached(dev)) {
 388                 /*
 389                  * XXX: We should probably deregister PIC
 390                  */
 391                 if (sc->gic_registered)
 392                         panic("Trying to detach registered PIC");
 393         }
 394         for (rid = 0; rid < (sc->gic_redists.nregions + 1); rid++)
 395                 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->gic_res[rid]);
 396
 397         for (i = 0; i <= mp_maxid; i++)
 398                 free(sc->gic_redists.pcpu[i], M_GIC_V3);
 399
 400         free(sc->gic_res, M_GIC_V3);
 401         free(sc->gic_redists.regions, M_GIC_V3);
 402
 403         return (0);
 404 }
 405
 406 static int
 407 gic_v3_print_child(device_t bus, device_t child)
 408 {
 409         struct resource_list *rl;
 410         int retval = 0;
 411
 412         rl = BUS_GET_RESOURCE_LIST(bus, child);
 413         KASSERT(rl != NULL, ("%s: No resource list", __func__));
 414         retval += bus_print_child_header(bus, child);
 415         retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx");
 416         retval += bus_print_child_footer(bus, child);
 417
 418         return (retval);
 419 }
 420
 421 static int
 422 gic_v3_get_domain(device_t dev, device_t child, int *domain)
 423 {
 424         struct gic_v3_devinfo *di;
 425
 426         di = device_get_ivars(child);
 427         if (di->gic_domain < 0)
 428                 return (ENOENT);
 429
 430         *domain = di->gic_domain;
 431         return (0);
 432 }
 433
 434 static int
 435 gic_v3_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
 436 {
 437         struct gic_v3_softc *sc;
 438
 439         sc = device_get_softc(dev);
 440
 441         switch (which) {
 442         case GICV3_IVAR_NIRQS:
 443                 *result = (intr_nirq - sc->gic_nirqs) / sc->gic_nchildren;
 444                 return (0);
 445         case GICV3_IVAR_REDIST:
 446                 *result = (uintptr_t)sc->gic_redists.pcpu[PCPU_GET(cpuid)];
 447                 return (0);
 448         case GIC_IVAR_HW_REV:
 449                 KASSERT(
 450                     GICR_PIDR2_ARCH(sc->gic_pidr2) == GICR_PIDR2_ARCH_GICv3 ||
 451                     GICR_PIDR2_ARCH(sc->gic_pidr2) == GICR_PIDR2_ARCH_GICv4,
 452                     ("gic_v3_read_ivar: Invalid GIC architecture: %d (%.08X)",
 453                      GICR_PIDR2_ARCH(sc->gic_pidr2), sc->gic_pidr2));
 454                 *result = GICR_PIDR2_ARCH(sc->gic_pidr2);
 455                 return (0);
 456         case GIC_IVAR_BUS:
 457                 KASSERT(sc->gic_bus != GIC_BUS_UNKNOWN,
 458                     ("gic_v3_read_ivar: Unknown bus type"));
 459                 KASSERT(sc->gic_bus <= GIC_BUS_MAX,
 460                     ("gic_v3_read_ivar: Invalid bus type %u", sc->gic_bus));
 461                 *result = sc->gic_bus;
 462                 return (0);
 463         }
 464
 465         return (ENOENT);
 466 }
 467
 468 int
 469 arm_gic_v3_intr(void *arg)
 470 {
 471         struct gic_v3_softc *sc = arg;
 472         struct gic_v3_irqsrc *gi;
 473         struct intr_pic *pic;
 474         uint64_t active_irq;
 475         struct trapframe *tf;
 476
 477         pic = sc->gic_pic;
 478
 479         while (1) {
 480                 if (CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1) {
 481                         /*
 482                          * Hardware:            Cavium ThunderX
 483                          * Chip revision:       Pass 1.0 (early version)
 484                          *                      Pass 1.1 (production)
 485                          * ERRATUM:             22978, 23154
 486                          */
 487                         __asm __volatile(
 488                             "nop;nop;nop;nop;nop;nop;nop;nop;   \n"
 489                             "mrs %0, ICC_IAR1_EL1               \n"
 490                             "nop;nop;nop;nop;                   \n"
 491                             "dsb sy                             \n"
 492                             : "=&r" (active_irq));
 493                 } else {
 494                         active_irq = gic_icc_read(IAR1);
 495                 }
 496
 497                 if (active_irq >= GIC_FIRST_LPI) {
 498                         intr_child_irq_handler(pic, active_irq);
 499                         continue;
 500                 }
 501
 502                 if (__predict_false(active_irq >= sc->gic_nirqs))
 503                         return (FILTER_HANDLED);
 504
 505                 tf = curthread->td_intr_frame;
 506                 gi = &sc->gic_irqs[active_irq];
 507                 if (active_irq <= GIC_LAST_SGI) {
 508                         /* Call EOI for all IPI before dispatch. */
 509                         gic_icc_write(EOIR1, (uint64_t)active_irq);
 510 #ifdef SMP
 511                         intr_ipi_dispatch(sgi_to_ipi[gi->gi_irq], tf);
 512 #else
 513                         device_printf(sc->dev, "SGI %ju on UP system detected\n",
 514                             (uintmax_t)(active_irq - GIC_FIRST_SGI));
 515 #endif
 516                 } else if (active_irq >= GIC_FIRST_PPI &&
 517                     active_irq <= GIC_LAST_SPI) {
 518                         if (gi->gi_trig == INTR_TRIGGER_EDGE)
 519                                 gic_icc_write(EOIR1, gi->gi_irq);
 520
 521                         if (intr_isrc_dispatch(&gi->gi_isrc, tf) != 0) {
 522                                 if (gi->gi_trig != INTR_TRIGGER_EDGE)
 523                                         gic_icc_write(EOIR1, gi->gi_irq);
 524                                 gic_v3_disable_intr(sc->dev, &gi->gi_isrc);
 525                                 device_printf(sc->dev,
 526                                     "Stray irq %lu disabled\n", active_irq);
 527                         }
 528                 }
 529         }
 530 }
 531
 532 #ifdef FDT
 533 static int
 534 gic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp,
 535     enum intr_polarity *polp, enum intr_trigger *trigp)
 536 {
 537         u_int irq;
 538
 539         if (ncells < 3)
 540                 return (EINVAL);
 541
 542         /*
 543          * The 1st cell is the interrupt type:
 544          *      0 = SPI
 545          *      1 = PPI
 546          * The 2nd cell contains the interrupt number:
 547          *      [0 - 987] for SPI
 548          *      [0 -  15] for PPI
 549          * The 3rd cell is the flags, encoded as follows:
 550          *   bits[3:0] trigger type and level flags
 551          *      1 = edge triggered
 552          *      2 = edge triggered (PPI only)
 553          *      4 = level-sensitive
 554          *      8 = level-sensitive (PPI only)
 555          */
 556         switch (cells[0]) {
 557         case 0:
 558                 irq = GIC_FIRST_SPI + cells[1];
 559                 /* SPI irq is checked later. */
 560                 break;
 561         case 1:
 562                 irq = GIC_FIRST_PPI + cells[1];
 563                 if (irq > GIC_LAST_PPI) {
 564                         device_printf(dev, "unsupported PPI interrupt "
 565                             "number %u\n", cells[1]);
 566                         return (EINVAL);
 567                 }
 568                 break;
 569         default:
 570                 device_printf(dev, "unsupported interrupt type "
 571                     "configuration %u\n", cells[0]);
 572                 return (EINVAL);
 573         }
 574
 575         switch (cells[2] & FDT_INTR_MASK) {
 576         case FDT_INTR_EDGE_RISING:
 577                 *trigp = INTR_TRIGGER_EDGE;
 578                 *polp = INTR_POLARITY_HIGH;
 579                 break;
 580         case FDT_INTR_EDGE_FALLING:
 581                 *trigp = INTR_TRIGGER_EDGE;
 582                 *polp = INTR_POLARITY_LOW;
 583                 break;
 584         case FDT_INTR_LEVEL_HIGH:
 585                 *trigp = INTR_TRIGGER_LEVEL;
 586                 *polp = INTR_POLARITY_HIGH;
 587                 break;
 588         case FDT_INTR_LEVEL_LOW:
 589                 *trigp = INTR_TRIGGER_LEVEL;
 590                 *polp = INTR_POLARITY_LOW;
 591                 break;
 592         default:
 593                 device_printf(dev, "unsupported trigger/polarity "
 594                     "configuration 0x%02x\n", cells[2]);
 595                 return (EINVAL);
 596         }
 597
 598         /* Check the interrupt is valid */
 599         if (irq >= GIC_FIRST_SPI && *polp != INTR_POLARITY_HIGH)
 600                 return (EINVAL);
 601
 602         *irqp = irq;
 603         return (0);
 604 }
 605 #endif
 606
 607 static int
 608 gic_map_msi(device_t dev, struct intr_map_data_msi *msi_data, u_int *irqp,
 609     enum intr_polarity *polp, enum intr_trigger *trigp)
 610 {
 611         struct gic_v3_irqsrc *gi;
 612
 613         /* SPI-mapped MSI */
 614         gi = (struct gic_v3_irqsrc *)msi_data->isrc;
 615         if (gi == NULL)
 616                 return (ENXIO);
 617
 618         *irqp = gi->gi_irq;
 619
 620         /* MSI/MSI-X interrupts are always edge triggered with high polarity */
 621         *polp = INTR_POLARITY_HIGH;
 622         *trigp = INTR_TRIGGER_EDGE;
 623
 624         return (0);
 625 }
 626
 627 static int
 628 do_gic_v3_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp,
 629     enum intr_polarity *polp, enum intr_trigger *trigp)
 630 {
 631         struct gic_v3_softc *sc;
 632         enum intr_polarity pol;
 633         enum intr_trigger trig;
 634         struct intr_map_data_msi *dam;
 635 #ifdef FDT
 636         struct intr_map_data_fdt *daf;
 637 #endif
 638 #ifdef DEV_ACPI
 639         struct intr_map_data_acpi *daa;
 640 #endif
 641         u_int irq;
 642
 643         sc = device_get_softc(dev);
 644
 645         switch (data->type) {
 646 #ifdef FDT
 647         case INTR_MAP_DATA_FDT:
 648                 daf = (struct intr_map_data_fdt *)data;
 649                 if (gic_map_fdt(dev, daf->ncells, daf->cells, &irq, &pol,
 650                     &trig) != 0)
 651                         return (EINVAL);
 652                 break;
 653 #endif
 654 #ifdef DEV_ACPI
 655         case INTR_MAP_DATA_ACPI:
 656                 daa = (struct intr_map_data_acpi *)data;
 657                 irq = daa->irq;
 658                 pol = daa->pol;
 659                 trig = daa->trig;
 660                 break;
 661 #endif
 662         case INTR_MAP_DATA_MSI:
 663                 /* SPI-mapped MSI */
 664                 dam = (struct intr_map_data_msi *)data;
 665                 if (gic_map_msi(dev, dam, &irq, &pol, &trig) != 0)
 666                         return (EINVAL);
 667                 break;
 668         default:
 669                 return (EINVAL);
 670         }
 671
 672         if (irq >= sc->gic_nirqs)
 673                 return (EINVAL);
 674         switch (pol) {
 675         case INTR_POLARITY_CONFORM:
 676         case INTR_POLARITY_LOW:
 677         case INTR_POLARITY_HIGH:
 678                 break;
 679         default:
 680                 return (EINVAL);
 681         }
 682         switch (trig) {
 683         case INTR_TRIGGER_CONFORM:
 684         case INTR_TRIGGER_EDGE:
 685         case INTR_TRIGGER_LEVEL:
 686                 break;
 687         default:
 688                 return (EINVAL);
 689         }
 690
 691         *irqp = irq;
 692         if (polp != NULL)
 693                 *polp = pol;
 694         if (trigp != NULL)
 695                 *trigp = trig;
 696         return (0);
 697 }
 698
 699 static int
 700 gic_v3_map_intr(device_t dev, struct intr_map_data *data,
 701     struct intr_irqsrc **isrcp)
 702 {
 703         struct gic_v3_softc *sc;
 704         int error;
 705         u_int irq;
 706
 707         error = do_gic_v3_map_intr(dev, data, &irq, NULL, NULL);
 708         if (error == 0) {
 709                 sc = device_get_softc(dev);
 710                 *isrcp = GIC_INTR_ISRC(sc, irq);
 711         }
 712         return (error);
 713 }
 714
 715 struct gic_v3_setup_periph_args {
 716         device_t                 dev;
 717         struct intr_irqsrc      *isrc;
 718 };
 719
 720 static void
 721 gic_v3_setup_intr_periph(void *argp)
 722 {
 723         struct gic_v3_setup_periph_args *args = argp;
 724         struct intr_irqsrc *isrc = args->isrc;
 725         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 726         device_t dev = args->dev;
 727         u_int irq = gi->gi_irq;
 728         struct gic_v3_softc *sc = device_get_softc(dev);
 729         uint32_t reg;
 730
 731         MPASS(irq <= GIC_LAST_SPI);
 732
 733         /*
 734          * We need the lock for both SGIs and PPIs for an atomic CPU_SET() at a
 735          * minimum, but we also need it below for SPIs.
 736          */
 737         mtx_lock_spin(&sc->gic_mtx);
 738
 739         if (isrc->isrc_flags & INTR_ISRCF_PPI)
 740                 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
 741
 742         if (irq >= GIC_FIRST_PPI && irq <= GIC_LAST_SPI) {
 743                 /* Set the trigger and polarity */
 744                 if (irq <= GIC_LAST_PPI)
 745                         reg = gic_r_read(sc, 4,
 746                             GICR_SGI_BASE_SIZE + GICD_ICFGR(irq));
 747                 else
 748                         reg = gic_d_read(sc, 4, GICD_ICFGR(irq));
 749                 if (gi->gi_trig == INTR_TRIGGER_LEVEL)
 750                         reg &= ~(2 << ((irq % 16) * 2));
 751                 else
 752                         reg |= 2 << ((irq % 16) * 2);
 753
 754                 if (irq <= GIC_LAST_PPI) {
 755                         gic_r_write(sc, 4,
 756                             GICR_SGI_BASE_SIZE + GICD_ICFGR(irq), reg);
 757                         gic_v3_wait_for_rwp(sc, REDIST);
 758                 } else {
 759                         gic_d_write(sc, 4, GICD_ICFGR(irq), reg);
 760                         gic_v3_wait_for_rwp(sc, DIST);
 761                 }
 762         }
 763
 764         mtx_unlock_spin(&sc->gic_mtx);
 765 }
 766
 767 static int
 768 gic_v3_setup_intr(device_t dev, struct intr_irqsrc *isrc,
 769     struct resource *res, struct intr_map_data *data)
 770 {
 771         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 772         struct gic_v3_setup_periph_args pargs;
 773         enum intr_trigger trig;
 774         enum intr_polarity pol;
 775         u_int irq;
 776         int error;
 777
 778         if (data == NULL)
 779                 return (ENOTSUP);
 780
 781         error = do_gic_v3_map_intr(dev, data, &irq, &pol, &trig);
 782         if (error != 0)
 783                 return (error);
 784
 785         if (gi->gi_irq != irq || pol == INTR_POLARITY_CONFORM ||
 786             trig == INTR_TRIGGER_CONFORM)
 787                 return (EINVAL);
 788
 789         /* Compare config if this is not first setup. */
 790         if (isrc->isrc_handlers != 0) {
 791                 if (pol != gi->gi_pol || trig != gi->gi_trig)
 792                         return (EINVAL);
 793                 else
 794                         return (0);
 795         }
 796
 797         /* For MSI/MSI-X we should have already configured these */
 798         if ((gi->gi_flags & GI_FLAG_MSI) == 0) {
 799                 gi->gi_pol = pol;
 800                 gi->gi_trig = trig;
 801         }
 802
 803         pargs.dev = dev;
 804         pargs.isrc = isrc;
 805
 806         if (isrc->isrc_flags & INTR_ISRCF_PPI) {
 807                 /*
 808                  * If APs haven't been fired up yet, smp_rendezvous() will just
 809                  * execute it on the single CPU and gic_v3_init_secondary() will
 810                  * clean up afterwards.
 811                  */
 812                 smp_rendezvous(NULL, gic_v3_setup_intr_periph, NULL, &pargs);
 813         } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) {
 814                 gic_v3_setup_intr_periph(&pargs);
 815                 gic_v3_bind_intr(dev, isrc);
 816         }
 817
 818         return (0);
 819 }
 820
 821 static int
 822 gic_v3_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
 823     struct resource *res, struct intr_map_data *data)
 824 {
 825         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 826
 827         if (isrc->isrc_handlers == 0 && (gi->gi_flags & GI_FLAG_MSI) == 0) {
 828                 gi->gi_pol = INTR_POLARITY_CONFORM;
 829                 gi->gi_trig = INTR_TRIGGER_CONFORM;
 830         }
 831
 832         return (0);
 833 }
 834
 835 static void
 836 gic_v3_disable_intr(device_t dev, struct intr_irqsrc *isrc)
 837 {
 838         struct gic_v3_softc *sc;
 839         struct gic_v3_irqsrc *gi;
 840         u_int irq;
 841
 842         sc = device_get_softc(dev);
 843         gi = (struct gic_v3_irqsrc *)isrc;
 844         irq = gi->gi_irq;
 845
 846         if (irq <= GIC_LAST_PPI) {
 847                 /* SGIs and PPIs in corresponding Re-Distributor */
 848                 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ICENABLER(irq),
 849                     GICD_I_MASK(irq));
 850                 gic_v3_wait_for_rwp(sc, REDIST);
 851         } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) {
 852                 /* SPIs in distributor */
 853                 gic_d_write(sc, 4, GICD_ICENABLER(irq), GICD_I_MASK(irq));
 854                 gic_v3_wait_for_rwp(sc, DIST);
 855         } else
 856                 panic("%s: Unsupported IRQ %u", __func__, irq);
 857 }
 858
 859 static void
 860 gic_v3_enable_intr_periph(void *argp)
 861 {
 862         struct gic_v3_setup_periph_args *args = argp;
 863         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)args->isrc;
 864         device_t dev = args->dev;
 865         struct gic_v3_softc *sc = device_get_softc(dev);
 866         u_int irq = gi->gi_irq;
 867
 868         /* SGIs and PPIs in corresponding Re-Distributor */
 869         gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ISENABLER(irq),
 870             GICD_I_MASK(irq));
 871         gic_v3_wait_for_rwp(sc, REDIST);
 872 }
 873
 874 static void
 875 gic_v3_enable_intr(device_t dev, struct intr_irqsrc *isrc)
 876 {
 877         struct gic_v3_setup_periph_args pargs;
 878         struct gic_v3_softc *sc;
 879         struct gic_v3_irqsrc *gi;
 880         u_int irq;
 881
 882         gi = (struct gic_v3_irqsrc *)isrc;
 883         irq = gi->gi_irq;
 884         pargs.isrc = isrc;
 885         pargs.dev = dev;
 886
 887         if (irq <= GIC_LAST_PPI) {
 888                 /*
 889                  * SGIs only need configured on the current AP.  We'll setup and
 890                  * enable IPIs as APs come online.
 891                  */
 892                 if (irq <= GIC_LAST_SGI)
 893                         gic_v3_enable_intr_periph(&pargs);
 894                 else
 895                         smp_rendezvous(NULL, gic_v3_enable_intr_periph, NULL,
 896                             &pargs);
 897                 return;
 898         }
 899
 900         sc = device_get_softc(dev);
 901
 902         if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) {
 903                 /* SPIs in distributor */
 904                 gic_d_write(sc, 4, GICD_ISENABLER(irq), GICD_I_MASK(irq));
 905                 gic_v3_wait_for_rwp(sc, DIST);
 906         } else
 907                 panic("%s: Unsupported IRQ %u", __func__, irq);
 908 }
 909
 910 static void
 911 gic_v3_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
 912 {
 913         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 914
 915         gic_v3_disable_intr(dev, isrc);
 916         gic_icc_write(EOIR1, gi->gi_irq);
 917 }
 918
 919 static void
 920 gic_v3_post_ithread(device_t dev, struct intr_irqsrc *isrc)
 921 {
 922
 923         gic_v3_enable_intr(dev, isrc);
 924 }
 925
 926 static void
 927 gic_v3_post_filter(device_t dev, struct intr_irqsrc *isrc)
 928 {
 929         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 930
 931         if (gi->gi_trig == INTR_TRIGGER_EDGE)
 932                 return;
 933
 934         gic_icc_write(EOIR1, gi->gi_irq);
 935 }
 936
 937 static int
 938 gic_v3_bind_intr(device_t dev, struct intr_irqsrc *isrc)
 939 {
 940         struct gic_v3_softc *sc;
 941         struct gic_v3_irqsrc *gi;
 942         int cpu;
 943
 944         gi = (struct gic_v3_irqsrc *)isrc;
 945
 946         KASSERT(gi->gi_irq >= GIC_FIRST_SPI && gi->gi_irq <= GIC_LAST_SPI,
 947             ("%s: Attempting to bind an invalid IRQ", __func__));
 948
 949         sc = device_get_softc(dev);
 950
 951         if (CPU_EMPTY(&isrc->isrc_cpu)) {
 952                 gic_irq_cpu = intr_irq_next_cpu(gic_irq_cpu, &all_cpus);
 953                 CPU_SETOF(gic_irq_cpu, &isrc->isrc_cpu);
 954                 gic_d_write(sc, 8, GICD_IROUTER(gi->gi_irq),
 955                     CPU_AFFINITY(gic_irq_cpu));
 956         } else {
 957                 /*
 958                  * We can only bind to a single CPU so select
 959                  * the first CPU found.
 960                  */
 961                 cpu = CPU_FFS(&isrc->isrc_cpu) - 1;
 962                 gic_d_write(sc, 8, GICD_IROUTER(gi->gi_irq), CPU_AFFINITY(cpu));
 963         }
 964
 965         return (0);
 966 }
 967
 968 #ifdef SMP
 969 static void
 970 gic_v3_init_secondary(device_t dev)
 971 {
 972         struct gic_v3_setup_periph_args pargs;
 973         device_t child;
 974         struct gic_v3_softc *sc;
 975         gic_v3_initseq_t *init_func;
 976         struct intr_irqsrc *isrc;
 977         u_int cpu, irq;
 978         int err, i;
 979
 980         sc = device_get_softc(dev);
 981         cpu = PCPU_GET(cpuid);
 982
 983         /* Train init sequence for boot CPU */
 984         for (init_func = gic_v3_secondary_init; *init_func != NULL;
 985             init_func++) {
 986                 err = (*init_func)(sc);
 987                 if (err != 0) {
 988                         device_printf(dev,
 989                             "Could not initialize GIC for CPU%u\n", cpu);
 990                         return;
 991                 }
 992         }
 993
 994         pargs.dev = dev;
 995
 996         /* Unmask attached SGI interrupts. */
 997         for (irq = GIC_FIRST_SGI; irq <= GIC_LAST_SGI; irq++) {
 998                 isrc = GIC_INTR_ISRC(sc, irq);
 999                 if (intr_isrc_init_on_cpu(isrc, cpu)) {
1000                         pargs.isrc = isrc;
1001                         gic_v3_enable_intr_periph(&pargs);
1002                 }
1003         }
1004
1005         /* Unmask attached PPI interrupts. */
1006         for (irq = GIC_FIRST_PPI; irq <= GIC_LAST_PPI; irq++) {
1007                 isrc = GIC_INTR_ISRC(sc, irq);
1008                 if (intr_isrc_init_on_cpu(isrc, cpu)) {
1009                         pargs.isrc = isrc;
1010                         gic_v3_setup_intr_periph(&pargs);
1011                         gic_v3_enable_intr_periph(&pargs);
1012                 }
1013         }
1014
1015         for (i = 0; i < sc->gic_nchildren; i++) {
1016                 child = sc->gic_children[i];
1017                 PIC_INIT_SECONDARY(child);
1018         }
1019 }
1020
1021 static void
1022 gic_v3_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus,
1023     u_int ipi)
1024 {
1025         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
1026         uint64_t aff, val, irq;
1027         int i;
1028
1029 #define GIC_AFF_MASK    (CPU_AFF3_MASK | CPU_AFF2_MASK | CPU_AFF1_MASK)
1030 #define GIC_AFFINITY(i) (CPU_AFFINITY(i) & GIC_AFF_MASK)
1031         aff = GIC_AFFINITY(0);
1032         irq = gi->gi_irq;
1033         val = 0;
1034
1035         /* Iterate through all CPUs in set */
1036         for (i = 0; i <= mp_maxid; i++) {
1037                 /* Move to the next affinity group */
1038                 if (aff != GIC_AFFINITY(i)) {
1039                         /* Send the IPI */
1040                         if (val != 0) {
1041                                 gic_icc_write(SGI1R, val);
1042                                 val = 0;
1043                         }
1044                         aff = GIC_AFFINITY(i);
1045                 }
1046
1047                 /* Send the IPI to this cpu */
1048                 if (CPU_ISSET(i, &cpus)) {
1049 #define ICC_SGI1R_AFFINITY(aff)                                 \
1050     (((uint64_t)CPU_AFF3(aff) << ICC_SGI1R_EL1_AFF3_SHIFT) |    \
1051      ((uint64_t)CPU_AFF2(aff) << ICC_SGI1R_EL1_AFF2_SHIFT) |    \
1052      ((uint64_t)CPU_AFF1(aff) << ICC_SGI1R_EL1_AFF1_SHIFT))
1053                         /* Set the affinity when the first at this level */
1054                         if (val == 0)
1055                                 val = ICC_SGI1R_AFFINITY(aff) |
1056                                     irq << ICC_SGI1R_EL1_SGIID_SHIFT;
1057                         /* Set the bit to send the IPI to te CPU */
1058                         val |= 1 << CPU_AFF0(CPU_AFFINITY(i));
1059                 }
1060         }
1061
1062         /* Send the IPI to the last cpu affinity group */
1063         if (val != 0)
1064                 gic_icc_write(SGI1R, val);
1065 #undef GIC_AFF_MASK
1066 #undef GIC_AFFINITY
1067 }
1068
1069 static int
1070 gic_v3_ipi_setup(device_t dev, u_int ipi, struct intr_irqsrc **isrcp)
1071 {
1072         struct intr_irqsrc *isrc;
1073         struct gic_v3_softc *sc = device_get_softc(dev);
1074
1075         if (sgi_first_unused > GIC_LAST_SGI)
1076                 return (ENOSPC);
1077
1078         isrc = GIC_INTR_ISRC(sc, sgi_first_unused);
1079         sgi_to_ipi[sgi_first_unused++] = ipi;
1080
1081         CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
1082
1083         *isrcp = isrc;
1084         return (0);
1085 }
1086 #endif /* SMP */
1087
1088 /*
1089  * Helper routines
1090  */
1091 static void
1092 gic_v3_wait_for_rwp(struct gic_v3_softc *sc, enum gic_v3_xdist xdist)
1093 {
1094         struct resource *res;
1095         u_int cpuid;
1096         size_t us_left = 1000000;
1097
1098         cpuid = PCPU_GET(cpuid);
1099
1100         switch (xdist) {
1101         case DIST:
1102                 res = sc->gic_dist;
1103                 break;
1104         case REDIST:
1105                 res = &sc->gic_redists.pcpu[cpuid]->res;
1106                 break;
1107         default:
1108                 KASSERT(0, ("%s: Attempt to wait for unknown RWP", __func__));
1109                 return;
1110         }
1111
1112         while ((bus_read_4(res, GICD_CTLR) & GICD_CTLR_RWP) != 0) {
1113                 DELAY(1);
1114                 if (us_left-- == 0)
1115                         panic("GICD Register write pending for too long");
1116         }
1117 }
1118
1119 /* CPU interface. */
1120 static __inline void
1121 gic_v3_cpu_priority(uint64_t mask)
1122 {
1123
1124         /* Set prority mask */
1125         gic_icc_write(PMR, mask & ICC_PMR_EL1_PRIO_MASK);
1126 }
1127
1128 static int
1129 gic_v3_cpu_enable_sre(struct gic_v3_softc *sc)
1130 {
1131         uint64_t sre;
1132         u_int cpuid;
1133
1134         cpuid = PCPU_GET(cpuid);
1135         /*
1136          * Set the SRE bit to enable access to GIC CPU interface
1137          * via system registers.
1138          */
1139         sre = READ_SPECIALREG(icc_sre_el1);
1140         sre |= ICC_SRE_EL1_SRE;
1141         WRITE_SPECIALREG(icc_sre_el1, sre);
1142         isb();
1143         /*
1144          * Now ensure that the bit is set.
1145          */
1146         sre = READ_SPECIALREG(icc_sre_el1);
1147         if ((sre & ICC_SRE_EL1_SRE) == 0) {
1148                 /* We are done. This was disabled in EL2 */
1149                 device_printf(sc->dev, "ERROR: CPU%u cannot enable CPU interface "
1150                     "via system registers\n", cpuid);
1151                 return (ENXIO);
1152         } else if (bootverbose) {
1153                 device_printf(sc->dev,
1154                     "CPU%u enabled CPU interface via system registers\n",
1155                     cpuid);
1156         }
1157
1158         return (0);
1159 }
1160
1161 static int
1162 gic_v3_cpu_init(struct gic_v3_softc *sc)
1163 {
1164         int err;
1165
1166         /* Enable access to CPU interface via system registers */
1167         err = gic_v3_cpu_enable_sre(sc);
1168         if (err != 0)
1169                 return (err);
1170         /* Priority mask to minimum - accept all interrupts */
1171         gic_v3_cpu_priority(GIC_PRIORITY_MIN);
1172         /* Disable EOI mode */
1173         gic_icc_clear(CTLR, ICC_CTLR_EL1_EOIMODE);
1174         /* Enable group 1 (insecure) interrups */
1175         gic_icc_set(IGRPEN1, ICC_IGRPEN0_EL1_EN);
1176
1177         return (0);
1178 }
1179
1180 /* Distributor */
1181 static int
1182 gic_v3_dist_init(struct gic_v3_softc *sc)
1183 {
1184         uint64_t aff;
1185         u_int i;
1186
1187         /*
1188          * 1. Disable the Distributor
1189          */
1190         gic_d_write(sc, 4, GICD_CTLR, 0);
1191         gic_v3_wait_for_rwp(sc, DIST);
1192
1193         /*
1194          * 2. Configure the Distributor
1195          */
1196         /* Set all SPIs to be Group 1 Non-secure */
1197         for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_IGROUPRn)
1198                 gic_d_write(sc, 4, GICD_IGROUPR(i), 0xFFFFFFFF);
1199
1200         /* Set all global interrupts to be level triggered, active low. */
1201         for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ICFGRn)
1202                 gic_d_write(sc, 4, GICD_ICFGR(i), 0x00000000);
1203
1204         /* Set priority to all shared interrupts */
1205         for (i = GIC_FIRST_SPI;
1206             i < sc->gic_nirqs; i += GICD_I_PER_IPRIORITYn) {
1207                 /* Set highest priority */
1208                 gic_d_write(sc, 4, GICD_IPRIORITYR(i), GIC_PRIORITY_MAX);
1209         }
1210
1211         /*
1212          * Disable all interrupts. Leave PPI and SGIs as they are enabled in
1213          * Re-Distributor registers.
1214          */
1215         for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ISENABLERn)
1216                 gic_d_write(sc, 4, GICD_ICENABLER(i), 0xFFFFFFFF);
1217
1218         gic_v3_wait_for_rwp(sc, DIST);
1219
1220         /*
1221          * 3. Enable Distributor
1222          */
1223         /* Enable Distributor with ARE, Group 1 */
1224         gic_d_write(sc, 4, GICD_CTLR, GICD_CTLR_ARE_NS | GICD_CTLR_G1A |
1225             GICD_CTLR_G1);
1226
1227         /*
1228          * 4. Route all interrupts to boot CPU.
1229          */
1230         aff = CPU_AFFINITY(0);
1231         for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i++)
1232                 gic_d_write(sc, 8, GICD_IROUTER(i), aff);
1233
1234         return (0);
1235 }
1236
1237 /* Re-Distributor */
1238 static int
1239 gic_v3_redist_alloc(struct gic_v3_softc *sc)
1240 {
1241         u_int cpuid;
1242
1243         /* Allocate struct resource for all CPU's Re-Distributor registers */
1244         for (cpuid = 0; cpuid <= mp_maxid; cpuid++)
1245                 if (CPU_ISSET(cpuid, &all_cpus) != 0)
1246                         sc->gic_redists.pcpu[cpuid] =
1247                                 malloc(sizeof(*sc->gic_redists.pcpu[0]),
1248                                     M_GIC_V3, M_WAITOK);
1249                 else
1250                         sc->gic_redists.pcpu[cpuid] = NULL;
1251         return (0);
1252 }
1253
1254 static int
1255 gic_v3_redist_find(struct gic_v3_softc *sc)
1256 {
1257         struct resource r_res;
1258         bus_space_handle_t r_bsh;
1259         uint64_t aff;
1260         uint64_t typer;
1261         uint32_t pidr2;
1262         u_int cpuid;
1263         size_t i;
1264
1265         cpuid = PCPU_GET(cpuid);
1266
1267         aff = CPU_AFFINITY(cpuid);
1268         /* Affinity in format for comparison with typer */
1269         aff = (CPU_AFF3(aff) << 24) | (CPU_AFF2(aff) << 16) |
1270             (CPU_AFF1(aff) << 8) | CPU_AFF0(aff);
1271
1272         if (bootverbose) {
1273                 device_printf(sc->dev,
1274                     "Start searching for Re-Distributor\n");
1275         }
1276         /* Iterate through Re-Distributor regions */
1277         for (i = 0; i < sc->gic_redists.nregions; i++) {
1278                 /* Take a copy of the region's resource */
1279                 r_res = *sc->gic_redists.regions[i];
1280                 r_bsh = rman_get_bushandle(&r_res);
1281
1282                 pidr2 = bus_read_4(&r_res, GICR_PIDR2);
1283                 switch (GICR_PIDR2_ARCH(pidr2)) {
1284                 case GICR_PIDR2_ARCH_GICv3: /* fall through */
1285                 case GICR_PIDR2_ARCH_GICv4:
1286                         break;
1287                 default:
1288                         device_printf(sc->dev,
1289                             "No Re-Distributor found for CPU%u\n", cpuid);
1290                         return (ENODEV);
1291                 }
1292
1293                 do {
1294                         typer = bus_read_8(&r_res, GICR_TYPER);
1295                         if ((typer >> GICR_TYPER_AFF_SHIFT) == aff) {
1296                                 KASSERT(sc->gic_redists.pcpu[cpuid] != NULL,
1297                                     ("Invalid pointer to per-CPU redistributor"));
1298                                 /* Copy res contents to its final destination */
1299                                 sc->gic_redists.pcpu[cpuid]->res = r_res;
1300                                 sc->gic_redists.pcpu[cpuid]->lpi_enabled = false;
1301                                 if (bootverbose) {
1302                                         device_printf(sc->dev,
1303                                             "CPU%u Re-Distributor has been found\n",
1304                                             cpuid);
1305                                 }
1306                                 return (0);
1307                         }
1308
1309                         r_bsh += (GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);
1310                         if ((typer & GICR_TYPER_VLPIS) != 0) {
1311                                 r_bsh +=
1312                                     (GICR_VLPI_BASE_SIZE + GICR_RESERVED_SIZE);
1313                         }
1314
1315                         rman_set_bushandle(&r_res, r_bsh);
1316                 } while ((typer & GICR_TYPER_LAST) == 0);
1317         }
1318
1319         device_printf(sc->dev, "No Re-Distributor found for CPU%u\n", cpuid);
1320         return (ENXIO);
1321 }
1322
1323 static int
1324 gic_v3_redist_wake(struct gic_v3_softc *sc)
1325 {
1326         uint32_t waker;
1327         size_t us_left = 1000000;
1328
1329         waker = gic_r_read(sc, 4, GICR_WAKER);
1330         /* Wake up Re-Distributor for this CPU */
1331         waker &= ~GICR_WAKER_PS;
1332         gic_r_write(sc, 4, GICR_WAKER, waker);
1333         /*
1334          * When clearing ProcessorSleep bit it is required to wait for
1335          * ChildrenAsleep to become zero following the processor power-on.
1336          */
1337         while ((gic_r_read(sc, 4, GICR_WAKER) & GICR_WAKER_CA) != 0) {
1338                 DELAY(1);
1339                 if (us_left-- == 0) {
1340                         panic("Could not wake Re-Distributor for CPU%u",
1341                             PCPU_GET(cpuid));
1342                 }
1343         }
1344
1345         if (bootverbose) {
1346                 device_printf(sc->dev, "CPU%u Re-Distributor woke up\n",
1347                     PCPU_GET(cpuid));
1348         }
1349
1350         return (0);
1351 }
1352
1353 static int
1354 gic_v3_redist_init(struct gic_v3_softc *sc)
1355 {
1356         int err;
1357         size_t i;
1358
1359         err = gic_v3_redist_find(sc);
1360         if (err != 0)
1361                 return (err);
1362
1363         err = gic_v3_redist_wake(sc);
1364         if (err != 0)
1365                 return (err);
1366
1367         /* Configure SGIs and PPIs to be Group1 Non-secure */
1368         gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_IGROUPR0,
1369             0xFFFFFFFF);
1370
1371         /* Disable SPIs */
1372         gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ICENABLER0,
1373             GICR_I_ENABLER_PPI_MASK);
1374         /* Enable SGIs */
1375         gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ISENABLER0,
1376             GICR_I_ENABLER_SGI_MASK);
1377
1378         /* Set priority for SGIs and PPIs */
1379         for (i = 0; i <= GIC_LAST_PPI; i += GICR_I_PER_IPRIORITYn) {
1380                 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_IPRIORITYR(i),
1381                     GIC_PRIORITY_MAX);
1382         }
1383
1384         gic_v3_wait_for_rwp(sc, REDIST);
1385
1386         return (0);
1387 }
1388
1389 /*
1390  * SPI-mapped Message Based Interrupts -- a GICv3 MSI/MSI-X controller.
1391  */
1392
1393 static int
1394 gic_v3_alloc_msi(device_t dev, device_t child, int count, int maxcount,
1395     device_t *pic, struct intr_irqsrc **srcs)
1396 {
1397         struct gic_v3_softc *sc;
1398         int i, irq, end_irq;
1399         bool found;
1400
1401         KASSERT(powerof2(count), ("%s: bad count", __func__));
1402         KASSERT(powerof2(maxcount), ("%s: bad maxcount", __func__));
1403
1404         sc = device_get_softc(dev);
1405
1406         mtx_lock(&sc->gic_mbi_mtx);
1407
1408         found = false;
1409         for (irq = sc->gic_mbi_start; irq < sc->gic_mbi_end; irq++) {
1410                 /* Start on an aligned interrupt */
1411                 if ((irq & (maxcount - 1)) != 0)
1412                         continue;
1413
1414                 /* Assume we found a valid range until shown otherwise */
1415                 found = true;
1416
1417                 /* Check this range is valid */
1418                 for (end_irq = irq; end_irq != irq + count; end_irq++) {
1419                         /* No free interrupts */
1420                         if (end_irq == sc->gic_mbi_end) {
1421                                 found = false;
1422                                 break;
1423                         }
1424
1425                         KASSERT((sc->gic_irqs[end_irq].gi_flags & GI_FLAG_MSI)!= 0,
1426                             ("%s: Non-MSI interrupt found", __func__));
1427
1428                         /* This is already used */
1429                         if ((sc->gic_irqs[end_irq].gi_flags & GI_FLAG_MSI_USED) ==
1430                             GI_FLAG_MSI_USED) {
1431                                 found = false;
1432                                 break;
1433                         }
1434                 }
1435                 if (found)
1436                         break;
1437         }
1438
1439         /* Not enough interrupts were found */
1440         if (!found || irq == sc->gic_mbi_end) {
1441                 mtx_unlock(&sc->gic_mbi_mtx);
1442                 return (ENXIO);
1443         }
1444
1445         for (i = 0; i < count; i++) {
1446                 /* Mark the interrupt as used */
1447                 sc->gic_irqs[irq + i].gi_flags |= GI_FLAG_MSI_USED;
1448         }
1449         mtx_unlock(&sc->gic_mbi_mtx);
1450
1451         for (i = 0; i < count; i++)
1452                 srcs[i] = (struct intr_irqsrc *)&sc->gic_irqs[irq + i];
1453         *pic = dev;
1454
1455         return (0);
1456 }
1457
1458 static int
1459 gic_v3_release_msi(device_t dev, device_t child, int count,
1460     struct intr_irqsrc **isrc)
1461 {
1462         struct gic_v3_softc *sc;
1463         struct gic_v3_irqsrc *gi;
1464         int i;
1465
1466         sc = device_get_softc(dev);
1467
1468         mtx_lock(&sc->gic_mbi_mtx);
1469         for (i = 0; i < count; i++) {
1470                 gi = (struct gic_v3_irqsrc *)isrc[i];
1471
1472                 KASSERT((gi->gi_flags & GI_FLAG_MSI_USED) == GI_FLAG_MSI_USED,
1473                     ("%s: Trying to release an unused MSI-X interrupt",
1474                     __func__));
1475
1476                 gi->gi_flags &= ~GI_FLAG_MSI_USED;
1477         }
1478         mtx_unlock(&sc->gic_mbi_mtx);
1479
1480         return (0);
1481 }
1482
1483 static int
1484 gic_v3_alloc_msix(device_t dev, device_t child, device_t *pic,
1485     struct intr_irqsrc **isrcp)
1486 {
1487         struct gic_v3_softc *sc;
1488         int irq;
1489
1490         sc = device_get_softc(dev);
1491
1492         mtx_lock(&sc->gic_mbi_mtx);
1493         /* Find an unused interrupt */
1494         for (irq = sc->gic_mbi_start; irq < sc->gic_mbi_end; irq++) {
1495                 KASSERT((sc->gic_irqs[irq].gi_flags & GI_FLAG_MSI) != 0,
1496                     ("%s: Non-MSI interrupt found", __func__));
1497                 if ((sc->gic_irqs[irq].gi_flags & GI_FLAG_MSI_USED) == 0)
1498                         break;
1499         }
1500         /* No free interrupt was found */
1501         if (irq == sc->gic_mbi_end) {
1502                 mtx_unlock(&sc->gic_mbi_mtx);
1503                 return (ENXIO);
1504         }
1505
1506         /* Mark the interrupt as used */
1507         sc->gic_irqs[irq].gi_flags |= GI_FLAG_MSI_USED;
1508         mtx_unlock(&sc->gic_mbi_mtx);
1509
1510         *isrcp = (struct intr_irqsrc *)&sc->gic_irqs[irq];
1511         *pic = dev;
1512
1513         return (0);
1514 }
1515
1516 static int
1517 gic_v3_release_msix(device_t dev, device_t child, struct intr_irqsrc *isrc)
1518 {
1519         struct gic_v3_softc *sc;
1520         struct gic_v3_irqsrc *gi;
1521
1522         sc = device_get_softc(dev);
1523         gi = (struct gic_v3_irqsrc *)isrc;
1524
1525         KASSERT((gi->gi_flags & GI_FLAG_MSI_USED) == GI_FLAG_MSI_USED,
1526             ("%s: Trying to release an unused MSI-X interrupt", __func__));
1527
1528         mtx_lock(&sc->gic_mbi_mtx);
1529         gi->gi_flags &= ~GI_FLAG_MSI_USED;
1530         mtx_unlock(&sc->gic_mbi_mtx);
1531
1532         return (0);
1533 }
1534
1535 static int
1536 gic_v3_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc,
1537     uint64_t *addr, uint32_t *data)
1538 {
1539         struct gic_v3_softc *sc = device_get_softc(dev);
1540         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
1541
1542         *addr = vtophys(rman_get_virtual(sc->gic_dist)) + GICD_SETSPI_NSR;
1543         *data = gi->gi_irq;
1544
1545         return (0);
1546 }