sys/arm64/arm64/gic_v3.c

   1 /*-
   2  * Copyright (c) 2015-2016 The FreeBSD Foundation
   3  * All rights reserved.
   4  *
   5  * This software was developed by Andrew Turner under
   6  * the sponsorship of the FreeBSD Foundation.
   7  *
   8  * This software was developed by Semihalf under
   9  * the sponsorship of the FreeBSD Foundation.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  */
  32
  33 #include "opt_platform.h"
  34
  35 #include <sys/cdefs.h>
  36 __FBSDID("$FreeBSD$");
  37
  38 #include <sys/param.h>
  39 #include <sys/systm.h>
  40 #include <sys/bitstring.h>
  41 #include <sys/bus.h>
  42 #include <sys/kernel.h>
  43 #include <sys/ktr.h>
  44 #include <sys/malloc.h>
  45 #include <sys/module.h>
  46 #include <sys/rman.h>
  47 #include <sys/pcpu.h>
  48 #include <sys/proc.h>
  49 #include <sys/cpuset.h>
  50 #include <sys/lock.h>
  51 #include <sys/mutex.h>
  52 #include <sys/smp.h>
  53
  54 #include <vm/vm.h>
  55 #include <vm/pmap.h>
  56
  57 #include <machine/bus.h>
  58 #include <machine/cpu.h>
  59 #include <machine/intr.h>
  60
  61 #ifdef FDT
  62 #include <dev/fdt/fdt_intr.h>
  63 #include <dev/ofw/ofw_bus_subr.h>
  64 #endif
  65
  66 #include "pic_if.h"
  67
  68 #include <arm/arm/gic_common.h>
  69 #include "gic_v3_reg.h"
  70 #include "gic_v3_var.h"
  71
  72 static bus_get_domain_t gic_v3_get_domain;
  73 static bus_read_ivar_t gic_v3_read_ivar;
  74
  75 static pic_disable_intr_t gic_v3_disable_intr;
  76 static pic_enable_intr_t gic_v3_enable_intr;
  77 static pic_map_intr_t gic_v3_map_intr;
  78 static pic_setup_intr_t gic_v3_setup_intr;
  79 static pic_teardown_intr_t gic_v3_teardown_intr;
  80 static pic_post_filter_t gic_v3_post_filter;
  81 static pic_post_ithread_t gic_v3_post_ithread;
  82 static pic_pre_ithread_t gic_v3_pre_ithread;
  83 static pic_bind_intr_t gic_v3_bind_intr;
  84 #ifdef SMP
  85 static pic_init_secondary_t gic_v3_init_secondary;
  86 static pic_ipi_send_t gic_v3_ipi_send;
  87 static pic_ipi_setup_t gic_v3_ipi_setup;
  88 #endif
  89
  90 static u_int gic_irq_cpu;
  91 #ifdef SMP
  92 static u_int sgi_to_ipi[GIC_LAST_SGI - GIC_FIRST_SGI + 1];
  93 static u_int sgi_first_unused = GIC_FIRST_SGI;
  94 #endif
  95
  96 static device_method_t gic_v3_methods[] = {
  97         /* Device interface */
  98         DEVMETHOD(device_detach,        gic_v3_detach),
  99
 100         /* Bus interface */
 101         DEVMETHOD(bus_get_domain,       gic_v3_get_domain),
 102         DEVMETHOD(bus_read_ivar,        gic_v3_read_ivar),
 103
 104         /* Interrupt controller interface */
 105         DEVMETHOD(pic_disable_intr,     gic_v3_disable_intr),
 106         DEVMETHOD(pic_enable_intr,      gic_v3_enable_intr),
 107         DEVMETHOD(pic_map_intr,         gic_v3_map_intr),
 108         DEVMETHOD(pic_setup_intr,       gic_v3_setup_intr),
 109         DEVMETHOD(pic_teardown_intr,    gic_v3_teardown_intr),
 110         DEVMETHOD(pic_post_filter,      gic_v3_post_filter),
 111         DEVMETHOD(pic_post_ithread,     gic_v3_post_ithread),
 112         DEVMETHOD(pic_pre_ithread,      gic_v3_pre_ithread),
 113 #ifdef SMP
 114         DEVMETHOD(pic_bind_intr,        gic_v3_bind_intr),
 115         DEVMETHOD(pic_init_secondary,   gic_v3_init_secondary),
 116         DEVMETHOD(pic_ipi_send,         gic_v3_ipi_send),
 117         DEVMETHOD(pic_ipi_setup,        gic_v3_ipi_setup),
 118 #endif
 119
 120         /* End */
 121         DEVMETHOD_END
 122 };
 123
 124 DEFINE_CLASS_0(gic, gic_v3_driver, gic_v3_methods,
 125     sizeof(struct gic_v3_softc));
 126
 127 /*
 128  * Driver-specific definitions.
 129  */
 130 MALLOC_DEFINE(M_GIC_V3, "GICv3", GIC_V3_DEVSTR);
 131
 132 /*
 133  * Helper functions and definitions.
 134  */
 135 /* Destination registers, either Distributor or Re-Distributor */
 136 enum gic_v3_xdist {
 137         DIST = 0,
 138         REDIST,
 139 };
 140
 141 struct gic_v3_irqsrc {
 142         struct intr_irqsrc      gi_isrc;
 143         uint32_t                gi_irq;
 144         enum intr_polarity      gi_pol;
 145         enum intr_trigger       gi_trig;
 146 };
 147
 148 /* Helper routines starting with gic_v3_ */
 149 static int gic_v3_dist_init(struct gic_v3_softc *);
 150 static int gic_v3_redist_alloc(struct gic_v3_softc *);
 151 static int gic_v3_redist_find(struct gic_v3_softc *);
 152 static int gic_v3_redist_init(struct gic_v3_softc *);
 153 static int gic_v3_cpu_init(struct gic_v3_softc *);
 154 static void gic_v3_wait_for_rwp(struct gic_v3_softc *, enum gic_v3_xdist);
 155
 156 /* A sequence of init functions for primary (boot) CPU */
 157 typedef int (*gic_v3_initseq_t) (struct gic_v3_softc *);
 158 /* Primary CPU initialization sequence */
 159 static gic_v3_initseq_t gic_v3_primary_init[] = {
 160         gic_v3_dist_init,
 161         gic_v3_redist_alloc,
 162         gic_v3_redist_init,
 163         gic_v3_cpu_init,
 164         NULL
 165 };
 166
 167 #ifdef SMP
 168 /* Secondary CPU initialization sequence */
 169 static gic_v3_initseq_t gic_v3_secondary_init[] = {
 170         gic_v3_redist_init,
 171         gic_v3_cpu_init,
 172         NULL
 173 };
 174 #endif
 175
 176 uint32_t
 177 gic_r_read_4(device_t dev, bus_size_t offset)
 178 {
 179         struct gic_v3_softc *sc;
 180
 181         sc = device_get_softc(dev);
 182         return (bus_read_4(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset));
 183 }
 184
 185 uint64_t
 186 gic_r_read_8(device_t dev, bus_size_t offset)
 187 {
 188         struct gic_v3_softc *sc;
 189
 190         sc = device_get_softc(dev);
 191         return (bus_read_8(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset));
 192 }
 193
 194 void
 195 gic_r_write_4(device_t dev, bus_size_t offset, uint32_t val)
 196 {
 197         struct gic_v3_softc *sc;
 198
 199         sc = device_get_softc(dev);
 200         bus_write_4(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset, val);
 201 }
 202
 203 void
 204 gic_r_write_8(device_t dev, bus_size_t offset, uint64_t val)
 205 {
 206         struct gic_v3_softc *sc;
 207
 208         sc = device_get_softc(dev);
 209         bus_write_8(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset, val);
 210 }
 211
 212 /*
 213  * Device interface.
 214  */
 215 int
 216 gic_v3_attach(device_t dev)
 217 {
 218         struct gic_v3_softc *sc;
 219         gic_v3_initseq_t *init_func;
 220         uint32_t typer;
 221         int rid;
 222         int err;
 223         size_t i;
 224         u_int irq;
 225         const char *name;
 226
 227         sc = device_get_softc(dev);
 228         sc->gic_registered = FALSE;
 229         sc->dev = dev;
 230         err = 0;
 231
 232         /* Initialize mutex */
 233         mtx_init(&sc->gic_mtx, "GICv3 lock", NULL, MTX_SPIN);
 234
 235         /*
 236          * Allocate array of struct resource.
 237          * One entry for Distributor and all remaining for Re-Distributor.
 238          */
 239         sc->gic_res = malloc(
 240             sizeof(*sc->gic_res) * (sc->gic_redists.nregions + 1),
 241             M_GIC_V3, M_WAITOK);
 242
 243         /* Now allocate corresponding resources */
 244         for (i = 0, rid = 0; i < (sc->gic_redists.nregions + 1); i++, rid++) {
 245                 sc->gic_res[rid] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 246                     &rid, RF_ACTIVE);
 247                 if (sc->gic_res[rid] == NULL)
 248                         return (ENXIO);
 249         }
 250
 251         /*
 252          * Distributor interface
 253          */
 254         sc->gic_dist = sc->gic_res[0];
 255
 256         /*
 257          * Re-Dristributor interface
 258          */
 259         /* Allocate space under region descriptions */
 260         sc->gic_redists.regions = malloc(
 261             sizeof(*sc->gic_redists.regions) * sc->gic_redists.nregions,
 262             M_GIC_V3, M_WAITOK);
 263
 264         /* Fill-up bus_space information for each region. */
 265         for (i = 0, rid = 1; i < sc->gic_redists.nregions; i++, rid++)
 266                 sc->gic_redists.regions[i] = sc->gic_res[rid];
 267
 268         /* Get the number of supported SPI interrupts */
 269         typer = gic_d_read(sc, 4, GICD_TYPER);
 270         sc->gic_nirqs = GICD_TYPER_I_NUM(typer);
 271         if (sc->gic_nirqs > GIC_I_NUM_MAX)
 272                 sc->gic_nirqs = GIC_I_NUM_MAX;
 273
 274         sc->gic_irqs = malloc(sizeof(*sc->gic_irqs) * sc->gic_nirqs,
 275             M_GIC_V3, M_WAITOK | M_ZERO);
 276         name = device_get_nameunit(dev);
 277         for (irq = 0; irq < sc->gic_nirqs; irq++) {
 278                 struct intr_irqsrc *isrc;
 279
 280                 sc->gic_irqs[irq].gi_irq = irq;
 281                 sc->gic_irqs[irq].gi_pol = INTR_POLARITY_CONFORM;
 282                 sc->gic_irqs[irq].gi_trig = INTR_TRIGGER_CONFORM;
 283
 284                 isrc = &sc->gic_irqs[irq].gi_isrc;
 285                 if (irq <= GIC_LAST_SGI) {
 286                         err = intr_isrc_register(isrc, sc->dev,
 287                             INTR_ISRCF_IPI, "%s,i%u", name, irq - GIC_FIRST_SGI);
 288                 } else if (irq <= GIC_LAST_PPI) {
 289                         err = intr_isrc_register(isrc, sc->dev,
 290                             INTR_ISRCF_PPI, "%s,p%u", name, irq - GIC_FIRST_PPI);
 291                 } else {
 292                         err = intr_isrc_register(isrc, sc->dev, 0,
 293                             "%s,s%u", name, irq - GIC_FIRST_SPI);
 294                 }
 295                 if (err != 0) {
 296                         /* XXX call intr_isrc_deregister() */
 297                         free(sc->gic_irqs, M_DEVBUF);
 298                         return (err);
 299                 }
 300         }
 301
 302         /*
 303          * Read the Peripheral ID2 register. This is an implementation
 304          * defined register, but seems to be implemented in all GICv3
 305          * parts and Linux expects it to be there.
 306          */
 307         sc->gic_pidr2 = gic_d_read(sc, 4, GICD_PIDR2);
 308
 309         /* Get the number of supported interrupt identifier bits */
 310         sc->gic_idbits = GICD_TYPER_IDBITS(typer);
 311
 312         if (bootverbose) {
 313                 device_printf(dev, "SPIs: %u, IDs: %u\n",
 314                     sc->gic_nirqs, (1 << sc->gic_idbits) - 1);
 315         }
 316
 317         /* Train init sequence for boot CPU */
 318         for (init_func = gic_v3_primary_init; *init_func != NULL; init_func++) {
 319                 err = (*init_func)(sc);
 320                 if (err != 0)
 321                         return (err);
 322         }
 323
 324         return (0);
 325 }
 326
 327 int
 328 gic_v3_detach(device_t dev)
 329 {
 330         struct gic_v3_softc *sc;
 331         size_t i;
 332         int rid;
 333
 334         sc = device_get_softc(dev);
 335
 336         if (device_is_attached(dev)) {
 337                 /*
 338                  * XXX: We should probably deregister PIC
 339                  */
 340                 if (sc->gic_registered)
 341                         panic("Trying to detach registered PIC");
 342         }
 343         for (rid = 0; rid < (sc->gic_redists.nregions + 1); rid++)
 344                 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->gic_res[rid]);
 345
 346         for (i = 0; i <= mp_maxid; i++)
 347                 free(sc->gic_redists.pcpu[i], M_GIC_V3);
 348
 349         free(sc->gic_res, M_GIC_V3);
 350         free(sc->gic_redists.regions, M_GIC_V3);
 351
 352         return (0);
 353 }
 354
 355 static int
 356 gic_v3_get_domain(device_t dev, device_t child, int *domain)
 357 {
 358         struct gic_v3_devinfo *di;
 359
 360         di = device_get_ivars(child);
 361         if (di->gic_domain < 0)
 362                 return (ENOENT);
 363
 364         *domain = di->gic_domain;
 365         return (0);
 366 }
 367
 368 static int
 369 gic_v3_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
 370 {
 371         struct gic_v3_softc *sc;
 372
 373         sc = device_get_softc(dev);
 374
 375         switch (which) {
 376         case GICV3_IVAR_NIRQS:
 377                 *result = (NIRQ - sc->gic_nirqs) / sc->gic_nchildren;
 378                 return (0);
 379         case GICV3_IVAR_REDIST_VADDR:
 380                 *result = (uintptr_t)rman_get_virtual(
 381                     sc->gic_redists.pcpu[PCPU_GET(cpuid)]);
 382                 return (0);
 383         case GIC_IVAR_HW_REV:
 384                 KASSERT(
 385                     GICR_PIDR2_ARCH(sc->gic_pidr2) == GICR_PIDR2_ARCH_GICv3 ||
 386                     GICR_PIDR2_ARCH(sc->gic_pidr2) == GICR_PIDR2_ARCH_GICv4,
 387                     ("gic_v3_read_ivar: Invalid GIC architecture: %d (%.08X)",
 388                      GICR_PIDR2_ARCH(sc->gic_pidr2), sc->gic_pidr2));
 389                 *result = GICR_PIDR2_ARCH(sc->gic_pidr2);
 390                 return (0);
 391         case GIC_IVAR_BUS:
 392                 KASSERT(sc->gic_bus != GIC_BUS_UNKNOWN,
 393                     ("gic_v3_read_ivar: Unknown bus type"));
 394                 KASSERT(sc->gic_bus <= GIC_BUS_MAX,
 395                     ("gic_v3_read_ivar: Invalid bus type %u", sc->gic_bus));
 396                 *result = sc->gic_bus;
 397                 return (0);
 398         }
 399
 400         return (ENOENT);
 401 }
 402
 403 int
 404 arm_gic_v3_intr(void *arg)
 405 {
 406         struct gic_v3_softc *sc = arg;
 407         struct gic_v3_irqsrc *gi;
 408         struct intr_pic *pic;
 409         uint64_t active_irq;
 410         struct trapframe *tf;
 411
 412         pic = sc->gic_pic;
 413
 414         while (1) {
 415                 if (CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1) {
 416                         /*
 417                          * Hardware:            Cavium ThunderX
 418                          * Chip revision:       Pass 1.0 (early version)
 419                          *                      Pass 1.1 (production)
 420                          * ERRATUM:             22978, 23154
 421                          */
 422                         __asm __volatile(
 423                             "nop;nop;nop;nop;nop;nop;nop;nop;   \n"
 424                             "mrs %0, ICC_IAR1_EL1               \n"
 425                             "nop;nop;nop;nop;                   \n"
 426                             "dsb sy                             \n"
 427                             : "=&r" (active_irq));
 428                 } else {
 429                         active_irq = gic_icc_read(IAR1);
 430                 }
 431
 432                 if (active_irq >= GIC_FIRST_LPI) {
 433                         intr_child_irq_handler(pic, active_irq);
 434                         continue;
 435                 }
 436
 437                 if (__predict_false(active_irq >= sc->gic_nirqs))
 438                         return (FILTER_HANDLED);
 439
 440                 tf = curthread->td_intr_frame;
 441                 gi = &sc->gic_irqs[active_irq];
 442                 if (active_irq <= GIC_LAST_SGI) {
 443                         /* Call EOI for all IPI before dispatch. */
 444                         gic_icc_write(EOIR1, (uint64_t)active_irq);
 445 #ifdef SMP
 446                         intr_ipi_dispatch(sgi_to_ipi[gi->gi_irq], tf);
 447 #else
 448                         device_printf(sc->dev, "SGI %ju on UP system detected\n",
 449                             (uintmax_t)(active_irq - GIC_FIRST_SGI));
 450 #endif
 451                 } else if (active_irq >= GIC_FIRST_PPI &&
 452                     active_irq <= GIC_LAST_SPI) {
 453                         if (gi->gi_trig == INTR_TRIGGER_EDGE)
 454                                 gic_icc_write(EOIR1, gi->gi_irq);
 455
 456                         if (intr_isrc_dispatch(&gi->gi_isrc, tf) != 0) {
 457                                 if (gi->gi_trig != INTR_TRIGGER_EDGE)
 458                                         gic_icc_write(EOIR1, gi->gi_irq);
 459                                 gic_v3_disable_intr(sc->dev, &gi->gi_isrc);
 460                                 device_printf(sc->dev,
 461                                     "Stray irq %lu disabled\n", active_irq);
 462                         }
 463                 }
 464         }
 465 }
 466
 467 #ifdef FDT
 468 static int
 469 gic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp,
 470     enum intr_polarity *polp, enum intr_trigger *trigp)
 471 {
 472         u_int irq;
 473
 474         if (ncells < 3)
 475                 return (EINVAL);
 476
 477         /*
 478          * The 1st cell is the interrupt type:
 479          *      0 = SPI
 480          *      1 = PPI
 481          * The 2nd cell contains the interrupt number:
 482          *      [0 - 987] for SPI
 483          *      [0 -  15] for PPI
 484          * The 3rd cell is the flags, encoded as follows:
 485          *   bits[3:0] trigger type and level flags
 486          *      1 = edge triggered
 487          *      2 = edge triggered (PPI only)
 488          *      4 = level-sensitive
 489          *      8 = level-sensitive (PPI only)
 490          */
 491         switch (cells[0]) {
 492         case 0:
 493                 irq = GIC_FIRST_SPI + cells[1];
 494                 /* SPI irq is checked later. */
 495                 break;
 496         case 1:
 497                 irq = GIC_FIRST_PPI + cells[1];
 498                 if (irq > GIC_LAST_PPI) {
 499                         device_printf(dev, "unsupported PPI interrupt "
 500                             "number %u\n", cells[1]);
 501                         return (EINVAL);
 502                 }
 503                 break;
 504         default:
 505                 device_printf(dev, "unsupported interrupt type "
 506                     "configuration %u\n", cells[0]);
 507                 return (EINVAL);
 508         }
 509
 510         switch (cells[2] & FDT_INTR_MASK) {
 511         case FDT_INTR_EDGE_RISING:
 512                 *trigp = INTR_TRIGGER_EDGE;
 513                 *polp = INTR_POLARITY_HIGH;
 514                 break;
 515         case FDT_INTR_EDGE_FALLING:
 516                 *trigp = INTR_TRIGGER_EDGE;
 517                 *polp = INTR_POLARITY_LOW;
 518                 break;
 519         case FDT_INTR_LEVEL_HIGH:
 520                 *trigp = INTR_TRIGGER_LEVEL;
 521                 *polp = INTR_POLARITY_HIGH;
 522                 break;
 523         case FDT_INTR_LEVEL_LOW:
 524                 *trigp = INTR_TRIGGER_LEVEL;
 525                 *polp = INTR_POLARITY_LOW;
 526                 break;
 527         default:
 528                 device_printf(dev, "unsupported trigger/polarity "
 529                     "configuration 0x%02x\n", cells[2]);
 530                 return (EINVAL);
 531         }
 532
 533         /* Check the interrupt is valid */
 534         if (irq >= GIC_FIRST_SPI && *polp != INTR_POLARITY_HIGH)
 535                 return (EINVAL);
 536
 537         *irqp = irq;
 538         return (0);
 539 }
 540 #endif
 541
 542 static int
 543 gic_map_msi(device_t dev, struct intr_map_data_msi *msi_data, u_int *irqp,
 544     enum intr_polarity *polp, enum intr_trigger *trigp)
 545 {
 546         struct gic_v3_irqsrc *gi;
 547
 548         /* SPI-mapped MSI */
 549         gi = (struct gic_v3_irqsrc *)msi_data->isrc;
 550         if (gi == NULL)
 551                 return (ENXIO);
 552
 553         *irqp = gi->gi_irq;
 554
 555         /* MSI/MSI-X interrupts are always edge triggered with high polarity */
 556         *polp = INTR_POLARITY_HIGH;
 557         *trigp = INTR_TRIGGER_EDGE;
 558
 559         return (0);
 560 }
 561
 562 static int
 563 do_gic_v3_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp,
 564     enum intr_polarity *polp, enum intr_trigger *trigp)
 565 {
 566         struct gic_v3_softc *sc;
 567         enum intr_polarity pol;
 568         enum intr_trigger trig;
 569         struct intr_map_data_msi *dam;
 570 #ifdef FDT
 571         struct intr_map_data_fdt *daf;
 572 #endif
 573         u_int irq;
 574
 575         sc = device_get_softc(dev);
 576
 577         switch (data->type) {
 578 #ifdef FDT
 579         case INTR_MAP_DATA_FDT:
 580                 daf = (struct intr_map_data_fdt *)data;
 581                 if (gic_map_fdt(dev, daf->ncells, daf->cells, &irq, &pol,
 582                     &trig) != 0)
 583                         return (EINVAL);
 584                 break;
 585 #endif
 586         case INTR_MAP_DATA_MSI:
 587                 /* SPI-mapped MSI */
 588                 dam = (struct intr_map_data_msi *)data;
 589                 if (gic_map_msi(dev, dam, &irq, &pol, &trig) != 0)
 590                         return (EINVAL);
 591                 break;
 592         default:
 593                 return (EINVAL);
 594         }
 595
 596         if (irq >= sc->gic_nirqs)
 597                 return (EINVAL);
 598         switch (pol) {
 599         case INTR_POLARITY_CONFORM:
 600         case INTR_POLARITY_LOW:
 601         case INTR_POLARITY_HIGH:
 602                 break;
 603         default:
 604                 return (EINVAL);
 605         }
 606         switch (trig) {
 607         case INTR_TRIGGER_CONFORM:
 608         case INTR_TRIGGER_EDGE:
 609         case INTR_TRIGGER_LEVEL:
 610                 break;
 611         default:
 612                 return (EINVAL);
 613         }
 614
 615         *irqp = irq;
 616         if (polp != NULL)
 617                 *polp = pol;
 618         if (trigp != NULL)
 619                 *trigp = trig;
 620         return (0);
 621 }
 622
 623 static int
 624 gic_v3_map_intr(device_t dev, struct intr_map_data *data,
 625     struct intr_irqsrc **isrcp)
 626 {
 627         struct gic_v3_softc *sc;
 628         int error;
 629         u_int irq;
 630
 631         error = do_gic_v3_map_intr(dev, data, &irq, NULL, NULL);
 632         if (error == 0) {
 633                 sc = device_get_softc(dev);
 634                 *isrcp = GIC_INTR_ISRC(sc, irq);
 635         }
 636         return (error);
 637 }
 638
 639 static int
 640 gic_v3_setup_intr(device_t dev, struct intr_irqsrc *isrc,
 641     struct resource *res, struct intr_map_data *data)
 642 {
 643         struct gic_v3_softc *sc = device_get_softc(dev);
 644         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 645         enum intr_trigger trig;
 646         enum intr_polarity pol;
 647         uint32_t reg;
 648         u_int irq;
 649         int error;
 650
 651         if (data == NULL)
 652                 return (ENOTSUP);
 653
 654         error = do_gic_v3_map_intr(dev, data, &irq, &pol, &trig);
 655         if (error != 0)
 656                 return (error);
 657
 658         if (gi->gi_irq != irq || pol == INTR_POLARITY_CONFORM ||
 659             trig == INTR_TRIGGER_CONFORM)
 660                 return (EINVAL);
 661
 662         /* Compare config if this is not first setup. */
 663         if (isrc->isrc_handlers != 0) {
 664                 if (pol != gi->gi_pol || trig != gi->gi_trig)
 665                         return (EINVAL);
 666                 else
 667                         return (0);
 668         }
 669
 670         gi->gi_pol = pol;
 671         gi->gi_trig = trig;
 672
 673         /*
 674          * XXX - In case that per CPU interrupt is going to be enabled in time
 675          *       when SMP is already started, we need some IPI call which
 676          *       enables it on others CPUs. Further, it's more complicated as
 677          *       pic_enable_source() and pic_disable_source() should act on
 678          *       per CPU basis only. Thus, it should be solved here somehow.
 679          */
 680         if (isrc->isrc_flags & INTR_ISRCF_PPI)
 681                 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
 682
 683         if (irq >= GIC_FIRST_PPI && irq <= GIC_LAST_SPI) {
 684                 mtx_lock_spin(&sc->gic_mtx);
 685
 686                 /* Set the trigger and polarity */
 687                 if (irq <= GIC_LAST_PPI)
 688                         reg = gic_r_read(sc, 4,
 689                             GICR_SGI_BASE_SIZE + GICD_ICFGR(irq));
 690                 else
 691                         reg = gic_d_read(sc, 4, GICD_ICFGR(irq));
 692                 if (trig == INTR_TRIGGER_LEVEL)
 693                         reg &= ~(2 << ((irq % 16) * 2));
 694                 else
 695                         reg |= 2 << ((irq % 16) * 2);
 696
 697                 if (irq <= GIC_LAST_PPI) {
 698                         gic_r_write(sc, 4,
 699                             GICR_SGI_BASE_SIZE + GICD_ICFGR(irq), reg);
 700                         gic_v3_wait_for_rwp(sc, REDIST);
 701                 } else {
 702                         gic_d_write(sc, 4, GICD_ICFGR(irq), reg);
 703                         gic_v3_wait_for_rwp(sc, DIST);
 704                 }
 705
 706                 mtx_unlock_spin(&sc->gic_mtx);
 707
 708                 gic_v3_bind_intr(dev, isrc);
 709         }
 710
 711         return (0);
 712 }
 713
 714 static int
 715 gic_v3_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
 716     struct resource *res, struct intr_map_data *data)
 717 {
 718         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 719
 720         if (isrc->isrc_handlers == 0) {
 721                 gi->gi_pol = INTR_POLARITY_CONFORM;
 722                 gi->gi_trig = INTR_TRIGGER_CONFORM;
 723         }
 724
 725         return (0);
 726 }
 727
 728 static void
 729 gic_v3_disable_intr(device_t dev, struct intr_irqsrc *isrc)
 730 {
 731         struct gic_v3_softc *sc;
 732         struct gic_v3_irqsrc *gi;
 733         u_int irq;
 734
 735         sc = device_get_softc(dev);
 736         gi = (struct gic_v3_irqsrc *)isrc;
 737         irq = gi->gi_irq;
 738
 739         if (irq <= GIC_LAST_PPI) {
 740                 /* SGIs and PPIs in corresponding Re-Distributor */
 741                 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ICENABLER(irq),
 742                     GICD_I_MASK(irq));
 743                 gic_v3_wait_for_rwp(sc, REDIST);
 744         } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) {
 745                 /* SPIs in distributor */
 746                 gic_d_write(sc, 4, GICD_ICENABLER(irq), GICD_I_MASK(irq));
 747                 gic_v3_wait_for_rwp(sc, DIST);
 748         } else
 749                 panic("%s: Unsupported IRQ %u", __func__, irq);
 750 }
 751
 752 static void
 753 gic_v3_enable_intr(device_t dev, struct intr_irqsrc *isrc)
 754 {
 755         struct gic_v3_softc *sc;
 756         struct gic_v3_irqsrc *gi;
 757         u_int irq;
 758
 759         sc = device_get_softc(dev);
 760         gi = (struct gic_v3_irqsrc *)isrc;
 761         irq = gi->gi_irq;
 762
 763         if (irq <= GIC_LAST_PPI) {
 764                 /* SGIs and PPIs in corresponding Re-Distributor */
 765                 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ISENABLER(irq),
 766                     GICD_I_MASK(irq));
 767                 gic_v3_wait_for_rwp(sc, REDIST);
 768         } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) {
 769                 /* SPIs in distributor */
 770                 gic_d_write(sc, 4, GICD_ISENABLER(irq), GICD_I_MASK(irq));
 771                 gic_v3_wait_for_rwp(sc, DIST);
 772         } else
 773                 panic("%s: Unsupported IRQ %u", __func__, irq);
 774 }
 775
 776 static void
 777 gic_v3_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
 778 {
 779         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 780
 781         gic_v3_disable_intr(dev, isrc);
 782         gic_icc_write(EOIR1, gi->gi_irq);
 783 }
 784
 785 static void
 786 gic_v3_post_ithread(device_t dev, struct intr_irqsrc *isrc)
 787 {
 788
 789         gic_v3_enable_intr(dev, isrc);
 790 }
 791
 792 static void
 793 gic_v3_post_filter(device_t dev, struct intr_irqsrc *isrc)
 794 {
 795         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 796
 797         if (gi->gi_trig == INTR_TRIGGER_EDGE)
 798                 return;
 799
 800         gic_icc_write(EOIR1, gi->gi_irq);
 801 }
 802
 803 static int
 804 gic_v3_bind_intr(device_t dev, struct intr_irqsrc *isrc)
 805 {
 806         struct gic_v3_softc *sc;
 807         struct gic_v3_irqsrc *gi;
 808         int cpu;
 809
 810         gi = (struct gic_v3_irqsrc *)isrc;
 811         if (gi->gi_irq <= GIC_LAST_PPI)
 812                 return (EINVAL);
 813
 814         KASSERT(gi->gi_irq >= GIC_FIRST_SPI && gi->gi_irq <= GIC_LAST_SPI,
 815             ("%s: Attempting to bind an invalid IRQ", __func__));
 816
 817         sc = device_get_softc(dev);
 818
 819         if (CPU_EMPTY(&isrc->isrc_cpu)) {
 820                 gic_irq_cpu = intr_irq_next_cpu(gic_irq_cpu, &all_cpus);
 821                 CPU_SETOF(gic_irq_cpu, &isrc->isrc_cpu);
 822                 gic_d_write(sc, 4, GICD_IROUTER(gi->gi_irq),
 823                     CPU_AFFINITY(gic_irq_cpu));
 824         } else {
 825                 /*
 826                  * We can only bind to a single CPU so select
 827                  * the first CPU found.
 828                  */
 829                 cpu = CPU_FFS(&isrc->isrc_cpu) - 1;
 830                 gic_d_write(sc, 4, GICD_IROUTER(gi->gi_irq), CPU_AFFINITY(cpu));
 831         }
 832
 833         return (0);
 834 }
 835
 836 #ifdef SMP
 837 static void
 838 gic_v3_init_secondary(device_t dev)
 839 {
 840         device_t child;
 841         struct gic_v3_softc *sc;
 842         gic_v3_initseq_t *init_func;
 843         struct intr_irqsrc *isrc;
 844         u_int cpu, irq;
 845         int err, i;
 846
 847         sc = device_get_softc(dev);
 848         cpu = PCPU_GET(cpuid);
 849
 850         /* Train init sequence for boot CPU */
 851         for (init_func = gic_v3_secondary_init; *init_func != NULL;
 852             init_func++) {
 853                 err = (*init_func)(sc);
 854                 if (err != 0) {
 855                         device_printf(dev,
 856                             "Could not initialize GIC for CPU%u\n", cpu);
 857                         return;
 858                 }
 859         }
 860
 861         /* Unmask attached SGI interrupts. */
 862         for (irq = GIC_FIRST_SGI; irq <= GIC_LAST_SGI; irq++) {
 863                 isrc = GIC_INTR_ISRC(sc, irq);
 864                 if (intr_isrc_init_on_cpu(isrc, cpu))
 865                         gic_v3_enable_intr(dev, isrc);
 866         }
 867
 868         /* Unmask attached PPI interrupts. */
 869         for (irq = GIC_FIRST_PPI; irq <= GIC_LAST_PPI; irq++) {
 870                 isrc = GIC_INTR_ISRC(sc, irq);
 871                 if (intr_isrc_init_on_cpu(isrc, cpu))
 872                         gic_v3_enable_intr(dev, isrc);
 873         }
 874
 875         for (i = 0; i < sc->gic_nchildren; i++) {
 876                 child = sc->gic_children[i];
 877                 PIC_INIT_SECONDARY(child);
 878         }
 879 }
 880
 881 static void
 882 gic_v3_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus,
 883     u_int ipi)
 884 {
 885         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 886         uint64_t aff, val, irq;
 887         int i;
 888
 889 #define GIC_AFF_MASK    (CPU_AFF3_MASK | CPU_AFF2_MASK | CPU_AFF1_MASK)
 890 #define GIC_AFFINITY(i) (CPU_AFFINITY(i) & GIC_AFF_MASK)
 891         aff = GIC_AFFINITY(0);
 892         irq = gi->gi_irq;
 893         val = 0;
 894
 895         /* Iterate through all CPUs in set */
 896         for (i = 0; i <= mp_maxid; i++) {
 897                 /* Move to the next affinity group */
 898                 if (aff != GIC_AFFINITY(i)) {
 899                         /* Send the IPI */
 900                         if (val != 0) {
 901                                 gic_icc_write(SGI1R, val);
 902                                 val = 0;
 903                         }
 904                         aff = GIC_AFFINITY(i);
 905                 }
 906
 907                 /* Send the IPI to this cpu */
 908                 if (CPU_ISSET(i, &cpus)) {
 909 #define ICC_SGI1R_AFFINITY(aff)                                 \
 910     (((uint64_t)CPU_AFF3(aff) << ICC_SGI1R_EL1_AFF3_SHIFT) |    \
 911      ((uint64_t)CPU_AFF2(aff) << ICC_SGI1R_EL1_AFF2_SHIFT) |    \
 912      ((uint64_t)CPU_AFF1(aff) << ICC_SGI1R_EL1_AFF1_SHIFT))
 913                         /* Set the affinity when the first at this level */
 914                         if (val == 0)
 915                                 val = ICC_SGI1R_AFFINITY(aff) |
 916                                     irq << ICC_SGI1R_EL1_SGIID_SHIFT;
 917                         /* Set the bit to send the IPI to te CPU */
 918                         val |= 1 << CPU_AFF0(CPU_AFFINITY(i));
 919                 }
 920         }
 921
 922         /* Send the IPI to the last cpu affinity group */
 923         if (val != 0)
 924                 gic_icc_write(SGI1R, val);
 925 #undef GIC_AFF_MASK
 926 #undef GIC_AFFINITY
 927 }
 928
 929 static int
 930 gic_v3_ipi_setup(device_t dev, u_int ipi, struct intr_irqsrc **isrcp)
 931 {
 932         struct intr_irqsrc *isrc;
 933         struct gic_v3_softc *sc = device_get_softc(dev);
 934
 935         if (sgi_first_unused > GIC_LAST_SGI)
 936                 return (ENOSPC);
 937
 938         isrc = GIC_INTR_ISRC(sc, sgi_first_unused);
 939         sgi_to_ipi[sgi_first_unused++] = ipi;
 940
 941         CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
 942
 943         *isrcp = isrc;
 944         return (0);
 945 }
 946 #endif /* SMP */
 947
 948 /*
 949  * Helper routines
 950  */
 951 static void
 952 gic_v3_wait_for_rwp(struct gic_v3_softc *sc, enum gic_v3_xdist xdist)
 953 {
 954         struct resource *res;
 955         u_int cpuid;
 956         size_t us_left = 1000000;
 957
 958         cpuid = PCPU_GET(cpuid);
 959
 960         switch (xdist) {
 961         case DIST:
 962                 res = sc->gic_dist;
 963                 break;
 964         case REDIST:
 965                 res = sc->gic_redists.pcpu[cpuid];
 966                 break;
 967         default:
 968                 KASSERT(0, ("%s: Attempt to wait for unknown RWP", __func__));
 969                 return;
 970         }
 971
 972         while ((bus_read_4(res, GICD_CTLR) & GICD_CTLR_RWP) != 0) {
 973                 DELAY(1);
 974                 if (us_left-- == 0)
 975                         panic("GICD Register write pending for too long");
 976         }
 977 }
 978
 979 /* CPU interface. */
 980 static __inline void
 981 gic_v3_cpu_priority(uint64_t mask)
 982 {
 983
 984         /* Set prority mask */
 985         gic_icc_write(PMR, mask & ICC_PMR_EL1_PRIO_MASK);
 986 }
 987
 988 static int
 989 gic_v3_cpu_enable_sre(struct gic_v3_softc *sc)
 990 {
 991         uint64_t sre;
 992         u_int cpuid;
 993
 994         cpuid = PCPU_GET(cpuid);
 995         /*
 996          * Set the SRE bit to enable access to GIC CPU interface
 997          * via system registers.
 998          */
 999         sre = READ_SPECIALREG(icc_sre_el1);
1000         sre |= ICC_SRE_EL1_SRE;
1001         WRITE_SPECIALREG(icc_sre_el1, sre);
1002         isb();
1003         /*
1004          * Now ensure that the bit is set.
1005          */
1006         sre = READ_SPECIALREG(icc_sre_el1);
1007         if ((sre & ICC_SRE_EL1_SRE) == 0) {
1008                 /* We are done. This was disabled in EL2 */
1009                 device_printf(sc->dev, "ERROR: CPU%u cannot enable CPU interface "
1010                     "via system registers\n", cpuid);
1011                 return (ENXIO);
1012         } else if (bootverbose) {
1013                 device_printf(sc->dev,
1014                     "CPU%u enabled CPU interface via system registers\n",
1015                     cpuid);
1016         }
1017
1018         return (0);
1019 }
1020
1021 static int
1022 gic_v3_cpu_init(struct gic_v3_softc *sc)
1023 {
1024         int err;
1025
1026         /* Enable access to CPU interface via system registers */
1027         err = gic_v3_cpu_enable_sre(sc);
1028         if (err != 0)
1029                 return (err);
1030         /* Priority mask to minimum - accept all interrupts */
1031         gic_v3_cpu_priority(GIC_PRIORITY_MIN);
1032         /* Disable EOI mode */
1033         gic_icc_clear(CTLR, ICC_CTLR_EL1_EOIMODE);
1034         /* Enable group 1 (insecure) interrups */
1035         gic_icc_set(IGRPEN1, ICC_IGRPEN0_EL1_EN);
1036
1037         return (0);
1038 }
1039
1040 /* Distributor */
1041 static int
1042 gic_v3_dist_init(struct gic_v3_softc *sc)
1043 {
1044         uint64_t aff;
1045         u_int i;
1046
1047         /*
1048          * 1. Disable the Distributor
1049          */
1050         gic_d_write(sc, 4, GICD_CTLR, 0);
1051         gic_v3_wait_for_rwp(sc, DIST);
1052
1053         /*
1054          * 2. Configure the Distributor
1055          */
1056         /* Set all SPIs to be Group 1 Non-secure */
1057         for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_IGROUPRn)
1058                 gic_d_write(sc, 4, GICD_IGROUPR(i), 0xFFFFFFFF);
1059
1060         /* Set all global interrupts to be level triggered, active low. */
1061         for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ICFGRn)
1062                 gic_d_write(sc, 4, GICD_ICFGR(i), 0x00000000);
1063
1064         /* Set priority to all shared interrupts */
1065         for (i = GIC_FIRST_SPI;
1066             i < sc->gic_nirqs; i += GICD_I_PER_IPRIORITYn) {
1067                 /* Set highest priority */
1068                 gic_d_write(sc, 4, GICD_IPRIORITYR(i), GIC_PRIORITY_MAX);
1069         }
1070
1071         /*
1072          * Disable all interrupts. Leave PPI and SGIs as they are enabled in
1073          * Re-Distributor registers.
1074          */
1075         for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ISENABLERn)
1076                 gic_d_write(sc, 4, GICD_ICENABLER(i), 0xFFFFFFFF);
1077
1078         gic_v3_wait_for_rwp(sc, DIST);
1079
1080         /*
1081          * 3. Enable Distributor
1082          */
1083         /* Enable Distributor with ARE, Group 1 */
1084         gic_d_write(sc, 4, GICD_CTLR, GICD_CTLR_ARE_NS | GICD_CTLR_G1A |
1085             GICD_CTLR_G1);
1086
1087         /*
1088          * 4. Route all interrupts to boot CPU.
1089          */
1090         aff = CPU_AFFINITY(0);
1091         for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i++)
1092                 gic_d_write(sc, 4, GICD_IROUTER(i), aff);
1093
1094         return (0);
1095 }
1096
1097 /* Re-Distributor */
1098 static int
1099 gic_v3_redist_alloc(struct gic_v3_softc *sc)
1100 {
1101         u_int cpuid;
1102
1103         /* Allocate struct resource for all CPU's Re-Distributor registers */
1104         for (cpuid = 0; cpuid <= mp_maxid; cpuid++)
1105                 if (CPU_ISSET(cpuid, &all_cpus) != 0)
1106                         sc->gic_redists.pcpu[cpuid] =
1107                                 malloc(sizeof(*sc->gic_redists.pcpu[0]),
1108                                     M_GIC_V3, M_WAITOK);
1109                 else
1110                         sc->gic_redists.pcpu[cpuid] = NULL;
1111         return (0);
1112 }
1113
1114 static int
1115 gic_v3_redist_find(struct gic_v3_softc *sc)
1116 {
1117         struct resource r_res;
1118         bus_space_handle_t r_bsh;
1119         uint64_t aff;
1120         uint64_t typer;
1121         uint32_t pidr2;
1122         u_int cpuid;
1123         size_t i;
1124
1125         cpuid = PCPU_GET(cpuid);
1126
1127         aff = CPU_AFFINITY(cpuid);
1128         /* Affinity in format for comparison with typer */
1129         aff = (CPU_AFF3(aff) << 24) | (CPU_AFF2(aff) << 16) |
1130             (CPU_AFF1(aff) << 8) | CPU_AFF0(aff);
1131
1132         if (bootverbose) {
1133                 device_printf(sc->dev,
1134                     "Start searching for Re-Distributor\n");
1135         }
1136         /* Iterate through Re-Distributor regions */
1137         for (i = 0; i < sc->gic_redists.nregions; i++) {
1138                 /* Take a copy of the region's resource */
1139                 r_res = *sc->gic_redists.regions[i];
1140                 r_bsh = rman_get_bushandle(&r_res);
1141
1142                 pidr2 = bus_read_4(&r_res, GICR_PIDR2);
1143                 switch (GICR_PIDR2_ARCH(pidr2)) {
1144                 case GICR_PIDR2_ARCH_GICv3: /* fall through */
1145                 case GICR_PIDR2_ARCH_GICv4:
1146                         break;
1147                 default:
1148                         device_printf(sc->dev,
1149                             "No Re-Distributor found for CPU%u\n", cpuid);
1150                         return (ENODEV);
1151                 }
1152
1153                 do {
1154                         typer = bus_read_8(&r_res, GICR_TYPER);
1155                         if ((typer >> GICR_TYPER_AFF_SHIFT) == aff) {
1156                                 KASSERT(sc->gic_redists.pcpu[cpuid] != NULL,
1157                                     ("Invalid pointer to per-CPU redistributor"));
1158                                 /* Copy res contents to its final destination */
1159                                 *sc->gic_redists.pcpu[cpuid] = r_res;
1160                                 if (bootverbose) {
1161                                         device_printf(sc->dev,
1162                                             "CPU%u Re-Distributor has been found\n",
1163                                             cpuid);
1164                                 }
1165                                 return (0);
1166                         }
1167
1168                         r_bsh += (GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);
1169                         if ((typer & GICR_TYPER_VLPIS) != 0) {
1170                                 r_bsh +=
1171                                     (GICR_VLPI_BASE_SIZE + GICR_RESERVED_SIZE);
1172                         }
1173
1174                         rman_set_bushandle(&r_res, r_bsh);
1175                 } while ((typer & GICR_TYPER_LAST) == 0);
1176         }
1177
1178         device_printf(sc->dev, "No Re-Distributor found for CPU%u\n", cpuid);
1179         return (ENXIO);
1180 }
1181
1182 static int
1183 gic_v3_redist_wake(struct gic_v3_softc *sc)
1184 {
1185         uint32_t waker;
1186         size_t us_left = 1000000;
1187
1188         waker = gic_r_read(sc, 4, GICR_WAKER);
1189         /* Wake up Re-Distributor for this CPU */
1190         waker &= ~GICR_WAKER_PS;
1191         gic_r_write(sc, 4, GICR_WAKER, waker);
1192         /*
1193          * When clearing ProcessorSleep bit it is required to wait for
1194          * ChildrenAsleep to become zero following the processor power-on.
1195          */
1196         while ((gic_r_read(sc, 4, GICR_WAKER) & GICR_WAKER_CA) != 0) {
1197                 DELAY(1);
1198                 if (us_left-- == 0) {
1199                         panic("Could not wake Re-Distributor for CPU%u",
1200                             PCPU_GET(cpuid));
1201                 }
1202         }
1203
1204         if (bootverbose) {
1205                 device_printf(sc->dev, "CPU%u Re-Distributor woke up\n",
1206                     PCPU_GET(cpuid));
1207         }
1208
1209         return (0);
1210 }
1211
1212 static int
1213 gic_v3_redist_init(struct gic_v3_softc *sc)
1214 {
1215         int err;
1216         size_t i;
1217
1218         err = gic_v3_redist_find(sc);
1219         if (err != 0)
1220                 return (err);
1221
1222         err = gic_v3_redist_wake(sc);
1223         if (err != 0)
1224                 return (err);
1225
1226         /* Configure SGIs and PPIs to be Group1 Non-secure */
1227         gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_IGROUPR0,
1228             0xFFFFFFFF);
1229
1230         /* Disable SPIs */
1231         gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ICENABLER0,
1232             GICR_I_ENABLER_PPI_MASK);
1233         /* Enable SGIs */
1234         gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ISENABLER0,
1235             GICR_I_ENABLER_SGI_MASK);
1236
1237         /* Set priority for SGIs and PPIs */
1238         for (i = 0; i <= GIC_LAST_PPI; i += GICR_I_PER_IPRIORITYn) {
1239                 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_IPRIORITYR(i),
1240                     GIC_PRIORITY_MAX);
1241         }
1242
1243         gic_v3_wait_for_rwp(sc, REDIST);
1244
1245         return (0);
1246 }