2 * Copyright (c) 2015-2016 The FreeBSD Foundation
5 * This software was developed by Andrew Turner under
6 * the sponsorship of the FreeBSD Foundation.
8 * This software was developed by Semihalf under
9 * the sponsorship of the FreeBSD Foundation.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #include "opt_platform.h"
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/bitstring.h>
43 #include <sys/kernel.h>
45 #include <sys/malloc.h>
46 #include <sys/module.h>
50 #include <sys/cpuset.h>
52 #include <sys/mutex.h>
58 #include <machine/bus.h>
59 #include <machine/cpu.h>
60 #include <machine/intr.h>
63 #include <dev/fdt/fdt_intr.h>
64 #include <dev/ofw/ofw_bus_subr.h>
68 #include <contrib/dev/acpica/include/acpi.h>
69 #include <dev/acpica/acpivar.h>
74 #include <arm/arm/gic_common.h>
75 #include "gic_v3_reg.h"
76 #include "gic_v3_var.h"
78 static bus_get_domain_t gic_v3_get_domain;
79 static bus_read_ivar_t gic_v3_read_ivar;
81 static pic_disable_intr_t gic_v3_disable_intr;
82 static pic_enable_intr_t gic_v3_enable_intr;
83 static pic_map_intr_t gic_v3_map_intr;
84 static pic_setup_intr_t gic_v3_setup_intr;
85 static pic_teardown_intr_t gic_v3_teardown_intr;
86 static pic_post_filter_t gic_v3_post_filter;
87 static pic_post_ithread_t gic_v3_post_ithread;
88 static pic_pre_ithread_t gic_v3_pre_ithread;
89 static pic_bind_intr_t gic_v3_bind_intr;
91 static pic_init_secondary_t gic_v3_init_secondary;
92 static pic_ipi_send_t gic_v3_ipi_send;
93 static pic_ipi_setup_t gic_v3_ipi_setup;
96 static u_int gic_irq_cpu;
98 static u_int sgi_to_ipi[GIC_LAST_SGI - GIC_FIRST_SGI + 1];
99 static u_int sgi_first_unused = GIC_FIRST_SGI;
102 static device_method_t gic_v3_methods[] = {
103 /* Device interface */
104 DEVMETHOD(device_detach, gic_v3_detach),
107 DEVMETHOD(bus_get_domain, gic_v3_get_domain),
108 DEVMETHOD(bus_read_ivar, gic_v3_read_ivar),
110 /* Interrupt controller interface */
111 DEVMETHOD(pic_disable_intr, gic_v3_disable_intr),
112 DEVMETHOD(pic_enable_intr, gic_v3_enable_intr),
113 DEVMETHOD(pic_map_intr, gic_v3_map_intr),
114 DEVMETHOD(pic_setup_intr, gic_v3_setup_intr),
115 DEVMETHOD(pic_teardown_intr, gic_v3_teardown_intr),
116 DEVMETHOD(pic_post_filter, gic_v3_post_filter),
117 DEVMETHOD(pic_post_ithread, gic_v3_post_ithread),
118 DEVMETHOD(pic_pre_ithread, gic_v3_pre_ithread),
120 DEVMETHOD(pic_bind_intr, gic_v3_bind_intr),
121 DEVMETHOD(pic_init_secondary, gic_v3_init_secondary),
122 DEVMETHOD(pic_ipi_send, gic_v3_ipi_send),
123 DEVMETHOD(pic_ipi_setup, gic_v3_ipi_setup),
130 DEFINE_CLASS_0(gic, gic_v3_driver, gic_v3_methods,
131 sizeof(struct gic_v3_softc));
134 * Driver-specific definitions.
136 MALLOC_DEFINE(M_GIC_V3, "GICv3", GIC_V3_DEVSTR);
139 * Helper functions and definitions.
141 /* Destination registers, either Distributor or Re-Distributor */
147 struct gic_v3_irqsrc {
148 struct intr_irqsrc gi_isrc;
150 enum intr_polarity gi_pol;
151 enum intr_trigger gi_trig;
154 /* Helper routines starting with gic_v3_ */
155 static int gic_v3_dist_init(struct gic_v3_softc *);
156 static int gic_v3_redist_alloc(struct gic_v3_softc *);
157 static int gic_v3_redist_find(struct gic_v3_softc *);
158 static int gic_v3_redist_init(struct gic_v3_softc *);
159 static int gic_v3_cpu_init(struct gic_v3_softc *);
160 static void gic_v3_wait_for_rwp(struct gic_v3_softc *, enum gic_v3_xdist);
162 /* A sequence of init functions for primary (boot) CPU */
163 typedef int (*gic_v3_initseq_t) (struct gic_v3_softc *);
164 /* Primary CPU initialization sequence */
165 static gic_v3_initseq_t gic_v3_primary_init[] = {
174 /* Secondary CPU initialization sequence */
175 static gic_v3_initseq_t gic_v3_secondary_init[] = {
183 gic_r_read_4(device_t dev, bus_size_t offset)
185 struct gic_v3_softc *sc;
186 struct resource *rdist;
188 sc = device_get_softc(dev);
189 rdist = &sc->gic_redists.pcpu[PCPU_GET(cpuid)]->res;
190 return (bus_read_4(rdist, offset));
194 gic_r_read_8(device_t dev, bus_size_t offset)
196 struct gic_v3_softc *sc;
197 struct resource *rdist;
199 sc = device_get_softc(dev);
200 rdist = &sc->gic_redists.pcpu[PCPU_GET(cpuid)]->res;
201 return (bus_read_8(rdist, offset));
205 gic_r_write_4(device_t dev, bus_size_t offset, uint32_t val)
207 struct gic_v3_softc *sc;
208 struct resource *rdist;
210 sc = device_get_softc(dev);
211 rdist = &sc->gic_redists.pcpu[PCPU_GET(cpuid)]->res;
212 bus_write_4(rdist, offset, val);
216 gic_r_write_8(device_t dev, bus_size_t offset, uint64_t val)
218 struct gic_v3_softc *sc;
219 struct resource *rdist;
221 sc = device_get_softc(dev);
222 rdist = &sc->gic_redists.pcpu[PCPU_GET(cpuid)]->res;
223 bus_write_8(rdist, offset, val);
230 gic_v3_attach(device_t dev)
232 struct gic_v3_softc *sc;
233 gic_v3_initseq_t *init_func;
241 sc = device_get_softc(dev);
242 sc->gic_registered = FALSE;
246 /* Initialize mutex */
247 mtx_init(&sc->gic_mtx, "GICv3 lock", NULL, MTX_SPIN);
250 * Allocate array of struct resource.
251 * One entry for Distributor and all remaining for Re-Distributor.
253 sc->gic_res = malloc(
254 sizeof(*sc->gic_res) * (sc->gic_redists.nregions + 1),
257 /* Now allocate corresponding resources */
258 for (i = 0, rid = 0; i < (sc->gic_redists.nregions + 1); i++, rid++) {
259 sc->gic_res[rid] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
261 if (sc->gic_res[rid] == NULL)
266 * Distributor interface
268 sc->gic_dist = sc->gic_res[0];
271 * Re-Dristributor interface
273 /* Allocate space under region descriptions */
274 sc->gic_redists.regions = malloc(
275 sizeof(*sc->gic_redists.regions) * sc->gic_redists.nregions,
278 /* Fill-up bus_space information for each region. */
279 for (i = 0, rid = 1; i < sc->gic_redists.nregions; i++, rid++)
280 sc->gic_redists.regions[i] = sc->gic_res[rid];
282 /* Get the number of supported SPI interrupts */
283 typer = gic_d_read(sc, 4, GICD_TYPER);
284 sc->gic_nirqs = GICD_TYPER_I_NUM(typer);
285 if (sc->gic_nirqs > GIC_I_NUM_MAX)
286 sc->gic_nirqs = GIC_I_NUM_MAX;
288 sc->gic_irqs = malloc(sizeof(*sc->gic_irqs) * sc->gic_nirqs,
289 M_GIC_V3, M_WAITOK | M_ZERO);
290 name = device_get_nameunit(dev);
291 for (irq = 0; irq < sc->gic_nirqs; irq++) {
292 struct intr_irqsrc *isrc;
294 sc->gic_irqs[irq].gi_irq = irq;
295 sc->gic_irqs[irq].gi_pol = INTR_POLARITY_CONFORM;
296 sc->gic_irqs[irq].gi_trig = INTR_TRIGGER_CONFORM;
298 isrc = &sc->gic_irqs[irq].gi_isrc;
299 if (irq <= GIC_LAST_SGI) {
300 err = intr_isrc_register(isrc, sc->dev,
301 INTR_ISRCF_IPI, "%s,i%u", name, irq - GIC_FIRST_SGI);
302 } else if (irq <= GIC_LAST_PPI) {
303 err = intr_isrc_register(isrc, sc->dev,
304 INTR_ISRCF_PPI, "%s,p%u", name, irq - GIC_FIRST_PPI);
306 err = intr_isrc_register(isrc, sc->dev, 0,
307 "%s,s%u", name, irq - GIC_FIRST_SPI);
310 /* XXX call intr_isrc_deregister() */
311 free(sc->gic_irqs, M_DEVBUF);
317 * Read the Peripheral ID2 register. This is an implementation
318 * defined register, but seems to be implemented in all GICv3
319 * parts and Linux expects it to be there.
321 sc->gic_pidr2 = gic_d_read(sc, 4, GICD_PIDR2);
323 /* Get the number of supported interrupt identifier bits */
324 sc->gic_idbits = GICD_TYPER_IDBITS(typer);
327 device_printf(dev, "SPIs: %u, IDs: %u\n",
328 sc->gic_nirqs, (1 << sc->gic_idbits) - 1);
331 /* Train init sequence for boot CPU */
332 for (init_func = gic_v3_primary_init; *init_func != NULL; init_func++) {
333 err = (*init_func)(sc);
342 gic_v3_detach(device_t dev)
344 struct gic_v3_softc *sc;
348 sc = device_get_softc(dev);
350 if (device_is_attached(dev)) {
352 * XXX: We should probably deregister PIC
354 if (sc->gic_registered)
355 panic("Trying to detach registered PIC");
357 for (rid = 0; rid < (sc->gic_redists.nregions + 1); rid++)
358 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->gic_res[rid]);
360 for (i = 0; i <= mp_maxid; i++)
361 free(sc->gic_redists.pcpu[i], M_GIC_V3);
363 free(sc->gic_res, M_GIC_V3);
364 free(sc->gic_redists.regions, M_GIC_V3);
370 gic_v3_get_domain(device_t dev, device_t child, int *domain)
372 struct gic_v3_devinfo *di;
374 di = device_get_ivars(child);
375 if (di->gic_domain < 0)
378 *domain = di->gic_domain;
383 gic_v3_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
385 struct gic_v3_softc *sc;
387 sc = device_get_softc(dev);
390 case GICV3_IVAR_NIRQS:
391 *result = (NIRQ - sc->gic_nirqs) / sc->gic_nchildren;
393 case GICV3_IVAR_REDIST:
394 *result = (uintptr_t)sc->gic_redists.pcpu[PCPU_GET(cpuid)];
396 case GIC_IVAR_HW_REV:
398 GICR_PIDR2_ARCH(sc->gic_pidr2) == GICR_PIDR2_ARCH_GICv3 ||
399 GICR_PIDR2_ARCH(sc->gic_pidr2) == GICR_PIDR2_ARCH_GICv4,
400 ("gic_v3_read_ivar: Invalid GIC architecture: %d (%.08X)",
401 GICR_PIDR2_ARCH(sc->gic_pidr2), sc->gic_pidr2));
402 *result = GICR_PIDR2_ARCH(sc->gic_pidr2);
405 KASSERT(sc->gic_bus != GIC_BUS_UNKNOWN,
406 ("gic_v3_read_ivar: Unknown bus type"));
407 KASSERT(sc->gic_bus <= GIC_BUS_MAX,
408 ("gic_v3_read_ivar: Invalid bus type %u", sc->gic_bus));
409 *result = sc->gic_bus;
417 arm_gic_v3_intr(void *arg)
419 struct gic_v3_softc *sc = arg;
420 struct gic_v3_irqsrc *gi;
421 struct intr_pic *pic;
423 struct trapframe *tf;
428 if (CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1) {
430 * Hardware: Cavium ThunderX
431 * Chip revision: Pass 1.0 (early version)
432 * Pass 1.1 (production)
433 * ERRATUM: 22978, 23154
436 "nop;nop;nop;nop;nop;nop;nop;nop; \n"
437 "mrs %0, ICC_IAR1_EL1 \n"
438 "nop;nop;nop;nop; \n"
440 : "=&r" (active_irq));
442 active_irq = gic_icc_read(IAR1);
445 if (active_irq >= GIC_FIRST_LPI) {
446 intr_child_irq_handler(pic, active_irq);
450 if (__predict_false(active_irq >= sc->gic_nirqs))
451 return (FILTER_HANDLED);
453 tf = curthread->td_intr_frame;
454 gi = &sc->gic_irqs[active_irq];
455 if (active_irq <= GIC_LAST_SGI) {
456 /* Call EOI for all IPI before dispatch. */
457 gic_icc_write(EOIR1, (uint64_t)active_irq);
459 intr_ipi_dispatch(sgi_to_ipi[gi->gi_irq], tf);
461 device_printf(sc->dev, "SGI %ju on UP system detected\n",
462 (uintmax_t)(active_irq - GIC_FIRST_SGI));
464 } else if (active_irq >= GIC_FIRST_PPI &&
465 active_irq <= GIC_LAST_SPI) {
466 if (gi->gi_trig == INTR_TRIGGER_EDGE)
467 gic_icc_write(EOIR1, gi->gi_irq);
469 if (intr_isrc_dispatch(&gi->gi_isrc, tf) != 0) {
470 if (gi->gi_trig != INTR_TRIGGER_EDGE)
471 gic_icc_write(EOIR1, gi->gi_irq);
472 gic_v3_disable_intr(sc->dev, &gi->gi_isrc);
473 device_printf(sc->dev,
474 "Stray irq %lu disabled\n", active_irq);
482 gic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp,
483 enum intr_polarity *polp, enum intr_trigger *trigp)
491 * The 1st cell is the interrupt type:
494 * The 2nd cell contains the interrupt number:
497 * The 3rd cell is the flags, encoded as follows:
498 * bits[3:0] trigger type and level flags
500 * 2 = edge triggered (PPI only)
501 * 4 = level-sensitive
502 * 8 = level-sensitive (PPI only)
506 irq = GIC_FIRST_SPI + cells[1];
507 /* SPI irq is checked later. */
510 irq = GIC_FIRST_PPI + cells[1];
511 if (irq > GIC_LAST_PPI) {
512 device_printf(dev, "unsupported PPI interrupt "
513 "number %u\n", cells[1]);
518 device_printf(dev, "unsupported interrupt type "
519 "configuration %u\n", cells[0]);
523 switch (cells[2] & FDT_INTR_MASK) {
524 case FDT_INTR_EDGE_RISING:
525 *trigp = INTR_TRIGGER_EDGE;
526 *polp = INTR_POLARITY_HIGH;
528 case FDT_INTR_EDGE_FALLING:
529 *trigp = INTR_TRIGGER_EDGE;
530 *polp = INTR_POLARITY_LOW;
532 case FDT_INTR_LEVEL_HIGH:
533 *trigp = INTR_TRIGGER_LEVEL;
534 *polp = INTR_POLARITY_HIGH;
536 case FDT_INTR_LEVEL_LOW:
537 *trigp = INTR_TRIGGER_LEVEL;
538 *polp = INTR_POLARITY_LOW;
541 device_printf(dev, "unsupported trigger/polarity "
542 "configuration 0x%02x\n", cells[2]);
546 /* Check the interrupt is valid */
547 if (irq >= GIC_FIRST_SPI && *polp != INTR_POLARITY_HIGH)
556 gic_map_msi(device_t dev, struct intr_map_data_msi *msi_data, u_int *irqp,
557 enum intr_polarity *polp, enum intr_trigger *trigp)
559 struct gic_v3_irqsrc *gi;
562 gi = (struct gic_v3_irqsrc *)msi_data->isrc;
568 /* MSI/MSI-X interrupts are always edge triggered with high polarity */
569 *polp = INTR_POLARITY_HIGH;
570 *trigp = INTR_TRIGGER_EDGE;
576 do_gic_v3_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp,
577 enum intr_polarity *polp, enum intr_trigger *trigp)
579 struct gic_v3_softc *sc;
580 enum intr_polarity pol;
581 enum intr_trigger trig;
582 struct intr_map_data_msi *dam;
584 struct intr_map_data_fdt *daf;
587 struct intr_map_data_acpi *daa;
591 sc = device_get_softc(dev);
593 switch (data->type) {
595 case INTR_MAP_DATA_FDT:
596 daf = (struct intr_map_data_fdt *)data;
597 if (gic_map_fdt(dev, daf->ncells, daf->cells, &irq, &pol,
603 case INTR_MAP_DATA_ACPI:
604 daa = (struct intr_map_data_acpi *)data;
610 case INTR_MAP_DATA_MSI:
612 dam = (struct intr_map_data_msi *)data;
613 if (gic_map_msi(dev, dam, &irq, &pol, &trig) != 0)
620 if (irq >= sc->gic_nirqs)
623 case INTR_POLARITY_CONFORM:
624 case INTR_POLARITY_LOW:
625 case INTR_POLARITY_HIGH:
631 case INTR_TRIGGER_CONFORM:
632 case INTR_TRIGGER_EDGE:
633 case INTR_TRIGGER_LEVEL:
648 gic_v3_map_intr(device_t dev, struct intr_map_data *data,
649 struct intr_irqsrc **isrcp)
651 struct gic_v3_softc *sc;
655 error = do_gic_v3_map_intr(dev, data, &irq, NULL, NULL);
657 sc = device_get_softc(dev);
658 *isrcp = GIC_INTR_ISRC(sc, irq);
664 gic_v3_setup_intr(device_t dev, struct intr_irqsrc *isrc,
665 struct resource *res, struct intr_map_data *data)
667 struct gic_v3_softc *sc = device_get_softc(dev);
668 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
669 enum intr_trigger trig;
670 enum intr_polarity pol;
678 error = do_gic_v3_map_intr(dev, data, &irq, &pol, &trig);
682 if (gi->gi_irq != irq || pol == INTR_POLARITY_CONFORM ||
683 trig == INTR_TRIGGER_CONFORM)
686 /* Compare config if this is not first setup. */
687 if (isrc->isrc_handlers != 0) {
688 if (pol != gi->gi_pol || trig != gi->gi_trig)
698 * XXX - In case that per CPU interrupt is going to be enabled in time
699 * when SMP is already started, we need some IPI call which
700 * enables it on others CPUs. Further, it's more complicated as
701 * pic_enable_source() and pic_disable_source() should act on
702 * per CPU basis only. Thus, it should be solved here somehow.
704 if (isrc->isrc_flags & INTR_ISRCF_PPI)
705 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
707 if (irq >= GIC_FIRST_PPI && irq <= GIC_LAST_SPI) {
708 mtx_lock_spin(&sc->gic_mtx);
710 /* Set the trigger and polarity */
711 if (irq <= GIC_LAST_PPI)
712 reg = gic_r_read(sc, 4,
713 GICR_SGI_BASE_SIZE + GICD_ICFGR(irq));
715 reg = gic_d_read(sc, 4, GICD_ICFGR(irq));
716 if (trig == INTR_TRIGGER_LEVEL)
717 reg &= ~(2 << ((irq % 16) * 2));
719 reg |= 2 << ((irq % 16) * 2);
721 if (irq <= GIC_LAST_PPI) {
723 GICR_SGI_BASE_SIZE + GICD_ICFGR(irq), reg);
724 gic_v3_wait_for_rwp(sc, REDIST);
726 gic_d_write(sc, 4, GICD_ICFGR(irq), reg);
727 gic_v3_wait_for_rwp(sc, DIST);
730 mtx_unlock_spin(&sc->gic_mtx);
732 gic_v3_bind_intr(dev, isrc);
739 gic_v3_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
740 struct resource *res, struct intr_map_data *data)
742 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
744 if (isrc->isrc_handlers == 0) {
745 gi->gi_pol = INTR_POLARITY_CONFORM;
746 gi->gi_trig = INTR_TRIGGER_CONFORM;
753 gic_v3_disable_intr(device_t dev, struct intr_irqsrc *isrc)
755 struct gic_v3_softc *sc;
756 struct gic_v3_irqsrc *gi;
759 sc = device_get_softc(dev);
760 gi = (struct gic_v3_irqsrc *)isrc;
763 if (irq <= GIC_LAST_PPI) {
764 /* SGIs and PPIs in corresponding Re-Distributor */
765 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ICENABLER(irq),
767 gic_v3_wait_for_rwp(sc, REDIST);
768 } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) {
769 /* SPIs in distributor */
770 gic_d_write(sc, 4, GICD_ICENABLER(irq), GICD_I_MASK(irq));
771 gic_v3_wait_for_rwp(sc, DIST);
773 panic("%s: Unsupported IRQ %u", __func__, irq);
777 gic_v3_enable_intr(device_t dev, struct intr_irqsrc *isrc)
779 struct gic_v3_softc *sc;
780 struct gic_v3_irqsrc *gi;
783 sc = device_get_softc(dev);
784 gi = (struct gic_v3_irqsrc *)isrc;
787 if (irq <= GIC_LAST_PPI) {
788 /* SGIs and PPIs in corresponding Re-Distributor */
789 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ISENABLER(irq),
791 gic_v3_wait_for_rwp(sc, REDIST);
792 } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) {
793 /* SPIs in distributor */
794 gic_d_write(sc, 4, GICD_ISENABLER(irq), GICD_I_MASK(irq));
795 gic_v3_wait_for_rwp(sc, DIST);
797 panic("%s: Unsupported IRQ %u", __func__, irq);
801 gic_v3_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
803 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
805 gic_v3_disable_intr(dev, isrc);
806 gic_icc_write(EOIR1, gi->gi_irq);
810 gic_v3_post_ithread(device_t dev, struct intr_irqsrc *isrc)
813 gic_v3_enable_intr(dev, isrc);
817 gic_v3_post_filter(device_t dev, struct intr_irqsrc *isrc)
819 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
821 if (gi->gi_trig == INTR_TRIGGER_EDGE)
824 gic_icc_write(EOIR1, gi->gi_irq);
828 gic_v3_bind_intr(device_t dev, struct intr_irqsrc *isrc)
830 struct gic_v3_softc *sc;
831 struct gic_v3_irqsrc *gi;
834 gi = (struct gic_v3_irqsrc *)isrc;
835 if (gi->gi_irq <= GIC_LAST_PPI)
838 KASSERT(gi->gi_irq >= GIC_FIRST_SPI && gi->gi_irq <= GIC_LAST_SPI,
839 ("%s: Attempting to bind an invalid IRQ", __func__));
841 sc = device_get_softc(dev);
843 if (CPU_EMPTY(&isrc->isrc_cpu)) {
844 gic_irq_cpu = intr_irq_next_cpu(gic_irq_cpu, &all_cpus);
845 CPU_SETOF(gic_irq_cpu, &isrc->isrc_cpu);
846 gic_d_write(sc, 4, GICD_IROUTER(gi->gi_irq),
847 CPU_AFFINITY(gic_irq_cpu));
850 * We can only bind to a single CPU so select
851 * the first CPU found.
853 cpu = CPU_FFS(&isrc->isrc_cpu) - 1;
854 gic_d_write(sc, 4, GICD_IROUTER(gi->gi_irq), CPU_AFFINITY(cpu));
862 gic_v3_init_secondary(device_t dev)
865 struct gic_v3_softc *sc;
866 gic_v3_initseq_t *init_func;
867 struct intr_irqsrc *isrc;
871 sc = device_get_softc(dev);
872 cpu = PCPU_GET(cpuid);
874 /* Train init sequence for boot CPU */
875 for (init_func = gic_v3_secondary_init; *init_func != NULL;
877 err = (*init_func)(sc);
880 "Could not initialize GIC for CPU%u\n", cpu);
885 /* Unmask attached SGI interrupts. */
886 for (irq = GIC_FIRST_SGI; irq <= GIC_LAST_SGI; irq++) {
887 isrc = GIC_INTR_ISRC(sc, irq);
888 if (intr_isrc_init_on_cpu(isrc, cpu))
889 gic_v3_enable_intr(dev, isrc);
892 /* Unmask attached PPI interrupts. */
893 for (irq = GIC_FIRST_PPI; irq <= GIC_LAST_PPI; irq++) {
894 isrc = GIC_INTR_ISRC(sc, irq);
895 if (intr_isrc_init_on_cpu(isrc, cpu))
896 gic_v3_enable_intr(dev, isrc);
899 for (i = 0; i < sc->gic_nchildren; i++) {
900 child = sc->gic_children[i];
901 PIC_INIT_SECONDARY(child);
906 gic_v3_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus,
909 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
910 uint64_t aff, val, irq;
913 #define GIC_AFF_MASK (CPU_AFF3_MASK | CPU_AFF2_MASK | CPU_AFF1_MASK)
914 #define GIC_AFFINITY(i) (CPU_AFFINITY(i) & GIC_AFF_MASK)
915 aff = GIC_AFFINITY(0);
919 /* Iterate through all CPUs in set */
920 for (i = 0; i <= mp_maxid; i++) {
921 /* Move to the next affinity group */
922 if (aff != GIC_AFFINITY(i)) {
925 gic_icc_write(SGI1R, val);
928 aff = GIC_AFFINITY(i);
931 /* Send the IPI to this cpu */
932 if (CPU_ISSET(i, &cpus)) {
933 #define ICC_SGI1R_AFFINITY(aff) \
934 (((uint64_t)CPU_AFF3(aff) << ICC_SGI1R_EL1_AFF3_SHIFT) | \
935 ((uint64_t)CPU_AFF2(aff) << ICC_SGI1R_EL1_AFF2_SHIFT) | \
936 ((uint64_t)CPU_AFF1(aff) << ICC_SGI1R_EL1_AFF1_SHIFT))
937 /* Set the affinity when the first at this level */
939 val = ICC_SGI1R_AFFINITY(aff) |
940 irq << ICC_SGI1R_EL1_SGIID_SHIFT;
941 /* Set the bit to send the IPI to te CPU */
942 val |= 1 << CPU_AFF0(CPU_AFFINITY(i));
946 /* Send the IPI to the last cpu affinity group */
948 gic_icc_write(SGI1R, val);
954 gic_v3_ipi_setup(device_t dev, u_int ipi, struct intr_irqsrc **isrcp)
956 struct intr_irqsrc *isrc;
957 struct gic_v3_softc *sc = device_get_softc(dev);
959 if (sgi_first_unused > GIC_LAST_SGI)
962 isrc = GIC_INTR_ISRC(sc, sgi_first_unused);
963 sgi_to_ipi[sgi_first_unused++] = ipi;
965 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
976 gic_v3_wait_for_rwp(struct gic_v3_softc *sc, enum gic_v3_xdist xdist)
978 struct resource *res;
980 size_t us_left = 1000000;
982 cpuid = PCPU_GET(cpuid);
989 res = &sc->gic_redists.pcpu[cpuid]->res;
992 KASSERT(0, ("%s: Attempt to wait for unknown RWP", __func__));
996 while ((bus_read_4(res, GICD_CTLR) & GICD_CTLR_RWP) != 0) {
999 panic("GICD Register write pending for too long");
1003 /* CPU interface. */
1004 static __inline void
1005 gic_v3_cpu_priority(uint64_t mask)
1008 /* Set prority mask */
1009 gic_icc_write(PMR, mask & ICC_PMR_EL1_PRIO_MASK);
1013 gic_v3_cpu_enable_sre(struct gic_v3_softc *sc)
1018 cpuid = PCPU_GET(cpuid);
1020 * Set the SRE bit to enable access to GIC CPU interface
1021 * via system registers.
1023 sre = READ_SPECIALREG(icc_sre_el1);
1024 sre |= ICC_SRE_EL1_SRE;
1025 WRITE_SPECIALREG(icc_sre_el1, sre);
1028 * Now ensure that the bit is set.
1030 sre = READ_SPECIALREG(icc_sre_el1);
1031 if ((sre & ICC_SRE_EL1_SRE) == 0) {
1032 /* We are done. This was disabled in EL2 */
1033 device_printf(sc->dev, "ERROR: CPU%u cannot enable CPU interface "
1034 "via system registers\n", cpuid);
1036 } else if (bootverbose) {
1037 device_printf(sc->dev,
1038 "CPU%u enabled CPU interface via system registers\n",
1046 gic_v3_cpu_init(struct gic_v3_softc *sc)
1050 /* Enable access to CPU interface via system registers */
1051 err = gic_v3_cpu_enable_sre(sc);
1054 /* Priority mask to minimum - accept all interrupts */
1055 gic_v3_cpu_priority(GIC_PRIORITY_MIN);
1056 /* Disable EOI mode */
1057 gic_icc_clear(CTLR, ICC_CTLR_EL1_EOIMODE);
1058 /* Enable group 1 (insecure) interrups */
1059 gic_icc_set(IGRPEN1, ICC_IGRPEN0_EL1_EN);
1066 gic_v3_dist_init(struct gic_v3_softc *sc)
1072 * 1. Disable the Distributor
1074 gic_d_write(sc, 4, GICD_CTLR, 0);
1075 gic_v3_wait_for_rwp(sc, DIST);
1078 * 2. Configure the Distributor
1080 /* Set all SPIs to be Group 1 Non-secure */
1081 for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_IGROUPRn)
1082 gic_d_write(sc, 4, GICD_IGROUPR(i), 0xFFFFFFFF);
1084 /* Set all global interrupts to be level triggered, active low. */
1085 for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ICFGRn)
1086 gic_d_write(sc, 4, GICD_ICFGR(i), 0x00000000);
1088 /* Set priority to all shared interrupts */
1089 for (i = GIC_FIRST_SPI;
1090 i < sc->gic_nirqs; i += GICD_I_PER_IPRIORITYn) {
1091 /* Set highest priority */
1092 gic_d_write(sc, 4, GICD_IPRIORITYR(i), GIC_PRIORITY_MAX);
1096 * Disable all interrupts. Leave PPI and SGIs as they are enabled in
1097 * Re-Distributor registers.
1099 for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ISENABLERn)
1100 gic_d_write(sc, 4, GICD_ICENABLER(i), 0xFFFFFFFF);
1102 gic_v3_wait_for_rwp(sc, DIST);
1105 * 3. Enable Distributor
1107 /* Enable Distributor with ARE, Group 1 */
1108 gic_d_write(sc, 4, GICD_CTLR, GICD_CTLR_ARE_NS | GICD_CTLR_G1A |
1112 * 4. Route all interrupts to boot CPU.
1114 aff = CPU_AFFINITY(0);
1115 for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i++)
1116 gic_d_write(sc, 4, GICD_IROUTER(i), aff);
1121 /* Re-Distributor */
1123 gic_v3_redist_alloc(struct gic_v3_softc *sc)
1127 /* Allocate struct resource for all CPU's Re-Distributor registers */
1128 for (cpuid = 0; cpuid <= mp_maxid; cpuid++)
1129 if (CPU_ISSET(cpuid, &all_cpus) != 0)
1130 sc->gic_redists.pcpu[cpuid] =
1131 malloc(sizeof(*sc->gic_redists.pcpu[0]),
1132 M_GIC_V3, M_WAITOK);
1134 sc->gic_redists.pcpu[cpuid] = NULL;
1139 gic_v3_redist_find(struct gic_v3_softc *sc)
1141 struct resource r_res;
1142 bus_space_handle_t r_bsh;
1149 cpuid = PCPU_GET(cpuid);
1151 aff = CPU_AFFINITY(cpuid);
1152 /* Affinity in format for comparison with typer */
1153 aff = (CPU_AFF3(aff) << 24) | (CPU_AFF2(aff) << 16) |
1154 (CPU_AFF1(aff) << 8) | CPU_AFF0(aff);
1157 device_printf(sc->dev,
1158 "Start searching for Re-Distributor\n");
1160 /* Iterate through Re-Distributor regions */
1161 for (i = 0; i < sc->gic_redists.nregions; i++) {
1162 /* Take a copy of the region's resource */
1163 r_res = *sc->gic_redists.regions[i];
1164 r_bsh = rman_get_bushandle(&r_res);
1166 pidr2 = bus_read_4(&r_res, GICR_PIDR2);
1167 switch (GICR_PIDR2_ARCH(pidr2)) {
1168 case GICR_PIDR2_ARCH_GICv3: /* fall through */
1169 case GICR_PIDR2_ARCH_GICv4:
1172 device_printf(sc->dev,
1173 "No Re-Distributor found for CPU%u\n", cpuid);
1178 typer = bus_read_8(&r_res, GICR_TYPER);
1179 if ((typer >> GICR_TYPER_AFF_SHIFT) == aff) {
1180 KASSERT(sc->gic_redists.pcpu[cpuid] != NULL,
1181 ("Invalid pointer to per-CPU redistributor"));
1182 /* Copy res contents to its final destination */
1183 sc->gic_redists.pcpu[cpuid]->res = r_res;
1184 sc->gic_redists.pcpu[cpuid]->lpi_enabled = false;
1186 device_printf(sc->dev,
1187 "CPU%u Re-Distributor has been found\n",
1193 r_bsh += (GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);
1194 if ((typer & GICR_TYPER_VLPIS) != 0) {
1196 (GICR_VLPI_BASE_SIZE + GICR_RESERVED_SIZE);
1199 rman_set_bushandle(&r_res, r_bsh);
1200 } while ((typer & GICR_TYPER_LAST) == 0);
1203 device_printf(sc->dev, "No Re-Distributor found for CPU%u\n", cpuid);
1208 gic_v3_redist_wake(struct gic_v3_softc *sc)
1211 size_t us_left = 1000000;
1213 waker = gic_r_read(sc, 4, GICR_WAKER);
1214 /* Wake up Re-Distributor for this CPU */
1215 waker &= ~GICR_WAKER_PS;
1216 gic_r_write(sc, 4, GICR_WAKER, waker);
1218 * When clearing ProcessorSleep bit it is required to wait for
1219 * ChildrenAsleep to become zero following the processor power-on.
1221 while ((gic_r_read(sc, 4, GICR_WAKER) & GICR_WAKER_CA) != 0) {
1223 if (us_left-- == 0) {
1224 panic("Could not wake Re-Distributor for CPU%u",
1230 device_printf(sc->dev, "CPU%u Re-Distributor woke up\n",
1238 gic_v3_redist_init(struct gic_v3_softc *sc)
1243 err = gic_v3_redist_find(sc);
1247 err = gic_v3_redist_wake(sc);
1251 /* Configure SGIs and PPIs to be Group1 Non-secure */
1252 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_IGROUPR0,
1256 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ICENABLER0,
1257 GICR_I_ENABLER_PPI_MASK);
1259 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ISENABLER0,
1260 GICR_I_ENABLER_SGI_MASK);
1262 /* Set priority for SGIs and PPIs */
1263 for (i = 0; i <= GIC_LAST_PPI; i += GICR_I_PER_IPRIORITYn) {
1264 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_IPRIORITYR(i),
1268 gic_v3_wait_for_rwp(sc, REDIST);