sys/arm64/arm64/gic_v3.c

   1 /*-
   2  * Copyright (c) 2015-2016 The FreeBSD Foundation
   3  * All rights reserved.
   4  *
   5  * This software was developed by Andrew Turner under
   6  * the sponsorship of the FreeBSD Foundation.
   7  *
   8  * This software was developed by Semihalf under
   9  * the sponsorship of the FreeBSD Foundation.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  */
  32
  33 #include "opt_platform.h"
  34
  35 #include <sys/cdefs.h>
  36 __FBSDID("$FreeBSD$");
  37
  38 #include <sys/param.h>
  39 #include <sys/systm.h>
  40 #include <sys/bitstring.h>
  41 #include <sys/bus.h>
  42 #include <sys/kernel.h>
  43 #include <sys/ktr.h>
  44 #include <sys/malloc.h>
  45 #include <sys/module.h>
  46 #include <sys/rman.h>
  47 #include <sys/pcpu.h>
  48 #include <sys/proc.h>
  49 #include <sys/cpuset.h>
  50 #include <sys/lock.h>
  51 #include <sys/mutex.h>
  52 #include <sys/smp.h>
  53
  54 #include <vm/vm.h>
  55 #include <vm/pmap.h>
  56
  57 #include <machine/bus.h>
  58 #include <machine/cpu.h>
  59 #include <machine/intr.h>
  60
  61 #ifdef FDT
  62 #include <dev/ofw/ofw_bus_subr.h>
  63 #endif
  64
  65 #include "pic_if.h"
  66
  67 #include "gic_v3_reg.h"
  68 #include "gic_v3_var.h"
  69
  70 static bus_read_ivar_t gic_v3_read_ivar;
  71
  72 static pic_disable_intr_t gic_v3_disable_intr;
  73 static pic_enable_intr_t gic_v3_enable_intr;
  74 static pic_map_intr_t gic_v3_map_intr;
  75 static pic_setup_intr_t gic_v3_setup_intr;
  76 static pic_teardown_intr_t gic_v3_teardown_intr;
  77 static pic_post_filter_t gic_v3_post_filter;
  78 static pic_post_ithread_t gic_v3_post_ithread;
  79 static pic_pre_ithread_t gic_v3_pre_ithread;
  80 static pic_bind_intr_t gic_v3_bind_intr;
  81 #ifdef SMP
  82 static pic_init_secondary_t gic_v3_init_secondary;
  83 static pic_ipi_send_t gic_v3_ipi_send;
  84 static pic_ipi_setup_t gic_v3_ipi_setup;
  85 #endif
  86
  87 static u_int gic_irq_cpu;
  88 #ifdef SMP
  89 static u_int sgi_to_ipi[GIC_LAST_SGI - GIC_FIRST_SGI + 1];
  90 static u_int sgi_first_unused = GIC_FIRST_SGI;
  91 #endif
  92
  93 static device_method_t gic_v3_methods[] = {
  94         /* Device interface */
  95         DEVMETHOD(device_detach,        gic_v3_detach),
  96
  97         /* Bus interface */
  98         DEVMETHOD(bus_read_ivar,        gic_v3_read_ivar),
  99
 100         /* Interrupt controller interface */
 101         DEVMETHOD(pic_disable_intr,     gic_v3_disable_intr),
 102         DEVMETHOD(pic_enable_intr,      gic_v3_enable_intr),
 103         DEVMETHOD(pic_map_intr,         gic_v3_map_intr),
 104         DEVMETHOD(pic_setup_intr,       gic_v3_setup_intr),
 105         DEVMETHOD(pic_teardown_intr,    gic_v3_teardown_intr),
 106         DEVMETHOD(pic_post_filter,      gic_v3_post_filter),
 107         DEVMETHOD(pic_post_ithread,     gic_v3_post_ithread),
 108         DEVMETHOD(pic_pre_ithread,      gic_v3_pre_ithread),
 109 #ifdef SMP
 110         DEVMETHOD(pic_bind_intr,        gic_v3_bind_intr),
 111         DEVMETHOD(pic_init_secondary,   gic_v3_init_secondary),
 112         DEVMETHOD(pic_ipi_send,         gic_v3_ipi_send),
 113         DEVMETHOD(pic_ipi_setup,        gic_v3_ipi_setup),
 114 #endif
 115
 116         /* End */
 117         DEVMETHOD_END
 118 };
 119
 120 DEFINE_CLASS_0(gic, gic_v3_driver, gic_v3_methods,
 121     sizeof(struct gic_v3_softc));
 122
 123 /*
 124  * Driver-specific definitions.
 125  */
 126 MALLOC_DEFINE(M_GIC_V3, "GICv3", GIC_V3_DEVSTR);
 127
 128 /*
 129  * Helper functions and definitions.
 130  */
 131 /* Destination registers, either Distributor or Re-Distributor */
 132 enum gic_v3_xdist {
 133         DIST = 0,
 134         REDIST,
 135 };
 136
 137 struct gic_v3_irqsrc {
 138         struct intr_irqsrc      gi_isrc;
 139         uint32_t                gi_irq;
 140         enum intr_polarity      gi_pol;
 141         enum intr_trigger       gi_trig;
 142 };
 143
 144 /* Helper routines starting with gic_v3_ */
 145 static int gic_v3_dist_init(struct gic_v3_softc *);
 146 static int gic_v3_redist_alloc(struct gic_v3_softc *);
 147 static int gic_v3_redist_find(struct gic_v3_softc *);
 148 static int gic_v3_redist_init(struct gic_v3_softc *);
 149 static int gic_v3_cpu_init(struct gic_v3_softc *);
 150 static void gic_v3_wait_for_rwp(struct gic_v3_softc *, enum gic_v3_xdist);
 151
 152 /* A sequence of init functions for primary (boot) CPU */
 153 typedef int (*gic_v3_initseq_t) (struct gic_v3_softc *);
 154 /* Primary CPU initialization sequence */
 155 static gic_v3_initseq_t gic_v3_primary_init[] = {
 156         gic_v3_dist_init,
 157         gic_v3_redist_alloc,
 158         gic_v3_redist_init,
 159         gic_v3_cpu_init,
 160         NULL
 161 };
 162
 163 #ifdef SMP
 164 /* Secondary CPU initialization sequence */
 165 static gic_v3_initseq_t gic_v3_secondary_init[] = {
 166         gic_v3_redist_init,
 167         gic_v3_cpu_init,
 168         NULL
 169 };
 170 #endif
 171
 172 uint32_t
 173 gic_r_read_4(device_t dev, bus_size_t offset)
 174 {
 175         struct gic_v3_softc *sc;
 176
 177         sc = device_get_softc(dev);
 178         return (bus_read_4(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset));
 179 }
 180
 181 uint64_t
 182 gic_r_read_8(device_t dev, bus_size_t offset)
 183 {
 184         struct gic_v3_softc *sc;
 185
 186         sc = device_get_softc(dev);
 187         return (bus_read_8(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset));
 188 }
 189
 190 void
 191 gic_r_write_4(device_t dev, bus_size_t offset, uint32_t val)
 192 {
 193         struct gic_v3_softc *sc;
 194
 195         sc = device_get_softc(dev);
 196         bus_write_4(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset, val);
 197 }
 198
 199 void
 200 gic_r_write_8(device_t dev, bus_size_t offset, uint64_t val)
 201 {
 202         struct gic_v3_softc *sc;
 203
 204         sc = device_get_softc(dev);
 205         bus_write_8(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset, val);
 206 }
 207
 208 /*
 209  * Device interface.
 210  */
 211 int
 212 gic_v3_attach(device_t dev)
 213 {
 214         struct gic_v3_softc *sc;
 215         gic_v3_initseq_t *init_func;
 216         uint32_t typer;
 217         int rid;
 218         int err;
 219         size_t i;
 220         u_int irq;
 221         const char *name;
 222
 223         sc = device_get_softc(dev);
 224         sc->gic_registered = FALSE;
 225         sc->dev = dev;
 226         err = 0;
 227
 228         /* Initialize mutex */
 229         mtx_init(&sc->gic_mtx, "GICv3 lock", NULL, MTX_SPIN);
 230
 231         /*
 232          * Allocate array of struct resource.
 233          * One entry for Distributor and all remaining for Re-Distributor.
 234          */
 235         sc->gic_res = malloc(
 236             sizeof(*sc->gic_res) * (sc->gic_redists.nregions + 1),
 237             M_GIC_V3, M_WAITOK);
 238
 239         /* Now allocate corresponding resources */
 240         for (i = 0, rid = 0; i < (sc->gic_redists.nregions + 1); i++, rid++) {
 241                 sc->gic_res[rid] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 242                     &rid, RF_ACTIVE);
 243                 if (sc->gic_res[rid] == NULL)
 244                         return (ENXIO);
 245         }
 246
 247         /*
 248          * Distributor interface
 249          */
 250         sc->gic_dist = sc->gic_res[0];
 251
 252         /*
 253          * Re-Dristributor interface
 254          */
 255         /* Allocate space under region descriptions */
 256         sc->gic_redists.regions = malloc(
 257             sizeof(*sc->gic_redists.regions) * sc->gic_redists.nregions,
 258             M_GIC_V3, M_WAITOK);
 259
 260         /* Fill-up bus_space information for each region. */
 261         for (i = 0, rid = 1; i < sc->gic_redists.nregions; i++, rid++)
 262                 sc->gic_redists.regions[i] = sc->gic_res[rid];
 263
 264         /* Get the number of supported SPI interrupts */
 265         typer = gic_d_read(sc, 4, GICD_TYPER);
 266         sc->gic_nirqs = GICD_TYPER_I_NUM(typer);
 267         if (sc->gic_nirqs > GIC_I_NUM_MAX)
 268                 sc->gic_nirqs = GIC_I_NUM_MAX;
 269
 270         sc->gic_irqs = malloc(sizeof(*sc->gic_irqs) * sc->gic_nirqs,
 271             M_GIC_V3, M_WAITOK | M_ZERO);
 272         name = device_get_nameunit(dev);
 273         for (irq = 0; irq < sc->gic_nirqs; irq++) {
 274                 struct intr_irqsrc *isrc;
 275
 276                 sc->gic_irqs[irq].gi_irq = irq;
 277                 sc->gic_irqs[irq].gi_pol = INTR_POLARITY_CONFORM;
 278                 sc->gic_irqs[irq].gi_trig = INTR_TRIGGER_CONFORM;
 279
 280                 isrc = &sc->gic_irqs[irq].gi_isrc;
 281                 if (irq <= GIC_LAST_SGI) {
 282                         err = intr_isrc_register(isrc, sc->dev,
 283                             INTR_ISRCF_IPI, "%s,i%u", name, irq - GIC_FIRST_SGI);
 284                 } else if (irq <= GIC_LAST_PPI) {
 285                         err = intr_isrc_register(isrc, sc->dev,
 286                             INTR_ISRCF_PPI, "%s,p%u", name, irq - GIC_FIRST_PPI);
 287                 } else {
 288                         err = intr_isrc_register(isrc, sc->dev, 0,
 289                             "%s,s%u", name, irq - GIC_FIRST_SPI);
 290                 }
 291                 if (err != 0) {
 292                         /* XXX call intr_isrc_deregister() */
 293                         free(sc->gic_irqs, M_DEVBUF);
 294                         return (err);
 295                 }
 296         }
 297
 298         /* Get the number of supported interrupt identifier bits */
 299         sc->gic_idbits = GICD_TYPER_IDBITS(typer);
 300
 301         if (bootverbose) {
 302                 device_printf(dev, "SPIs: %u, IDs: %u\n",
 303                     sc->gic_nirqs, (1 << sc->gic_idbits) - 1);
 304         }
 305
 306         /* Train init sequence for boot CPU */
 307         for (init_func = gic_v3_primary_init; *init_func != NULL; init_func++) {
 308                 err = (*init_func)(sc);
 309                 if (err != 0)
 310                         return (err);
 311         }
 312
 313         return (0);
 314 }
 315
 316 int
 317 gic_v3_detach(device_t dev)
 318 {
 319         struct gic_v3_softc *sc;
 320         size_t i;
 321         int rid;
 322
 323         sc = device_get_softc(dev);
 324
 325         if (device_is_attached(dev)) {
 326                 /*
 327                  * XXX: We should probably deregister PIC
 328                  */
 329                 if (sc->gic_registered)
 330                         panic("Trying to detach registered PIC");
 331         }
 332         for (rid = 0; rid < (sc->gic_redists.nregions + 1); rid++)
 333                 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->gic_res[rid]);
 334
 335         for (i = 0; i < mp_ncpus; i++)
 336                 free(sc->gic_redists.pcpu[i], M_GIC_V3);
 337
 338         free(sc->gic_res, M_GIC_V3);
 339         free(sc->gic_redists.regions, M_GIC_V3);
 340
 341         return (0);
 342 }
 343
 344 static int
 345 gic_v3_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
 346 {
 347         struct gic_v3_softc *sc;
 348
 349         sc = device_get_softc(dev);
 350
 351         switch (which) {
 352         case GICV3_IVAR_NIRQS:
 353                 *result = sc->gic_nirqs;
 354                 return (0);
 355         case GICV3_IVAR_REDIST_VADDR:
 356                 *result = (uintptr_t)rman_get_virtual(
 357                     sc->gic_redists.pcpu[PCPU_GET(cpuid)]);
 358                 return (0);
 359         }
 360
 361         return (ENOENT);
 362 }
 363
 364 int
 365 arm_gic_v3_intr(void *arg)
 366 {
 367         struct gic_v3_softc *sc = arg;
 368         struct gic_v3_irqsrc *gi;
 369         struct intr_pic *pic;
 370         uint64_t active_irq;
 371         struct trapframe *tf;
 372         bool first;
 373
 374         first = true;
 375         pic = sc->gic_pic;
 376
 377         while (1) {
 378                 if (CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1) {
 379                         /*
 380                          * Hardware:            Cavium ThunderX
 381                          * Chip revision:       Pass 1.0 (early version)
 382                          *                      Pass 1.1 (production)
 383                          * ERRATUM:             22978, 23154
 384                          */
 385                         __asm __volatile(
 386                             "nop;nop;nop;nop;nop;nop;nop;nop;   \n"
 387                             "mrs %0, ICC_IAR1_EL1               \n"
 388                             "nop;nop;nop;nop;                   \n"
 389                             "dsb sy                             \n"
 390                             : "=&r" (active_irq));
 391                 } else {
 392                         active_irq = gic_icc_read(IAR1);
 393                 }
 394
 395                 if (active_irq >= GIC_FIRST_LPI) {
 396                         intr_child_irq_handler(pic, active_irq);
 397                         continue;
 398                 }
 399
 400                 if (__predict_false(active_irq >= sc->gic_nirqs))
 401                         return (FILTER_HANDLED);
 402
 403                 tf = curthread->td_intr_frame;
 404                 gi = &sc->gic_irqs[active_irq];
 405                 if (active_irq <= GIC_LAST_SGI) {
 406                         /* Call EOI for all IPI before dispatch. */
 407                         gic_icc_write(EOIR1, (uint64_t)active_irq);
 408 #ifdef SMP
 409                         intr_ipi_dispatch(sgi_to_ipi[gi->gi_irq], tf);
 410 #else
 411                         device_printf(sc->dev, "SGI %ju on UP system detected\n",
 412                             (uintmax_t)(active_irq - GIC_FIRST_SGI));
 413 #endif
 414                 } else if (active_irq >= GIC_FIRST_PPI &&
 415                     active_irq <= GIC_LAST_SPI) {
 416                         if (gi->gi_pol == INTR_TRIGGER_EDGE)
 417                                 gic_icc_write(EOIR1, gi->gi_irq);
 418
 419                         if (intr_isrc_dispatch(&gi->gi_isrc, tf) != 0) {
 420                                 if (gi->gi_pol != INTR_TRIGGER_EDGE)
 421                                         gic_icc_write(EOIR1, gi->gi_irq);
 422                                 gic_v3_disable_intr(sc->dev, &gi->gi_isrc);
 423                                 device_printf(sc->dev,
 424                                     "Stray irq %lu disabled\n", active_irq);
 425                         }
 426                 }
 427         }
 428 }
 429
 430 #ifdef FDT
 431 static int
 432 gic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp,
 433     enum intr_polarity *polp, enum intr_trigger *trigp)
 434 {
 435         u_int irq;
 436
 437         if (ncells < 3)
 438                 return (EINVAL);
 439
 440         /*
 441          * The 1st cell is the interrupt type:
 442          *      0 = SPI
 443          *      1 = PPI
 444          * The 2nd cell contains the interrupt number:
 445          *      [0 - 987] for SPI
 446          *      [0 -  15] for PPI
 447          * The 3rd cell is the flags, encoded as follows:
 448          *   bits[3:0] trigger type and level flags
 449          *      1 = edge triggered
 450          *      2 = edge triggered (PPI only)
 451          *      4 = level-sensitive
 452          *      8 = level-sensitive (PPI only)
 453          */
 454         switch (cells[0]) {
 455         case 0:
 456                 irq = GIC_FIRST_SPI + cells[1];
 457                 /* SPI irq is checked later. */
 458                 break;
 459         case 1:
 460                 irq = GIC_FIRST_PPI + cells[1];
 461                 if (irq > GIC_LAST_PPI) {
 462                         device_printf(dev, "unsupported PPI interrupt "
 463                             "number %u\n", cells[1]);
 464                         return (EINVAL);
 465                 }
 466                 break;
 467         default:
 468                 device_printf(dev, "unsupported interrupt type "
 469                     "configuration %u\n", cells[0]);
 470                 return (EINVAL);
 471         }
 472
 473         switch (cells[2] & 0xf) {
 474         case 1:
 475                 *trigp = INTR_TRIGGER_EDGE;
 476                 *polp = INTR_POLARITY_HIGH;
 477                 break;
 478         case 2:
 479                 *trigp = INTR_TRIGGER_EDGE;
 480                 *polp = INTR_POLARITY_LOW;
 481                 break;
 482         case 4:
 483                 *trigp = INTR_TRIGGER_LEVEL;
 484                 *polp = INTR_POLARITY_HIGH;
 485                 break;
 486         case 8:
 487                 *trigp = INTR_TRIGGER_LEVEL;
 488                 *polp = INTR_POLARITY_LOW;
 489                 break;
 490         default:
 491                 device_printf(dev, "unsupported trigger/polarity "
 492                     "configuration 0x%02x\n", cells[2]);
 493                 return (EINVAL);
 494         }
 495
 496         /* Check the interrupt is valid */
 497         if (irq >= GIC_FIRST_SPI && *polp != INTR_POLARITY_HIGH)
 498                 return (EINVAL);
 499
 500         *irqp = irq;
 501         return (0);
 502 }
 503 #endif
 504
 505 static int
 506 gic_map_msi(device_t dev, struct intr_map_data_msi *msi_data, u_int *irqp,
 507     enum intr_polarity *polp, enum intr_trigger *trigp)
 508 {
 509         struct gic_v3_irqsrc *gi;
 510
 511         /* SPI-mapped MSI */
 512         gi = (struct gic_v3_irqsrc *)msi_data->isrc;
 513         if (gi == NULL)
 514                 return (ENXIO);
 515
 516         *irqp = gi->gi_irq;
 517
 518         /* MSI/MSI-X interrupts are always edge triggered with high polarity */
 519         *polp = INTR_POLARITY_HIGH;
 520         *trigp = INTR_TRIGGER_EDGE;
 521
 522         return (0);
 523 }
 524
 525 static int
 526 do_gic_v3_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp,
 527     enum intr_polarity *polp, enum intr_trigger *trigp)
 528 {
 529         struct gic_v3_softc *sc;
 530         enum intr_polarity pol;
 531         enum intr_trigger trig;
 532         struct intr_map_data_msi *dam;
 533 #ifdef FDT
 534         struct intr_map_data_fdt *daf;
 535 #endif
 536         u_int irq;
 537
 538         sc = device_get_softc(dev);
 539
 540         switch (data->type) {
 541 #ifdef FDT
 542         case INTR_MAP_DATA_FDT:
 543                 daf = (struct intr_map_data_fdt *)data;
 544                 if (gic_map_fdt(dev, daf->ncells, daf->cells, &irq, &pol,
 545                     &trig) != 0)
 546                         return (EINVAL);
 547                 break;
 548 #endif
 549         case INTR_MAP_DATA_MSI:
 550                 /* SPI-mapped MSI */
 551                 dam = (struct intr_map_data_msi *)data;
 552                 if (gic_map_msi(dev, dam, &irq, &pol, &trig) != 0)
 553                         return (EINVAL);
 554                 break;
 555         default:
 556                 return (EINVAL);
 557         }
 558
 559         if (irq >= sc->gic_nirqs)
 560                 return (EINVAL);
 561         switch (pol) {
 562         case INTR_POLARITY_CONFORM:
 563         case INTR_POLARITY_LOW:
 564         case INTR_POLARITY_HIGH:
 565                 break;
 566         default:
 567                 return (EINVAL);
 568         }
 569         switch (trig) {
 570         case INTR_TRIGGER_CONFORM:
 571         case INTR_TRIGGER_EDGE:
 572         case INTR_TRIGGER_LEVEL:
 573                 break;
 574         default:
 575                 return (EINVAL);
 576         }
 577
 578         *irqp = irq;
 579         if (polp != NULL)
 580                 *polp = pol;
 581         if (trigp != NULL)
 582                 *trigp = trig;
 583         return (0);
 584 }
 585
 586 static int
 587 gic_v3_map_intr(device_t dev, struct intr_map_data *data,
 588     struct intr_irqsrc **isrcp)
 589 {
 590         struct gic_v3_softc *sc;
 591         int error;
 592         u_int irq;
 593
 594         error = do_gic_v3_map_intr(dev, data, &irq, NULL, NULL);
 595         if (error == 0) {
 596                 sc = device_get_softc(dev);
 597                 *isrcp = GIC_INTR_ISRC(sc, irq);
 598         }
 599         return (error);
 600 }
 601
 602 static int
 603 gic_v3_setup_intr(device_t dev, struct intr_irqsrc *isrc,
 604     struct resource *res, struct intr_map_data *data)
 605 {
 606         struct gic_v3_softc *sc = device_get_softc(dev);
 607         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 608         enum intr_trigger trig;
 609         enum intr_polarity pol;
 610         uint32_t reg;
 611         u_int irq;
 612         int error;
 613
 614         if (data == NULL)
 615                 return (ENOTSUP);
 616
 617         error = do_gic_v3_map_intr(dev, data, &irq, &pol, &trig);
 618         if (error != 0)
 619                 return (error);
 620
 621         if (gi->gi_irq != irq || pol == INTR_POLARITY_CONFORM ||
 622             trig == INTR_TRIGGER_CONFORM)
 623                 return (EINVAL);
 624
 625         /* Compare config if this is not first setup. */
 626         if (isrc->isrc_handlers != 0) {
 627                 if (pol != gi->gi_pol || trig != gi->gi_trig)
 628                         return (EINVAL);
 629                 else
 630                         return (0);
 631         }
 632
 633         gi->gi_pol = pol;
 634         gi->gi_trig = trig;
 635
 636         /*
 637          * XXX - In case that per CPU interrupt is going to be enabled in time
 638          *       when SMP is already started, we need some IPI call which
 639          *       enables it on others CPUs. Further, it's more complicated as
 640          *       pic_enable_source() and pic_disable_source() should act on
 641          *       per CPU basis only. Thus, it should be solved here somehow.
 642          */
 643         if (isrc->isrc_flags & INTR_ISRCF_PPI)
 644                 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
 645
 646         if (irq >= GIC_FIRST_PPI && irq <= GIC_LAST_SPI) {
 647                 mtx_lock_spin(&sc->gic_mtx);
 648
 649                 /* Set the trigger and polarity */
 650                 if (irq <= GIC_LAST_PPI)
 651                         reg = gic_r_read(sc, 4,
 652                             GICR_SGI_BASE_SIZE + GICD_ICFGR(irq));
 653                 else
 654                         reg = gic_d_read(sc, 4, GICD_ICFGR(irq));
 655                 if (trig == INTR_TRIGGER_LEVEL)
 656                         reg &= ~(2 << ((irq % 16) * 2));
 657                 else
 658                         reg |= 2 << ((irq % 16) * 2);
 659
 660                 if (irq <= GIC_LAST_PPI) {
 661                         gic_r_write(sc, 4,
 662                             GICR_SGI_BASE_SIZE + GICD_ICFGR(irq), reg);
 663                         gic_v3_wait_for_rwp(sc, REDIST);
 664                 } else {
 665                         gic_d_write(sc, 4, GICD_ICFGR(irq), reg);
 666                         gic_v3_wait_for_rwp(sc, DIST);
 667                 }
 668
 669                 mtx_unlock_spin(&sc->gic_mtx);
 670
 671                 gic_v3_bind_intr(dev, isrc);
 672         }
 673
 674         return (0);
 675 }
 676
 677 static int
 678 gic_v3_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
 679     struct resource *res, struct intr_map_data *data)
 680 {
 681         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 682
 683         if (isrc->isrc_handlers == 0) {
 684                 gi->gi_pol = INTR_POLARITY_CONFORM;
 685                 gi->gi_trig = INTR_TRIGGER_CONFORM;
 686         }
 687
 688         return (0);
 689 }
 690
 691 static void
 692 gic_v3_disable_intr(device_t dev, struct intr_irqsrc *isrc)
 693 {
 694         struct gic_v3_softc *sc;
 695         struct gic_v3_irqsrc *gi;
 696         u_int irq;
 697
 698         sc = device_get_softc(dev);
 699         gi = (struct gic_v3_irqsrc *)isrc;
 700         irq = gi->gi_irq;
 701
 702         if (irq <= GIC_LAST_PPI) {
 703                 /* SGIs and PPIs in corresponding Re-Distributor */
 704                 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ICENABLER(irq),
 705                     GICD_I_MASK(irq));
 706                 gic_v3_wait_for_rwp(sc, REDIST);
 707         } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) {
 708                 /* SPIs in distributor */
 709                 gic_d_write(sc, 4, GICD_ICENABLER(irq), GICD_I_MASK(irq));
 710                 gic_v3_wait_for_rwp(sc, DIST);
 711         } else
 712                 panic("%s: Unsupported IRQ %u", __func__, irq);
 713 }
 714
 715 static void
 716 gic_v3_enable_intr(device_t dev, struct intr_irqsrc *isrc)
 717 {
 718         struct gic_v3_softc *sc;
 719         struct gic_v3_irqsrc *gi;
 720         u_int irq;
 721
 722         sc = device_get_softc(dev);
 723         gi = (struct gic_v3_irqsrc *)isrc;
 724         irq = gi->gi_irq;
 725
 726         if (irq <= GIC_LAST_PPI) {
 727                 /* SGIs and PPIs in corresponding Re-Distributor */
 728                 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ISENABLER(irq),
 729                     GICD_I_MASK(irq));
 730                 gic_v3_wait_for_rwp(sc, REDIST);
 731         } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) {
 732                 /* SPIs in distributor */
 733                 gic_d_write(sc, 4, GICD_ISENABLER(irq), GICD_I_MASK(irq));
 734                 gic_v3_wait_for_rwp(sc, DIST);
 735         } else
 736                 panic("%s: Unsupported IRQ %u", __func__, irq);
 737 }
 738
 739 static void
 740 gic_v3_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
 741 {
 742         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 743
 744         gic_v3_disable_intr(dev, isrc);
 745         gic_icc_write(EOIR1, gi->gi_irq);
 746 }
 747
 748 static void
 749 gic_v3_post_ithread(device_t dev, struct intr_irqsrc *isrc)
 750 {
 751
 752         gic_v3_enable_intr(dev, isrc);
 753 }
 754
 755 static void
 756 gic_v3_post_filter(device_t dev, struct intr_irqsrc *isrc)
 757 {
 758         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 759
 760         if (gi->gi_pol == INTR_TRIGGER_EDGE)
 761                 return;
 762
 763         gic_icc_write(EOIR1, gi->gi_irq);
 764 }
 765
 766 static int
 767 gic_v3_bind_intr(device_t dev, struct intr_irqsrc *isrc)
 768 {
 769         struct gic_v3_softc *sc;
 770         struct gic_v3_irqsrc *gi;
 771         int cpu;
 772
 773         gi = (struct gic_v3_irqsrc *)isrc;
 774         if (gi->gi_irq <= GIC_LAST_PPI)
 775                 return (EINVAL);
 776
 777         KASSERT(gi->gi_irq >= GIC_FIRST_SPI && gi->gi_irq <= GIC_LAST_SPI,
 778             ("%s: Attempting to bind an invalid IRQ", __func__));
 779
 780         sc = device_get_softc(dev);
 781
 782         if (CPU_EMPTY(&isrc->isrc_cpu)) {
 783                 gic_irq_cpu = intr_irq_next_cpu(gic_irq_cpu, &all_cpus);
 784                 CPU_SETOF(gic_irq_cpu, &isrc->isrc_cpu);
 785                 gic_d_write(sc, 4, GICD_IROUTER(gi->gi_irq),
 786                     CPU_AFFINITY(gic_irq_cpu));
 787         } else {
 788                 /*
 789                  * We can only bind to a single CPU so select
 790                  * the first CPU found.
 791                  */
 792                 cpu = CPU_FFS(&isrc->isrc_cpu) - 1;
 793                 gic_d_write(sc, 4, GICD_IROUTER(gi->gi_irq), CPU_AFFINITY(cpu));
 794         }
 795
 796         return (0);
 797 }
 798
 799 #ifdef SMP
 800 static void
 801 gic_v3_init_secondary(device_t dev)
 802 {
 803         device_t child;
 804         struct gic_v3_softc *sc;
 805         gic_v3_initseq_t *init_func;
 806         struct intr_irqsrc *isrc;
 807         u_int cpu, irq;
 808         int err, i;
 809
 810         sc = device_get_softc(dev);
 811         cpu = PCPU_GET(cpuid);
 812
 813         /* Train init sequence for boot CPU */
 814         for (init_func = gic_v3_secondary_init; *init_func != NULL;
 815             init_func++) {
 816                 err = (*init_func)(sc);
 817                 if (err != 0) {
 818                         device_printf(dev,
 819                             "Could not initialize GIC for CPU%u\n", cpu);
 820                         return;
 821                 }
 822         }
 823
 824         /* Unmask attached SGI interrupts. */
 825         for (irq = GIC_FIRST_SGI; irq <= GIC_LAST_SGI; irq++) {
 826                 isrc = GIC_INTR_ISRC(sc, irq);
 827                 if (intr_isrc_init_on_cpu(isrc, cpu))
 828                         gic_v3_enable_intr(dev, isrc);
 829         }
 830
 831         /* Unmask attached PPI interrupts. */
 832         for (irq = GIC_FIRST_PPI; irq <= GIC_LAST_PPI; irq++) {
 833                 isrc = GIC_INTR_ISRC(sc, irq);
 834                 if (intr_isrc_init_on_cpu(isrc, cpu))
 835                         gic_v3_enable_intr(dev, isrc);
 836         }
 837
 838         for (i = 0; i < sc->gic_nchildren; i++) {
 839                 child = sc->gic_children[i];
 840                 PIC_INIT_SECONDARY(child);
 841         }
 842 }
 843
 844 static void
 845 gic_v3_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus,
 846     u_int ipi)
 847 {
 848         struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
 849         uint64_t aff, val, irq;
 850         int i;
 851
 852 #define GIC_AFF_MASK    (CPU_AFF3_MASK | CPU_AFF2_MASK | CPU_AFF1_MASK)
 853 #define GIC_AFFINITY(i) (CPU_AFFINITY(i) & GIC_AFF_MASK)
 854         aff = GIC_AFFINITY(0);
 855         irq = gi->gi_irq;
 856         val = 0;
 857
 858         /* Iterate through all CPUs in set */
 859         for (i = 0; i < mp_ncpus; i++) {
 860                 /* Move to the next affinity group */
 861                 if (aff != GIC_AFFINITY(i)) {
 862                         /* Send the IPI */
 863                         if (val != 0) {
 864                                 gic_icc_write(SGI1R, val);
 865                                 val = 0;
 866                         }
 867                         aff = GIC_AFFINITY(i);
 868                 }
 869
 870                 /* Send the IPI to this cpu */
 871                 if (CPU_ISSET(i, &cpus)) {
 872 #define ICC_SGI1R_AFFINITY(aff)                                 \
 873     (((uint64_t)CPU_AFF3(aff) << ICC_SGI1R_EL1_AFF3_SHIFT) |    \
 874      ((uint64_t)CPU_AFF2(aff) << ICC_SGI1R_EL1_AFF2_SHIFT) |    \
 875      ((uint64_t)CPU_AFF1(aff) << ICC_SGI1R_EL1_AFF1_SHIFT))
 876                         /* Set the affinity when the first at this level */
 877                         if (val == 0)
 878                                 val = ICC_SGI1R_AFFINITY(aff) |
 879                                     irq << ICC_SGI1R_EL1_SGIID_SHIFT;
 880                         /* Set the bit to send the IPI to te CPU */
 881                         val |= 1 << CPU_AFF0(CPU_AFFINITY(i));
 882                 }
 883         }
 884
 885         /* Send the IPI to the last cpu affinity group */
 886         if (val != 0)
 887                 gic_icc_write(SGI1R, val);
 888 #undef GIC_AFF_MASK
 889 #undef GIC_AFFINITY
 890 }
 891
 892 static int
 893 gic_v3_ipi_setup(device_t dev, u_int ipi, struct intr_irqsrc **isrcp)
 894 {
 895         struct intr_irqsrc *isrc;
 896         struct gic_v3_softc *sc = device_get_softc(dev);
 897
 898         if (sgi_first_unused > GIC_LAST_SGI)
 899                 return (ENOSPC);
 900
 901         isrc = GIC_INTR_ISRC(sc, sgi_first_unused);
 902         sgi_to_ipi[sgi_first_unused++] = ipi;
 903
 904         CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
 905
 906         *isrcp = isrc;
 907         return (0);
 908 }
 909 #endif /* SMP */
 910
 911 /*
 912  * Helper routines
 913  */
 914 static void
 915 gic_v3_wait_for_rwp(struct gic_v3_softc *sc, enum gic_v3_xdist xdist)
 916 {
 917         struct resource *res;
 918         u_int cpuid;
 919         size_t us_left = 1000000;
 920
 921         cpuid = PCPU_GET(cpuid);
 922
 923         switch (xdist) {
 924         case DIST:
 925                 res = sc->gic_dist;
 926                 break;
 927         case REDIST:
 928                 res = sc->gic_redists.pcpu[cpuid];
 929                 break;
 930         default:
 931                 KASSERT(0, ("%s: Attempt to wait for unknown RWP", __func__));
 932                 return;
 933         }
 934
 935         while ((bus_read_4(res, GICD_CTLR) & GICD_CTLR_RWP) != 0) {
 936                 DELAY(1);
 937                 if (us_left-- == 0)
 938                         panic("GICD Register write pending for too long");
 939         }
 940 }
 941
 942 /* CPU interface. */
 943 static __inline void
 944 gic_v3_cpu_priority(uint64_t mask)
 945 {
 946
 947         /* Set prority mask */
 948         gic_icc_write(PMR, mask & ICC_PMR_EL1_PRIO_MASK);
 949 }
 950
 951 static int
 952 gic_v3_cpu_enable_sre(struct gic_v3_softc *sc)
 953 {
 954         uint64_t sre;
 955         u_int cpuid;
 956
 957         cpuid = PCPU_GET(cpuid);
 958         /*
 959          * Set the SRE bit to enable access to GIC CPU interface
 960          * via system registers.
 961          */
 962         sre = READ_SPECIALREG(icc_sre_el1);
 963         sre |= ICC_SRE_EL1_SRE;
 964         WRITE_SPECIALREG(icc_sre_el1, sre);
 965         isb();
 966         /*
 967          * Now ensure that the bit is set.
 968          */
 969         sre = READ_SPECIALREG(icc_sre_el1);
 970         if ((sre & ICC_SRE_EL1_SRE) == 0) {
 971                 /* We are done. This was disabled in EL2 */
 972                 device_printf(sc->dev, "ERROR: CPU%u cannot enable CPU interface "
 973                     "via system registers\n", cpuid);
 974                 return (ENXIO);
 975         } else if (bootverbose) {
 976                 device_printf(sc->dev,
 977                     "CPU%u enabled CPU interface via system registers\n",
 978                     cpuid);
 979         }
 980
 981         return (0);
 982 }
 983
 984 static int
 985 gic_v3_cpu_init(struct gic_v3_softc *sc)
 986 {
 987         int err;
 988
 989         /* Enable access to CPU interface via system registers */
 990         err = gic_v3_cpu_enable_sre(sc);
 991         if (err != 0)
 992                 return (err);
 993         /* Priority mask to minimum - accept all interrupts */
 994         gic_v3_cpu_priority(GIC_PRIORITY_MIN);
 995         /* Disable EOI mode */
 996         gic_icc_clear(CTLR, ICC_CTLR_EL1_EOIMODE);
 997         /* Enable group 1 (insecure) interrups */
 998         gic_icc_set(IGRPEN1, ICC_IGRPEN0_EL1_EN);
 999
1000         return (0);
1001 }
1002
1003 /* Distributor */
1004 static int
1005 gic_v3_dist_init(struct gic_v3_softc *sc)
1006 {
1007         uint64_t aff;
1008         u_int i;
1009
1010         /*
1011          * 1. Disable the Distributor
1012          */
1013         gic_d_write(sc, 4, GICD_CTLR, 0);
1014         gic_v3_wait_for_rwp(sc, DIST);
1015
1016         /*
1017          * 2. Configure the Distributor
1018          */
1019         /* Set all global interrupts to be level triggered, active low. */
1020         for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ICFGRn)
1021                 gic_d_write(sc, 4, GICD_ICFGR(i), 0x00000000);
1022
1023         /* Set priority to all shared interrupts */
1024         for (i = GIC_FIRST_SPI;
1025             i < sc->gic_nirqs; i += GICD_I_PER_IPRIORITYn) {
1026                 /* Set highest priority */
1027                 gic_d_write(sc, 4, GICD_IPRIORITYR(i), GIC_PRIORITY_MAX);
1028         }
1029
1030         /*
1031          * Disable all interrupts. Leave PPI and SGIs as they are enabled in
1032          * Re-Distributor registers.
1033          */
1034         for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ISENABLERn)
1035                 gic_d_write(sc, 4, GICD_ICENABLER(i), 0xFFFFFFFF);
1036
1037         gic_v3_wait_for_rwp(sc, DIST);
1038
1039         /*
1040          * 3. Enable Distributor
1041          */
1042         /* Enable Distributor with ARE, Group 1 */
1043         gic_d_write(sc, 4, GICD_CTLR, GICD_CTLR_ARE_NS | GICD_CTLR_G1A |
1044             GICD_CTLR_G1);
1045
1046         /*
1047          * 4. Route all interrupts to boot CPU.
1048          */
1049         aff = CPU_AFFINITY(0);
1050         for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i++)
1051                 gic_d_write(sc, 4, GICD_IROUTER(i), aff);
1052
1053         return (0);
1054 }
1055
1056 /* Re-Distributor */
1057 static int
1058 gic_v3_redist_alloc(struct gic_v3_softc *sc)
1059 {
1060         u_int cpuid;
1061
1062         /* Allocate struct resource for all CPU's Re-Distributor registers */
1063         for (cpuid = 0; cpuid < mp_ncpus; cpuid++)
1064                 if (CPU_ISSET(cpuid, &all_cpus) != 0)
1065                         sc->gic_redists.pcpu[cpuid] =
1066                                 malloc(sizeof(*sc->gic_redists.pcpu[0]),
1067                                     M_GIC_V3, M_WAITOK);
1068                 else
1069                         sc->gic_redists.pcpu[cpuid] = NULL;
1070         return (0);
1071 }
1072
1073 static int
1074 gic_v3_redist_find(struct gic_v3_softc *sc)
1075 {
1076         struct resource r_res;
1077         bus_space_handle_t r_bsh;
1078         uint64_t aff;
1079         uint64_t typer;
1080         uint32_t pidr2;
1081         u_int cpuid;
1082         size_t i;
1083
1084         cpuid = PCPU_GET(cpuid);
1085
1086         aff = CPU_AFFINITY(cpuid);
1087         /* Affinity in format for comparison with typer */
1088         aff = (CPU_AFF3(aff) << 24) | (CPU_AFF2(aff) << 16) |
1089             (CPU_AFF1(aff) << 8) | CPU_AFF0(aff);
1090
1091         if (bootverbose) {
1092                 device_printf(sc->dev,
1093                     "Start searching for Re-Distributor\n");
1094         }
1095         /* Iterate through Re-Distributor regions */
1096         for (i = 0; i < sc->gic_redists.nregions; i++) {
1097                 /* Take a copy of the region's resource */
1098                 r_res = *sc->gic_redists.regions[i];
1099                 r_bsh = rman_get_bushandle(&r_res);
1100
1101                 pidr2 = bus_read_4(&r_res, GICR_PIDR2);
1102                 switch (pidr2 & GICR_PIDR2_ARCH_MASK) {
1103                 case GICR_PIDR2_ARCH_GICv3: /* fall through */
1104                 case GICR_PIDR2_ARCH_GICv4:
1105                         break;
1106                 default:
1107                         device_printf(sc->dev,
1108                             "No Re-Distributor found for CPU%u\n", cpuid);
1109                         return (ENODEV);
1110                 }
1111
1112                 do {
1113                         typer = bus_read_8(&r_res, GICR_TYPER);
1114                         if ((typer >> GICR_TYPER_AFF_SHIFT) == aff) {
1115                                 KASSERT(sc->gic_redists.pcpu[cpuid] != NULL,
1116                                     ("Invalid pointer to per-CPU redistributor"));
1117                                 /* Copy res contents to its final destination */
1118                                 *sc->gic_redists.pcpu[cpuid] = r_res;
1119                                 if (bootverbose) {
1120                                         device_printf(sc->dev,
1121                                             "CPU%u Re-Distributor has been found\n",
1122                                             cpuid);
1123                                 }
1124                                 return (0);
1125                         }
1126
1127                         r_bsh += (GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);
1128                         if ((typer & GICR_TYPER_VLPIS) != 0) {
1129                                 r_bsh +=
1130                                     (GICR_VLPI_BASE_SIZE + GICR_RESERVED_SIZE);
1131                         }
1132
1133                         rman_set_bushandle(&r_res, r_bsh);
1134                 } while ((typer & GICR_TYPER_LAST) == 0);
1135         }
1136
1137         device_printf(sc->dev, "No Re-Distributor found for CPU%u\n", cpuid);
1138         return (ENXIO);
1139 }
1140
1141 static int
1142 gic_v3_redist_wake(struct gic_v3_softc *sc)
1143 {
1144         uint32_t waker;
1145         size_t us_left = 1000000;
1146
1147         waker = gic_r_read(sc, 4, GICR_WAKER);
1148         /* Wake up Re-Distributor for this CPU */
1149         waker &= ~GICR_WAKER_PS;
1150         gic_r_write(sc, 4, GICR_WAKER, waker);
1151         /*
1152          * When clearing ProcessorSleep bit it is required to wait for
1153          * ChildrenAsleep to become zero following the processor power-on.
1154          */
1155         while ((gic_r_read(sc, 4, GICR_WAKER) & GICR_WAKER_CA) != 0) {
1156                 DELAY(1);
1157                 if (us_left-- == 0) {
1158                         panic("Could not wake Re-Distributor for CPU%u",
1159                             PCPU_GET(cpuid));
1160                 }
1161         }
1162
1163         if (bootverbose) {
1164                 device_printf(sc->dev, "CPU%u Re-Distributor woke up\n",
1165                     PCPU_GET(cpuid));
1166         }
1167
1168         return (0);
1169 }
1170
1171 static int
1172 gic_v3_redist_init(struct gic_v3_softc *sc)
1173 {
1174         int err;
1175         size_t i;
1176
1177         err = gic_v3_redist_find(sc);
1178         if (err != 0)
1179                 return (err);
1180
1181         err = gic_v3_redist_wake(sc);
1182         if (err != 0)
1183                 return (err);
1184
1185         /* Disable SPIs */
1186         gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ICENABLER0,
1187             GICR_I_ENABLER_PPI_MASK);
1188         /* Enable SGIs */
1189         gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ISENABLER0,
1190             GICR_I_ENABLER_SGI_MASK);
1191
1192         /* Set priority for SGIs and PPIs */
1193         for (i = 0; i <= GIC_LAST_PPI; i += GICR_I_PER_IPRIORITYn) {
1194                 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_IPRIORITYR(i),
1195                     GIC_PRIORITY_MAX);
1196         }
1197
1198         gic_v3_wait_for_rwp(sc, REDIST);
1199
1200         return (0);
1201 }