2 * Copyright (c) 2015-2016 The FreeBSD Foundation
5 * This software was developed by Andrew Turner under
6 * the sponsorship of the FreeBSD Foundation.
8 * This software was developed by Semihalf under
9 * the sponsorship of the FreeBSD Foundation.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #include "opt_platform.h"
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/bitstring.h>
43 #include <sys/kernel.h>
45 #include <sys/malloc.h>
46 #include <sys/module.h>
50 #include <sys/cpuset.h>
52 #include <sys/mutex.h>
58 #include <machine/bus.h>
59 #include <machine/cpu.h>
60 #include <machine/intr.h>
63 #include <dev/fdt/fdt_intr.h>
64 #include <dev/ofw/ofw_bus_subr.h>
68 #include <contrib/dev/acpica/include/acpi.h>
69 #include <dev/acpica/acpivar.h>
74 #include <arm/arm/gic_common.h>
75 #include "gic_v3_reg.h"
76 #include "gic_v3_var.h"
78 static bus_get_domain_t gic_v3_get_domain;
79 static bus_read_ivar_t gic_v3_read_ivar;
81 static pic_disable_intr_t gic_v3_disable_intr;
82 static pic_enable_intr_t gic_v3_enable_intr;
83 static pic_map_intr_t gic_v3_map_intr;
84 static pic_setup_intr_t gic_v3_setup_intr;
85 static pic_teardown_intr_t gic_v3_teardown_intr;
86 static pic_post_filter_t gic_v3_post_filter;
87 static pic_post_ithread_t gic_v3_post_ithread;
88 static pic_pre_ithread_t gic_v3_pre_ithread;
89 static pic_bind_intr_t gic_v3_bind_intr;
91 static pic_init_secondary_t gic_v3_init_secondary;
92 static pic_ipi_send_t gic_v3_ipi_send;
93 static pic_ipi_setup_t gic_v3_ipi_setup;
96 static u_int gic_irq_cpu;
98 static u_int sgi_to_ipi[GIC_LAST_SGI - GIC_FIRST_SGI + 1];
99 static u_int sgi_first_unused = GIC_FIRST_SGI;
102 static device_method_t gic_v3_methods[] = {
103 /* Device interface */
104 DEVMETHOD(device_detach, gic_v3_detach),
107 DEVMETHOD(bus_get_domain, gic_v3_get_domain),
108 DEVMETHOD(bus_read_ivar, gic_v3_read_ivar),
110 /* Interrupt controller interface */
111 DEVMETHOD(pic_disable_intr, gic_v3_disable_intr),
112 DEVMETHOD(pic_enable_intr, gic_v3_enable_intr),
113 DEVMETHOD(pic_map_intr, gic_v3_map_intr),
114 DEVMETHOD(pic_setup_intr, gic_v3_setup_intr),
115 DEVMETHOD(pic_teardown_intr, gic_v3_teardown_intr),
116 DEVMETHOD(pic_post_filter, gic_v3_post_filter),
117 DEVMETHOD(pic_post_ithread, gic_v3_post_ithread),
118 DEVMETHOD(pic_pre_ithread, gic_v3_pre_ithread),
120 DEVMETHOD(pic_bind_intr, gic_v3_bind_intr),
121 DEVMETHOD(pic_init_secondary, gic_v3_init_secondary),
122 DEVMETHOD(pic_ipi_send, gic_v3_ipi_send),
123 DEVMETHOD(pic_ipi_setup, gic_v3_ipi_setup),
130 DEFINE_CLASS_0(gic, gic_v3_driver, gic_v3_methods,
131 sizeof(struct gic_v3_softc));
134 * Driver-specific definitions.
136 MALLOC_DEFINE(M_GIC_V3, "GICv3", GIC_V3_DEVSTR);
139 * Helper functions and definitions.
141 /* Destination registers, either Distributor or Re-Distributor */
147 struct gic_v3_irqsrc {
148 struct intr_irqsrc gi_isrc;
150 enum intr_polarity gi_pol;
151 enum intr_trigger gi_trig;
154 /* Helper routines starting with gic_v3_ */
155 static int gic_v3_dist_init(struct gic_v3_softc *);
156 static int gic_v3_redist_alloc(struct gic_v3_softc *);
157 static int gic_v3_redist_find(struct gic_v3_softc *);
158 static int gic_v3_redist_init(struct gic_v3_softc *);
159 static int gic_v3_cpu_init(struct gic_v3_softc *);
160 static void gic_v3_wait_for_rwp(struct gic_v3_softc *, enum gic_v3_xdist);
162 /* A sequence of init functions for primary (boot) CPU */
163 typedef int (*gic_v3_initseq_t) (struct gic_v3_softc *);
164 /* Primary CPU initialization sequence */
165 static gic_v3_initseq_t gic_v3_primary_init[] = {
174 /* Secondary CPU initialization sequence */
175 static gic_v3_initseq_t gic_v3_secondary_init[] = {
183 gic_r_read_4(device_t dev, bus_size_t offset)
185 struct gic_v3_softc *sc;
187 sc = device_get_softc(dev);
188 return (bus_read_4(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset));
192 gic_r_read_8(device_t dev, bus_size_t offset)
194 struct gic_v3_softc *sc;
196 sc = device_get_softc(dev);
197 return (bus_read_8(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset));
201 gic_r_write_4(device_t dev, bus_size_t offset, uint32_t val)
203 struct gic_v3_softc *sc;
205 sc = device_get_softc(dev);
206 bus_write_4(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset, val);
210 gic_r_write_8(device_t dev, bus_size_t offset, uint64_t val)
212 struct gic_v3_softc *sc;
214 sc = device_get_softc(dev);
215 bus_write_8(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset, val);
222 gic_v3_attach(device_t dev)
224 struct gic_v3_softc *sc;
225 gic_v3_initseq_t *init_func;
233 sc = device_get_softc(dev);
234 sc->gic_registered = FALSE;
238 /* Initialize mutex */
239 mtx_init(&sc->gic_mtx, "GICv3 lock", NULL, MTX_SPIN);
242 * Allocate array of struct resource.
243 * One entry for Distributor and all remaining for Re-Distributor.
245 sc->gic_res = malloc(
246 sizeof(*sc->gic_res) * (sc->gic_redists.nregions + 1),
249 /* Now allocate corresponding resources */
250 for (i = 0, rid = 0; i < (sc->gic_redists.nregions + 1); i++, rid++) {
251 sc->gic_res[rid] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
253 if (sc->gic_res[rid] == NULL)
258 * Distributor interface
260 sc->gic_dist = sc->gic_res[0];
263 * Re-Dristributor interface
265 /* Allocate space under region descriptions */
266 sc->gic_redists.regions = malloc(
267 sizeof(*sc->gic_redists.regions) * sc->gic_redists.nregions,
270 /* Fill-up bus_space information for each region. */
271 for (i = 0, rid = 1; i < sc->gic_redists.nregions; i++, rid++)
272 sc->gic_redists.regions[i] = sc->gic_res[rid];
274 /* Get the number of supported SPI interrupts */
275 typer = gic_d_read(sc, 4, GICD_TYPER);
276 sc->gic_nirqs = GICD_TYPER_I_NUM(typer);
277 if (sc->gic_nirqs > GIC_I_NUM_MAX)
278 sc->gic_nirqs = GIC_I_NUM_MAX;
280 sc->gic_irqs = malloc(sizeof(*sc->gic_irqs) * sc->gic_nirqs,
281 M_GIC_V3, M_WAITOK | M_ZERO);
282 name = device_get_nameunit(dev);
283 for (irq = 0; irq < sc->gic_nirqs; irq++) {
284 struct intr_irqsrc *isrc;
286 sc->gic_irqs[irq].gi_irq = irq;
287 sc->gic_irqs[irq].gi_pol = INTR_POLARITY_CONFORM;
288 sc->gic_irqs[irq].gi_trig = INTR_TRIGGER_CONFORM;
290 isrc = &sc->gic_irqs[irq].gi_isrc;
291 if (irq <= GIC_LAST_SGI) {
292 err = intr_isrc_register(isrc, sc->dev,
293 INTR_ISRCF_IPI, "%s,i%u", name, irq - GIC_FIRST_SGI);
294 } else if (irq <= GIC_LAST_PPI) {
295 err = intr_isrc_register(isrc, sc->dev,
296 INTR_ISRCF_PPI, "%s,p%u", name, irq - GIC_FIRST_PPI);
298 err = intr_isrc_register(isrc, sc->dev, 0,
299 "%s,s%u", name, irq - GIC_FIRST_SPI);
302 /* XXX call intr_isrc_deregister() */
303 free(sc->gic_irqs, M_DEVBUF);
309 * Read the Peripheral ID2 register. This is an implementation
310 * defined register, but seems to be implemented in all GICv3
311 * parts and Linux expects it to be there.
313 sc->gic_pidr2 = gic_d_read(sc, 4, GICD_PIDR2);
315 /* Get the number of supported interrupt identifier bits */
316 sc->gic_idbits = GICD_TYPER_IDBITS(typer);
319 device_printf(dev, "SPIs: %u, IDs: %u\n",
320 sc->gic_nirqs, (1 << sc->gic_idbits) - 1);
323 /* Train init sequence for boot CPU */
324 for (init_func = gic_v3_primary_init; *init_func != NULL; init_func++) {
325 err = (*init_func)(sc);
334 gic_v3_detach(device_t dev)
336 struct gic_v3_softc *sc;
340 sc = device_get_softc(dev);
342 if (device_is_attached(dev)) {
344 * XXX: We should probably deregister PIC
346 if (sc->gic_registered)
347 panic("Trying to detach registered PIC");
349 for (rid = 0; rid < (sc->gic_redists.nregions + 1); rid++)
350 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->gic_res[rid]);
352 for (i = 0; i <= mp_maxid; i++)
353 free(sc->gic_redists.pcpu[i], M_GIC_V3);
355 free(sc->gic_res, M_GIC_V3);
356 free(sc->gic_redists.regions, M_GIC_V3);
362 gic_v3_get_domain(device_t dev, device_t child, int *domain)
364 struct gic_v3_devinfo *di;
366 di = device_get_ivars(child);
367 if (di->gic_domain < 0)
370 *domain = di->gic_domain;
375 gic_v3_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
377 struct gic_v3_softc *sc;
379 sc = device_get_softc(dev);
382 case GICV3_IVAR_NIRQS:
383 *result = (NIRQ - sc->gic_nirqs) / sc->gic_nchildren;
385 case GICV3_IVAR_REDIST_VADDR:
386 *result = (uintptr_t)rman_get_virtual(
387 sc->gic_redists.pcpu[PCPU_GET(cpuid)]);
389 case GIC_IVAR_HW_REV:
391 GICR_PIDR2_ARCH(sc->gic_pidr2) == GICR_PIDR2_ARCH_GICv3 ||
392 GICR_PIDR2_ARCH(sc->gic_pidr2) == GICR_PIDR2_ARCH_GICv4,
393 ("gic_v3_read_ivar: Invalid GIC architecture: %d (%.08X)",
394 GICR_PIDR2_ARCH(sc->gic_pidr2), sc->gic_pidr2));
395 *result = GICR_PIDR2_ARCH(sc->gic_pidr2);
398 KASSERT(sc->gic_bus != GIC_BUS_UNKNOWN,
399 ("gic_v3_read_ivar: Unknown bus type"));
400 KASSERT(sc->gic_bus <= GIC_BUS_MAX,
401 ("gic_v3_read_ivar: Invalid bus type %u", sc->gic_bus));
402 *result = sc->gic_bus;
410 arm_gic_v3_intr(void *arg)
412 struct gic_v3_softc *sc = arg;
413 struct gic_v3_irqsrc *gi;
414 struct intr_pic *pic;
416 struct trapframe *tf;
421 if (CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1) {
423 * Hardware: Cavium ThunderX
424 * Chip revision: Pass 1.0 (early version)
425 * Pass 1.1 (production)
426 * ERRATUM: 22978, 23154
429 "nop;nop;nop;nop;nop;nop;nop;nop; \n"
430 "mrs %0, ICC_IAR1_EL1 \n"
431 "nop;nop;nop;nop; \n"
433 : "=&r" (active_irq));
435 active_irq = gic_icc_read(IAR1);
438 if (active_irq >= GIC_FIRST_LPI) {
439 intr_child_irq_handler(pic, active_irq);
443 if (__predict_false(active_irq >= sc->gic_nirqs))
444 return (FILTER_HANDLED);
446 tf = curthread->td_intr_frame;
447 gi = &sc->gic_irqs[active_irq];
448 if (active_irq <= GIC_LAST_SGI) {
449 /* Call EOI for all IPI before dispatch. */
450 gic_icc_write(EOIR1, (uint64_t)active_irq);
452 intr_ipi_dispatch(sgi_to_ipi[gi->gi_irq], tf);
454 device_printf(sc->dev, "SGI %ju on UP system detected\n",
455 (uintmax_t)(active_irq - GIC_FIRST_SGI));
457 } else if (active_irq >= GIC_FIRST_PPI &&
458 active_irq <= GIC_LAST_SPI) {
459 if (gi->gi_trig == INTR_TRIGGER_EDGE)
460 gic_icc_write(EOIR1, gi->gi_irq);
462 if (intr_isrc_dispatch(&gi->gi_isrc, tf) != 0) {
463 if (gi->gi_trig != INTR_TRIGGER_EDGE)
464 gic_icc_write(EOIR1, gi->gi_irq);
465 gic_v3_disable_intr(sc->dev, &gi->gi_isrc);
466 device_printf(sc->dev,
467 "Stray irq %lu disabled\n", active_irq);
475 gic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp,
476 enum intr_polarity *polp, enum intr_trigger *trigp)
484 * The 1st cell is the interrupt type:
487 * The 2nd cell contains the interrupt number:
490 * The 3rd cell is the flags, encoded as follows:
491 * bits[3:0] trigger type and level flags
493 * 2 = edge triggered (PPI only)
494 * 4 = level-sensitive
495 * 8 = level-sensitive (PPI only)
499 irq = GIC_FIRST_SPI + cells[1];
500 /* SPI irq is checked later. */
503 irq = GIC_FIRST_PPI + cells[1];
504 if (irq > GIC_LAST_PPI) {
505 device_printf(dev, "unsupported PPI interrupt "
506 "number %u\n", cells[1]);
511 device_printf(dev, "unsupported interrupt type "
512 "configuration %u\n", cells[0]);
516 switch (cells[2] & FDT_INTR_MASK) {
517 case FDT_INTR_EDGE_RISING:
518 *trigp = INTR_TRIGGER_EDGE;
519 *polp = INTR_POLARITY_HIGH;
521 case FDT_INTR_EDGE_FALLING:
522 *trigp = INTR_TRIGGER_EDGE;
523 *polp = INTR_POLARITY_LOW;
525 case FDT_INTR_LEVEL_HIGH:
526 *trigp = INTR_TRIGGER_LEVEL;
527 *polp = INTR_POLARITY_HIGH;
529 case FDT_INTR_LEVEL_LOW:
530 *trigp = INTR_TRIGGER_LEVEL;
531 *polp = INTR_POLARITY_LOW;
534 device_printf(dev, "unsupported trigger/polarity "
535 "configuration 0x%02x\n", cells[2]);
539 /* Check the interrupt is valid */
540 if (irq >= GIC_FIRST_SPI && *polp != INTR_POLARITY_HIGH)
549 gic_map_msi(device_t dev, struct intr_map_data_msi *msi_data, u_int *irqp,
550 enum intr_polarity *polp, enum intr_trigger *trigp)
552 struct gic_v3_irqsrc *gi;
555 gi = (struct gic_v3_irqsrc *)msi_data->isrc;
561 /* MSI/MSI-X interrupts are always edge triggered with high polarity */
562 *polp = INTR_POLARITY_HIGH;
563 *trigp = INTR_TRIGGER_EDGE;
569 do_gic_v3_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp,
570 enum intr_polarity *polp, enum intr_trigger *trigp)
572 struct gic_v3_softc *sc;
573 enum intr_polarity pol;
574 enum intr_trigger trig;
575 struct intr_map_data_msi *dam;
577 struct intr_map_data_fdt *daf;
580 struct intr_map_data_acpi *daa;
584 sc = device_get_softc(dev);
586 switch (data->type) {
588 case INTR_MAP_DATA_FDT:
589 daf = (struct intr_map_data_fdt *)data;
590 if (gic_map_fdt(dev, daf->ncells, daf->cells, &irq, &pol,
596 case INTR_MAP_DATA_ACPI:
597 daa = (struct intr_map_data_acpi *)data;
603 case INTR_MAP_DATA_MSI:
605 dam = (struct intr_map_data_msi *)data;
606 if (gic_map_msi(dev, dam, &irq, &pol, &trig) != 0)
613 if (irq >= sc->gic_nirqs)
616 case INTR_POLARITY_CONFORM:
617 case INTR_POLARITY_LOW:
618 case INTR_POLARITY_HIGH:
624 case INTR_TRIGGER_CONFORM:
625 case INTR_TRIGGER_EDGE:
626 case INTR_TRIGGER_LEVEL:
641 gic_v3_map_intr(device_t dev, struct intr_map_data *data,
642 struct intr_irqsrc **isrcp)
644 struct gic_v3_softc *sc;
648 error = do_gic_v3_map_intr(dev, data, &irq, NULL, NULL);
650 sc = device_get_softc(dev);
651 *isrcp = GIC_INTR_ISRC(sc, irq);
657 gic_v3_setup_intr(device_t dev, struct intr_irqsrc *isrc,
658 struct resource *res, struct intr_map_data *data)
660 struct gic_v3_softc *sc = device_get_softc(dev);
661 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
662 enum intr_trigger trig;
663 enum intr_polarity pol;
671 error = do_gic_v3_map_intr(dev, data, &irq, &pol, &trig);
675 if (gi->gi_irq != irq || pol == INTR_POLARITY_CONFORM ||
676 trig == INTR_TRIGGER_CONFORM)
679 /* Compare config if this is not first setup. */
680 if (isrc->isrc_handlers != 0) {
681 if (pol != gi->gi_pol || trig != gi->gi_trig)
691 * XXX - In case that per CPU interrupt is going to be enabled in time
692 * when SMP is already started, we need some IPI call which
693 * enables it on others CPUs. Further, it's more complicated as
694 * pic_enable_source() and pic_disable_source() should act on
695 * per CPU basis only. Thus, it should be solved here somehow.
697 if (isrc->isrc_flags & INTR_ISRCF_PPI)
698 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
700 if (irq >= GIC_FIRST_PPI && irq <= GIC_LAST_SPI) {
701 mtx_lock_spin(&sc->gic_mtx);
703 /* Set the trigger and polarity */
704 if (irq <= GIC_LAST_PPI)
705 reg = gic_r_read(sc, 4,
706 GICR_SGI_BASE_SIZE + GICD_ICFGR(irq));
708 reg = gic_d_read(sc, 4, GICD_ICFGR(irq));
709 if (trig == INTR_TRIGGER_LEVEL)
710 reg &= ~(2 << ((irq % 16) * 2));
712 reg |= 2 << ((irq % 16) * 2);
714 if (irq <= GIC_LAST_PPI) {
716 GICR_SGI_BASE_SIZE + GICD_ICFGR(irq), reg);
717 gic_v3_wait_for_rwp(sc, REDIST);
719 gic_d_write(sc, 4, GICD_ICFGR(irq), reg);
720 gic_v3_wait_for_rwp(sc, DIST);
723 mtx_unlock_spin(&sc->gic_mtx);
725 gic_v3_bind_intr(dev, isrc);
732 gic_v3_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
733 struct resource *res, struct intr_map_data *data)
735 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
737 if (isrc->isrc_handlers == 0) {
738 gi->gi_pol = INTR_POLARITY_CONFORM;
739 gi->gi_trig = INTR_TRIGGER_CONFORM;
746 gic_v3_disable_intr(device_t dev, struct intr_irqsrc *isrc)
748 struct gic_v3_softc *sc;
749 struct gic_v3_irqsrc *gi;
752 sc = device_get_softc(dev);
753 gi = (struct gic_v3_irqsrc *)isrc;
756 if (irq <= GIC_LAST_PPI) {
757 /* SGIs and PPIs in corresponding Re-Distributor */
758 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ICENABLER(irq),
760 gic_v3_wait_for_rwp(sc, REDIST);
761 } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) {
762 /* SPIs in distributor */
763 gic_d_write(sc, 4, GICD_ICENABLER(irq), GICD_I_MASK(irq));
764 gic_v3_wait_for_rwp(sc, DIST);
766 panic("%s: Unsupported IRQ %u", __func__, irq);
770 gic_v3_enable_intr(device_t dev, struct intr_irqsrc *isrc)
772 struct gic_v3_softc *sc;
773 struct gic_v3_irqsrc *gi;
776 sc = device_get_softc(dev);
777 gi = (struct gic_v3_irqsrc *)isrc;
780 if (irq <= GIC_LAST_PPI) {
781 /* SGIs and PPIs in corresponding Re-Distributor */
782 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ISENABLER(irq),
784 gic_v3_wait_for_rwp(sc, REDIST);
785 } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) {
786 /* SPIs in distributor */
787 gic_d_write(sc, 4, GICD_ISENABLER(irq), GICD_I_MASK(irq));
788 gic_v3_wait_for_rwp(sc, DIST);
790 panic("%s: Unsupported IRQ %u", __func__, irq);
794 gic_v3_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
796 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
798 gic_v3_disable_intr(dev, isrc);
799 gic_icc_write(EOIR1, gi->gi_irq);
803 gic_v3_post_ithread(device_t dev, struct intr_irqsrc *isrc)
806 gic_v3_enable_intr(dev, isrc);
810 gic_v3_post_filter(device_t dev, struct intr_irqsrc *isrc)
812 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
814 if (gi->gi_trig == INTR_TRIGGER_EDGE)
817 gic_icc_write(EOIR1, gi->gi_irq);
821 gic_v3_bind_intr(device_t dev, struct intr_irqsrc *isrc)
823 struct gic_v3_softc *sc;
824 struct gic_v3_irqsrc *gi;
827 gi = (struct gic_v3_irqsrc *)isrc;
828 if (gi->gi_irq <= GIC_LAST_PPI)
831 KASSERT(gi->gi_irq >= GIC_FIRST_SPI && gi->gi_irq <= GIC_LAST_SPI,
832 ("%s: Attempting to bind an invalid IRQ", __func__));
834 sc = device_get_softc(dev);
836 if (CPU_EMPTY(&isrc->isrc_cpu)) {
837 gic_irq_cpu = intr_irq_next_cpu(gic_irq_cpu, &all_cpus);
838 CPU_SETOF(gic_irq_cpu, &isrc->isrc_cpu);
839 gic_d_write(sc, 4, GICD_IROUTER(gi->gi_irq),
840 CPU_AFFINITY(gic_irq_cpu));
843 * We can only bind to a single CPU so select
844 * the first CPU found.
846 cpu = CPU_FFS(&isrc->isrc_cpu) - 1;
847 gic_d_write(sc, 4, GICD_IROUTER(gi->gi_irq), CPU_AFFINITY(cpu));
855 gic_v3_init_secondary(device_t dev)
858 struct gic_v3_softc *sc;
859 gic_v3_initseq_t *init_func;
860 struct intr_irqsrc *isrc;
864 sc = device_get_softc(dev);
865 cpu = PCPU_GET(cpuid);
867 /* Train init sequence for boot CPU */
868 for (init_func = gic_v3_secondary_init; *init_func != NULL;
870 err = (*init_func)(sc);
873 "Could not initialize GIC for CPU%u\n", cpu);
878 /* Unmask attached SGI interrupts. */
879 for (irq = GIC_FIRST_SGI; irq <= GIC_LAST_SGI; irq++) {
880 isrc = GIC_INTR_ISRC(sc, irq);
881 if (intr_isrc_init_on_cpu(isrc, cpu))
882 gic_v3_enable_intr(dev, isrc);
885 /* Unmask attached PPI interrupts. */
886 for (irq = GIC_FIRST_PPI; irq <= GIC_LAST_PPI; irq++) {
887 isrc = GIC_INTR_ISRC(sc, irq);
888 if (intr_isrc_init_on_cpu(isrc, cpu))
889 gic_v3_enable_intr(dev, isrc);
892 for (i = 0; i < sc->gic_nchildren; i++) {
893 child = sc->gic_children[i];
894 PIC_INIT_SECONDARY(child);
899 gic_v3_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus,
902 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
903 uint64_t aff, val, irq;
906 #define GIC_AFF_MASK (CPU_AFF3_MASK | CPU_AFF2_MASK | CPU_AFF1_MASK)
907 #define GIC_AFFINITY(i) (CPU_AFFINITY(i) & GIC_AFF_MASK)
908 aff = GIC_AFFINITY(0);
912 /* Iterate through all CPUs in set */
913 for (i = 0; i <= mp_maxid; i++) {
914 /* Move to the next affinity group */
915 if (aff != GIC_AFFINITY(i)) {
918 gic_icc_write(SGI1R, val);
921 aff = GIC_AFFINITY(i);
924 /* Send the IPI to this cpu */
925 if (CPU_ISSET(i, &cpus)) {
926 #define ICC_SGI1R_AFFINITY(aff) \
927 (((uint64_t)CPU_AFF3(aff) << ICC_SGI1R_EL1_AFF3_SHIFT) | \
928 ((uint64_t)CPU_AFF2(aff) << ICC_SGI1R_EL1_AFF2_SHIFT) | \
929 ((uint64_t)CPU_AFF1(aff) << ICC_SGI1R_EL1_AFF1_SHIFT))
930 /* Set the affinity when the first at this level */
932 val = ICC_SGI1R_AFFINITY(aff) |
933 irq << ICC_SGI1R_EL1_SGIID_SHIFT;
934 /* Set the bit to send the IPI to te CPU */
935 val |= 1 << CPU_AFF0(CPU_AFFINITY(i));
939 /* Send the IPI to the last cpu affinity group */
941 gic_icc_write(SGI1R, val);
947 gic_v3_ipi_setup(device_t dev, u_int ipi, struct intr_irqsrc **isrcp)
949 struct intr_irqsrc *isrc;
950 struct gic_v3_softc *sc = device_get_softc(dev);
952 if (sgi_first_unused > GIC_LAST_SGI)
955 isrc = GIC_INTR_ISRC(sc, sgi_first_unused);
956 sgi_to_ipi[sgi_first_unused++] = ipi;
958 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
969 gic_v3_wait_for_rwp(struct gic_v3_softc *sc, enum gic_v3_xdist xdist)
971 struct resource *res;
973 size_t us_left = 1000000;
975 cpuid = PCPU_GET(cpuid);
982 res = sc->gic_redists.pcpu[cpuid];
985 KASSERT(0, ("%s: Attempt to wait for unknown RWP", __func__));
989 while ((bus_read_4(res, GICD_CTLR) & GICD_CTLR_RWP) != 0) {
992 panic("GICD Register write pending for too long");
998 gic_v3_cpu_priority(uint64_t mask)
1001 /* Set prority mask */
1002 gic_icc_write(PMR, mask & ICC_PMR_EL1_PRIO_MASK);
1006 gic_v3_cpu_enable_sre(struct gic_v3_softc *sc)
1011 cpuid = PCPU_GET(cpuid);
1013 * Set the SRE bit to enable access to GIC CPU interface
1014 * via system registers.
1016 sre = READ_SPECIALREG(icc_sre_el1);
1017 sre |= ICC_SRE_EL1_SRE;
1018 WRITE_SPECIALREG(icc_sre_el1, sre);
1021 * Now ensure that the bit is set.
1023 sre = READ_SPECIALREG(icc_sre_el1);
1024 if ((sre & ICC_SRE_EL1_SRE) == 0) {
1025 /* We are done. This was disabled in EL2 */
1026 device_printf(sc->dev, "ERROR: CPU%u cannot enable CPU interface "
1027 "via system registers\n", cpuid);
1029 } else if (bootverbose) {
1030 device_printf(sc->dev,
1031 "CPU%u enabled CPU interface via system registers\n",
1039 gic_v3_cpu_init(struct gic_v3_softc *sc)
1043 /* Enable access to CPU interface via system registers */
1044 err = gic_v3_cpu_enable_sre(sc);
1047 /* Priority mask to minimum - accept all interrupts */
1048 gic_v3_cpu_priority(GIC_PRIORITY_MIN);
1049 /* Disable EOI mode */
1050 gic_icc_clear(CTLR, ICC_CTLR_EL1_EOIMODE);
1051 /* Enable group 1 (insecure) interrups */
1052 gic_icc_set(IGRPEN1, ICC_IGRPEN0_EL1_EN);
1059 gic_v3_dist_init(struct gic_v3_softc *sc)
1065 * 1. Disable the Distributor
1067 gic_d_write(sc, 4, GICD_CTLR, 0);
1068 gic_v3_wait_for_rwp(sc, DIST);
1071 * 2. Configure the Distributor
1073 /* Set all SPIs to be Group 1 Non-secure */
1074 for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_IGROUPRn)
1075 gic_d_write(sc, 4, GICD_IGROUPR(i), 0xFFFFFFFF);
1077 /* Set all global interrupts to be level triggered, active low. */
1078 for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ICFGRn)
1079 gic_d_write(sc, 4, GICD_ICFGR(i), 0x00000000);
1081 /* Set priority to all shared interrupts */
1082 for (i = GIC_FIRST_SPI;
1083 i < sc->gic_nirqs; i += GICD_I_PER_IPRIORITYn) {
1084 /* Set highest priority */
1085 gic_d_write(sc, 4, GICD_IPRIORITYR(i), GIC_PRIORITY_MAX);
1089 * Disable all interrupts. Leave PPI and SGIs as they are enabled in
1090 * Re-Distributor registers.
1092 for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ISENABLERn)
1093 gic_d_write(sc, 4, GICD_ICENABLER(i), 0xFFFFFFFF);
1095 gic_v3_wait_for_rwp(sc, DIST);
1098 * 3. Enable Distributor
1100 /* Enable Distributor with ARE, Group 1 */
1101 gic_d_write(sc, 4, GICD_CTLR, GICD_CTLR_ARE_NS | GICD_CTLR_G1A |
1105 * 4. Route all interrupts to boot CPU.
1107 aff = CPU_AFFINITY(0);
1108 for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i++)
1109 gic_d_write(sc, 4, GICD_IROUTER(i), aff);
1114 /* Re-Distributor */
1116 gic_v3_redist_alloc(struct gic_v3_softc *sc)
1120 /* Allocate struct resource for all CPU's Re-Distributor registers */
1121 for (cpuid = 0; cpuid <= mp_maxid; cpuid++)
1122 if (CPU_ISSET(cpuid, &all_cpus) != 0)
1123 sc->gic_redists.pcpu[cpuid] =
1124 malloc(sizeof(*sc->gic_redists.pcpu[0]),
1125 M_GIC_V3, M_WAITOK);
1127 sc->gic_redists.pcpu[cpuid] = NULL;
1132 gic_v3_redist_find(struct gic_v3_softc *sc)
1134 struct resource r_res;
1135 bus_space_handle_t r_bsh;
1142 cpuid = PCPU_GET(cpuid);
1144 aff = CPU_AFFINITY(cpuid);
1145 /* Affinity in format for comparison with typer */
1146 aff = (CPU_AFF3(aff) << 24) | (CPU_AFF2(aff) << 16) |
1147 (CPU_AFF1(aff) << 8) | CPU_AFF0(aff);
1150 device_printf(sc->dev,
1151 "Start searching for Re-Distributor\n");
1153 /* Iterate through Re-Distributor regions */
1154 for (i = 0; i < sc->gic_redists.nregions; i++) {
1155 /* Take a copy of the region's resource */
1156 r_res = *sc->gic_redists.regions[i];
1157 r_bsh = rman_get_bushandle(&r_res);
1159 pidr2 = bus_read_4(&r_res, GICR_PIDR2);
1160 switch (GICR_PIDR2_ARCH(pidr2)) {
1161 case GICR_PIDR2_ARCH_GICv3: /* fall through */
1162 case GICR_PIDR2_ARCH_GICv4:
1165 device_printf(sc->dev,
1166 "No Re-Distributor found for CPU%u\n", cpuid);
1171 typer = bus_read_8(&r_res, GICR_TYPER);
1172 if ((typer >> GICR_TYPER_AFF_SHIFT) == aff) {
1173 KASSERT(sc->gic_redists.pcpu[cpuid] != NULL,
1174 ("Invalid pointer to per-CPU redistributor"));
1175 /* Copy res contents to its final destination */
1176 *sc->gic_redists.pcpu[cpuid] = r_res;
1178 device_printf(sc->dev,
1179 "CPU%u Re-Distributor has been found\n",
1185 r_bsh += (GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);
1186 if ((typer & GICR_TYPER_VLPIS) != 0) {
1188 (GICR_VLPI_BASE_SIZE + GICR_RESERVED_SIZE);
1191 rman_set_bushandle(&r_res, r_bsh);
1192 } while ((typer & GICR_TYPER_LAST) == 0);
1195 device_printf(sc->dev, "No Re-Distributor found for CPU%u\n", cpuid);
1200 gic_v3_redist_wake(struct gic_v3_softc *sc)
1203 size_t us_left = 1000000;
1205 waker = gic_r_read(sc, 4, GICR_WAKER);
1206 /* Wake up Re-Distributor for this CPU */
1207 waker &= ~GICR_WAKER_PS;
1208 gic_r_write(sc, 4, GICR_WAKER, waker);
1210 * When clearing ProcessorSleep bit it is required to wait for
1211 * ChildrenAsleep to become zero following the processor power-on.
1213 while ((gic_r_read(sc, 4, GICR_WAKER) & GICR_WAKER_CA) != 0) {
1215 if (us_left-- == 0) {
1216 panic("Could not wake Re-Distributor for CPU%u",
1222 device_printf(sc->dev, "CPU%u Re-Distributor woke up\n",
1230 gic_v3_redist_init(struct gic_v3_softc *sc)
1235 err = gic_v3_redist_find(sc);
1239 err = gic_v3_redist_wake(sc);
1243 /* Configure SGIs and PPIs to be Group1 Non-secure */
1244 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_IGROUPR0,
1248 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ICENABLER0,
1249 GICR_I_ENABLER_PPI_MASK);
1251 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ISENABLER0,
1252 GICR_I_ENABLER_SGI_MASK);
1254 /* Set priority for SGIs and PPIs */
1255 for (i = 0; i <= GIC_LAST_PPI; i += GICR_I_PER_IPRIORITYn) {
1256 gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_IPRIORITYR(i),
1260 gic_v3_wait_for_rwp(sc, REDIST);