2 * Copyright (c) 2015 The FreeBSD Foundation
5 * This software was developed by Semihalf under
6 * the sponsorship of the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #ifndef _GIC_V3_REG_H_
33 #define _GIC_V3_REG_H_
36 * Maximum number of interrupts
37 * supported by GIC (including SGIs, PPIs and SPIs)
39 #define GIC_I_NUM_MAX (1020)
41 * Priority MAX/MIN values
43 #define GIC_PRIORITY_MAX (0x00UL)
44 /* Upper value is determined by LPI max priority */
45 #define GIC_PRIORITY_MIN (0xFCUL)
47 /* Numbers for software generated interrupts */
48 #define GIC_FIRST_SGI (0)
49 #define GIC_LAST_SGI (15)
50 /* Numbers for private peripheral interrupts */
51 #define GIC_FIRST_PPI (16)
52 #define GIC_LAST_PPI (31)
53 /* Numbers for spared peripheral interrupts */
54 #define GIC_FIRST_SPI (32)
55 #define GIC_LAST_SPI (1019)
56 /* Numbers for local peripheral interrupts */
57 #define GIC_FIRST_LPI (8192)
63 #define GICD_CTLR_G1 (1 << 0)
64 #define GICD_CTLR_G1A (1 << 1)
65 #define GICD_CTLR_ARE_NS (1 << 4)
66 #define GICD_CTLR_RWP (1 << 31)
68 #define GICD_TYPER_IDBITS(n) ((((n) >> 19) & 0x1F) + 1)
73 #define GICD_IROUTER(n) (0x6000 + ((n) * 8))
75 #define GICD_PIDR4 0xFFD0
76 #define GICD_PIDR5 0xFFD4
77 #define GICD_PIDR6 0xFFD8
78 #define GICD_PIDR7 0xFFDC
79 #define GICD_PIDR0 0xFFE0
80 #define GICD_PIDR1 0xFFE4
81 #define GICD_PIDR2 0xFFE8
83 #define GICR_PIDR2_ARCH_SHIFT 4
84 #define GICR_PIDR2_ARCH_MASK 0xF0
85 #define GICR_PIDR2_ARCH(x) \
86 (((x) & GICR_PIDR2_ARCH_MASK) >> GICR_PIDR2_ARCH_SHIFT)
87 #define GICR_PIDR2_ARCH_GICv3 0x3
88 #define GICR_PIDR2_ARCH_GICv4 0x4
90 #define GICD_PIDR3 0xFFEC
92 /* Redistributor registers */
93 #define GICR_CTLR GICD_CTLR
94 #define GICR_CTLR_LPI_ENABLE (1 << 0)
96 #define GICR_PIDR2 GICD_PIDR2
98 #define GICR_TYPER (0x0008)
99 #define GICR_TYPER_PLPIS (1 << 0)
100 #define GICR_TYPER_VLPIS (1 << 1)
101 #define GICR_TYPER_LAST (1 << 4)
102 #define GICR_TYPER_CPUNUM_SHIFT (8)
103 #define GICR_TYPER_CPUNUM_MASK (0xFFFUL << GICR_TYPER_CPUNUM_SHIFT)
104 #define GICR_TYPER_CPUNUM(x) \
105 (((x) & GICR_TYPER_CPUNUM_MASK) >> GICR_TYPER_CPUNUM_SHIFT)
106 #define GICR_TYPER_AFF_SHIFT (32)
108 #define GICR_WAKER (0x0014)
109 #define GICR_WAKER_PS (1 << 1) /* Processor sleep */
110 #define GICR_WAKER_CA (1 << 2) /* Children asleep */
112 #define GICR_PROPBASER (0x0070)
113 #define GICR_PROPBASER_IDBITS_MASK 0x1FUL
116 * 0x0 - Device-nGnRnE
117 * 0x1 - Normal Inner Non-cacheable
118 * 0x2 - Normal Inner Read-allocate, Write-through
119 * 0x3 - Normal Inner Read-allocate, Write-back
120 * 0x4 - Normal Inner Write-allocate, Write-through
121 * 0x5 - Normal Inner Write-allocate, Write-back
122 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through
123 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back
125 #define GICR_PROPBASER_CACHE_SHIFT 7
126 #define GICR_PROPBASER_CACHE_DnGnRnE 0x0UL
127 #define GICR_PROPBASER_CACHE_NIN 0x1UL
128 #define GICR_PROPBASER_CACHE_NIRAWT 0x2UL
129 #define GICR_PROPBASER_CACHE_NIRAWB 0x3UL
130 #define GICR_PROPBASER_CACHE_NIWAWT 0x4UL
131 #define GICR_PROPBASER_CACHE_NIWAWB 0x5UL
132 #define GICR_PROPBASER_CACHE_NIRAWAWT 0x6UL
133 #define GICR_PROPBASER_CACHE_NIRAWAWB 0x7UL
134 #define GICR_PROPBASER_CACHE_MASK \
135 (0x7UL << GICR_PROPBASER_CACHE_SHIFT)
139 * 0x0 - Non-shareable
140 * 0x1 - Inner-shareable
141 * 0x2 - Outer-shareable
142 * 0x3 - Reserved. Threated as 0x0
144 #define GICR_PROPBASER_SHARE_SHIFT 10
145 #define GICR_PROPBASER_SHARE_NS 0x0UL
146 #define GICR_PROPBASER_SHARE_IS 0x1UL
147 #define GICR_PROPBASER_SHARE_OS 0x2UL
148 #define GICR_PROPBASER_SHARE_RES 0x3UL
149 #define GICR_PROPBASER_SHARE_MASK \
150 (0x3UL << GICR_PROPBASER_SHARE_SHIFT)
152 #define GICR_PENDBASER (0x0078)
155 * 0x0 - Device-nGnRnE
156 * 0x1 - Normal Inner Non-cacheable
157 * 0x2 - Normal Inner Read-allocate, Write-through
158 * 0x3 - Normal Inner Read-allocate, Write-back
159 * 0x4 - Normal Inner Write-allocate, Write-through
160 * 0x5 - Normal Inner Write-allocate, Write-back
161 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through
162 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back
164 #define GICR_PENDBASER_CACHE_SHIFT 7
165 #define GICR_PENDBASER_CACHE_DnGnRnE 0x0UL
166 #define GICR_PENDBASER_CACHE_NIN 0x1UL
167 #define GICR_PENDBASER_CACHE_NIRAWT 0x2UL
168 #define GICR_PENDBASER_CACHE_NIRAWB 0x3UL
169 #define GICR_PENDBASER_CACHE_NIWAWT 0x4UL
170 #define GICR_PENDBASER_CACHE_NIWAWB 0x5UL
171 #define GICR_PENDBASER_CACHE_NIRAWAWT 0x6UL
172 #define GICR_PENDBASER_CACHE_NIRAWAWB 0x7UL
173 #define GICR_PENDBASER_CACHE_MASK \
174 (0x7UL << GICR_PENDBASER_CACHE_SHIFT)
178 * 0x0 - Non-shareable
179 * 0x1 - Inner-shareable
180 * 0x2 - Outer-shareable
181 * 0x3 - Reserved. Threated as 0x0
183 #define GICR_PENDBASER_SHARE_SHIFT 10
184 #define GICR_PENDBASER_SHARE_NS 0x0UL
185 #define GICR_PENDBASER_SHARE_IS 0x1UL
186 #define GICR_PENDBASER_SHARE_OS 0x2UL
187 #define GICR_PENDBASER_SHARE_RES 0x3UL
188 #define GICR_PENDBASER_SHARE_MASK \
189 (0x3UL << GICR_PENDBASER_SHARE_SHIFT)
191 /* Re-distributor registers for SGIs and PPIs */
192 #define GICR_RD_BASE_SIZE PAGE_SIZE_64K
193 #define GICR_SGI_BASE_SIZE PAGE_SIZE_64K
194 #define GICR_VLPI_BASE_SIZE PAGE_SIZE_64K
195 #define GICR_RESERVED_SIZE PAGE_SIZE_64K
197 #define GICR_IGROUPR0 (0x0080)
198 #define GICR_ISENABLER0 (0x0100)
199 #define GICR_ICENABLER0 (0x0180)
200 #define GICR_I_ENABLER_SGI_MASK (0x0000FFFF)
201 #define GICR_I_ENABLER_PPI_MASK (0xFFFF0000)
203 #define GICR_I_PER_IPRIORITYn (GICD_I_PER_IPRIORITYn)
206 #define GITS_PIDR2 GICR_PIDR2
207 #define GITS_PIDR2_ARCH_MASK GICR_PIDR2_ARCH_MASK
208 #define GITS_PIDR2_ARCH_GICv3 GICR_PIDR2_ARCH_GICv3
209 #define GITS_PIDR2_ARCH_GICv4 GICR_PIDR2_ARCH_GICv4
211 #define GITS_CTLR (0x0000)
212 #define GITS_CTLR_EN (1 << 0)
214 #define GITS_IIDR (0x0004)
215 #define GITS_IIDR_PRODUCT_SHIFT 24
216 #define GITS_IIDR_PRODUCT_MASK (0xff << GITS_IIDR_PRODUCT_SHIFT)
217 #define GITS_IIDR_VARIANT_SHIFT 16
218 #define GITS_IIDR_VARIANT_MASK (0xf << GITS_IIDR_VARIANT_SHIFT)
219 #define GITS_IIDR_REVISION_SHIFT 12
220 #define GITS_IIDR_REVISION_MASK (0xf << GITS_IIDR_REVISION_SHIFT)
221 #define GITS_IIDR_IMPLEMENTOR_SHIFT 0
222 #define GITS_IIDR_IMPLEMENTOR_MASK (0xfff << GITS_IIDR_IMPLEMENTOR_SHIFT)
224 #define GITS_IIDR_RAW(impl, prod, var, rev) \
225 ((prod) << GITS_IIDR_PRODUCT_SHIFT | \
226 (var) << GITS_IIDR_VARIANT_SHIFT | \
227 (rev) << GITS_IIDR_REVISION_SHIFT | \
228 (impl) << GITS_IIDR_IMPLEMENTOR_SHIFT)
230 #define GITS_IIDR_IMPL_CAVIUM (0x34c)
231 #define GITS_IIDR_PROD_THUNDER (0xa1)
232 #define GITS_IIDR_VAR_THUNDER_1 (0x0)
234 #define GITS_CBASER (0x0080)
235 #define GITS_CBASER_VALID (1UL << 63)
238 * 0x0 - Device-nGnRnE
239 * 0x1 - Normal Inner Non-cacheable
240 * 0x2 - Normal Inner Read-allocate, Write-through
241 * 0x3 - Normal Inner Read-allocate, Write-back
242 * 0x4 - Normal Inner Write-allocate, Write-through
243 * 0x5 - Normal Inner Write-allocate, Write-back
244 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through
245 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back
247 #define GITS_CBASER_CACHE_SHIFT 59
248 #define GITS_CBASER_CACHE_DnGnRnE 0x0UL
249 #define GITS_CBASER_CACHE_NIN 0x1UL
250 #define GITS_CBASER_CACHE_NIRAWT 0x2UL
251 #define GITS_CBASER_CACHE_NIRAWB 0x3UL
252 #define GITS_CBASER_CACHE_NIWAWT 0x4UL
253 #define GITS_CBASER_CACHE_NIWAWB 0x5UL
254 #define GITS_CBASER_CACHE_NIRAWAWT 0x6UL
255 #define GITS_CBASER_CACHE_NIRAWAWB 0x7UL
256 #define GITS_CBASER_CACHE_MASK (0x7UL << GITS_CBASER_CACHE_SHIFT)
259 * 0x0 - Non-shareable
260 * 0x1 - Inner-shareable
261 * 0x2 - Outer-shareable
262 * 0x3 - Reserved. Threated as 0x0
264 #define GITS_CBASER_SHARE_SHIFT 10
265 #define GITS_CBASER_SHARE_NS 0x0UL
266 #define GITS_CBASER_SHARE_IS 0x1UL
267 #define GITS_CBASER_SHARE_OS 0x2UL
268 #define GITS_CBASER_SHARE_RES 0x3UL
269 #define GITS_CBASER_SHARE_MASK \
270 (0x3UL << GITS_CBASER_SHARE_SHIFT)
272 #define GITS_CBASER_PA_SHIFT 12
273 #define GITS_CBASER_PA_MASK (0xFFFFFFFFFUL << GITS_CBASER_PA_SHIFT)
275 #define GITS_CWRITER (0x0088)
276 #define GITS_CREADR (0x0090)
278 #define GITS_BASER_BASE (0x0100)
279 #define GITS_BASER(x) (GITS_BASER_BASE + (x) * 8)
281 #define GITS_BASER_VALID (1UL << 63)
283 #define GITS_BASER_TYPE_SHIFT 56
284 #define GITS_BASER_TYPE(x) \
285 (((x) & GITS_BASER_TYPE_MASK) >> GITS_BASER_TYPE_SHIFT)
286 #define GITS_BASER_TYPE_UNIMPL 0x0UL /* Unimplemented */
287 #define GITS_BASER_TYPE_DEV 0x1UL /* Devices */
288 #define GITS_BASER_TYPE_VP 0x2UL /* Virtual Processors */
289 #define GITS_BASER_TYPE_PP 0x3UL /* Physical Processors */
290 #define GITS_BASER_TYPE_IC 0x4UL /* Interrupt Collections */
291 #define GITS_BASER_TYPE_RES5 0x5UL /* Reserved */
292 #define GITS_BASER_TYPE_RES6 0x6UL /* Reserved */
293 #define GITS_BASER_TYPE_RES7 0x7UL /* Reserved */
294 #define GITS_BASER_TYPE_MASK (0x7UL << GITS_BASER_TYPE_SHIFT)
297 * 0x0 - Non-cacheable, non-bufferable
298 * 0x1 - Non-cacheable
299 * 0x2 - Read-allocate, Write-through
300 * 0x3 - Read-allocate, Write-back
301 * 0x4 - Write-allocate, Write-through
302 * 0x5 - Write-allocate, Write-back
303 * 0x6 - Read-allocate, Write-allocate, Write-through
304 * 0x7 - Read-allocate, Write-allocate, Write-back
306 #define GITS_BASER_CACHE_SHIFT 59
307 #define GITS_BASER_CACHE_NCNB 0x0UL
308 #define GITS_BASER_CACHE_NC 0x1UL
309 #define GITS_BASER_CACHE_RAWT 0x2UL
310 #define GITS_BASER_CACHE_RAWB 0x3UL
311 #define GITS_BASER_CACHE_WAWT 0x4UL
312 #define GITS_BASER_CACHE_WAWB 0x5UL
313 #define GITS_BASER_CACHE_RAWAWT 0x6UL
314 #define GITS_BASER_CACHE_RAWAWB 0x7UL
315 #define GITS_BASER_CACHE_MASK (0x7UL << GITS_BASER_CACHE_SHIFT)
317 #define GITS_BASER_ESIZE_SHIFT 48
318 #define GITS_BASER_ESIZE_MASK (0x1FUL << GITS_BASER_ESIZE_SHIFT)
319 #define GITS_BASER_ESIZE(x) \
320 ((((x) & GITS_BASER_ESIZE_MASK) >> GITS_BASER_ESIZE_SHIFT) + 1)
322 #define GITS_BASER_PA_SHIFT 12
323 #define GITS_BASER_PA_MASK (0xFFFFFFFFFUL << GITS_BASER_PA_SHIFT)
327 * 0x0 - Non-shareable
328 * 0x1 - Inner-shareable
329 * 0x2 - Outer-shareable
330 * 0x3 - Reserved. Threated as 0x0
332 #define GITS_BASER_SHARE_SHIFT 10
333 #define GITS_BASER_SHARE_NS 0x0UL
334 #define GITS_BASER_SHARE_IS 0x1UL
335 #define GITS_BASER_SHARE_OS 0x2UL
336 #define GITS_BASER_SHARE_RES 0x3UL
337 #define GITS_BASER_SHARE_MASK (0x3UL << GITS_BASER_SHARE_SHIFT)
339 #define GITS_BASER_PSZ_SHIFT 8
340 #define GITS_BASER_PSZ_4K 0x0UL
341 #define GITS_BASER_PSZ_16K 0x1UL
342 #define GITS_BASER_PSZ_64K 0x2UL
343 #define GITS_BASER_PSZ_MASK (0x3UL << GITS_BASER_PSZ_SHIFT)
345 #define GITS_BASER_SIZE_MASK 0xFFUL
347 #define GITS_BASER_NUM 8
349 #define GITS_TYPER (0x0008)
350 #define GITS_TYPER_PTA (1UL << 19)
351 #define GITS_TYPER_DEVB_SHIFT 13
352 #define GITS_TYPER_DEVB_MASK (0x1FUL << GITS_TYPER_DEVB_SHIFT)
353 /* Number of device identifiers implemented */
354 #define GITS_TYPER_DEVB(x) \
355 ((((x) & GITS_TYPER_DEVB_MASK) >> GITS_TYPER_DEVB_SHIFT) + 1)
356 #define GITS_TYPER_ITTES_SHIFT 4
357 #define GITS_TYPER_ITTES_MASK (0xFUL << GITS_TYPER_ITTES_SHIFT)
358 /* Number of bytes per ITT Entry */
359 #define GITS_TYPER_ITTES(x) \
360 ((((x) & GITS_TYPER_ITTES_MASK) >> GITS_TYPER_ITTES_SHIFT) + 1)
362 #define GITS_TRANSLATER (0x10040)
366 #define LPI_CONF_PRIO_MASK (0xFC)
367 #define LPI_CONF_GROUP1 (1 << 1)
368 #define LPI_CONF_ENABLE (1 << 0)
375 * Registers list (ICC_xyz_EL1):
377 * PMR - Priority Mask Register
378 * * interrupts of priority higher than specified
379 * in this mask will be signalled to the CPU.
380 * (0xff - lowest possible prio., 0x00 - highest prio.)
382 * CTLR - Control Register
383 * * controls behavior of the CPU interface and displays
384 * implemented features.
386 * IGRPEN1 - Interrupt Group 1 Enable Register
388 * IAR1 - Interrupt Acknowledge Register Group 1
389 * * contains number of the highest priority pending
390 * interrupt from the Group 1.
392 * EOIR1 - End of Interrupt Register Group 1
393 * * Writes inform CPU interface about completed Group 1
394 * interrupts processing.
397 #define gic_icc_write(reg, val) \
399 WRITE_SPECIALREG(ICC_ ##reg ##_EL1, val); \
403 #define gic_icc_read(reg) \
407 val = READ_SPECIALREG(ICC_ ##reg ##_EL1); \
411 #define gic_icc_set(reg, mask) \
414 val = gic_icc_read(reg); \
416 gic_icc_write(reg, val); \
419 #define gic_icc_clear(reg, mask) \
422 val = gic_icc_read(reg); \
424 gic_icc_write(reg, val); \
427 #endif /* _GIC_V3_REG_H_ */