2 * Copyright (c) 2015 The FreeBSD Foundation
5 * This software was developed by Semihalf under
6 * the sponsorship of the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #ifndef _GIC_V3_REG_H_
33 #define _GIC_V3_REG_H_
36 * Maximum number of interrupts
37 * supported by GIC (including SGIs, PPIs and SPIs)
39 #define GIC_I_NUM_MAX (1020)
41 * Priority MAX/MIN values
43 #define GIC_PRIORITY_MAX (0x00UL)
44 /* Upper value is determined by LPI max priority */
45 #define GIC_PRIORITY_MIN (0xFCUL)
47 /* Numbers for software generated interrupts */
48 #define GIC_FIRST_SGI (0)
49 #define GIC_LAST_SGI (15)
50 /* Numbers for private peripheral interrupts */
51 #define GIC_FIRST_PPI (16)
52 #define GIC_LAST_PPI (31)
53 /* Numbers for spared peripheral interrupts */
54 #define GIC_FIRST_SPI (32)
55 #define GIC_LAST_SPI (1019)
56 /* Numbers for local peripheral interrupts */
57 #define GIC_FIRST_LPI (8192)
62 #define GICD_CTLR (0x0000)
63 #define GICD_CTLR_G1 (1 << 0)
64 #define GICD_CTLR_G1A (1 << 1)
65 #define GICD_CTLR_ARE_NS (1 << 4)
66 #define GICD_CTLR_RWP (1 << 31)
68 #define GICD_TYPER (0x0004)
69 #define GICD_TYPER_IDBITS(n) ((((n) >> 19) & 0x1F) + 1)
70 #define GICD_TYPER_I_NUM(n) ((((n) & 0xF1) + 1) * 32)
72 #define GICD_ISENABLER(n) (0x0100 + (((n) >> 5) * 4))
73 #define GICD_I_PER_ISENABLERn (32)
75 #define GICD_ICENABLER(n) (0x0180 + (((n) >> 5) * 4))
76 #define GICD_IPRIORITYR(n) (0x0400 + (((n) >> 2) * 4))
77 #define GICD_I_PER_IPRIORITYn (4)
79 #define GICD_I_MASK(n) (1 << ((n) % 32))
81 #define GICD_ICFGR(n) (0x0C00 + (((n) >> 4) * 4))
82 /* First bit is a polarity bit (0 - low, 1 - high) */
83 #define GICD_ICFGR_POL_LOW (0 << 0)
84 #define GICD_ICFGR_POL_HIGH (1 << 0)
85 #define GICD_ICFGR_POL_MASK (0x1)
86 /* Second bit is a trigger bit (0 - level, 1 - edge) */
87 #define GICD_ICFGR_TRIG_LVL (0 << 1)
88 #define GICD_ICFGR_TRIG_EDGE (1 << 1)
89 #define GICD_ICFGR_TRIG_MASK (0x2)
91 #define GICD_I_PER_ICFGRn (16)
96 #define GICD_IROUTER(n) (0x6000 + ((n) * 8))
97 #define GICD_PIDR2 (0xFFE8)
99 #define GICR_PIDR2_ARCH_MASK (0xF0)
100 #define GICR_PIDR2_ARCH_GICv3 (0x30)
101 #define GICR_PIDR2_ARCH_GICv4 (0x40)
103 /* Redistributor registers */
104 #define GICR_CTLR GICD_CTLR
105 #define GICR_CTLR_LPI_ENABLE (1 << 0)
107 #define GICR_PIDR2 GICD_PIDR2
109 #define GICR_TYPER (0x0008)
110 #define GICR_TYPER_PLPIS (1 << 0)
111 #define GICR_TYPER_VLPIS (1 << 1)
112 #define GICR_TYPER_LAST (1 << 4)
113 #define GICR_TYPER_CPUNUM_SHIFT (8)
114 #define GICR_TYPER_CPUNUM_MASK (0xFFFUL << GICR_TYPER_CPUNUM_SHIFT)
115 #define GICR_TYPER_CPUNUM(x) \
116 (((x) & GICR_TYPER_CPUNUM_MASK) >> GICR_TYPER_CPUNUM_SHIFT)
117 #define GICR_TYPER_AFF_SHIFT (32)
119 #define GICR_WAKER (0x0014)
120 #define GICR_WAKER_PS (1 << 1) /* Processor sleep */
121 #define GICR_WAKER_CA (1 << 2) /* Children asleep */
123 #define GICR_PROPBASER (0x0070)
124 #define GICR_PROPBASER_IDBITS_MASK 0x1FUL
127 * 0x0 - Device-nGnRnE
128 * 0x1 - Normal Inner Non-cacheable
129 * 0x2 - Normal Inner Read-allocate, Write-through
130 * 0x3 - Normal Inner Read-allocate, Write-back
131 * 0x4 - Normal Inner Write-allocate, Write-through
132 * 0x5 - Normal Inner Write-allocate, Write-back
133 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through
134 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back
136 #define GICR_PROPBASER_CACHE_SHIFT 7
137 #define GICR_PROPBASER_CACHE_DnGnRnE 0x0UL
138 #define GICR_PROPBASER_CACHE_NIN 0x1UL
139 #define GICR_PROPBASER_CACHE_NIRAWT 0x2UL
140 #define GICR_PROPBASER_CACHE_NIRAWB 0x3UL
141 #define GICR_PROPBASER_CACHE_NIWAWT 0x4UL
142 #define GICR_PROPBASER_CACHE_NIWAWB 0x5UL
143 #define GICR_PROPBASER_CACHE_NIRAWAWT 0x6UL
144 #define GICR_PROPBASER_CACHE_NIRAWAWB 0x7UL
148 * 0x0 - Non-shareable
149 * 0x1 - Inner-shareable
150 * 0x2 - Outer-shareable
151 * 0x3 - Reserved. Threated as 0x0
153 #define GICR_PROPBASER_SHARE_SHIFT 10
154 #define GICR_PROPBASER_SHARE_NS 0x0UL
155 #define GICR_PROPBASER_SHARE_IS 0x1UL
156 #define GICR_PROPBASER_SHARE_OS 0x2UL
157 #define GICR_PROPBASER_SHARE_RES 0x3UL
158 #define GICR_PROPBASER_SHARE_MASK \
159 (0x3UL << GICR_PROPBASER_SHARE_SHIFT)
161 #define GICR_PENDBASER (0x0078)
164 * 0x0 - Device-nGnRnE
165 * 0x1 - Normal Inner Non-cacheable
166 * 0x2 - Normal Inner Read-allocate, Write-through
167 * 0x3 - Normal Inner Read-allocate, Write-back
168 * 0x4 - Normal Inner Write-allocate, Write-through
169 * 0x5 - Normal Inner Write-allocate, Write-back
170 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through
171 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back
173 #define GICR_PENDBASER_CACHE_SHIFT 7
174 #define GICR_PENDBASER_CACHE_DnGnRnE 0x0UL
175 #define GICR_PENDBASER_CACHE_NIN 0x1UL
176 #define GICR_PENDBASER_CACHE_NIRAWT 0x2UL
177 #define GICR_PENDBASER_CACHE_NIRAWB 0x3UL
178 #define GICR_PENDBASER_CACHE_NIWAWT 0x4UL
179 #define GICR_PENDBASER_CACHE_NIWAWB 0x5UL
180 #define GICR_PENDBASER_CACHE_NIRAWAWT 0x6UL
181 #define GICR_PENDBASER_CACHE_NIRAWAWB 0x7UL
185 * 0x0 - Non-shareable
186 * 0x1 - Inner-shareable
187 * 0x2 - Outer-shareable
188 * 0x3 - Reserved. Threated as 0x0
190 #define GICR_PENDBASER_SHARE_SHIFT 10
191 #define GICR_PENDBASER_SHARE_NS 0x0UL
192 #define GICR_PENDBASER_SHARE_IS 0x1UL
193 #define GICR_PENDBASER_SHARE_OS 0x2UL
194 #define GICR_PENDBASER_SHARE_RES 0x3UL
195 #define GICR_PENDBASER_SHARE_MASK \
196 (0x3UL << GICR_PENDBASER_SHARE_SHIFT)
198 /* Re-distributor registers for SGIs and PPIs */
199 #define GICR_RD_BASE_SIZE PAGE_SIZE_64K
200 #define GICR_SGI_BASE_SIZE PAGE_SIZE_64K
201 #define GICR_VLPI_BASE_SIZE PAGE_SIZE_64K
202 #define GICR_RESERVED_SIZE PAGE_SIZE_64K
204 #define GICR_ISENABLER0 (0x0100)
205 #define GICR_ICENABLER0 (0x0180)
206 #define GICR_I_ENABLER_SGI_MASK (0x0000FFFF)
207 #define GICR_I_ENABLER_PPI_MASK (0xFFFF0000)
209 #define GICR_I_PER_IPRIORITYn (GICD_I_PER_IPRIORITYn)
212 #define GITS_PIDR2 GICR_PIDR2
213 #define GITS_PIDR2_ARCH_MASK GICR_PIDR2_ARCH_MASK
214 #define GITS_PIDR2_ARCH_GICv3 GICR_PIDR2_ARCH_GICv3
215 #define GITS_PIDR2_ARCH_GICv4 GICR_PIDR2_ARCH_GICv4
217 #define GITS_CTLR (0x0000)
218 #define GITS_CTLR_EN (1 << 0)
220 #define GITS_CBASER (0x0080)
221 #define GITS_CBASER_VALID (1UL << 63)
224 * 0x0 - Device-nGnRnE
225 * 0x1 - Normal Inner Non-cacheable
226 * 0x2 - Normal Inner Read-allocate, Write-through
227 * 0x3 - Normal Inner Read-allocate, Write-back
228 * 0x4 - Normal Inner Write-allocate, Write-through
229 * 0x5 - Normal Inner Write-allocate, Write-back
230 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through
231 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back
233 #define GITS_CBASER_CACHE_SHIFT 59
234 #define GITS_CBASER_CACHE_DnGnRnE 0x0UL
235 #define GITS_CBASER_CACHE_NIN 0x1UL
236 #define GITS_CBASER_CACHE_NIRAWT 0x2UL
237 #define GITS_CBASER_CACHE_NIRAWB 0x3UL
238 #define GITS_CBASER_CACHE_NIWAWT 0x4UL
239 #define GITS_CBASER_CACHE_NIWAWB 0x5UL
240 #define GITS_CBASER_CACHE_NIRAWAWT 0x6UL
241 #define GITS_CBASER_CACHE_NIRAWAWB 0x7UL
242 #define GITS_CBASER_CACHE_MASK (0x7UL << GITS_CBASER_TYPE_SHIFT)
245 * 0x0 - Non-shareable
246 * 0x1 - Inner-shareable
247 * 0x2 - Outer-shareable
248 * 0x3 - Reserved. Threated as 0x0
250 #define GITS_CBASER_SHARE_SHIFT 10
251 #define GITS_CBASER_SHARE_NS 0x0UL
252 #define GITS_CBASER_SHARE_IS 0x1UL
253 #define GITS_CBASER_SHARE_OS 0x2UL
254 #define GITS_CBASER_SHARE_RES 0x3UL
255 #define GITS_CBASER_SHARE_MASK \
256 (0x3UL << GITS_CBASER_SHARE_SHIFT)
258 #define GITS_CBASER_PA_SHIFT 12
259 #define GITS_CBASER_PA_MASK (0xFFFFFFFFFUL << GITS_CBASER_PA_SHIFT)
261 #define GITS_CWRITER (0x0088)
262 #define GITS_CREADR (0x0090)
264 #define GITS_BASER_BASE (0x0100)
265 #define GITS_BASER(x) (GITS_BASER_BASE + (x) * 8)
267 #define GITS_BASER_VALID (1UL << 63)
269 #define GITS_BASER_TYPE_SHIFT 56
270 #define GITS_BASER_TYPE(x) \
271 (((x) & GITS_BASER_TYPE_MASK) >> GITS_BASER_TYPE_SHIFT)
272 #define GITS_BASER_TYPE_UNIMPL 0x0UL /* Unimplemented */
273 #define GITS_BASER_TYPE_DEV 0x1UL /* Devices */
274 #define GITS_BASER_TYPE_VP 0x2UL /* Virtual Processors */
275 #define GITS_BASER_TYPE_PP 0x3UL /* Physical Processors */
276 #define GITS_BASER_TYPE_IC 0x4UL /* Interrupt Collections */
277 #define GITS_BASER_TYPE_RES5 0x5UL /* Reserved */
278 #define GITS_BASER_TYPE_RES6 0x6UL /* Reserved */
279 #define GITS_BASER_TYPE_RES7 0x7UL /* Reserved */
280 #define GITS_BASER_TYPE_MASK (0x7UL << GITS_BASER_TYPE_SHIFT)
283 * 0x0 - Non-cacheable, non-bufferable
284 * 0x1 - Non-cacheable
285 * 0x2 - Read-allocate, Write-through
286 * 0x3 - Read-allocate, Write-back
287 * 0x4 - Write-allocate, Write-through
288 * 0x5 - Write-allocate, Write-back
289 * 0x6 - Read-allocate, Write-allocate, Write-through
290 * 0x7 - Read-allocate, Write-allocate, Write-back
292 #define GITS_BASER_CACHE_SHIFT 59
293 #define GITS_BASER_CACHE_NCNB 0x0UL
294 #define GITS_BASER_CACHE_NC 0x1UL
295 #define GITS_BASER_CACHE_RAWT 0x2UL
296 #define GITS_BASER_CACHE_RAWB 0x3UL
297 #define GITS_BASER_CACHE_WAWT 0x4UL
298 #define GITS_BASER_CACHE_WAWB 0x5UL
299 #define GITS_BASER_CACHE_RAWAWT 0x6UL
300 #define GITS_BASER_CACHE_RAWAWB 0x7UL
301 #define GITS_BASER_CACHE_MASK (0x7UL << GITS_BASER_CACHE_SHIFT)
303 #define GITS_BASER_ESIZE_SHIFT 48
304 #define GITS_BASER_ESIZE_MASK (0x1FUL << GITS_BASER_ESIZE_SHIFT)
305 #define GITS_BASER_ESIZE(x) \
306 ((((x) & GITS_BASER_ESIZE_MASK) >> GITS_BASER_ESIZE_SHIFT) + 1)
308 #define GITS_BASER_PA_SHIFT 12
309 #define GITS_BASER_PA_MASK (0xFFFFFFFFFUL << GITS_BASER_PA_SHIFT)
313 * 0x0 - Non-shareable
314 * 0x1 - Inner-shareable
315 * 0x2 - Outer-shareable
316 * 0x3 - Reserved. Threated as 0x0
318 #define GITS_BASER_SHARE_SHIFT 10
319 #define GITS_BASER_SHARE_NS 0x0UL
320 #define GITS_BASER_SHARE_IS 0x1UL
321 #define GITS_BASER_SHARE_OS 0x2UL
322 #define GITS_BASER_SHARE_RES 0x3UL
323 #define GITS_BASER_SHARE_MASK (0x3UL << GITS_BASER_SHARE_SHIFT)
325 #define GITS_BASER_PSZ_SHIFT 8
326 #define GITS_BASER_PSZ_4K 0x0UL
327 #define GITS_BASER_PSZ_16K 0x1UL
328 #define GITS_BASER_PSZ_64K 0x2UL
329 #define GITS_BASER_PSZ_MASK (0x3UL << GITS_BASER_PSZ_SHIFT)
331 #define GITS_BASER_SIZE_MASK 0xFFUL
333 #define GITS_BASER_NUM 8
335 #define GITS_TYPER (0x0008)
336 #define GITS_TYPER_PTA (1UL << 19)
337 #define GITS_TYPER_DEVB_SHIFT 13
338 #define GITS_TYPER_DEVB_MASK (0x1FUL << GITS_TYPER_DEVB_SHIFT)
339 /* Number of device identifiers implemented */
340 #define GITS_TYPER_DEVB(x) \
341 ((((x) & GITS_TYPER_DEVB_MASK) >> GITS_TYPER_DEVB_SHIFT) + 1)
342 #define GITS_TYPER_ITTES_SHIFT 4
343 #define GITS_TYPER_ITTES_MASK (0xFUL << GITS_TYPER_ITTES_SHIFT)
344 /* Number of bytes per ITT Entry */
345 #define GITS_TYPER_ITTES(x) \
346 ((((x) & GITS_TYPER_ITTES_MASK) >> GITS_TYPER_ITTES_SHIFT) + 1)
348 #define GITS_TRANSLATER (0x10040)
352 #define LPI_CONF_PRIO_MASK (0xFC)
353 #define LPI_CONF_GROUP1 (1 << 1)
354 #define LPI_CONF_ENABLE (1 << 0)
361 * Registers list (ICC_xyz_EL1):
363 * PMR - Priority Mask Register
364 * * interrupts of priority higher than specified
365 * in this mask will be signalled to the CPU.
366 * (0xff - lowest possible prio., 0x00 - highest prio.)
368 * CTLR - Control Register
369 * * controls behavior of the CPU interface and displays
370 * implemented features.
372 * IGRPEN1 - Interrupt Group 1 Enable Register
374 * IAR1 - Interrupt Acknowledge Register Group 1
375 * * contains number of the highest priority pending
376 * interrupt from the Group 1.
378 * EOIR1 - End of Interrupt Register Group 1
379 * * Writes inform CPU interface about completed Group 1
380 * interrupts processing.
383 #define gic_icc_write(reg, val) \
385 WRITE_SPECIALREG(ICC_ ##reg ##_EL1, val); \
389 #define gic_icc_read(reg) \
393 val = READ_SPECIALREG(ICC_ ##reg ##_EL1); \
397 #define gic_icc_set(reg, mask) \
400 val = gic_icc_read(reg); \
402 gic_icc_write(reg, val); \
405 #define gic_icc_clear(reg, mask) \
408 val = gic_icc_read(reg); \
410 gic_icc_write(reg, val); \
413 #endif /* _GIC_V3_REG_H_ */