2 * Copyright (c) 2015 The FreeBSD Foundation
5 * This software was developed by Semihalf under
6 * the sponsorship of the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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32 #ifndef _GIC_V3_VAR_H_
33 #define _GIC_V3_VAR_H_
35 #include <arm/arm/gic_common.h>
37 #define GIC_V3_DEVSTR "ARM Generic Interrupt Controller v3.0"
39 DECLARE_CLASS(gic_v3_driver);
44 vm_offset_t conf_base;
45 vm_offset_t pend_base[MAXCPU];
51 * Re-Distributor region description.
52 * We will have few of those depending
53 * on the #redistributor-regions property in FDT.
55 struct resource ** regions;
56 /* Number of Re-Distributor regions */
58 /* Per-CPU Re-Distributor handler */
59 struct resource * pcpu[MAXCPU];
61 struct redist_lpis lpis;
66 struct resource ** gic_res;
69 struct resource * gic_dist;
71 struct gic_redists gic_redists;
79 boolean_t gic_registered;
82 device_t *gic_children;
83 struct intr_pic *gic_pic;
84 struct gic_v3_irqsrc *gic_irqs;
88 struct gic_v3_devinfo {
93 #define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc)
95 MALLOC_DECLARE(M_GIC_V3);
98 #define GICV3_IVAR_NIRQS 1000
99 #define GICV3_IVAR_REDIST_VADDR 1001
101 __BUS_ACCESSOR(gicv3, nirqs, GICV3, NIRQS, u_int);
102 __BUS_ACCESSOR(gicv3, redist_vaddr, GICV3, REDIST_VADDR, void *);
105 int gic_v3_attach(device_t dev);
106 int gic_v3_detach(device_t dev);
107 int arm_gic_v3_intr(void *);
109 uint32_t gic_r_read_4(device_t, bus_size_t);
110 uint64_t gic_r_read_8(device_t, bus_size_t);
111 void gic_r_write_4(device_t, bus_size_t, uint32_t var);
112 void gic_r_write_8(device_t, bus_size_t, uint64_t var);
115 * GIC Distributor accessors.
116 * Notice that only GIC sofc can be passed.
118 #define gic_d_read(sc, len, reg) \
120 bus_read_##len(sc->gic_dist, reg); \
123 #define gic_d_write(sc, len, reg, val) \
125 bus_write_##len(sc->gic_dist, reg, val);\
128 /* GIC Re-Distributor accessors (per-CPU) */
129 #define gic_r_read(sc, len, reg) \
131 u_int cpu = PCPU_GET(cpuid); \
134 sc->gic_redists.pcpu[cpu], \
138 #define gic_r_write(sc, len, reg, val) \
140 u_int cpu = PCPU_GET(cpuid); \
143 sc->gic_redists.pcpu[cpu], \
147 #endif /* _GIC_V3_VAR_H_ */