2 * Copyright (c) 2015 The FreeBSD Foundation
4 * This software was developed by Semihalf under
5 * the sponsorship of the FreeBSD Foundation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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31 #ifndef _GIC_V3_VAR_H_
32 #define _GIC_V3_VAR_H_
34 #include <arm/arm/gic_common.h>
36 #define GIC_V3_DEVSTR "ARM Generic Interrupt Controller v3.0"
38 DECLARE_CLASS(gic_v3_driver);
43 struct resource res; /* mem resource for redist */
44 vm_offset_t pend_base;
45 bool lpi_enabled; /* redist LPI configured? */
50 * Re-Distributor region description.
51 * We will have few of those depending
52 * on the #redistributor-regions property in FDT.
54 struct resource ** regions;
55 /* Number of Re-Distributor regions */
57 /* Per-CPU Re-Distributor data */
58 struct redist_pcpu *pcpu[MAXCPU];
63 struct resource ** gic_res;
66 struct resource * gic_dist;
68 struct gic_redists gic_redists;
70 /* Message Based Interrupts */
73 struct mtx gic_mbi_mtx;
81 boolean_t gic_registered;
84 device_t *gic_children;
85 struct intr_pic *gic_pic;
86 struct gic_v3_irqsrc *gic_irqs;
89 struct gic_v3_devinfo {
94 #define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc)
96 MALLOC_DECLARE(M_GIC_V3);
99 #define GICV3_IVAR_NIRQS 1000
100 /* 1001 was GICV3_IVAR_REDIST_VADDR */
101 #define GICV3_IVAR_REDIST 1002
103 __BUS_ACCESSOR(gicv3, nirqs, GICV3, NIRQS, u_int);
104 __BUS_ACCESSOR(gicv3, redist, GICV3, REDIST, void *);
107 int gic_v3_attach(device_t dev);
108 int gic_v3_detach(device_t dev);
109 int arm_gic_v3_intr(void *);
111 uint32_t gic_r_read_4(device_t, bus_size_t);
112 uint64_t gic_r_read_8(device_t, bus_size_t);
113 void gic_r_write_4(device_t, bus_size_t, uint32_t var);
114 void gic_r_write_8(device_t, bus_size_t, uint64_t var);
117 * GIC Distributor accessors.
118 * Notice that only GIC sofc can be passed.
120 #define gic_d_read(sc, len, reg) \
122 bus_read_##len(sc->gic_dist, reg); \
125 #define gic_d_write(sc, len, reg, val) \
127 bus_write_##len(sc->gic_dist, reg, val);\
130 /* GIC Re-Distributor accessors (per-CPU) */
131 #define gic_r_read(sc, len, reg) \
133 u_int cpu = PCPU_GET(cpuid); \
136 &sc->gic_redists.pcpu[cpu]->res, \
140 #define gic_r_write(sc, len, reg, val) \
142 u_int cpu = PCPU_GET(cpuid); \
145 &sc->gic_redists.pcpu[cpu]->res, \
149 #endif /* _GIC_V3_VAR_H_ */