sys/arm64/arm64/gicv3_its.c

   1 /*-
   2  * Copyright (c) 2015-2016 The FreeBSD Foundation
   3  * All rights reserved.
   4  *
   5  * This software was developed by Andrew Turner under
   6  * the sponsorship of the FreeBSD Foundation.
   7  *
   8  * This software was developed by Semihalf under
   9  * the sponsorship of the FreeBSD Foundation.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  */
  32
  33 #include "opt_acpi.h"
  34 #include "opt_platform.h"
  35
  36 #include <sys/cdefs.h>
  37 __FBSDID("$FreeBSD$");
  38
  39 #include <sys/param.h>
  40 #include <sys/systm.h>
  41 #include <sys/bus.h>
  42 #include <sys/cpuset.h>
  43 #include <sys/endian.h>
  44 #include <sys/kernel.h>
  45 #include <sys/lock.h>
  46 #include <sys/malloc.h>
  47 #include <sys/module.h>
  48 #include <sys/mutex.h>
  49 #include <sys/proc.h>
  50 #include <sys/queue.h>
  51 #include <sys/rman.h>
  52 #include <sys/smp.h>
  53 #include <sys/vmem.h>
  54
  55 #include <vm/vm.h>
  56 #include <vm/pmap.h>
  57
  58 #include <machine/bus.h>
  59 #include <machine/intr.h>
  60
  61 #include <arm/arm/gic_common.h>
  62 #include <arm64/arm64/gic_v3_reg.h>
  63 #include <arm64/arm64/gic_v3_var.h>
  64
  65 #ifdef FDT
  66 #include <dev/ofw/openfirm.h>
  67 #include <dev/ofw/ofw_bus.h>
  68 #include <dev/ofw/ofw_bus_subr.h>
  69 #endif
  70 #include <dev/pci/pcireg.h>
  71 #include <dev/pci/pcivar.h>
  72
  73 #include "pcib_if.h"
  74 #include "pic_if.h"
  75 #include "msi_if.h"
  76
  77 MALLOC_DEFINE(M_GICV3_ITS, "GICv3 ITS",
  78     "ARM GICv3 Interrupt Translation Service");
  79
  80 #define LPI_NIRQS               (64 * 1024)
  81
  82 /* The size and alignment of the command circular buffer */
  83 #define ITS_CMDQ_SIZE           (64 * 1024)     /* Must be a multiple of 4K */
  84 #define ITS_CMDQ_ALIGN          (64 * 1024)
  85
  86 #define LPI_CONFTAB_SIZE        LPI_NIRQS
  87 #define LPI_CONFTAB_ALIGN       (64 * 1024)
  88 #define LPI_CONFTAB_MAX_ADDR    ((1ul << 48) - 1) /* We need a 47 bit PA */
  89
  90 /* 1 bit per SPI, PPI, and SGI (8k), and 1 bit per LPI (LPI_CONFTAB_SIZE) */
  91 #define LPI_PENDTAB_SIZE        ((LPI_NIRQS + GIC_FIRST_LPI) / 8)
  92 #define LPI_PENDTAB_ALIGN       (64 * 1024)
  93 #define LPI_PENDTAB_MAX_ADDR    ((1ul << 48) - 1) /* We need a 47 bit PA */
  94
  95 #define LPI_INT_TRANS_TAB_ALIGN 256
  96 #define LPI_INT_TRANS_TAB_MAX_ADDR ((1ul << 48) - 1)
  97
  98 /* ITS commands encoding */
  99 #define ITS_CMD_MOVI            (0x01)
 100 #define ITS_CMD_SYNC            (0x05)
 101 #define ITS_CMD_MAPD            (0x08)
 102 #define ITS_CMD_MAPC            (0x09)
 103 #define ITS_CMD_MAPTI           (0x0a)
 104 #define ITS_CMD_MAPI            (0x0b)
 105 #define ITS_CMD_INV             (0x0c)
 106 #define ITS_CMD_INVALL          (0x0d)
 107 /* Command */
 108 #define CMD_COMMAND_MASK        (0xFFUL)
 109 /* PCI device ID */
 110 #define CMD_DEVID_SHIFT         (32)
 111 #define CMD_DEVID_MASK          (0xFFFFFFFFUL << CMD_DEVID_SHIFT)
 112 /* Size of IRQ ID bitfield */
 113 #define CMD_SIZE_MASK           (0xFFUL)
 114 /* Virtual LPI ID */
 115 #define CMD_ID_MASK             (0xFFFFFFFFUL)
 116 /* Physical LPI ID */
 117 #define CMD_PID_SHIFT           (32)
 118 #define CMD_PID_MASK            (0xFFFFFFFFUL << CMD_PID_SHIFT)
 119 /* Collection */
 120 #define CMD_COL_MASK            (0xFFFFUL)
 121 /* Target (CPU or Re-Distributor) */
 122 #define CMD_TARGET_SHIFT        (16)
 123 #define CMD_TARGET_MASK         (0xFFFFFFFFUL << CMD_TARGET_SHIFT)
 124 /* Interrupt Translation Table address */
 125 #define CMD_ITT_MASK            (0xFFFFFFFFFF00UL)
 126 /* Valid command bit */
 127 #define CMD_VALID_SHIFT         (63)
 128 #define CMD_VALID_MASK          (1UL << CMD_VALID_SHIFT)
 129
 130 #define ITS_TARGET_NONE         0xFBADBEEF
 131
 132 /* LPI chunk owned by ITS device */
 133 struct lpi_chunk {
 134         u_int   lpi_base;
 135         u_int   lpi_free;       /* First free LPI in set */
 136         u_int   lpi_num;        /* Total number of LPIs in chunk */
 137         u_int   lpi_busy;       /* Number of busy LPIs in chink */
 138 };
 139
 140 /* ITS device */
 141 struct its_dev {
 142         TAILQ_ENTRY(its_dev)    entry;
 143         /* PCI device */
 144         device_t                pci_dev;
 145         /* Device ID (i.e. PCI device ID) */
 146         uint32_t                devid;
 147         /* List of assigned LPIs */
 148         struct lpi_chunk        lpis;
 149         /* Virtual address of ITT */
 150         vm_offset_t             itt;
 151         size_t                  itt_size;
 152 };
 153
 154 /*
 155  * ITS command descriptor.
 156  * Idea for command description passing taken from Linux.
 157  */
 158 struct its_cmd_desc {
 159         uint8_t cmd_type;
 160
 161         union {
 162                 struct {
 163                         struct its_dev *its_dev;
 164                         struct its_col *col;
 165                         uint32_t id;
 166                 } cmd_desc_movi;
 167
 168                 struct {
 169                         struct its_col *col;
 170                 } cmd_desc_sync;
 171
 172                 struct {
 173                         struct its_col *col;
 174                         uint8_t valid;
 175                 } cmd_desc_mapc;
 176
 177                 struct {
 178                         struct its_dev *its_dev;
 179                         struct its_col *col;
 180                         uint32_t pid;
 181                         uint32_t id;
 182                 } cmd_desc_mapvi;
 183
 184                 struct {
 185                         struct its_dev *its_dev;
 186                         struct its_col *col;
 187                         uint32_t pid;
 188                 } cmd_desc_mapi;
 189
 190                 struct {
 191                         struct its_dev *its_dev;
 192                         uint8_t valid;
 193                 } cmd_desc_mapd;
 194
 195                 struct {
 196                         struct its_dev *its_dev;
 197                         struct its_col *col;
 198                         uint32_t pid;
 199                 } cmd_desc_inv;
 200
 201                 struct {
 202                         struct its_col *col;
 203                 } cmd_desc_invall;
 204         };
 205 };
 206
 207 /* ITS command. Each command is 32 bytes long */
 208 struct its_cmd {
 209         uint64_t        cmd_dword[4];   /* ITS command double word */
 210 };
 211
 212 /* An ITS private table */
 213 struct its_ptable {
 214         vm_offset_t     ptab_vaddr;
 215         unsigned long   ptab_size;
 216 };
 217
 218 /* ITS collection description. */
 219 struct its_col {
 220         uint64_t        col_target;     /* Target Re-Distributor */
 221         uint64_t        col_id;         /* Collection ID */
 222 };
 223
 224 struct gicv3_its_irqsrc {
 225         struct intr_irqsrc      gi_isrc;
 226         u_int                   gi_id;
 227         u_int                   gi_lpi;
 228         struct its_dev          *gi_its_dev;
 229 };
 230
 231 struct gicv3_its_softc {
 232         struct intr_pic *sc_pic;
 233         struct resource *sc_its_res;
 234
 235         cpuset_t        sc_cpus;
 236         u_int           gic_irq_cpu;
 237
 238         struct its_ptable sc_its_ptab[GITS_BASER_NUM];
 239         struct its_col *sc_its_cols[MAXCPU];    /* Per-CPU collections */
 240
 241         /*
 242          * TODO: We should get these from the parent as we only want a
 243          * single copy of each across the interrupt controller.
 244          */
 245         uint8_t         *sc_conf_base;
 246         vm_offset_t sc_pend_base[MAXCPU];
 247
 248         /* Command handling */
 249         struct mtx sc_its_cmd_lock;
 250         struct its_cmd *sc_its_cmd_base; /* Command circular buffer address */
 251         size_t sc_its_cmd_next_idx;
 252
 253         vmem_t *sc_irq_alloc;
 254         struct gicv3_its_irqsrc *sc_irqs;
 255         u_int   sc_irq_base;
 256         u_int   sc_irq_length;
 257
 258         struct mtx sc_its_dev_lock;
 259         TAILQ_HEAD(its_dev_list, its_dev) sc_its_dev_list;
 260
 261 #define ITS_FLAGS_CMDQ_FLUSH            0x00000001
 262 #define ITS_FLAGS_LPI_CONF_FLUSH        0x00000002
 263 #define ITS_FLAGS_ERRATA_CAVIUM_22375   0x00000004
 264         u_int sc_its_flags;
 265 };
 266
 267 static void *conf_base;
 268
 269 typedef void (its_quirk_func_t)(device_t);
 270 static its_quirk_func_t its_quirk_cavium_22375;
 271
 272 static const struct {
 273         const char *desc;
 274         uint32_t iidr;
 275         uint32_t iidr_mask;
 276         its_quirk_func_t *func;
 277 } its_quirks[] = {
 278         {
 279                 /* Cavium ThunderX Pass 1.x */
 280                 .desc = "Cavium ThunderX errata: 22375, 24313",
 281                 .iidr = GITS_IIDR_RAW(GITS_IIDR_IMPL_CAVIUM,
 282                     GITS_IIDR_PROD_THUNDER, GITS_IIDR_VAR_THUNDER_1, 0),
 283                 .iidr_mask = ~GITS_IIDR_REVISION_MASK,
 284                 .func = its_quirk_cavium_22375,
 285         },
 286 };
 287
 288 #define gic_its_read_4(sc, reg)                 \
 289     bus_read_4((sc)->sc_its_res, (reg))
 290 #define gic_its_read_8(sc, reg)                 \
 291     bus_read_8((sc)->sc_its_res, (reg))
 292
 293 #define gic_its_write_4(sc, reg, val)           \
 294     bus_write_4((sc)->sc_its_res, (reg), (val))
 295 #define gic_its_write_8(sc, reg, val)           \
 296     bus_write_8((sc)->sc_its_res, (reg), (val))
 297
 298 static device_attach_t gicv3_its_attach;
 299 static device_detach_t gicv3_its_detach;
 300
 301 static pic_disable_intr_t gicv3_its_disable_intr;
 302 static pic_enable_intr_t gicv3_its_enable_intr;
 303 static pic_map_intr_t gicv3_its_map_intr;
 304 static pic_setup_intr_t gicv3_its_setup_intr;
 305 static pic_post_filter_t gicv3_its_post_filter;
 306 static pic_post_ithread_t gicv3_its_post_ithread;
 307 static pic_pre_ithread_t gicv3_its_pre_ithread;
 308 static pic_bind_intr_t gicv3_its_bind_intr;
 309 #ifdef SMP
 310 static pic_init_secondary_t gicv3_its_init_secondary;
 311 #endif
 312 static msi_alloc_msi_t gicv3_its_alloc_msi;
 313 static msi_release_msi_t gicv3_its_release_msi;
 314 static msi_alloc_msix_t gicv3_its_alloc_msix;
 315 static msi_release_msix_t gicv3_its_release_msix;
 316 static msi_map_msi_t gicv3_its_map_msi;
 317
 318 static void its_cmd_movi(device_t, struct gicv3_its_irqsrc *);
 319 static void its_cmd_mapc(device_t, struct its_col *, uint8_t);
 320 static void its_cmd_mapti(device_t, struct gicv3_its_irqsrc *);
 321 static void its_cmd_mapd(device_t, struct its_dev *, uint8_t);
 322 static void its_cmd_inv(device_t, struct its_dev *, struct gicv3_its_irqsrc *);
 323 static void its_cmd_invall(device_t, struct its_col *);
 324
 325 static device_method_t gicv3_its_methods[] = {
 326         /* Device interface */
 327         DEVMETHOD(device_detach,        gicv3_its_detach),
 328
 329         /* Interrupt controller interface */
 330         DEVMETHOD(pic_disable_intr,     gicv3_its_disable_intr),
 331         DEVMETHOD(pic_enable_intr,      gicv3_its_enable_intr),
 332         DEVMETHOD(pic_map_intr,         gicv3_its_map_intr),
 333         DEVMETHOD(pic_setup_intr,       gicv3_its_setup_intr),
 334         DEVMETHOD(pic_post_filter,      gicv3_its_post_filter),
 335         DEVMETHOD(pic_post_ithread,     gicv3_its_post_ithread),
 336         DEVMETHOD(pic_pre_ithread,      gicv3_its_pre_ithread),
 337 #ifdef SMP
 338         DEVMETHOD(pic_bind_intr,        gicv3_its_bind_intr),
 339         DEVMETHOD(pic_init_secondary,   gicv3_its_init_secondary),
 340 #endif
 341
 342         /* MSI/MSI-X */
 343         DEVMETHOD(msi_alloc_msi,        gicv3_its_alloc_msi),
 344         DEVMETHOD(msi_release_msi,      gicv3_its_release_msi),
 345         DEVMETHOD(msi_alloc_msix,       gicv3_its_alloc_msix),
 346         DEVMETHOD(msi_release_msix,     gicv3_its_release_msix),
 347         DEVMETHOD(msi_map_msi,          gicv3_its_map_msi),
 348
 349         /* End */
 350         DEVMETHOD_END
 351 };
 352
 353 static DEFINE_CLASS_0(gic, gicv3_its_driver, gicv3_its_methods,
 354     sizeof(struct gicv3_its_softc));
 355
 356 static void
 357 gicv3_its_cmdq_init(struct gicv3_its_softc *sc)
 358 {
 359         vm_paddr_t cmd_paddr;
 360         uint64_t reg, tmp;
 361
 362         /* Set up the command circular buffer */
 363         sc->sc_its_cmd_base = contigmalloc(ITS_CMDQ_SIZE, M_GICV3_ITS,
 364             M_WAITOK | M_ZERO, 0, (1ul << 48) - 1, ITS_CMDQ_ALIGN, 0);
 365         sc->sc_its_cmd_next_idx = 0;
 366
 367         cmd_paddr = vtophys(sc->sc_its_cmd_base);
 368
 369         /* Set the base of the command buffer */
 370         reg = GITS_CBASER_VALID |
 371             (GITS_CBASER_CACHE_NIWAWB << GITS_CBASER_CACHE_SHIFT) |
 372             cmd_paddr | (GITS_CBASER_SHARE_IS << GITS_CBASER_SHARE_SHIFT) |
 373             (ITS_CMDQ_SIZE / 4096 - 1);
 374         gic_its_write_8(sc, GITS_CBASER, reg);
 375
 376         /* Read back to check for fixed value fields */
 377         tmp = gic_its_read_8(sc, GITS_CBASER);
 378
 379         if ((tmp & GITS_CBASER_SHARE_MASK) !=
 380             (GITS_CBASER_SHARE_IS << GITS_CBASER_SHARE_SHIFT)) {
 381                 /* Check if the hardware reported non-shareable */
 382                 if ((tmp & GITS_CBASER_SHARE_MASK) ==
 383                     (GITS_CBASER_SHARE_NS << GITS_CBASER_SHARE_SHIFT)) {
 384                         /* If so remove the cache attribute */
 385                         reg &= ~GITS_CBASER_CACHE_MASK;
 386                         reg &= ~GITS_CBASER_SHARE_MASK;
 387                         /* Set to Non-cacheable, Non-shareable */
 388                         reg |= GITS_CBASER_CACHE_NIN << GITS_CBASER_CACHE_SHIFT;
 389                         reg |= GITS_CBASER_SHARE_NS << GITS_CBASER_SHARE_SHIFT;
 390
 391                         gic_its_write_8(sc, GITS_CBASER, reg);
 392                 }
 393
 394                 /* The command queue has to be flushed after each command */
 395                 sc->sc_its_flags |= ITS_FLAGS_CMDQ_FLUSH;
 396         }
 397
 398         /* Get the next command from the start of the buffer */
 399         gic_its_write_8(sc, GITS_CWRITER, 0x0);
 400 }
 401
 402 static int
 403 gicv3_its_table_init(device_t dev, struct gicv3_its_softc *sc)
 404 {
 405         vm_offset_t table;
 406         vm_paddr_t paddr;
 407         uint64_t cache, reg, share, tmp, type;
 408         size_t esize, its_tbl_size, nidents, nitspages, npages;
 409         int i, page_size;
 410         int devbits;
 411
 412         if ((sc->sc_its_flags & ITS_FLAGS_ERRATA_CAVIUM_22375) != 0) {
 413                 /*
 414                  * GITS_TYPER[17:13] of ThunderX reports that device IDs
 415                  * are to be 21 bits in length. The entry size of the ITS
 416                  * table can be read from GITS_BASERn[52:48] and on ThunderX
 417                  * is supposed to be 8 bytes in length (for device table).
 418                  * Finally the page size that is to be used by ITS to access
 419                  * this table will be set to 64KB.
 420                  *
 421                  * This gives 0x200000 entries of size 0x8 bytes covered by
 422                  * 256 pages each of which 64KB in size. The number of pages
 423                  * (minus 1) should then be written to GITS_BASERn[7:0]. In
 424                  * that case this value would be 0xFF but on ThunderX the
 425                  * maximum value that HW accepts is 0xFD.
 426                  *
 427                  * Set an arbitrary number of device ID bits to 20 in order
 428                  * to limit the number of entries in ITS device table to
 429                  * 0x100000 and the table size to 8MB.
 430                  */
 431                 devbits = 20;
 432                 cache = 0;
 433         } else {
 434                 devbits = GITS_TYPER_DEVB(gic_its_read_8(sc, GITS_TYPER));
 435                 cache = GITS_BASER_CACHE_WAWB;
 436         }
 437         share = GITS_BASER_SHARE_IS;
 438         page_size = PAGE_SIZE_64K;
 439
 440         for (i = 0; i < GITS_BASER_NUM; i++) {
 441                 reg = gic_its_read_8(sc, GITS_BASER(i));
 442                 /* The type of table */
 443                 type = GITS_BASER_TYPE(reg);
 444                 /* The table entry size */
 445                 esize = GITS_BASER_ESIZE(reg);
 446
 447                 switch(type) {
 448                 case GITS_BASER_TYPE_DEV:
 449                         nidents = (1 << devbits);
 450                         its_tbl_size = esize * nidents;
 451                         its_tbl_size = roundup2(its_tbl_size, PAGE_SIZE_64K);
 452                         break;
 453                 case GITS_BASER_TYPE_VP:
 454                 case GITS_BASER_TYPE_PP: /* Undocumented? */
 455                 case GITS_BASER_TYPE_IC:
 456                         its_tbl_size = page_size;
 457                         break;
 458                 default:
 459                         continue;
 460                 }
 461                 npages = howmany(its_tbl_size, PAGE_SIZE);
 462
 463                 /* Allocate the table */
 464                 table = (vm_offset_t)contigmalloc(npages * PAGE_SIZE,
 465                     M_GICV3_ITS, M_WAITOK | M_ZERO, 0, (1ul << 48) - 1,
 466                     PAGE_SIZE_64K, 0);
 467
 468                 sc->sc_its_ptab[i].ptab_vaddr = table;
 469                 sc->sc_its_ptab[i].ptab_size = npages * PAGE_SIZE;
 470
 471                 paddr = vtophys(table);
 472
 473                 while (1) {
 474                         nitspages = howmany(its_tbl_size, page_size);
 475
 476                         /* Clear the fields we will be setting */
 477                         reg &= ~(GITS_BASER_VALID |
 478                             GITS_BASER_CACHE_MASK | GITS_BASER_TYPE_MASK |
 479                             GITS_BASER_ESIZE_MASK | GITS_BASER_PA_MASK |
 480                             GITS_BASER_SHARE_MASK | GITS_BASER_PSZ_MASK |
 481                             GITS_BASER_SIZE_MASK);
 482                         /* Set the new values */
 483                         reg |= GITS_BASER_VALID |
 484                             (cache << GITS_BASER_CACHE_SHIFT) |
 485                             (type << GITS_BASER_TYPE_SHIFT) |
 486                             ((esize - 1) << GITS_BASER_ESIZE_SHIFT) |
 487                             paddr | (share << GITS_BASER_SHARE_SHIFT) |
 488                             (nitspages - 1);
 489
 490                         switch (page_size) {
 491                         case PAGE_SIZE:         /* 4KB */
 492                                 reg |=
 493                                     GITS_BASER_PSZ_4K << GITS_BASER_PSZ_SHIFT;
 494                                 break;
 495                         case PAGE_SIZE_16K:     /* 16KB */
 496                                 reg |=
 497                                     GITS_BASER_PSZ_16K << GITS_BASER_PSZ_SHIFT;
 498                                 break;
 499                         case PAGE_SIZE_64K:     /* 64KB */
 500                                 reg |=
 501                                     GITS_BASER_PSZ_64K << GITS_BASER_PSZ_SHIFT;
 502                                 break;
 503                         }
 504
 505                         gic_its_write_8(sc, GITS_BASER(i), reg);
 506
 507                         /* Read back to check */
 508                         tmp = gic_its_read_8(sc, GITS_BASER(i));
 509
 510                         /* Do the shareability masks line up? */
 511                         if ((tmp & GITS_BASER_SHARE_MASK) !=
 512                             (reg & GITS_BASER_SHARE_MASK)) {
 513                                 share = (tmp & GITS_BASER_SHARE_MASK) >>
 514                                     GITS_BASER_SHARE_SHIFT;
 515                                 continue;
 516                         }
 517
 518                         if ((tmp & GITS_BASER_PSZ_MASK) !=
 519                             (reg & GITS_BASER_PSZ_MASK)) {
 520                                 switch (page_size) {
 521                                 case PAGE_SIZE_16K:
 522                                         page_size = PAGE_SIZE;
 523                                         continue;
 524                                 case PAGE_SIZE_64K:
 525                                         page_size = PAGE_SIZE_16K;
 526                                         continue;
 527                                 }
 528                         }
 529
 530                         if (tmp != reg) {
 531                                 device_printf(dev, "GITS_BASER%d: "
 532                                     "unable to be updated: %lx != %lx\n",
 533                                     i, reg, tmp);
 534                                 return (ENXIO);
 535                         }
 536
 537                         /* We should have made all needed changes */
 538                         break;
 539                 }
 540         }
 541
 542         return (0);
 543 }
 544
 545 static void
 546 gicv3_its_conftable_init(struct gicv3_its_softc *sc)
 547 {
 548         void *conf_table;
 549
 550         conf_table = atomic_load_ptr(&conf_base);
 551         if (conf_table == NULL) {
 552                 conf_table = contigmalloc(LPI_CONFTAB_SIZE,
 553                     M_GICV3_ITS, M_WAITOK, 0, LPI_CONFTAB_MAX_ADDR,
 554                     LPI_CONFTAB_ALIGN, 0);
 555
 556                 if (atomic_cmpset_ptr((uintptr_t *)&conf_base,
 557                     (uintptr_t)NULL, (uintptr_t)conf_table) == 0) {
 558                         contigfree(conf_table, LPI_CONFTAB_SIZE, M_GICV3_ITS);
 559                         conf_table = atomic_load_ptr(&conf_base);
 560                 }
 561         }
 562         sc->sc_conf_base = conf_table;
 563
 564         /* Set the default configuration */
 565         memset(sc->sc_conf_base, GIC_PRIORITY_MAX | LPI_CONF_GROUP1,
 566             LPI_CONFTAB_SIZE);
 567
 568         /* Flush the table to memory */
 569         cpu_dcache_wb_range((vm_offset_t)sc->sc_conf_base, LPI_CONFTAB_SIZE);
 570 }
 571
 572 static void
 573 gicv3_its_pendtables_init(struct gicv3_its_softc *sc)
 574 {
 575         int i;
 576
 577         for (i = 0; i <= mp_maxid; i++) {
 578                 if (CPU_ISSET(i, &sc->sc_cpus) == 0)
 579                         continue;
 580
 581                 sc->sc_pend_base[i] = (vm_offset_t)contigmalloc(
 582                     LPI_PENDTAB_SIZE, M_GICV3_ITS, M_WAITOK | M_ZERO,
 583                     0, LPI_PENDTAB_MAX_ADDR, LPI_PENDTAB_ALIGN, 0);
 584
 585                 /* Flush so the ITS can see the memory */
 586                 cpu_dcache_wb_range((vm_offset_t)sc->sc_pend_base[i],
 587                     LPI_PENDTAB_SIZE);
 588         }
 589 }
 590
 591 static void
 592 its_init_cpu_lpi(device_t dev, struct gicv3_its_softc *sc)
 593 {
 594         device_t gicv3;
 595         uint64_t xbaser, tmp;
 596         uint32_t ctlr;
 597         u_int cpuid;
 598
 599         gicv3 = device_get_parent(dev);
 600         cpuid = PCPU_GET(cpuid);
 601
 602         /* Disable LPIs */
 603         ctlr = gic_r_read_4(gicv3, GICR_CTLR);
 604         ctlr &= ~GICR_CTLR_LPI_ENABLE;
 605         gic_r_write_4(gicv3, GICR_CTLR, ctlr);
 606
 607         /* Make sure changes are observable my the GIC */
 608         dsb(sy);
 609
 610         /*
 611          * Set the redistributor base
 612          */
 613         xbaser = vtophys(sc->sc_conf_base) |
 614             (GICR_PROPBASER_SHARE_IS << GICR_PROPBASER_SHARE_SHIFT) |
 615             (GICR_PROPBASER_CACHE_NIWAWB << GICR_PROPBASER_CACHE_SHIFT) |
 616             (flsl(LPI_CONFTAB_SIZE | GIC_FIRST_LPI) - 1);
 617         gic_r_write_8(gicv3, GICR_PROPBASER, xbaser);
 618
 619         /* Check the cache attributes we set */
 620         tmp = gic_r_read_8(gicv3, GICR_PROPBASER);
 621
 622         if ((tmp & GICR_PROPBASER_SHARE_MASK) !=
 623             (xbaser & GICR_PROPBASER_SHARE_MASK)) {
 624                 if ((tmp & GICR_PROPBASER_SHARE_MASK) ==
 625                     (GICR_PROPBASER_SHARE_NS << GICR_PROPBASER_SHARE_SHIFT)) {
 626                         /* We need to mark as non-cacheable */
 627                         xbaser &= ~(GICR_PROPBASER_SHARE_MASK |
 628                             GICR_PROPBASER_CACHE_MASK);
 629                         /* Non-cacheable */
 630                         xbaser |= GICR_PROPBASER_CACHE_NIN <<
 631                             GICR_PROPBASER_CACHE_SHIFT;
 632                         /* Non-sareable */
 633                         xbaser |= GICR_PROPBASER_SHARE_NS <<
 634                             GICR_PROPBASER_SHARE_SHIFT;
 635                         gic_r_write_8(gicv3, GICR_PROPBASER, xbaser);
 636                 }
 637                 sc->sc_its_flags |= ITS_FLAGS_LPI_CONF_FLUSH;
 638         }
 639
 640         /*
 641          * Set the LPI pending table base
 642          */
 643         xbaser = vtophys(sc->sc_pend_base[cpuid]) |
 644             (GICR_PENDBASER_CACHE_NIWAWB << GICR_PENDBASER_CACHE_SHIFT) |
 645             (GICR_PENDBASER_SHARE_IS << GICR_PENDBASER_SHARE_SHIFT);
 646
 647         gic_r_write_8(gicv3, GICR_PENDBASER, xbaser);
 648
 649         tmp = gic_r_read_8(gicv3, GICR_PENDBASER);
 650
 651         if ((tmp & GICR_PENDBASER_SHARE_MASK) ==
 652             (GICR_PENDBASER_SHARE_NS << GICR_PENDBASER_SHARE_SHIFT)) {
 653                 /* Clear the cahce and shareability bits */
 654                 xbaser &= ~(GICR_PENDBASER_CACHE_MASK |
 655                     GICR_PENDBASER_SHARE_MASK);
 656                 /* Mark as non-shareable */
 657                 xbaser |= GICR_PENDBASER_SHARE_NS << GICR_PENDBASER_SHARE_SHIFT;
 658                 /* And non-cacheable */
 659                 xbaser |= GICR_PENDBASER_CACHE_NIN <<
 660                     GICR_PENDBASER_CACHE_SHIFT;
 661         }
 662
 663         /* Enable LPIs */
 664         ctlr = gic_r_read_4(gicv3, GICR_CTLR);
 665         ctlr |= GICR_CTLR_LPI_ENABLE;
 666         gic_r_write_4(gicv3, GICR_CTLR, ctlr);
 667
 668         /* Make sure the GIC has seen everything */
 669         dsb(sy);
 670 }
 671
 672 static int
 673 its_init_cpu(device_t dev, struct gicv3_its_softc *sc)
 674 {
 675         device_t gicv3;
 676         vm_paddr_t target;
 677         u_int cpuid;
 678         struct redist_pcpu *rpcpu;
 679
 680         gicv3 = device_get_parent(dev);
 681         cpuid = PCPU_GET(cpuid);
 682         if (!CPU_ISSET(cpuid, &sc->sc_cpus))
 683                 return (0);
 684
 685         /* Check if the ITS is enabled on this CPU */
 686         if ((gic_r_read_4(gicv3, GICR_TYPER) & GICR_TYPER_PLPIS) == 0)
 687                 return (ENXIO);
 688
 689         rpcpu = gicv3_get_redist(dev);
 690
 691         /* Do per-cpu LPI init once */
 692         if (!rpcpu->lpi_enabled) {
 693                 its_init_cpu_lpi(dev, sc);
 694                 rpcpu->lpi_enabled = true;
 695         }
 696
 697         if ((gic_its_read_8(sc, GITS_TYPER) & GITS_TYPER_PTA) != 0) {
 698                 /* This ITS wants the redistributor physical address */
 699                 target = vtophys(rman_get_virtual(&rpcpu->res));
 700         } else {
 701                 /* This ITS wants the unique processor number */
 702                 target = GICR_TYPER_CPUNUM(gic_r_read_8(gicv3, GICR_TYPER)) <<
 703                     CMD_TARGET_SHIFT;
 704         }
 705
 706         sc->sc_its_cols[cpuid]->col_target = target;
 707         sc->sc_its_cols[cpuid]->col_id = cpuid;
 708
 709         its_cmd_mapc(dev, sc->sc_its_cols[cpuid], 1);
 710         its_cmd_invall(dev, sc->sc_its_cols[cpuid]);
 711
 712         return (0);
 713 }
 714
 715 static int
 716 gicv3_its_attach(device_t dev)
 717 {
 718         struct gicv3_its_softc *sc;
 719         const char *name;
 720         uint32_t iidr;
 721         int domain, err, i, rid;
 722
 723         sc = device_get_softc(dev);
 724
 725         sc->sc_irq_length = gicv3_get_nirqs(dev);
 726         sc->sc_irq_base = GIC_FIRST_LPI;
 727         sc->sc_irq_base += device_get_unit(dev) * sc->sc_irq_length;
 728
 729         rid = 0;
 730         sc->sc_its_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 731             RF_ACTIVE);
 732         if (sc->sc_its_res == NULL) {
 733                 device_printf(dev, "Could not allocate memory\n");
 734                 return (ENXIO);
 735         }
 736
 737         iidr = gic_its_read_4(sc, GITS_IIDR);
 738         for (i = 0; i < nitems(its_quirks); i++) {
 739                 if ((iidr & its_quirks[i].iidr_mask) == its_quirks[i].iidr) {
 740                         if (bootverbose) {
 741                                 device_printf(dev, "Applying %s\n",
 742                                     its_quirks[i].desc);
 743                         }
 744                         its_quirks[i].func(dev);
 745                         break;
 746                 }
 747         }
 748
 749         /* Allocate the private tables */
 750         err = gicv3_its_table_init(dev, sc);
 751         if (err != 0)
 752                 return (err);
 753
 754         /* Protects access to the device list */
 755         mtx_init(&sc->sc_its_dev_lock, "ITS device lock", NULL, MTX_SPIN);
 756
 757         /* Protects access to the ITS command circular buffer. */
 758         mtx_init(&sc->sc_its_cmd_lock, "ITS cmd lock", NULL, MTX_SPIN);
 759
 760         CPU_ZERO(&sc->sc_cpus);
 761         if (bus_get_domain(dev, &domain) == 0) {
 762                 if (domain < MAXMEMDOM)
 763                         CPU_COPY(&cpuset_domain[domain], &sc->sc_cpus);
 764         } else {
 765                 CPU_COPY(&all_cpus, &sc->sc_cpus);
 766         }
 767
 768         /* Allocate the command circular buffer */
 769         gicv3_its_cmdq_init(sc);
 770
 771         /* Allocate the per-CPU collections */
 772         for (int cpu = 0; cpu <= mp_maxid; cpu++)
 773                 if (CPU_ISSET(cpu, &sc->sc_cpus) != 0)
 774                         sc->sc_its_cols[cpu] = malloc(
 775                             sizeof(*sc->sc_its_cols[0]), M_GICV3_ITS,
 776                             M_WAITOK | M_ZERO);
 777                 else
 778                         sc->sc_its_cols[cpu] = NULL;
 779
 780         /* Enable the ITS */
 781         gic_its_write_4(sc, GITS_CTLR,
 782             gic_its_read_4(sc, GITS_CTLR) | GITS_CTLR_EN);
 783
 784         /* Create the LPI configuration table */
 785         gicv3_its_conftable_init(sc);
 786
 787         /* And the pending tebles */
 788         gicv3_its_pendtables_init(sc);
 789
 790         /* Enable LPIs on this CPU */
 791         its_init_cpu(dev, sc);
 792
 793         TAILQ_INIT(&sc->sc_its_dev_list);
 794
 795         /*
 796          * Create the vmem object to allocate INTRNG IRQs from. We try to
 797          * use all IRQs not already used by the GICv3.
 798          * XXX: This assumes there are no other interrupt controllers in the
 799          * system.
 800          */
 801         sc->sc_irq_alloc = vmem_create(device_get_nameunit(dev), 0,
 802             gicv3_get_nirqs(dev), 1, 0, M_FIRSTFIT | M_WAITOK);
 803
 804         sc->sc_irqs = malloc(sizeof(*sc->sc_irqs) * sc->sc_irq_length,
 805             M_GICV3_ITS, M_WAITOK | M_ZERO);
 806         name = device_get_nameunit(dev);
 807         for (i = 0; i < sc->sc_irq_length; i++) {
 808                 sc->sc_irqs[i].gi_id = -1;
 809                 sc->sc_irqs[i].gi_lpi = i + sc->sc_irq_base - GIC_FIRST_LPI;
 810                 err = intr_isrc_register(&sc->sc_irqs[i].gi_isrc, dev, 0,
 811                     "%s,%u", name, i);
 812         }
 813
 814         return (0);
 815 }
 816
 817 static int
 818 gicv3_its_detach(device_t dev)
 819 {
 820
 821         return (ENXIO);
 822 }
 823
 824 static void
 825 its_quirk_cavium_22375(device_t dev)
 826 {
 827         struct gicv3_its_softc *sc;
 828
 829         sc = device_get_softc(dev);
 830         sc->sc_its_flags |= ITS_FLAGS_ERRATA_CAVIUM_22375;
 831 }
 832
 833 static void
 834 gicv3_its_disable_intr(device_t dev, struct intr_irqsrc *isrc)
 835 {
 836         struct gicv3_its_softc *sc;
 837         struct gicv3_its_irqsrc *girq;
 838         uint8_t *conf;
 839
 840         sc = device_get_softc(dev);
 841         girq = (struct gicv3_its_irqsrc *)isrc;
 842         conf = sc->sc_conf_base;
 843
 844         conf[girq->gi_lpi] &= ~LPI_CONF_ENABLE;
 845
 846         if ((sc->sc_its_flags & ITS_FLAGS_LPI_CONF_FLUSH) != 0) {
 847                 /* Clean D-cache under command. */
 848                 cpu_dcache_wb_range((vm_offset_t)&conf[girq->gi_lpi], 1);
 849         } else {
 850                 /* DSB inner shareable, store */
 851                 dsb(ishst);
 852         }
 853
 854         its_cmd_inv(dev, girq->gi_its_dev, girq);
 855 }
 856
 857 static void
 858 gicv3_its_enable_intr(device_t dev, struct intr_irqsrc *isrc)
 859 {
 860         struct gicv3_its_softc *sc;
 861         struct gicv3_its_irqsrc *girq;
 862         uint8_t *conf;
 863
 864         sc = device_get_softc(dev);
 865         girq = (struct gicv3_its_irqsrc *)isrc;
 866         conf = sc->sc_conf_base;
 867
 868         conf[girq->gi_lpi] |= LPI_CONF_ENABLE;
 869
 870         if ((sc->sc_its_flags & ITS_FLAGS_LPI_CONF_FLUSH) != 0) {
 871                 /* Clean D-cache under command. */
 872                 cpu_dcache_wb_range((vm_offset_t)&conf[girq->gi_lpi], 1);
 873         } else {
 874                 /* DSB inner shareable, store */
 875                 dsb(ishst);
 876         }
 877
 878         its_cmd_inv(dev, girq->gi_its_dev, girq);
 879 }
 880
 881 static int
 882 gicv3_its_intr(void *arg, uintptr_t irq)
 883 {
 884         struct gicv3_its_softc *sc = arg;
 885         struct gicv3_its_irqsrc *girq;
 886         struct trapframe *tf;
 887
 888         irq -= sc->sc_irq_base;
 889         girq = &sc->sc_irqs[irq];
 890         if (girq == NULL)
 891                 panic("gicv3_its_intr: Invalid interrupt %ld",
 892                     irq + sc->sc_irq_base);
 893
 894         tf = curthread->td_intr_frame;
 895         intr_isrc_dispatch(&girq->gi_isrc, tf);
 896         return (FILTER_HANDLED);
 897 }
 898
 899 static void
 900 gicv3_its_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
 901 {
 902         struct gicv3_its_irqsrc *girq;
 903         struct gicv3_its_softc *sc;
 904
 905         sc = device_get_softc(dev);
 906         girq = (struct gicv3_its_irqsrc *)isrc;
 907         gicv3_its_disable_intr(dev, isrc);
 908         gic_icc_write(EOIR1, girq->gi_lpi + GIC_FIRST_LPI);
 909 }
 910
 911 static void
 912 gicv3_its_post_ithread(device_t dev, struct intr_irqsrc *isrc)
 913 {
 914
 915         gicv3_its_enable_intr(dev, isrc);
 916 }
 917
 918 static void
 919 gicv3_its_post_filter(device_t dev, struct intr_irqsrc *isrc)
 920 {
 921         struct gicv3_its_irqsrc *girq;
 922         struct gicv3_its_softc *sc;
 923
 924         sc = device_get_softc(dev);
 925         girq = (struct gicv3_its_irqsrc *)isrc;
 926         gic_icc_write(EOIR1, girq->gi_lpi + GIC_FIRST_LPI);
 927 }
 928
 929 static int
 930 gicv3_its_select_cpu(device_t dev, struct intr_irqsrc *isrc)
 931 {
 932         struct gicv3_its_softc *sc;
 933
 934         sc = device_get_softc(dev);
 935         if (CPU_EMPTY(&isrc->isrc_cpu)) {
 936                 sc->gic_irq_cpu = intr_irq_next_cpu(sc->gic_irq_cpu,
 937                     &sc->sc_cpus);
 938                 CPU_SETOF(sc->gic_irq_cpu, &isrc->isrc_cpu);
 939         }
 940
 941         return (0);
 942 }
 943
 944 static int
 945 gicv3_its_bind_intr(device_t dev, struct intr_irqsrc *isrc)
 946 {
 947         struct gicv3_its_irqsrc *girq;
 948
 949         gicv3_its_select_cpu(dev, isrc);
 950
 951         girq = (struct gicv3_its_irqsrc *)isrc;
 952         its_cmd_movi(dev, girq);
 953         return (0);
 954 }
 955
 956 static int
 957 gicv3_its_map_intr(device_t dev, struct intr_map_data *data,
 958     struct intr_irqsrc **isrcp)
 959 {
 960
 961         /*
 962          * This should never happen, we only call this function to map
 963          * interrupts found before the controller driver is ready.
 964          */
 965         panic("gicv3_its_map_intr: Unable to map a MSI interrupt");
 966 }
 967
 968 static int
 969 gicv3_its_setup_intr(device_t dev, struct intr_irqsrc *isrc,
 970     struct resource *res, struct intr_map_data *data)
 971 {
 972
 973         /* Bind the interrupt to a CPU */
 974         gicv3_its_bind_intr(dev, isrc);
 975
 976         return (0);
 977 }
 978
 979 #ifdef SMP
 980 static void
 981 gicv3_its_init_secondary(device_t dev)
 982 {
 983         struct gicv3_its_softc *sc;
 984
 985         sc = device_get_softc(dev);
 986
 987         /*
 988          * This is fatal as otherwise we may bind interrupts to this CPU.
 989          * We need a way to tell the interrupt framework to only bind to a
 990          * subset of given CPUs when it performs the shuffle.
 991          */
 992         if (its_init_cpu(dev, sc) != 0)
 993                 panic("gicv3_its_init_secondary: No usable ITS on CPU%d",
 994                     PCPU_GET(cpuid));
 995 }
 996 #endif
 997
 998 static uint32_t
 999 its_get_devid(device_t pci_dev)
1000 {
1001         uintptr_t id;
1002
1003         if (pci_get_id(pci_dev, PCI_ID_MSI, &id) != 0)
1004                 panic("its_get_devid: Unable to get the MSI DeviceID");
1005
1006         return (id);
1007 }
1008
1009 static struct its_dev *
1010 its_device_find(device_t dev, device_t child)
1011 {
1012         struct gicv3_its_softc *sc;
1013         struct its_dev *its_dev = NULL;
1014
1015         sc = device_get_softc(dev);
1016
1017         mtx_lock_spin(&sc->sc_its_dev_lock);
1018         TAILQ_FOREACH(its_dev, &sc->sc_its_dev_list, entry) {
1019                 if (its_dev->pci_dev == child)
1020                         break;
1021         }
1022         mtx_unlock_spin(&sc->sc_its_dev_lock);
1023
1024         return (its_dev);
1025 }
1026
1027 static struct its_dev *
1028 its_device_get(device_t dev, device_t child, u_int nvecs)
1029 {
1030         struct gicv3_its_softc *sc;
1031         struct its_dev *its_dev;
1032         vmem_addr_t irq_base;
1033         size_t esize;
1034
1035         sc = device_get_softc(dev);
1036
1037         its_dev = its_device_find(dev, child);
1038         if (its_dev != NULL)
1039                 return (its_dev);
1040
1041         its_dev = malloc(sizeof(*its_dev), M_GICV3_ITS, M_NOWAIT | M_ZERO);
1042         if (its_dev == NULL)
1043                 return (NULL);
1044
1045         its_dev->pci_dev = child;
1046         its_dev->devid = its_get_devid(child);
1047
1048         its_dev->lpis.lpi_busy = 0;
1049         its_dev->lpis.lpi_num = nvecs;
1050         its_dev->lpis.lpi_free = nvecs;
1051
1052         if (vmem_alloc(sc->sc_irq_alloc, nvecs, M_FIRSTFIT | M_NOWAIT,
1053             &irq_base) != 0) {
1054                 free(its_dev, M_GICV3_ITS);
1055                 return (NULL);
1056         }
1057         its_dev->lpis.lpi_base = irq_base;
1058
1059         /* Get ITT entry size */
1060         esize = GITS_TYPER_ITTES(gic_its_read_8(sc, GITS_TYPER));
1061
1062         /*
1063          * Allocate ITT for this device.
1064          * PA has to be 256 B aligned. At least two entries for device.
1065          */
1066         its_dev->itt_size = roundup2(MAX(nvecs, 2) * esize, 256);
1067         its_dev->itt = (vm_offset_t)contigmalloc(its_dev->itt_size,
1068             M_GICV3_ITS, M_NOWAIT | M_ZERO, 0, LPI_INT_TRANS_TAB_MAX_ADDR,
1069             LPI_INT_TRANS_TAB_ALIGN, 0);
1070         if (its_dev->itt == 0) {
1071                 vmem_free(sc->sc_irq_alloc, its_dev->lpis.lpi_base, nvecs);
1072                 free(its_dev, M_GICV3_ITS);
1073                 return (NULL);
1074         }
1075
1076         mtx_lock_spin(&sc->sc_its_dev_lock);
1077         TAILQ_INSERT_TAIL(&sc->sc_its_dev_list, its_dev, entry);
1078         mtx_unlock_spin(&sc->sc_its_dev_lock);
1079
1080         /* Map device to its ITT */
1081         its_cmd_mapd(dev, its_dev, 1);
1082
1083         return (its_dev);
1084 }
1085
1086 static void
1087 its_device_release(device_t dev, struct its_dev *its_dev)
1088 {
1089         struct gicv3_its_softc *sc;
1090
1091         KASSERT(its_dev->lpis.lpi_busy == 0,
1092             ("its_device_release: Trying to release an inuse ITS device"));
1093
1094         /* Unmap device in ITS */
1095         its_cmd_mapd(dev, its_dev, 0);
1096
1097         sc = device_get_softc(dev);
1098
1099         /* Remove the device from the list of devices */
1100         mtx_lock_spin(&sc->sc_its_dev_lock);
1101         TAILQ_REMOVE(&sc->sc_its_dev_list, its_dev, entry);
1102         mtx_unlock_spin(&sc->sc_its_dev_lock);
1103
1104         /* Free ITT */
1105         KASSERT(its_dev->itt != 0, ("Invalid ITT in valid ITS device"));
1106         contigfree((void *)its_dev->itt, its_dev->itt_size, M_GICV3_ITS);
1107
1108         /* Free the IRQ allocation */
1109         vmem_free(sc->sc_irq_alloc, its_dev->lpis.lpi_base,
1110             its_dev->lpis.lpi_num);
1111
1112         free(its_dev, M_GICV3_ITS);
1113 }
1114
1115 static int
1116 gicv3_its_alloc_msi(device_t dev, device_t child, int count, int maxcount,
1117     device_t *pic, struct intr_irqsrc **srcs)
1118 {
1119         struct gicv3_its_softc *sc;
1120         struct gicv3_its_irqsrc *girq;
1121         struct its_dev *its_dev;
1122         u_int irq;
1123         int i;
1124
1125         its_dev = its_device_get(dev, child, count);
1126         if (its_dev == NULL)
1127                 return (ENXIO);
1128
1129         KASSERT(its_dev->lpis.lpi_free >= count,
1130             ("gicv3_its_alloc_msi: No free LPIs"));
1131         sc = device_get_softc(dev);
1132         irq = its_dev->lpis.lpi_base + its_dev->lpis.lpi_num -
1133             its_dev->lpis.lpi_free;
1134         for (i = 0; i < count; i++, irq++) {
1135                 its_dev->lpis.lpi_free--;
1136                 girq = &sc->sc_irqs[irq];
1137                 girq->gi_id = i;
1138                 girq->gi_its_dev = its_dev;
1139                 srcs[i] = (struct intr_irqsrc *)girq;
1140
1141                 /* Map the message to the given IRQ */
1142                 gicv3_its_select_cpu(dev, (struct intr_irqsrc *)girq);
1143                 its_cmd_mapti(dev, girq);
1144         }
1145         its_dev->lpis.lpi_busy += count;
1146         *pic = dev;
1147
1148         return (0);
1149 }
1150
1151 static int
1152 gicv3_its_release_msi(device_t dev, device_t child, int count,
1153     struct intr_irqsrc **isrc)
1154 {
1155         struct gicv3_its_irqsrc *girq;
1156         struct its_dev *its_dev;
1157         int i;
1158
1159         its_dev = its_device_find(dev, child);
1160
1161         KASSERT(its_dev != NULL,
1162             ("gicv3_its_release_msi: Releasing a MSI interrupt with "
1163              "no ITS device"));
1164         KASSERT(its_dev->lpis.lpi_busy >= count,
1165             ("gicv3_its_release_msi: Releasing more interrupts than "
1166              "were allocated: releasing %d, allocated %d", count,
1167              its_dev->lpis.lpi_busy));
1168         for (i = 0; i < count; i++) {
1169                 girq = (struct gicv3_its_irqsrc *)isrc[i];
1170                 girq->gi_id = -1;
1171                 girq->gi_its_dev = NULL;
1172         }
1173         its_dev->lpis.lpi_busy -= count;
1174
1175         if (its_dev->lpis.lpi_busy == 0)
1176                 its_device_release(dev, its_dev);
1177
1178         return (0);
1179 }
1180
1181 static int
1182 gicv3_its_alloc_msix(device_t dev, device_t child, device_t *pic,
1183     struct intr_irqsrc **isrcp)
1184 {
1185         struct gicv3_its_softc *sc;
1186         struct gicv3_its_irqsrc *girq;
1187         struct its_dev *its_dev;
1188         u_int nvecs, irq;
1189
1190         nvecs = pci_msix_count(child);
1191         its_dev = its_device_get(dev, child, nvecs);
1192         if (its_dev == NULL)
1193                 return (ENXIO);
1194
1195         KASSERT(its_dev->lpis.lpi_free > 0,
1196             ("gicv3_its_alloc_msix: No free LPIs"));
1197         sc = device_get_softc(dev);
1198         irq = its_dev->lpis.lpi_base + its_dev->lpis.lpi_num -
1199             its_dev->lpis.lpi_free;
1200         girq = &sc->sc_irqs[irq];
1201         girq->gi_id = its_dev->lpis.lpi_busy;
1202         girq->gi_its_dev = its_dev;
1203
1204         its_dev->lpis.lpi_free--;
1205         its_dev->lpis.lpi_busy++;
1206
1207         /* Map the message to the given IRQ */
1208         gicv3_its_select_cpu(dev, (struct intr_irqsrc *)girq);
1209         its_cmd_mapti(dev, girq);
1210
1211         *pic = dev;
1212         *isrcp = (struct intr_irqsrc *)girq;
1213
1214         return (0);
1215 }
1216
1217 static int
1218 gicv3_its_release_msix(device_t dev, device_t child, struct intr_irqsrc *isrc)
1219 {
1220         struct gicv3_its_irqsrc *girq;
1221         struct its_dev *its_dev;
1222
1223         its_dev = its_device_find(dev, child);
1224
1225         KASSERT(its_dev != NULL,
1226             ("gicv3_its_release_msix: Releasing a MSI-X interrupt with "
1227              "no ITS device"));
1228         KASSERT(its_dev->lpis.lpi_busy > 0,
1229             ("gicv3_its_release_msix: Releasing more interrupts than "
1230              "were allocated: allocated %d", its_dev->lpis.lpi_busy));
1231         girq = (struct gicv3_its_irqsrc *)isrc;
1232         girq->gi_its_dev = NULL;
1233         girq->gi_id = -1;
1234         its_dev->lpis.lpi_busy--;
1235
1236         if (its_dev->lpis.lpi_busy == 0)
1237                 its_device_release(dev, its_dev);
1238
1239         return (0);
1240 }
1241
1242 static int
1243 gicv3_its_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc,
1244     uint64_t *addr, uint32_t *data)
1245 {
1246         struct gicv3_its_softc *sc;
1247         struct gicv3_its_irqsrc *girq;
1248
1249         sc = device_get_softc(dev);
1250         girq = (struct gicv3_its_irqsrc *)isrc;
1251
1252         *addr = vtophys(rman_get_virtual(sc->sc_its_res)) + GITS_TRANSLATER;
1253         *data = girq->gi_id;
1254
1255         return (0);
1256 }
1257
1258 /*
1259  * Commands handling.
1260  */
1261
1262 static __inline void
1263 cmd_format_command(struct its_cmd *cmd, uint8_t cmd_type)
1264 {
1265         /* Command field: DW0 [7:0] */
1266         cmd->cmd_dword[0] &= htole64(~CMD_COMMAND_MASK);
1267         cmd->cmd_dword[0] |= htole64(cmd_type);
1268 }
1269
1270 static __inline void
1271 cmd_format_devid(struct its_cmd *cmd, uint32_t devid)
1272 {
1273         /* Device ID field: DW0 [63:32] */
1274         cmd->cmd_dword[0] &= htole64(~CMD_DEVID_MASK);
1275         cmd->cmd_dword[0] |= htole64((uint64_t)devid << CMD_DEVID_SHIFT);
1276 }
1277
1278 static __inline void
1279 cmd_format_size(struct its_cmd *cmd, uint16_t size)
1280 {
1281         /* Size field: DW1 [4:0] */
1282         cmd->cmd_dword[1] &= htole64(~CMD_SIZE_MASK);
1283         cmd->cmd_dword[1] |= htole64((size & CMD_SIZE_MASK));
1284 }
1285
1286 static __inline void
1287 cmd_format_id(struct its_cmd *cmd, uint32_t id)
1288 {
1289         /* ID field: DW1 [31:0] */
1290         cmd->cmd_dword[1] &= htole64(~CMD_ID_MASK);
1291         cmd->cmd_dword[1] |= htole64(id);
1292 }
1293
1294 static __inline void
1295 cmd_format_pid(struct its_cmd *cmd, uint32_t pid)
1296 {
1297         /* Physical ID field: DW1 [63:32] */
1298         cmd->cmd_dword[1] &= htole64(~CMD_PID_MASK);
1299         cmd->cmd_dword[1] |= htole64((uint64_t)pid << CMD_PID_SHIFT);
1300 }
1301
1302 static __inline void
1303 cmd_format_col(struct its_cmd *cmd, uint16_t col_id)
1304 {
1305         /* Collection field: DW2 [16:0] */
1306         cmd->cmd_dword[2] &= htole64(~CMD_COL_MASK);
1307         cmd->cmd_dword[2] |= htole64(col_id);
1308 }
1309
1310 static __inline void
1311 cmd_format_target(struct its_cmd *cmd, uint64_t target)
1312 {
1313         /* Target Address field: DW2 [47:16] */
1314         cmd->cmd_dword[2] &= htole64(~CMD_TARGET_MASK);
1315         cmd->cmd_dword[2] |= htole64(target & CMD_TARGET_MASK);
1316 }
1317
1318 static __inline void
1319 cmd_format_itt(struct its_cmd *cmd, uint64_t itt)
1320 {
1321         /* ITT Address field: DW2 [47:8] */
1322         cmd->cmd_dword[2] &= htole64(~CMD_ITT_MASK);
1323         cmd->cmd_dword[2] |= htole64(itt & CMD_ITT_MASK);
1324 }
1325
1326 static __inline void
1327 cmd_format_valid(struct its_cmd *cmd, uint8_t valid)
1328 {
1329         /* Valid field: DW2 [63] */
1330         cmd->cmd_dword[2] &= htole64(~CMD_VALID_MASK);
1331         cmd->cmd_dword[2] |= htole64((uint64_t)valid << CMD_VALID_SHIFT);
1332 }
1333
1334 static inline bool
1335 its_cmd_queue_full(struct gicv3_its_softc *sc)
1336 {
1337         size_t read_idx, next_write_idx;
1338
1339         /* Get the index of the next command */
1340         next_write_idx = (sc->sc_its_cmd_next_idx + 1) %
1341             (ITS_CMDQ_SIZE / sizeof(struct its_cmd));
1342         /* And the index of the current command being read */
1343         read_idx = gic_its_read_4(sc, GITS_CREADR) / sizeof(struct its_cmd);
1344
1345         /*
1346          * The queue is full when the write offset points
1347          * at the command before the current read offset.
1348          */
1349         return (next_write_idx == read_idx);
1350 }
1351
1352 static inline void
1353 its_cmd_sync(struct gicv3_its_softc *sc, struct its_cmd *cmd)
1354 {
1355
1356         if ((sc->sc_its_flags & ITS_FLAGS_CMDQ_FLUSH) != 0) {
1357                 /* Clean D-cache under command. */
1358                 cpu_dcache_wb_range((vm_offset_t)cmd, sizeof(*cmd));
1359         } else {
1360                 /* DSB inner shareable, store */
1361                 dsb(ishst);
1362         }
1363
1364 }
1365
1366 static inline uint64_t
1367 its_cmd_cwriter_offset(struct gicv3_its_softc *sc, struct its_cmd *cmd)
1368 {
1369         uint64_t off;
1370
1371         off = (cmd - sc->sc_its_cmd_base) * sizeof(*cmd);
1372
1373         return (off);
1374 }
1375
1376 static void
1377 its_cmd_wait_completion(device_t dev, struct its_cmd *cmd_first,
1378     struct its_cmd *cmd_last)
1379 {
1380         struct gicv3_its_softc *sc;
1381         uint64_t first, last, read;
1382         size_t us_left;
1383
1384         sc = device_get_softc(dev);
1385
1386         /*
1387          * XXX ARM64TODO: This is obviously a significant delay.
1388          * The reason for that is that currently the time frames for
1389          * the command to complete are not known.
1390          */
1391         us_left = 1000000;
1392
1393         first = its_cmd_cwriter_offset(sc, cmd_first);
1394         last = its_cmd_cwriter_offset(sc, cmd_last);
1395
1396         for (;;) {
1397                 read = gic_its_read_8(sc, GITS_CREADR);
1398                 if (first < last) {
1399                         if (read < first || read >= last)
1400                                 break;
1401                 } else if (read < first && read >= last)
1402                         break;
1403
1404                 if (us_left-- == 0) {
1405                         /* This means timeout */
1406                         device_printf(dev,
1407                             "Timeout while waiting for CMD completion.\n");
1408                         return;
1409                 }
1410                 DELAY(1);
1411         }
1412 }
1413
1414
1415 static struct its_cmd *
1416 its_cmd_alloc_locked(device_t dev)
1417 {
1418         struct gicv3_its_softc *sc;
1419         struct its_cmd *cmd;
1420         size_t us_left;
1421
1422         sc = device_get_softc(dev);
1423
1424         /*
1425          * XXX ARM64TODO: This is obviously a significant delay.
1426          * The reason for that is that currently the time frames for
1427          * the command to complete (and therefore free the descriptor)
1428          * are not known.
1429          */
1430         us_left = 1000000;
1431
1432         mtx_assert(&sc->sc_its_cmd_lock, MA_OWNED);
1433         while (its_cmd_queue_full(sc)) {
1434                 if (us_left-- == 0) {
1435                         /* Timeout while waiting for free command */
1436                         device_printf(dev,
1437                             "Timeout while waiting for free command\n");
1438                         return (NULL);
1439                 }
1440                 DELAY(1);
1441         }
1442
1443         cmd = &sc->sc_its_cmd_base[sc->sc_its_cmd_next_idx];
1444         sc->sc_its_cmd_next_idx++;
1445         sc->sc_its_cmd_next_idx %= ITS_CMDQ_SIZE / sizeof(struct its_cmd);
1446
1447         return (cmd);
1448 }
1449
1450 static uint64_t
1451 its_cmd_prepare(struct its_cmd *cmd, struct its_cmd_desc *desc)
1452 {
1453         uint64_t target;
1454         uint8_t cmd_type;
1455         u_int size;
1456
1457         cmd_type = desc->cmd_type;
1458         target = ITS_TARGET_NONE;
1459
1460         switch (cmd_type) {
1461         case ITS_CMD_MOVI:      /* Move interrupt ID to another collection */
1462                 target = desc->cmd_desc_movi.col->col_target;
1463                 cmd_format_command(cmd, ITS_CMD_MOVI);
1464                 cmd_format_id(cmd, desc->cmd_desc_movi.id);
1465                 cmd_format_col(cmd, desc->cmd_desc_movi.col->col_id);
1466                 cmd_format_devid(cmd, desc->cmd_desc_movi.its_dev->devid);
1467                 break;
1468         case ITS_CMD_SYNC:      /* Wait for previous commands completion */
1469                 target = desc->cmd_desc_sync.col->col_target;
1470                 cmd_format_command(cmd, ITS_CMD_SYNC);
1471                 cmd_format_target(cmd, target);
1472                 break;
1473         case ITS_CMD_MAPD:      /* Assign ITT to device */
1474                 cmd_format_command(cmd, ITS_CMD_MAPD);
1475                 cmd_format_itt(cmd, vtophys(desc->cmd_desc_mapd.its_dev->itt));
1476                 /*
1477                  * Size describes number of bits to encode interrupt IDs
1478                  * supported by the device minus one.
1479                  * When V (valid) bit is zero, this field should be written
1480                  * as zero.
1481                  */
1482                 if (desc->cmd_desc_mapd.valid != 0) {
1483                         size = fls(desc->cmd_desc_mapd.its_dev->lpis.lpi_num);
1484                         size = MAX(1, size) - 1;
1485                 } else
1486                         size = 0;
1487
1488                 cmd_format_size(cmd, size);
1489                 cmd_format_devid(cmd, desc->cmd_desc_mapd.its_dev->devid);
1490                 cmd_format_valid(cmd, desc->cmd_desc_mapd.valid);
1491                 break;
1492         case ITS_CMD_MAPC:      /* Map collection to Re-Distributor */
1493                 target = desc->cmd_desc_mapc.col->col_target;
1494                 cmd_format_command(cmd, ITS_CMD_MAPC);
1495                 cmd_format_col(cmd, desc->cmd_desc_mapc.col->col_id);
1496                 cmd_format_valid(cmd, desc->cmd_desc_mapc.valid);
1497                 cmd_format_target(cmd, target);
1498                 break;
1499         case ITS_CMD_MAPTI:
1500                 target = desc->cmd_desc_mapvi.col->col_target;
1501                 cmd_format_command(cmd, ITS_CMD_MAPTI);
1502                 cmd_format_devid(cmd, desc->cmd_desc_mapvi.its_dev->devid);
1503                 cmd_format_id(cmd, desc->cmd_desc_mapvi.id);
1504                 cmd_format_pid(cmd, desc->cmd_desc_mapvi.pid);
1505                 cmd_format_col(cmd, desc->cmd_desc_mapvi.col->col_id);
1506                 break;
1507         case ITS_CMD_MAPI:
1508                 target = desc->cmd_desc_mapi.col->col_target;
1509                 cmd_format_command(cmd, ITS_CMD_MAPI);
1510                 cmd_format_devid(cmd, desc->cmd_desc_mapi.its_dev->devid);
1511                 cmd_format_id(cmd, desc->cmd_desc_mapi.pid);
1512                 cmd_format_col(cmd, desc->cmd_desc_mapi.col->col_id);
1513                 break;
1514         case ITS_CMD_INV:
1515                 target = desc->cmd_desc_inv.col->col_target;
1516                 cmd_format_command(cmd, ITS_CMD_INV);
1517                 cmd_format_devid(cmd, desc->cmd_desc_inv.its_dev->devid);
1518                 cmd_format_id(cmd, desc->cmd_desc_inv.pid);
1519                 break;
1520         case ITS_CMD_INVALL:
1521                 cmd_format_command(cmd, ITS_CMD_INVALL);
1522                 cmd_format_col(cmd, desc->cmd_desc_invall.col->col_id);
1523                 break;
1524         default:
1525                 panic("its_cmd_prepare: Invalid command: %x", cmd_type);
1526         }
1527
1528         return (target);
1529 }
1530
1531 static int
1532 its_cmd_send(device_t dev, struct its_cmd_desc *desc)
1533 {
1534         struct gicv3_its_softc *sc;
1535         struct its_cmd *cmd, *cmd_sync, *cmd_write;
1536         struct its_col col_sync;
1537         struct its_cmd_desc desc_sync;
1538         uint64_t target, cwriter;
1539
1540         sc = device_get_softc(dev);
1541         mtx_lock_spin(&sc->sc_its_cmd_lock);
1542         cmd = its_cmd_alloc_locked(dev);
1543         if (cmd == NULL) {
1544                 device_printf(dev, "could not allocate ITS command\n");
1545                 mtx_unlock_spin(&sc->sc_its_cmd_lock);
1546                 return (EBUSY);
1547         }
1548
1549         target = its_cmd_prepare(cmd, desc);
1550         its_cmd_sync(sc, cmd);
1551
1552         if (target != ITS_TARGET_NONE) {
1553                 cmd_sync = its_cmd_alloc_locked(dev);
1554                 if (cmd_sync != NULL) {
1555                         desc_sync.cmd_type = ITS_CMD_SYNC;
1556                         col_sync.col_target = target;
1557                         desc_sync.cmd_desc_sync.col = &col_sync;
1558                         its_cmd_prepare(cmd_sync, &desc_sync);
1559                         its_cmd_sync(sc, cmd_sync);
1560                 }
1561         }
1562
1563         /* Update GITS_CWRITER */
1564         cwriter = sc->sc_its_cmd_next_idx * sizeof(struct its_cmd);
1565         gic_its_write_8(sc, GITS_CWRITER, cwriter);
1566         cmd_write = &sc->sc_its_cmd_base[sc->sc_its_cmd_next_idx];
1567         mtx_unlock_spin(&sc->sc_its_cmd_lock);
1568
1569         its_cmd_wait_completion(dev, cmd, cmd_write);
1570
1571         return (0);
1572 }
1573
1574 /* Handlers to send commands */
1575 static void
1576 its_cmd_movi(device_t dev, struct gicv3_its_irqsrc *girq)
1577 {
1578         struct gicv3_its_softc *sc;
1579         struct its_cmd_desc desc;
1580         struct its_col *col;
1581
1582         sc = device_get_softc(dev);
1583         col = sc->sc_its_cols[CPU_FFS(&girq->gi_isrc.isrc_cpu) - 1];
1584
1585         desc.cmd_type = ITS_CMD_MOVI;
1586         desc.cmd_desc_movi.its_dev = girq->gi_its_dev;
1587         desc.cmd_desc_movi.col = col;
1588         desc.cmd_desc_movi.id = girq->gi_id;
1589
1590         its_cmd_send(dev, &desc);
1591 }
1592
1593 static void
1594 its_cmd_mapc(device_t dev, struct its_col *col, uint8_t valid)
1595 {
1596         struct its_cmd_desc desc;
1597
1598         desc.cmd_type = ITS_CMD_MAPC;
1599         desc.cmd_desc_mapc.col = col;
1600         /*
1601          * Valid bit set - map the collection.
1602          * Valid bit cleared - unmap the collection.
1603          */
1604         desc.cmd_desc_mapc.valid = valid;
1605
1606         its_cmd_send(dev, &desc);
1607 }
1608
1609 static void
1610 its_cmd_mapti(device_t dev, struct gicv3_its_irqsrc *girq)
1611 {
1612         struct gicv3_its_softc *sc;
1613         struct its_cmd_desc desc;
1614         struct its_col *col;
1615         u_int col_id;
1616
1617         sc = device_get_softc(dev);
1618
1619         col_id = CPU_FFS(&girq->gi_isrc.isrc_cpu) - 1;
1620         col = sc->sc_its_cols[col_id];
1621
1622         desc.cmd_type = ITS_CMD_MAPTI;
1623         desc.cmd_desc_mapvi.its_dev = girq->gi_its_dev;
1624         desc.cmd_desc_mapvi.col = col;
1625         /* The EventID sent to the device */
1626         desc.cmd_desc_mapvi.id = girq->gi_id;
1627         /* The physical interrupt presented to softeware */
1628         desc.cmd_desc_mapvi.pid = girq->gi_lpi + GIC_FIRST_LPI;
1629
1630         its_cmd_send(dev, &desc);
1631 }
1632
1633 static void
1634 its_cmd_mapd(device_t dev, struct its_dev *its_dev, uint8_t valid)
1635 {
1636         struct its_cmd_desc desc;
1637
1638         desc.cmd_type = ITS_CMD_MAPD;
1639         desc.cmd_desc_mapd.its_dev = its_dev;
1640         desc.cmd_desc_mapd.valid = valid;
1641
1642         its_cmd_send(dev, &desc);
1643 }
1644
1645 static void
1646 its_cmd_inv(device_t dev, struct its_dev *its_dev,
1647     struct gicv3_its_irqsrc *girq)
1648 {
1649         struct gicv3_its_softc *sc;
1650         struct its_cmd_desc desc;
1651         struct its_col *col;
1652
1653         sc = device_get_softc(dev);
1654         col = sc->sc_its_cols[CPU_FFS(&girq->gi_isrc.isrc_cpu) - 1];
1655
1656         desc.cmd_type = ITS_CMD_INV;
1657         /* The EventID sent to the device */
1658         desc.cmd_desc_inv.pid = girq->gi_id;
1659         desc.cmd_desc_inv.its_dev = its_dev;
1660         desc.cmd_desc_inv.col = col;
1661
1662         its_cmd_send(dev, &desc);
1663 }
1664
1665 static void
1666 its_cmd_invall(device_t dev, struct its_col *col)
1667 {
1668         struct its_cmd_desc desc;
1669
1670         desc.cmd_type = ITS_CMD_INVALL;
1671         desc.cmd_desc_invall.col = col;
1672
1673         its_cmd_send(dev, &desc);
1674 }
1675
1676 #ifdef FDT
1677 static device_probe_t gicv3_its_fdt_probe;
1678 static device_attach_t gicv3_its_fdt_attach;
1679
1680 static device_method_t gicv3_its_fdt_methods[] = {
1681         /* Device interface */
1682         DEVMETHOD(device_probe,         gicv3_its_fdt_probe),
1683         DEVMETHOD(device_attach,        gicv3_its_fdt_attach),
1684
1685         /* End */
1686         DEVMETHOD_END
1687 };
1688
1689 #define its_baseclasses its_fdt_baseclasses
1690 DEFINE_CLASS_1(its, gicv3_its_fdt_driver, gicv3_its_fdt_methods,
1691     sizeof(struct gicv3_its_softc), gicv3_its_driver);
1692 #undef its_baseclasses
1693 static devclass_t gicv3_its_fdt_devclass;
1694
1695 EARLY_DRIVER_MODULE(its_fdt, gic, gicv3_its_fdt_driver,
1696     gicv3_its_fdt_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
1697
1698 static int
1699 gicv3_its_fdt_probe(device_t dev)
1700 {
1701
1702         if (!ofw_bus_status_okay(dev))
1703                 return (ENXIO);
1704
1705         if (!ofw_bus_is_compatible(dev, "arm,gic-v3-its"))
1706                 return (ENXIO);
1707
1708         device_set_desc(dev, "ARM GIC Interrupt Translation Service");
1709         return (BUS_PROBE_DEFAULT);
1710 }
1711
1712 static int
1713 gicv3_its_fdt_attach(device_t dev)
1714 {
1715         struct gicv3_its_softc *sc;
1716         phandle_t xref;
1717         int err;
1718
1719         sc = device_get_softc(dev);
1720         err = gicv3_its_attach(dev);
1721         if (err != 0)
1722                 return (err);
1723
1724         /* Register this device as a interrupt controller */
1725         xref = OF_xref_from_node(ofw_bus_get_node(dev));
1726         sc->sc_pic = intr_pic_register(dev, xref);
1727         intr_pic_add_handler(device_get_parent(dev), sc->sc_pic,
1728             gicv3_its_intr, sc, sc->sc_irq_base, sc->sc_irq_length);
1729
1730         /* Register this device to handle MSI interrupts */
1731         intr_msi_register(dev, xref);
1732
1733         return (0);
1734 }
1735 #endif
1736
1737 #ifdef DEV_ACPI
1738 static device_probe_t gicv3_its_acpi_probe;
1739 static device_attach_t gicv3_its_acpi_attach;
1740
1741 static device_method_t gicv3_its_acpi_methods[] = {
1742         /* Device interface */
1743         DEVMETHOD(device_probe,         gicv3_its_acpi_probe),
1744         DEVMETHOD(device_attach,        gicv3_its_acpi_attach),
1745
1746         /* End */
1747         DEVMETHOD_END
1748 };
1749
1750 #define its_baseclasses its_acpi_baseclasses
1751 DEFINE_CLASS_1(its, gicv3_its_acpi_driver, gicv3_its_acpi_methods,
1752     sizeof(struct gicv3_its_softc), gicv3_its_driver);
1753 #undef its_baseclasses
1754 static devclass_t gicv3_its_acpi_devclass;
1755
1756 EARLY_DRIVER_MODULE(its_acpi, gic, gicv3_its_acpi_driver,
1757     gicv3_its_acpi_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
1758
1759 static int
1760 gicv3_its_acpi_probe(device_t dev)
1761 {
1762
1763         if (gic_get_bus(dev) != GIC_BUS_ACPI)
1764                 return (EINVAL);
1765
1766         if (gic_get_hw_rev(dev) < 3)
1767                 return (EINVAL);
1768
1769         device_set_desc(dev, "ARM GIC Interrupt Translation Service");
1770         return (BUS_PROBE_DEFAULT);
1771 }
1772
1773 static int
1774 gicv3_its_acpi_attach(device_t dev)
1775 {
1776         struct gicv3_its_softc *sc;
1777         struct gic_v3_devinfo *di;
1778         int err;
1779
1780         sc = device_get_softc(dev);
1781         err = gicv3_its_attach(dev);
1782         if (err != 0)
1783                 return (err);
1784
1785         di = device_get_ivars(dev);
1786         sc->sc_pic = intr_pic_register(dev, di->msi_xref);
1787         intr_pic_add_handler(device_get_parent(dev), sc->sc_pic,
1788             gicv3_its_intr, sc, sc->sc_irq_base, sc->sc_irq_length);
1789
1790         /* Register this device to handle MSI interrupts */
1791         intr_msi_register(dev, di->msi_xref);
1792
1793         return (0);
1794 }
1795 #endif