2 * Copyright (c) 2015-2016 The FreeBSD Foundation
5 * This software was developed by Andrew Turner under
6 * the sponsorship of the FreeBSD Foundation.
8 * This software was developed by Semihalf under
9 * the sponsorship of the FreeBSD Foundation.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #include "opt_platform.h"
35 #include "opt_iommu.h"
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/cpuset.h>
44 #include <sys/endian.h>
45 #include <sys/kernel.h>
47 #include <sys/malloc.h>
48 #include <sys/module.h>
49 #include <sys/mutex.h>
51 #include <sys/taskqueue.h>
53 #include <sys/queue.h>
57 #include <sys/sysctl.h>
62 #include <vm/vm_page.h>
64 #include <machine/bus.h>
65 #include <machine/intr.h>
67 #include <arm/arm/gic_common.h>
68 #include <arm64/arm64/gic_v3_reg.h>
69 #include <arm64/arm64/gic_v3_var.h>
72 #include <dev/ofw/openfirm.h>
73 #include <dev/ofw/ofw_bus.h>
74 #include <dev/ofw/ofw_bus_subr.h>
76 #include <dev/pci/pcireg.h>
77 #include <dev/pci/pcivar.h>
80 #include <dev/iommu/iommu.h>
81 #include <dev/iommu/iommu_gas.h>
88 MALLOC_DEFINE(M_GICV3_ITS, "GICv3 ITS",
89 "ARM GICv3 Interrupt Translation Service");
91 #define LPI_NIRQS (64 * 1024)
93 /* The size and alignment of the command circular buffer */
94 #define ITS_CMDQ_SIZE (64 * 1024) /* Must be a multiple of 4K */
95 #define ITS_CMDQ_ALIGN (64 * 1024)
97 #define LPI_CONFTAB_SIZE LPI_NIRQS
98 #define LPI_CONFTAB_ALIGN (64 * 1024)
99 #define LPI_CONFTAB_MAX_ADDR ((1ul << 48) - 1) /* We need a 47 bit PA */
101 /* 1 bit per SPI, PPI, and SGI (8k), and 1 bit per LPI (LPI_CONFTAB_SIZE) */
102 #define LPI_PENDTAB_SIZE ((LPI_NIRQS + GIC_FIRST_LPI) / 8)
103 #define LPI_PENDTAB_ALIGN (64 * 1024)
104 #define LPI_PENDTAB_MAX_ADDR ((1ul << 48) - 1) /* We need a 47 bit PA */
106 #define LPI_INT_TRANS_TAB_ALIGN 256
107 #define LPI_INT_TRANS_TAB_MAX_ADDR ((1ul << 48) - 1)
109 /* ITS commands encoding */
110 #define ITS_CMD_MOVI (0x01)
111 #define ITS_CMD_SYNC (0x05)
112 #define ITS_CMD_MAPD (0x08)
113 #define ITS_CMD_MAPC (0x09)
114 #define ITS_CMD_MAPTI (0x0a)
115 #define ITS_CMD_MAPI (0x0b)
116 #define ITS_CMD_INV (0x0c)
117 #define ITS_CMD_INVALL (0x0d)
119 #define CMD_COMMAND_MASK (0xFFUL)
121 #define CMD_DEVID_SHIFT (32)
122 #define CMD_DEVID_MASK (0xFFFFFFFFUL << CMD_DEVID_SHIFT)
123 /* Size of IRQ ID bitfield */
124 #define CMD_SIZE_MASK (0xFFUL)
126 #define CMD_ID_MASK (0xFFFFFFFFUL)
127 /* Physical LPI ID */
128 #define CMD_PID_SHIFT (32)
129 #define CMD_PID_MASK (0xFFFFFFFFUL << CMD_PID_SHIFT)
131 #define CMD_COL_MASK (0xFFFFUL)
132 /* Target (CPU or Re-Distributor) */
133 #define CMD_TARGET_SHIFT (16)
134 #define CMD_TARGET_MASK (0xFFFFFFFFUL << CMD_TARGET_SHIFT)
135 /* Interrupt Translation Table address */
136 #define CMD_ITT_MASK (0xFFFFFFFFFF00UL)
137 /* Valid command bit */
138 #define CMD_VALID_SHIFT (63)
139 #define CMD_VALID_MASK (1UL << CMD_VALID_SHIFT)
141 #define ITS_TARGET_NONE 0xFBADBEEF
143 /* LPI chunk owned by ITS device */
146 u_int lpi_free; /* First free LPI in set */
147 u_int lpi_num; /* Total number of LPIs in chunk */
148 u_int lpi_busy; /* Number of busy LPIs in chink */
153 TAILQ_ENTRY(its_dev) entry;
156 /* Device ID (i.e. PCI device ID) */
158 /* List of assigned LPIs */
159 struct lpi_chunk lpis;
160 /* Virtual address of ITT */
166 * ITS command descriptor.
167 * Idea for command description passing taken from Linux.
169 struct its_cmd_desc {
174 struct its_dev *its_dev;
189 struct its_dev *its_dev;
196 struct its_dev *its_dev;
202 struct its_dev *its_dev;
207 struct its_dev *its_dev;
218 /* ITS command. Each command is 32 bytes long */
220 uint64_t cmd_dword[4]; /* ITS command double word */
223 /* An ITS private table */
225 vm_offset_t ptab_vaddr;
226 unsigned long ptab_size;
229 /* ITS collection description. */
231 uint64_t col_target; /* Target Re-Distributor */
232 uint64_t col_id; /* Collection ID */
235 struct gicv3_its_irqsrc {
236 struct intr_irqsrc gi_isrc;
239 struct its_dev *gi_its_dev;
240 TAILQ_ENTRY(gicv3_its_irqsrc) gi_link;
243 struct gicv3_its_softc {
245 struct intr_pic *sc_pic;
246 struct resource *sc_its_res;
251 struct its_ptable sc_its_ptab[GITS_BASER_NUM];
252 struct its_col *sc_its_cols[MAXCPU]; /* Per-CPU collections */
255 * TODO: We should get these from the parent as we only want a
256 * single copy of each across the interrupt controller.
258 uint8_t *sc_conf_base;
259 vm_offset_t sc_pend_base[MAXCPU];
261 /* Command handling */
262 struct mtx sc_its_cmd_lock;
263 struct its_cmd *sc_its_cmd_base; /* Command circular buffer address */
264 size_t sc_its_cmd_next_idx;
266 vmem_t *sc_irq_alloc;
267 struct gicv3_its_irqsrc **sc_irqs;
272 struct mtx sc_its_dev_lock;
273 TAILQ_HEAD(its_dev_list, its_dev) sc_its_dev_list;
274 TAILQ_HEAD(free_irqs, gicv3_its_irqsrc) sc_free_irqs;
276 #define ITS_FLAGS_CMDQ_FLUSH 0x00000001
277 #define ITS_FLAGS_LPI_CONF_FLUSH 0x00000002
278 #define ITS_FLAGS_ERRATA_CAVIUM_22375 0x00000004
281 vm_page_t ma; /* fake msi page */
284 static void *conf_base;
286 typedef void (its_quirk_func_t)(device_t);
287 static its_quirk_func_t its_quirk_cavium_22375;
289 static const struct {
293 its_quirk_func_t *func;
296 /* Cavium ThunderX Pass 1.x */
297 .desc = "Cavium ThunderX errata: 22375, 24313",
298 .iidr = GITS_IIDR_RAW(GITS_IIDR_IMPL_CAVIUM,
299 GITS_IIDR_PROD_THUNDER, GITS_IIDR_VAR_THUNDER_1, 0),
300 .iidr_mask = ~GITS_IIDR_REVISION_MASK,
301 .func = its_quirk_cavium_22375,
305 #define gic_its_read_4(sc, reg) \
306 bus_read_4((sc)->sc_its_res, (reg))
307 #define gic_its_read_8(sc, reg) \
308 bus_read_8((sc)->sc_its_res, (reg))
310 #define gic_its_write_4(sc, reg, val) \
311 bus_write_4((sc)->sc_its_res, (reg), (val))
312 #define gic_its_write_8(sc, reg, val) \
313 bus_write_8((sc)->sc_its_res, (reg), (val))
315 static device_attach_t gicv3_its_attach;
316 static device_detach_t gicv3_its_detach;
318 static pic_disable_intr_t gicv3_its_disable_intr;
319 static pic_enable_intr_t gicv3_its_enable_intr;
320 static pic_map_intr_t gicv3_its_map_intr;
321 static pic_setup_intr_t gicv3_its_setup_intr;
322 static pic_post_filter_t gicv3_its_post_filter;
323 static pic_post_ithread_t gicv3_its_post_ithread;
324 static pic_pre_ithread_t gicv3_its_pre_ithread;
325 static pic_bind_intr_t gicv3_its_bind_intr;
327 static pic_init_secondary_t gicv3_its_init_secondary;
329 static msi_alloc_msi_t gicv3_its_alloc_msi;
330 static msi_release_msi_t gicv3_its_release_msi;
331 static msi_alloc_msix_t gicv3_its_alloc_msix;
332 static msi_release_msix_t gicv3_its_release_msix;
333 static msi_map_msi_t gicv3_its_map_msi;
335 static msi_iommu_init_t gicv3_iommu_init;
336 static msi_iommu_deinit_t gicv3_iommu_deinit;
339 static void its_cmd_movi(device_t, struct gicv3_its_irqsrc *);
340 static void its_cmd_mapc(device_t, struct its_col *, uint8_t);
341 static void its_cmd_mapti(device_t, struct gicv3_its_irqsrc *);
342 static void its_cmd_mapd(device_t, struct its_dev *, uint8_t);
343 static void its_cmd_inv(device_t, struct its_dev *, struct gicv3_its_irqsrc *);
344 static void its_cmd_invall(device_t, struct its_col *);
346 static device_method_t gicv3_its_methods[] = {
347 /* Device interface */
348 DEVMETHOD(device_detach, gicv3_its_detach),
350 /* Interrupt controller interface */
351 DEVMETHOD(pic_disable_intr, gicv3_its_disable_intr),
352 DEVMETHOD(pic_enable_intr, gicv3_its_enable_intr),
353 DEVMETHOD(pic_map_intr, gicv3_its_map_intr),
354 DEVMETHOD(pic_setup_intr, gicv3_its_setup_intr),
355 DEVMETHOD(pic_post_filter, gicv3_its_post_filter),
356 DEVMETHOD(pic_post_ithread, gicv3_its_post_ithread),
357 DEVMETHOD(pic_pre_ithread, gicv3_its_pre_ithread),
359 DEVMETHOD(pic_bind_intr, gicv3_its_bind_intr),
360 DEVMETHOD(pic_init_secondary, gicv3_its_init_secondary),
364 DEVMETHOD(msi_alloc_msi, gicv3_its_alloc_msi),
365 DEVMETHOD(msi_release_msi, gicv3_its_release_msi),
366 DEVMETHOD(msi_alloc_msix, gicv3_its_alloc_msix),
367 DEVMETHOD(msi_release_msix, gicv3_its_release_msix),
368 DEVMETHOD(msi_map_msi, gicv3_its_map_msi),
370 DEVMETHOD(msi_iommu_init, gicv3_iommu_init),
371 DEVMETHOD(msi_iommu_deinit, gicv3_iommu_deinit),
378 static DEFINE_CLASS_0(gic, gicv3_its_driver, gicv3_its_methods,
379 sizeof(struct gicv3_its_softc));
382 gicv3_its_cmdq_init(struct gicv3_its_softc *sc)
384 vm_paddr_t cmd_paddr;
387 /* Set up the command circular buffer */
388 sc->sc_its_cmd_base = contigmalloc(ITS_CMDQ_SIZE, M_GICV3_ITS,
389 M_WAITOK | M_ZERO, 0, (1ul << 48) - 1, ITS_CMDQ_ALIGN, 0);
390 sc->sc_its_cmd_next_idx = 0;
392 cmd_paddr = vtophys(sc->sc_its_cmd_base);
394 /* Set the base of the command buffer */
395 reg = GITS_CBASER_VALID |
396 (GITS_CBASER_CACHE_NIWAWB << GITS_CBASER_CACHE_SHIFT) |
397 cmd_paddr | (GITS_CBASER_SHARE_IS << GITS_CBASER_SHARE_SHIFT) |
398 (ITS_CMDQ_SIZE / 4096 - 1);
399 gic_its_write_8(sc, GITS_CBASER, reg);
401 /* Read back to check for fixed value fields */
402 tmp = gic_its_read_8(sc, GITS_CBASER);
404 if ((tmp & GITS_CBASER_SHARE_MASK) !=
405 (GITS_CBASER_SHARE_IS << GITS_CBASER_SHARE_SHIFT)) {
406 /* Check if the hardware reported non-shareable */
407 if ((tmp & GITS_CBASER_SHARE_MASK) ==
408 (GITS_CBASER_SHARE_NS << GITS_CBASER_SHARE_SHIFT)) {
409 /* If so remove the cache attribute */
410 reg &= ~GITS_CBASER_CACHE_MASK;
411 reg &= ~GITS_CBASER_SHARE_MASK;
412 /* Set to Non-cacheable, Non-shareable */
413 reg |= GITS_CBASER_CACHE_NIN << GITS_CBASER_CACHE_SHIFT;
414 reg |= GITS_CBASER_SHARE_NS << GITS_CBASER_SHARE_SHIFT;
416 gic_its_write_8(sc, GITS_CBASER, reg);
419 /* The command queue has to be flushed after each command */
420 sc->sc_its_flags |= ITS_FLAGS_CMDQ_FLUSH;
423 /* Get the next command from the start of the buffer */
424 gic_its_write_8(sc, GITS_CWRITER, 0x0);
428 gicv3_its_table_init(device_t dev, struct gicv3_its_softc *sc)
432 uint64_t cache, reg, share, tmp, type;
433 size_t esize, its_tbl_size, nidents, nitspages, npages;
437 if ((sc->sc_its_flags & ITS_FLAGS_ERRATA_CAVIUM_22375) != 0) {
439 * GITS_TYPER[17:13] of ThunderX reports that device IDs
440 * are to be 21 bits in length. The entry size of the ITS
441 * table can be read from GITS_BASERn[52:48] and on ThunderX
442 * is supposed to be 8 bytes in length (for device table).
443 * Finally the page size that is to be used by ITS to access
444 * this table will be set to 64KB.
446 * This gives 0x200000 entries of size 0x8 bytes covered by
447 * 256 pages each of which 64KB in size. The number of pages
448 * (minus 1) should then be written to GITS_BASERn[7:0]. In
449 * that case this value would be 0xFF but on ThunderX the
450 * maximum value that HW accepts is 0xFD.
452 * Set an arbitrary number of device ID bits to 20 in order
453 * to limit the number of entries in ITS device table to
454 * 0x100000 and the table size to 8MB.
459 devbits = GITS_TYPER_DEVB(gic_its_read_8(sc, GITS_TYPER));
460 cache = GITS_BASER_CACHE_WAWB;
462 share = GITS_BASER_SHARE_IS;
463 page_size = PAGE_SIZE_64K;
465 for (i = 0; i < GITS_BASER_NUM; i++) {
466 reg = gic_its_read_8(sc, GITS_BASER(i));
467 /* The type of table */
468 type = GITS_BASER_TYPE(reg);
469 /* The table entry size */
470 esize = GITS_BASER_ESIZE(reg);
473 case GITS_BASER_TYPE_DEV:
474 nidents = (1 << devbits);
475 its_tbl_size = esize * nidents;
476 its_tbl_size = roundup2(its_tbl_size, PAGE_SIZE_64K);
478 case GITS_BASER_TYPE_VP:
479 case GITS_BASER_TYPE_PP: /* Undocumented? */
480 case GITS_BASER_TYPE_IC:
481 its_tbl_size = page_size;
486 npages = howmany(its_tbl_size, PAGE_SIZE);
488 /* Allocate the table */
489 table = (vm_offset_t)contigmalloc(npages * PAGE_SIZE,
490 M_GICV3_ITS, M_WAITOK | M_ZERO, 0, (1ul << 48) - 1,
493 sc->sc_its_ptab[i].ptab_vaddr = table;
494 sc->sc_its_ptab[i].ptab_size = npages * PAGE_SIZE;
496 paddr = vtophys(table);
499 nitspages = howmany(its_tbl_size, page_size);
501 /* Clear the fields we will be setting */
502 reg &= ~(GITS_BASER_VALID |
503 GITS_BASER_CACHE_MASK | GITS_BASER_TYPE_MASK |
504 GITS_BASER_ESIZE_MASK | GITS_BASER_PA_MASK |
505 GITS_BASER_SHARE_MASK | GITS_BASER_PSZ_MASK |
506 GITS_BASER_SIZE_MASK);
507 /* Set the new values */
508 reg |= GITS_BASER_VALID |
509 (cache << GITS_BASER_CACHE_SHIFT) |
510 (type << GITS_BASER_TYPE_SHIFT) |
511 ((esize - 1) << GITS_BASER_ESIZE_SHIFT) |
512 paddr | (share << GITS_BASER_SHARE_SHIFT) |
516 case PAGE_SIZE_4K: /* 4KB */
518 GITS_BASER_PSZ_4K << GITS_BASER_PSZ_SHIFT;
520 case PAGE_SIZE_16K: /* 16KB */
522 GITS_BASER_PSZ_16K << GITS_BASER_PSZ_SHIFT;
524 case PAGE_SIZE_64K: /* 64KB */
526 GITS_BASER_PSZ_64K << GITS_BASER_PSZ_SHIFT;
530 gic_its_write_8(sc, GITS_BASER(i), reg);
532 /* Read back to check */
533 tmp = gic_its_read_8(sc, GITS_BASER(i));
535 /* Do the shareability masks line up? */
536 if ((tmp & GITS_BASER_SHARE_MASK) !=
537 (reg & GITS_BASER_SHARE_MASK)) {
538 share = (tmp & GITS_BASER_SHARE_MASK) >>
539 GITS_BASER_SHARE_SHIFT;
543 if ((tmp & GITS_BASER_PSZ_MASK) !=
544 (reg & GITS_BASER_PSZ_MASK)) {
547 page_size = PAGE_SIZE_4K;
550 page_size = PAGE_SIZE_16K;
556 device_printf(dev, "GITS_BASER%d: "
557 "unable to be updated: %lx != %lx\n",
562 /* We should have made all needed changes */
571 gicv3_its_conftable_init(struct gicv3_its_softc *sc)
575 conf_table = atomic_load_ptr(&conf_base);
576 if (conf_table == NULL) {
577 conf_table = contigmalloc(LPI_CONFTAB_SIZE,
578 M_GICV3_ITS, M_WAITOK, 0, LPI_CONFTAB_MAX_ADDR,
579 LPI_CONFTAB_ALIGN, 0);
581 if (atomic_cmpset_ptr((uintptr_t *)&conf_base,
582 (uintptr_t)NULL, (uintptr_t)conf_table) == 0) {
583 contigfree(conf_table, LPI_CONFTAB_SIZE, M_GICV3_ITS);
584 conf_table = atomic_load_ptr(&conf_base);
587 sc->sc_conf_base = conf_table;
589 /* Set the default configuration */
590 memset(sc->sc_conf_base, GIC_PRIORITY_MAX | LPI_CONF_GROUP1,
593 /* Flush the table to memory */
594 cpu_dcache_wb_range((vm_offset_t)sc->sc_conf_base, LPI_CONFTAB_SIZE);
598 gicv3_its_pendtables_init(struct gicv3_its_softc *sc)
602 for (i = 0; i <= mp_maxid; i++) {
603 if (CPU_ISSET(i, &sc->sc_cpus) == 0)
606 sc->sc_pend_base[i] = (vm_offset_t)contigmalloc(
607 LPI_PENDTAB_SIZE, M_GICV3_ITS, M_WAITOK | M_ZERO,
608 0, LPI_PENDTAB_MAX_ADDR, LPI_PENDTAB_ALIGN, 0);
610 /* Flush so the ITS can see the memory */
611 cpu_dcache_wb_range((vm_offset_t)sc->sc_pend_base[i],
617 its_init_cpu_lpi(device_t dev, struct gicv3_its_softc *sc)
620 uint64_t xbaser, tmp;
624 gicv3 = device_get_parent(dev);
625 cpuid = PCPU_GET(cpuid);
628 ctlr = gic_r_read_4(gicv3, GICR_CTLR);
629 ctlr &= ~GICR_CTLR_LPI_ENABLE;
630 gic_r_write_4(gicv3, GICR_CTLR, ctlr);
632 /* Make sure changes are observable my the GIC */
636 * Set the redistributor base
638 xbaser = vtophys(sc->sc_conf_base) |
639 (GICR_PROPBASER_SHARE_IS << GICR_PROPBASER_SHARE_SHIFT) |
640 (GICR_PROPBASER_CACHE_NIWAWB << GICR_PROPBASER_CACHE_SHIFT) |
641 (flsl(LPI_CONFTAB_SIZE | GIC_FIRST_LPI) - 1);
642 gic_r_write_8(gicv3, GICR_PROPBASER, xbaser);
644 /* Check the cache attributes we set */
645 tmp = gic_r_read_8(gicv3, GICR_PROPBASER);
647 if ((tmp & GICR_PROPBASER_SHARE_MASK) !=
648 (xbaser & GICR_PROPBASER_SHARE_MASK)) {
649 if ((tmp & GICR_PROPBASER_SHARE_MASK) ==
650 (GICR_PROPBASER_SHARE_NS << GICR_PROPBASER_SHARE_SHIFT)) {
651 /* We need to mark as non-cacheable */
652 xbaser &= ~(GICR_PROPBASER_SHARE_MASK |
653 GICR_PROPBASER_CACHE_MASK);
655 xbaser |= GICR_PROPBASER_CACHE_NIN <<
656 GICR_PROPBASER_CACHE_SHIFT;
658 xbaser |= GICR_PROPBASER_SHARE_NS <<
659 GICR_PROPBASER_SHARE_SHIFT;
660 gic_r_write_8(gicv3, GICR_PROPBASER, xbaser);
662 sc->sc_its_flags |= ITS_FLAGS_LPI_CONF_FLUSH;
666 * Set the LPI pending table base
668 xbaser = vtophys(sc->sc_pend_base[cpuid]) |
669 (GICR_PENDBASER_CACHE_NIWAWB << GICR_PENDBASER_CACHE_SHIFT) |
670 (GICR_PENDBASER_SHARE_IS << GICR_PENDBASER_SHARE_SHIFT);
672 gic_r_write_8(gicv3, GICR_PENDBASER, xbaser);
674 tmp = gic_r_read_8(gicv3, GICR_PENDBASER);
676 if ((tmp & GICR_PENDBASER_SHARE_MASK) ==
677 (GICR_PENDBASER_SHARE_NS << GICR_PENDBASER_SHARE_SHIFT)) {
678 /* Clear the cahce and shareability bits */
679 xbaser &= ~(GICR_PENDBASER_CACHE_MASK |
680 GICR_PENDBASER_SHARE_MASK);
681 /* Mark as non-shareable */
682 xbaser |= GICR_PENDBASER_SHARE_NS << GICR_PENDBASER_SHARE_SHIFT;
683 /* And non-cacheable */
684 xbaser |= GICR_PENDBASER_CACHE_NIN <<
685 GICR_PENDBASER_CACHE_SHIFT;
689 ctlr = gic_r_read_4(gicv3, GICR_CTLR);
690 ctlr |= GICR_CTLR_LPI_ENABLE;
691 gic_r_write_4(gicv3, GICR_CTLR, ctlr);
693 /* Make sure the GIC has seen everything */
698 its_init_cpu(device_t dev, struct gicv3_its_softc *sc)
703 struct redist_pcpu *rpcpu;
705 gicv3 = device_get_parent(dev);
706 cpuid = PCPU_GET(cpuid);
707 if (!CPU_ISSET(cpuid, &sc->sc_cpus))
710 /* Check if the ITS is enabled on this CPU */
711 if ((gic_r_read_8(gicv3, GICR_TYPER) & GICR_TYPER_PLPIS) == 0)
714 rpcpu = gicv3_get_redist(dev);
716 /* Do per-cpu LPI init once */
717 if (!rpcpu->lpi_enabled) {
718 its_init_cpu_lpi(dev, sc);
719 rpcpu->lpi_enabled = true;
722 if ((gic_its_read_8(sc, GITS_TYPER) & GITS_TYPER_PTA) != 0) {
723 /* This ITS wants the redistributor physical address */
724 target = vtophys(rman_get_virtual(&rpcpu->res));
726 /* This ITS wants the unique processor number */
727 target = GICR_TYPER_CPUNUM(gic_r_read_8(gicv3, GICR_TYPER)) <<
731 sc->sc_its_cols[cpuid]->col_target = target;
732 sc->sc_its_cols[cpuid]->col_id = cpuid;
734 its_cmd_mapc(dev, sc->sc_its_cols[cpuid], 1);
735 its_cmd_invall(dev, sc->sc_its_cols[cpuid]);
741 gicv3_its_sysctl_trace_enable(SYSCTL_HANDLER_ARGS)
743 struct gicv3_its_softc *sc;
748 rv = sysctl_handle_bool(oidp, &sc->trace_enable, 0, req);
749 if (rv != 0 || req->newptr == NULL)
751 if (sc->trace_enable)
752 gic_its_write_8(sc, GITS_TRKCTLR, 3);
754 gic_its_write_8(sc, GITS_TRKCTLR, 0);
760 gicv3_its_sysctl_trace_regs(SYSCTL_HANDLER_ARGS)
762 struct gicv3_its_softc *sc;
767 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
769 device_printf(sc->dev, "Could not allocate sbuf for output.\n");
773 sbuf_printf(sb, "GITS_TRKCTLR: 0x%08X\n",
774 gic_its_read_4(sc, GITS_TRKCTLR));
775 sbuf_printf(sb, "GITS_TRKR: 0x%08X\n",
776 gic_its_read_4(sc, GITS_TRKR));
777 sbuf_printf(sb, "GITS_TRKDIDR: 0x%08X\n",
778 gic_its_read_4(sc, GITS_TRKDIDR));
779 sbuf_printf(sb, "GITS_TRKPIDR: 0x%08X\n",
780 gic_its_read_4(sc, GITS_TRKPIDR));
781 sbuf_printf(sb, "GITS_TRKVIDR: 0x%08X\n",
782 gic_its_read_4(sc, GITS_TRKVIDR));
783 sbuf_printf(sb, "GITS_TRKTGTR: 0x%08X\n",
784 gic_its_read_4(sc, GITS_TRKTGTR));
786 err = sbuf_finish(sb);
788 device_printf(sc->dev, "Error finishing sbuf: %d\n", err);
794 gicv3_its_init_sysctl(struct gicv3_its_softc *sc)
796 struct sysctl_oid *oid, *child;
797 struct sysctl_ctx_list *ctx_list;
799 ctx_list = device_get_sysctl_ctx(sc->dev);
800 child = device_get_sysctl_tree(sc->dev);
801 oid = SYSCTL_ADD_NODE(ctx_list,
802 SYSCTL_CHILDREN(child), OID_AUTO, "tracing",
803 CTLFLAG_RD| CTLFLAG_MPSAFE, NULL, "Messages tracing");
808 SYSCTL_ADD_PROC(ctx_list,
809 SYSCTL_CHILDREN(oid), OID_AUTO, "enable",
810 CTLTYPE_U8 | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
811 gicv3_its_sysctl_trace_enable, "CU", "Enable tracing");
812 SYSCTL_ADD_PROC(ctx_list,
813 SYSCTL_CHILDREN(oid), OID_AUTO, "capture",
814 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
815 gicv3_its_sysctl_trace_regs, "", "Captured tracing registers.");
821 gicv3_its_attach(device_t dev)
823 struct gicv3_its_softc *sc;
824 int domain, err, i, rid;
828 sc = device_get_softc(dev);
830 sc->sc_irq_length = gicv3_get_nirqs(dev);
831 sc->sc_irq_base = GIC_FIRST_LPI;
832 sc->sc_irq_base += device_get_unit(dev) * sc->sc_irq_length;
835 sc->sc_its_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
837 if (sc->sc_its_res == NULL) {
838 device_printf(dev, "Could not allocate memory\n");
842 phys = rounddown2(vtophys(rman_get_virtual(sc->sc_its_res)) +
843 GITS_TRANSLATER, PAGE_SIZE);
844 sc->ma = malloc(sizeof(struct vm_page), M_DEVBUF, M_WAITOK | M_ZERO);
845 vm_page_initfake(sc->ma, phys, VM_MEMATTR_DEFAULT);
847 iidr = gic_its_read_4(sc, GITS_IIDR);
848 for (i = 0; i < nitems(its_quirks); i++) {
849 if ((iidr & its_quirks[i].iidr_mask) == its_quirks[i].iidr) {
851 device_printf(dev, "Applying %s\n",
854 its_quirks[i].func(dev);
859 /* Allocate the private tables */
860 err = gicv3_its_table_init(dev, sc);
864 /* Protects access to the device list */
865 mtx_init(&sc->sc_its_dev_lock, "ITS device lock", NULL, MTX_SPIN);
867 /* Protects access to the ITS command circular buffer. */
868 mtx_init(&sc->sc_its_cmd_lock, "ITS cmd lock", NULL, MTX_SPIN);
870 CPU_ZERO(&sc->sc_cpus);
871 if (bus_get_domain(dev, &domain) == 0) {
872 if (domain < MAXMEMDOM)
873 CPU_COPY(&cpuset_domain[domain], &sc->sc_cpus);
875 CPU_COPY(&all_cpus, &sc->sc_cpus);
878 /* Allocate the command circular buffer */
879 gicv3_its_cmdq_init(sc);
881 /* Allocate the per-CPU collections */
882 for (int cpu = 0; cpu <= mp_maxid; cpu++)
883 if (CPU_ISSET(cpu, &sc->sc_cpus) != 0)
884 sc->sc_its_cols[cpu] = malloc(
885 sizeof(*sc->sc_its_cols[0]), M_GICV3_ITS,
888 sc->sc_its_cols[cpu] = NULL;
891 gic_its_write_4(sc, GITS_CTLR,
892 gic_its_read_4(sc, GITS_CTLR) | GITS_CTLR_EN);
894 /* Create the LPI configuration table */
895 gicv3_its_conftable_init(sc);
897 /* And the pending tebles */
898 gicv3_its_pendtables_init(sc);
900 /* Enable LPIs on this CPU */
901 its_init_cpu(dev, sc);
903 TAILQ_INIT(&sc->sc_its_dev_list);
904 TAILQ_INIT(&sc->sc_free_irqs);
907 * Create the vmem object to allocate INTRNG IRQs from. We try to
908 * use all IRQs not already used by the GICv3.
909 * XXX: This assumes there are no other interrupt controllers in the
912 sc->sc_irq_alloc = vmem_create(device_get_nameunit(dev), 0,
913 gicv3_get_nirqs(dev), 1, 0, M_FIRSTFIT | M_WAITOK);
915 sc->sc_irqs = malloc(sizeof(*sc->sc_irqs) * sc->sc_irq_length,
916 M_GICV3_ITS, M_WAITOK | M_ZERO);
918 /* For GIC-500 install tracking sysctls. */
919 if ((iidr & (GITS_IIDR_PRODUCT_MASK | GITS_IIDR_IMPLEMENTOR_MASK)) ==
920 GITS_IIDR_RAW(GITS_IIDR_IMPL_ARM, GITS_IIDR_PROD_GIC500, 0, 0))
921 gicv3_its_init_sysctl(sc);
927 gicv3_its_detach(device_t dev)
934 its_quirk_cavium_22375(device_t dev)
936 struct gicv3_its_softc *sc;
938 sc = device_get_softc(dev);
939 sc->sc_its_flags |= ITS_FLAGS_ERRATA_CAVIUM_22375;
943 gicv3_its_disable_intr(device_t dev, struct intr_irqsrc *isrc)
945 struct gicv3_its_softc *sc;
946 struct gicv3_its_irqsrc *girq;
949 sc = device_get_softc(dev);
950 girq = (struct gicv3_its_irqsrc *)isrc;
951 conf = sc->sc_conf_base;
953 conf[girq->gi_lpi] &= ~LPI_CONF_ENABLE;
955 if ((sc->sc_its_flags & ITS_FLAGS_LPI_CONF_FLUSH) != 0) {
956 /* Clean D-cache under command. */
957 cpu_dcache_wb_range((vm_offset_t)&conf[girq->gi_lpi], 1);
959 /* DSB inner shareable, store */
963 its_cmd_inv(dev, girq->gi_its_dev, girq);
967 gicv3_its_enable_intr(device_t dev, struct intr_irqsrc *isrc)
969 struct gicv3_its_softc *sc;
970 struct gicv3_its_irqsrc *girq;
973 sc = device_get_softc(dev);
974 girq = (struct gicv3_its_irqsrc *)isrc;
975 conf = sc->sc_conf_base;
977 conf[girq->gi_lpi] |= LPI_CONF_ENABLE;
979 if ((sc->sc_its_flags & ITS_FLAGS_LPI_CONF_FLUSH) != 0) {
980 /* Clean D-cache under command. */
981 cpu_dcache_wb_range((vm_offset_t)&conf[girq->gi_lpi], 1);
983 /* DSB inner shareable, store */
987 its_cmd_inv(dev, girq->gi_its_dev, girq);
991 gicv3_its_intr(void *arg, uintptr_t irq)
993 struct gicv3_its_softc *sc = arg;
994 struct gicv3_its_irqsrc *girq;
995 struct trapframe *tf;
997 irq -= sc->sc_irq_base;
998 girq = sc->sc_irqs[irq];
1000 panic("gicv3_its_intr: Invalid interrupt %ld",
1001 irq + sc->sc_irq_base);
1003 tf = curthread->td_intr_frame;
1004 intr_isrc_dispatch(&girq->gi_isrc, tf);
1005 return (FILTER_HANDLED);
1009 gicv3_its_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
1011 struct gicv3_its_irqsrc *girq;
1012 struct gicv3_its_softc *sc;
1014 sc = device_get_softc(dev);
1015 girq = (struct gicv3_its_irqsrc *)isrc;
1016 gicv3_its_disable_intr(dev, isrc);
1017 gic_icc_write(EOIR1, girq->gi_lpi + GIC_FIRST_LPI);
1021 gicv3_its_post_ithread(device_t dev, struct intr_irqsrc *isrc)
1024 gicv3_its_enable_intr(dev, isrc);
1028 gicv3_its_post_filter(device_t dev, struct intr_irqsrc *isrc)
1030 struct gicv3_its_irqsrc *girq;
1031 struct gicv3_its_softc *sc;
1033 sc = device_get_softc(dev);
1034 girq = (struct gicv3_its_irqsrc *)isrc;
1035 gic_icc_write(EOIR1, girq->gi_lpi + GIC_FIRST_LPI);
1039 gicv3_its_select_cpu(device_t dev, struct intr_irqsrc *isrc)
1041 struct gicv3_its_softc *sc;
1043 sc = device_get_softc(dev);
1044 if (CPU_EMPTY(&isrc->isrc_cpu)) {
1045 sc->gic_irq_cpu = intr_irq_next_cpu(sc->gic_irq_cpu,
1047 CPU_SETOF(sc->gic_irq_cpu, &isrc->isrc_cpu);
1054 gicv3_its_bind_intr(device_t dev, struct intr_irqsrc *isrc)
1056 struct gicv3_its_irqsrc *girq;
1058 gicv3_its_select_cpu(dev, isrc);
1060 girq = (struct gicv3_its_irqsrc *)isrc;
1061 its_cmd_movi(dev, girq);
1066 gicv3_its_map_intr(device_t dev, struct intr_map_data *data,
1067 struct intr_irqsrc **isrcp)
1071 * This should never happen, we only call this function to map
1072 * interrupts found before the controller driver is ready.
1074 panic("gicv3_its_map_intr: Unable to map a MSI interrupt");
1078 gicv3_its_setup_intr(device_t dev, struct intr_irqsrc *isrc,
1079 struct resource *res, struct intr_map_data *data)
1082 /* Bind the interrupt to a CPU */
1083 gicv3_its_bind_intr(dev, isrc);
1090 gicv3_its_init_secondary(device_t dev)
1092 struct gicv3_its_softc *sc;
1094 sc = device_get_softc(dev);
1097 * This is fatal as otherwise we may bind interrupts to this CPU.
1098 * We need a way to tell the interrupt framework to only bind to a
1099 * subset of given CPUs when it performs the shuffle.
1101 if (its_init_cpu(dev, sc) != 0)
1102 panic("gicv3_its_init_secondary: No usable ITS on CPU%d",
1108 its_get_devid(device_t pci_dev)
1112 if (pci_get_id(pci_dev, PCI_ID_MSI, &id) != 0)
1113 panic("%s: %s: Unable to get the MSI DeviceID", __func__,
1114 device_get_nameunit(pci_dev));
1119 static struct its_dev *
1120 its_device_find(device_t dev, device_t child)
1122 struct gicv3_its_softc *sc;
1123 struct its_dev *its_dev = NULL;
1125 sc = device_get_softc(dev);
1127 mtx_lock_spin(&sc->sc_its_dev_lock);
1128 TAILQ_FOREACH(its_dev, &sc->sc_its_dev_list, entry) {
1129 if (its_dev->pci_dev == child)
1132 mtx_unlock_spin(&sc->sc_its_dev_lock);
1137 static struct its_dev *
1138 its_device_get(device_t dev, device_t child, u_int nvecs)
1140 struct gicv3_its_softc *sc;
1141 struct its_dev *its_dev;
1142 vmem_addr_t irq_base;
1145 sc = device_get_softc(dev);
1147 its_dev = its_device_find(dev, child);
1148 if (its_dev != NULL)
1151 its_dev = malloc(sizeof(*its_dev), M_GICV3_ITS, M_NOWAIT | M_ZERO);
1152 if (its_dev == NULL)
1155 its_dev->pci_dev = child;
1156 its_dev->devid = its_get_devid(child);
1158 its_dev->lpis.lpi_busy = 0;
1159 its_dev->lpis.lpi_num = nvecs;
1160 its_dev->lpis.lpi_free = nvecs;
1162 if (vmem_alloc(sc->sc_irq_alloc, nvecs, M_FIRSTFIT | M_NOWAIT,
1164 free(its_dev, M_GICV3_ITS);
1167 its_dev->lpis.lpi_base = irq_base;
1169 /* Get ITT entry size */
1170 esize = GITS_TYPER_ITTES(gic_its_read_8(sc, GITS_TYPER));
1173 * Allocate ITT for this device.
1174 * PA has to be 256 B aligned. At least two entries for device.
1176 its_dev->itt_size = roundup2(MAX(nvecs, 2) * esize, 256);
1177 its_dev->itt = (vm_offset_t)contigmalloc(its_dev->itt_size,
1178 M_GICV3_ITS, M_NOWAIT | M_ZERO, 0, LPI_INT_TRANS_TAB_MAX_ADDR,
1179 LPI_INT_TRANS_TAB_ALIGN, 0);
1180 if (its_dev->itt == 0) {
1181 vmem_free(sc->sc_irq_alloc, its_dev->lpis.lpi_base, nvecs);
1182 free(its_dev, M_GICV3_ITS);
1186 mtx_lock_spin(&sc->sc_its_dev_lock);
1187 TAILQ_INSERT_TAIL(&sc->sc_its_dev_list, its_dev, entry);
1188 mtx_unlock_spin(&sc->sc_its_dev_lock);
1190 /* Map device to its ITT */
1191 its_cmd_mapd(dev, its_dev, 1);
1197 its_device_release(device_t dev, struct its_dev *its_dev)
1199 struct gicv3_its_softc *sc;
1201 KASSERT(its_dev->lpis.lpi_busy == 0,
1202 ("its_device_release: Trying to release an inuse ITS device"));
1204 /* Unmap device in ITS */
1205 its_cmd_mapd(dev, its_dev, 0);
1207 sc = device_get_softc(dev);
1209 /* Remove the device from the list of devices */
1210 mtx_lock_spin(&sc->sc_its_dev_lock);
1211 TAILQ_REMOVE(&sc->sc_its_dev_list, its_dev, entry);
1212 mtx_unlock_spin(&sc->sc_its_dev_lock);
1215 KASSERT(its_dev->itt != 0, ("Invalid ITT in valid ITS device"));
1216 contigfree((void *)its_dev->itt, its_dev->itt_size, M_GICV3_ITS);
1218 /* Free the IRQ allocation */
1219 vmem_free(sc->sc_irq_alloc, its_dev->lpis.lpi_base,
1220 its_dev->lpis.lpi_num);
1222 free(its_dev, M_GICV3_ITS);
1225 static struct gicv3_its_irqsrc *
1226 gicv3_its_alloc_irqsrc(device_t dev, struct gicv3_its_softc *sc, u_int irq)
1228 struct gicv3_its_irqsrc *girq = NULL;
1230 KASSERT(sc->sc_irqs[irq] == NULL,
1231 ("%s: Interrupt %u already allocated", __func__, irq));
1232 mtx_lock_spin(&sc->sc_its_dev_lock);
1233 if (!TAILQ_EMPTY(&sc->sc_free_irqs)) {
1234 girq = TAILQ_FIRST(&sc->sc_free_irqs);
1235 TAILQ_REMOVE(&sc->sc_free_irqs, girq, gi_link);
1237 mtx_unlock_spin(&sc->sc_its_dev_lock);
1239 girq = malloc(sizeof(*girq), M_GICV3_ITS,
1244 if (intr_isrc_register(&girq->gi_isrc, dev, 0,
1245 "%s,%u", device_get_nameunit(dev), irq) != 0) {
1246 free(girq, M_GICV3_ITS);
1250 girq->gi_lpi = irq + sc->sc_irq_base - GIC_FIRST_LPI;
1251 sc->sc_irqs[irq] = girq;
1257 gicv3_its_release_irqsrc(struct gicv3_its_softc *sc,
1258 struct gicv3_its_irqsrc *girq)
1262 mtx_assert(&sc->sc_its_dev_lock, MA_OWNED);
1264 irq = girq->gi_lpi + GIC_FIRST_LPI - sc->sc_irq_base;
1265 sc->sc_irqs[irq] = NULL;
1268 girq->gi_its_dev = NULL;
1269 TAILQ_INSERT_TAIL(&sc->sc_free_irqs, girq, gi_link);
1273 gicv3_its_alloc_msi(device_t dev, device_t child, int count, int maxcount,
1274 device_t *pic, struct intr_irqsrc **srcs)
1276 struct gicv3_its_softc *sc;
1277 struct gicv3_its_irqsrc *girq;
1278 struct its_dev *its_dev;
1282 its_dev = its_device_get(dev, child, count);
1283 if (its_dev == NULL)
1286 KASSERT(its_dev->lpis.lpi_free >= count,
1287 ("gicv3_its_alloc_msi: No free LPIs"));
1288 sc = device_get_softc(dev);
1289 irq = its_dev->lpis.lpi_base + its_dev->lpis.lpi_num -
1290 its_dev->lpis.lpi_free;
1292 /* Allocate the irqsrc for each MSI */
1293 for (i = 0; i < count; i++, irq++) {
1294 its_dev->lpis.lpi_free--;
1295 srcs[i] = (struct intr_irqsrc *)gicv3_its_alloc_irqsrc(dev,
1297 if (srcs[i] == NULL)
1301 /* The allocation failed, release them */
1303 mtx_lock_spin(&sc->sc_its_dev_lock);
1304 for (i = 0; i < count; i++) {
1305 girq = (struct gicv3_its_irqsrc *)srcs[i];
1308 gicv3_its_release_irqsrc(sc, girq);
1311 mtx_unlock_spin(&sc->sc_its_dev_lock);
1315 /* Finish the allocation now we have all MSI irqsrcs */
1316 for (i = 0; i < count; i++) {
1317 girq = (struct gicv3_its_irqsrc *)srcs[i];
1319 girq->gi_its_dev = its_dev;
1321 /* Map the message to the given IRQ */
1322 gicv3_its_select_cpu(dev, (struct intr_irqsrc *)girq);
1323 its_cmd_mapti(dev, girq);
1325 its_dev->lpis.lpi_busy += count;
1332 gicv3_its_release_msi(device_t dev, device_t child, int count,
1333 struct intr_irqsrc **isrc)
1335 struct gicv3_its_softc *sc;
1336 struct gicv3_its_irqsrc *girq;
1337 struct its_dev *its_dev;
1340 its_dev = its_device_find(dev, child);
1342 KASSERT(its_dev != NULL,
1343 ("gicv3_its_release_msi: Releasing a MSI interrupt with "
1345 KASSERT(its_dev->lpis.lpi_busy >= count,
1346 ("gicv3_its_release_msi: Releasing more interrupts than "
1347 "were allocated: releasing %d, allocated %d", count,
1348 its_dev->lpis.lpi_busy));
1350 sc = device_get_softc(dev);
1351 mtx_lock_spin(&sc->sc_its_dev_lock);
1352 for (i = 0; i < count; i++) {
1353 girq = (struct gicv3_its_irqsrc *)isrc[i];
1354 gicv3_its_release_irqsrc(sc, girq);
1356 mtx_unlock_spin(&sc->sc_its_dev_lock);
1357 its_dev->lpis.lpi_busy -= count;
1359 if (its_dev->lpis.lpi_busy == 0)
1360 its_device_release(dev, its_dev);
1366 gicv3_its_alloc_msix(device_t dev, device_t child, device_t *pic,
1367 struct intr_irqsrc **isrcp)
1369 struct gicv3_its_softc *sc;
1370 struct gicv3_its_irqsrc *girq;
1371 struct its_dev *its_dev;
1374 nvecs = pci_msix_count(child);
1375 its_dev = its_device_get(dev, child, nvecs);
1376 if (its_dev == NULL)
1379 KASSERT(its_dev->lpis.lpi_free > 0,
1380 ("gicv3_its_alloc_msix: No free LPIs"));
1381 sc = device_get_softc(dev);
1382 irq = its_dev->lpis.lpi_base + its_dev->lpis.lpi_num -
1383 its_dev->lpis.lpi_free;
1385 girq = gicv3_its_alloc_irqsrc(dev, sc, irq);
1388 girq->gi_id = its_dev->lpis.lpi_busy;
1389 girq->gi_its_dev = its_dev;
1391 its_dev->lpis.lpi_free--;
1392 its_dev->lpis.lpi_busy++;
1394 /* Map the message to the given IRQ */
1395 gicv3_its_select_cpu(dev, (struct intr_irqsrc *)girq);
1396 its_cmd_mapti(dev, girq);
1399 *isrcp = (struct intr_irqsrc *)girq;
1405 gicv3_its_release_msix(device_t dev, device_t child, struct intr_irqsrc *isrc)
1407 struct gicv3_its_softc *sc;
1408 struct gicv3_its_irqsrc *girq;
1409 struct its_dev *its_dev;
1411 its_dev = its_device_find(dev, child);
1413 KASSERT(its_dev != NULL,
1414 ("gicv3_its_release_msix: Releasing a MSI-X interrupt with "
1416 KASSERT(its_dev->lpis.lpi_busy > 0,
1417 ("gicv3_its_release_msix: Releasing more interrupts than "
1418 "were allocated: allocated %d", its_dev->lpis.lpi_busy));
1420 sc = device_get_softc(dev);
1421 girq = (struct gicv3_its_irqsrc *)isrc;
1422 mtx_lock_spin(&sc->sc_its_dev_lock);
1423 gicv3_its_release_irqsrc(sc, girq);
1424 mtx_unlock_spin(&sc->sc_its_dev_lock);
1425 its_dev->lpis.lpi_busy--;
1427 if (its_dev->lpis.lpi_busy == 0)
1428 its_device_release(dev, its_dev);
1434 gicv3_its_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc,
1435 uint64_t *addr, uint32_t *data)
1437 struct gicv3_its_softc *sc;
1438 struct gicv3_its_irqsrc *girq;
1440 sc = device_get_softc(dev);
1441 girq = (struct gicv3_its_irqsrc *)isrc;
1443 *addr = vtophys(rman_get_virtual(sc->sc_its_res)) + GITS_TRANSLATER;
1444 *data = girq->gi_id;
1451 gicv3_iommu_init(device_t dev, device_t child, struct iommu_domain **domain)
1453 struct gicv3_its_softc *sc;
1454 struct iommu_ctx *ctx;
1457 sc = device_get_softc(dev);
1458 ctx = iommu_get_dev_ctx(child);
1459 error = iommu_map_msi(ctx, PAGE_SIZE, GITS_TRANSLATER,
1460 IOMMU_MAP_ENTRY_WRITE, IOMMU_MF_CANWAIT, &sc->ma);
1461 *domain = iommu_get_ctx_domain(ctx);
1467 gicv3_iommu_deinit(device_t dev, device_t child)
1469 struct iommu_ctx *ctx;
1471 ctx = iommu_get_dev_ctx(child);
1472 iommu_unmap_msi(ctx);
1477 * Commands handling.
1480 static __inline void
1481 cmd_format_command(struct its_cmd *cmd, uint8_t cmd_type)
1483 /* Command field: DW0 [7:0] */
1484 cmd->cmd_dword[0] &= htole64(~CMD_COMMAND_MASK);
1485 cmd->cmd_dword[0] |= htole64(cmd_type);
1488 static __inline void
1489 cmd_format_devid(struct its_cmd *cmd, uint32_t devid)
1491 /* Device ID field: DW0 [63:32] */
1492 cmd->cmd_dword[0] &= htole64(~CMD_DEVID_MASK);
1493 cmd->cmd_dword[0] |= htole64((uint64_t)devid << CMD_DEVID_SHIFT);
1496 static __inline void
1497 cmd_format_size(struct its_cmd *cmd, uint16_t size)
1499 /* Size field: DW1 [4:0] */
1500 cmd->cmd_dword[1] &= htole64(~CMD_SIZE_MASK);
1501 cmd->cmd_dword[1] |= htole64((size & CMD_SIZE_MASK));
1504 static __inline void
1505 cmd_format_id(struct its_cmd *cmd, uint32_t id)
1507 /* ID field: DW1 [31:0] */
1508 cmd->cmd_dword[1] &= htole64(~CMD_ID_MASK);
1509 cmd->cmd_dword[1] |= htole64(id);
1512 static __inline void
1513 cmd_format_pid(struct its_cmd *cmd, uint32_t pid)
1515 /* Physical ID field: DW1 [63:32] */
1516 cmd->cmd_dword[1] &= htole64(~CMD_PID_MASK);
1517 cmd->cmd_dword[1] |= htole64((uint64_t)pid << CMD_PID_SHIFT);
1520 static __inline void
1521 cmd_format_col(struct its_cmd *cmd, uint16_t col_id)
1523 /* Collection field: DW2 [16:0] */
1524 cmd->cmd_dword[2] &= htole64(~CMD_COL_MASK);
1525 cmd->cmd_dword[2] |= htole64(col_id);
1528 static __inline void
1529 cmd_format_target(struct its_cmd *cmd, uint64_t target)
1531 /* Target Address field: DW2 [47:16] */
1532 cmd->cmd_dword[2] &= htole64(~CMD_TARGET_MASK);
1533 cmd->cmd_dword[2] |= htole64(target & CMD_TARGET_MASK);
1536 static __inline void
1537 cmd_format_itt(struct its_cmd *cmd, uint64_t itt)
1539 /* ITT Address field: DW2 [47:8] */
1540 cmd->cmd_dword[2] &= htole64(~CMD_ITT_MASK);
1541 cmd->cmd_dword[2] |= htole64(itt & CMD_ITT_MASK);
1544 static __inline void
1545 cmd_format_valid(struct its_cmd *cmd, uint8_t valid)
1547 /* Valid field: DW2 [63] */
1548 cmd->cmd_dword[2] &= htole64(~CMD_VALID_MASK);
1549 cmd->cmd_dword[2] |= htole64((uint64_t)valid << CMD_VALID_SHIFT);
1553 its_cmd_queue_full(struct gicv3_its_softc *sc)
1555 size_t read_idx, next_write_idx;
1557 /* Get the index of the next command */
1558 next_write_idx = (sc->sc_its_cmd_next_idx + 1) %
1559 (ITS_CMDQ_SIZE / sizeof(struct its_cmd));
1560 /* And the index of the current command being read */
1561 read_idx = gic_its_read_4(sc, GITS_CREADR) / sizeof(struct its_cmd);
1564 * The queue is full when the write offset points
1565 * at the command before the current read offset.
1567 return (next_write_idx == read_idx);
1571 its_cmd_sync(struct gicv3_its_softc *sc, struct its_cmd *cmd)
1574 if ((sc->sc_its_flags & ITS_FLAGS_CMDQ_FLUSH) != 0) {
1575 /* Clean D-cache under command. */
1576 cpu_dcache_wb_range((vm_offset_t)cmd, sizeof(*cmd));
1578 /* DSB inner shareable, store */
1584 static inline uint64_t
1585 its_cmd_cwriter_offset(struct gicv3_its_softc *sc, struct its_cmd *cmd)
1589 off = (cmd - sc->sc_its_cmd_base) * sizeof(*cmd);
1595 its_cmd_wait_completion(device_t dev, struct its_cmd *cmd_first,
1596 struct its_cmd *cmd_last)
1598 struct gicv3_its_softc *sc;
1599 uint64_t first, last, read;
1602 sc = device_get_softc(dev);
1605 * XXX ARM64TODO: This is obviously a significant delay.
1606 * The reason for that is that currently the time frames for
1607 * the command to complete are not known.
1611 first = its_cmd_cwriter_offset(sc, cmd_first);
1612 last = its_cmd_cwriter_offset(sc, cmd_last);
1615 read = gic_its_read_8(sc, GITS_CREADR);
1617 if (read < first || read >= last)
1619 } else if (read < first && read >= last)
1622 if (us_left-- == 0) {
1623 /* This means timeout */
1625 "Timeout while waiting for CMD completion.\n");
1632 static struct its_cmd *
1633 its_cmd_alloc_locked(device_t dev)
1635 struct gicv3_its_softc *sc;
1636 struct its_cmd *cmd;
1639 sc = device_get_softc(dev);
1642 * XXX ARM64TODO: This is obviously a significant delay.
1643 * The reason for that is that currently the time frames for
1644 * the command to complete (and therefore free the descriptor)
1649 mtx_assert(&sc->sc_its_cmd_lock, MA_OWNED);
1650 while (its_cmd_queue_full(sc)) {
1651 if (us_left-- == 0) {
1652 /* Timeout while waiting for free command */
1654 "Timeout while waiting for free command\n");
1660 cmd = &sc->sc_its_cmd_base[sc->sc_its_cmd_next_idx];
1661 sc->sc_its_cmd_next_idx++;
1662 sc->sc_its_cmd_next_idx %= ITS_CMDQ_SIZE / sizeof(struct its_cmd);
1668 its_cmd_prepare(struct its_cmd *cmd, struct its_cmd_desc *desc)
1674 cmd_type = desc->cmd_type;
1675 target = ITS_TARGET_NONE;
1678 case ITS_CMD_MOVI: /* Move interrupt ID to another collection */
1679 target = desc->cmd_desc_movi.col->col_target;
1680 cmd_format_command(cmd, ITS_CMD_MOVI);
1681 cmd_format_id(cmd, desc->cmd_desc_movi.id);
1682 cmd_format_col(cmd, desc->cmd_desc_movi.col->col_id);
1683 cmd_format_devid(cmd, desc->cmd_desc_movi.its_dev->devid);
1685 case ITS_CMD_SYNC: /* Wait for previous commands completion */
1686 target = desc->cmd_desc_sync.col->col_target;
1687 cmd_format_command(cmd, ITS_CMD_SYNC);
1688 cmd_format_target(cmd, target);
1690 case ITS_CMD_MAPD: /* Assign ITT to device */
1691 cmd_format_command(cmd, ITS_CMD_MAPD);
1692 cmd_format_itt(cmd, vtophys(desc->cmd_desc_mapd.its_dev->itt));
1694 * Size describes number of bits to encode interrupt IDs
1695 * supported by the device minus one.
1696 * When V (valid) bit is zero, this field should be written
1699 if (desc->cmd_desc_mapd.valid != 0) {
1700 size = fls(desc->cmd_desc_mapd.its_dev->lpis.lpi_num);
1701 size = MAX(1, size) - 1;
1705 cmd_format_size(cmd, size);
1706 cmd_format_devid(cmd, desc->cmd_desc_mapd.its_dev->devid);
1707 cmd_format_valid(cmd, desc->cmd_desc_mapd.valid);
1709 case ITS_CMD_MAPC: /* Map collection to Re-Distributor */
1710 target = desc->cmd_desc_mapc.col->col_target;
1711 cmd_format_command(cmd, ITS_CMD_MAPC);
1712 cmd_format_col(cmd, desc->cmd_desc_mapc.col->col_id);
1713 cmd_format_valid(cmd, desc->cmd_desc_mapc.valid);
1714 cmd_format_target(cmd, target);
1717 target = desc->cmd_desc_mapvi.col->col_target;
1718 cmd_format_command(cmd, ITS_CMD_MAPTI);
1719 cmd_format_devid(cmd, desc->cmd_desc_mapvi.its_dev->devid);
1720 cmd_format_id(cmd, desc->cmd_desc_mapvi.id);
1721 cmd_format_pid(cmd, desc->cmd_desc_mapvi.pid);
1722 cmd_format_col(cmd, desc->cmd_desc_mapvi.col->col_id);
1725 target = desc->cmd_desc_mapi.col->col_target;
1726 cmd_format_command(cmd, ITS_CMD_MAPI);
1727 cmd_format_devid(cmd, desc->cmd_desc_mapi.its_dev->devid);
1728 cmd_format_id(cmd, desc->cmd_desc_mapi.pid);
1729 cmd_format_col(cmd, desc->cmd_desc_mapi.col->col_id);
1732 target = desc->cmd_desc_inv.col->col_target;
1733 cmd_format_command(cmd, ITS_CMD_INV);
1734 cmd_format_devid(cmd, desc->cmd_desc_inv.its_dev->devid);
1735 cmd_format_id(cmd, desc->cmd_desc_inv.pid);
1737 case ITS_CMD_INVALL:
1738 cmd_format_command(cmd, ITS_CMD_INVALL);
1739 cmd_format_col(cmd, desc->cmd_desc_invall.col->col_id);
1742 panic("its_cmd_prepare: Invalid command: %x", cmd_type);
1749 its_cmd_send(device_t dev, struct its_cmd_desc *desc)
1751 struct gicv3_its_softc *sc;
1752 struct its_cmd *cmd, *cmd_sync, *cmd_write;
1753 struct its_col col_sync;
1754 struct its_cmd_desc desc_sync;
1755 uint64_t target, cwriter;
1757 sc = device_get_softc(dev);
1758 mtx_lock_spin(&sc->sc_its_cmd_lock);
1759 cmd = its_cmd_alloc_locked(dev);
1761 device_printf(dev, "could not allocate ITS command\n");
1762 mtx_unlock_spin(&sc->sc_its_cmd_lock);
1766 target = its_cmd_prepare(cmd, desc);
1767 its_cmd_sync(sc, cmd);
1769 if (target != ITS_TARGET_NONE) {
1770 cmd_sync = its_cmd_alloc_locked(dev);
1771 if (cmd_sync != NULL) {
1772 desc_sync.cmd_type = ITS_CMD_SYNC;
1773 col_sync.col_target = target;
1774 desc_sync.cmd_desc_sync.col = &col_sync;
1775 its_cmd_prepare(cmd_sync, &desc_sync);
1776 its_cmd_sync(sc, cmd_sync);
1780 /* Update GITS_CWRITER */
1781 cwriter = sc->sc_its_cmd_next_idx * sizeof(struct its_cmd);
1782 gic_its_write_8(sc, GITS_CWRITER, cwriter);
1783 cmd_write = &sc->sc_its_cmd_base[sc->sc_its_cmd_next_idx];
1784 mtx_unlock_spin(&sc->sc_its_cmd_lock);
1786 its_cmd_wait_completion(dev, cmd, cmd_write);
1791 /* Handlers to send commands */
1793 its_cmd_movi(device_t dev, struct gicv3_its_irqsrc *girq)
1795 struct gicv3_its_softc *sc;
1796 struct its_cmd_desc desc;
1797 struct its_col *col;
1799 sc = device_get_softc(dev);
1800 col = sc->sc_its_cols[CPU_FFS(&girq->gi_isrc.isrc_cpu) - 1];
1802 desc.cmd_type = ITS_CMD_MOVI;
1803 desc.cmd_desc_movi.its_dev = girq->gi_its_dev;
1804 desc.cmd_desc_movi.col = col;
1805 desc.cmd_desc_movi.id = girq->gi_id;
1807 its_cmd_send(dev, &desc);
1811 its_cmd_mapc(device_t dev, struct its_col *col, uint8_t valid)
1813 struct its_cmd_desc desc;
1815 desc.cmd_type = ITS_CMD_MAPC;
1816 desc.cmd_desc_mapc.col = col;
1818 * Valid bit set - map the collection.
1819 * Valid bit cleared - unmap the collection.
1821 desc.cmd_desc_mapc.valid = valid;
1823 its_cmd_send(dev, &desc);
1827 its_cmd_mapti(device_t dev, struct gicv3_its_irqsrc *girq)
1829 struct gicv3_its_softc *sc;
1830 struct its_cmd_desc desc;
1831 struct its_col *col;
1834 sc = device_get_softc(dev);
1836 col_id = CPU_FFS(&girq->gi_isrc.isrc_cpu) - 1;
1837 col = sc->sc_its_cols[col_id];
1839 desc.cmd_type = ITS_CMD_MAPTI;
1840 desc.cmd_desc_mapvi.its_dev = girq->gi_its_dev;
1841 desc.cmd_desc_mapvi.col = col;
1842 /* The EventID sent to the device */
1843 desc.cmd_desc_mapvi.id = girq->gi_id;
1844 /* The physical interrupt presented to softeware */
1845 desc.cmd_desc_mapvi.pid = girq->gi_lpi + GIC_FIRST_LPI;
1847 its_cmd_send(dev, &desc);
1851 its_cmd_mapd(device_t dev, struct its_dev *its_dev, uint8_t valid)
1853 struct its_cmd_desc desc;
1855 desc.cmd_type = ITS_CMD_MAPD;
1856 desc.cmd_desc_mapd.its_dev = its_dev;
1857 desc.cmd_desc_mapd.valid = valid;
1859 its_cmd_send(dev, &desc);
1863 its_cmd_inv(device_t dev, struct its_dev *its_dev,
1864 struct gicv3_its_irqsrc *girq)
1866 struct gicv3_its_softc *sc;
1867 struct its_cmd_desc desc;
1868 struct its_col *col;
1870 sc = device_get_softc(dev);
1871 col = sc->sc_its_cols[CPU_FFS(&girq->gi_isrc.isrc_cpu) - 1];
1873 desc.cmd_type = ITS_CMD_INV;
1874 /* The EventID sent to the device */
1875 desc.cmd_desc_inv.pid = girq->gi_id;
1876 desc.cmd_desc_inv.its_dev = its_dev;
1877 desc.cmd_desc_inv.col = col;
1879 its_cmd_send(dev, &desc);
1883 its_cmd_invall(device_t dev, struct its_col *col)
1885 struct its_cmd_desc desc;
1887 desc.cmd_type = ITS_CMD_INVALL;
1888 desc.cmd_desc_invall.col = col;
1890 its_cmd_send(dev, &desc);
1894 static device_probe_t gicv3_its_fdt_probe;
1895 static device_attach_t gicv3_its_fdt_attach;
1897 static device_method_t gicv3_its_fdt_methods[] = {
1898 /* Device interface */
1899 DEVMETHOD(device_probe, gicv3_its_fdt_probe),
1900 DEVMETHOD(device_attach, gicv3_its_fdt_attach),
1906 #define its_baseclasses its_fdt_baseclasses
1907 DEFINE_CLASS_1(its, gicv3_its_fdt_driver, gicv3_its_fdt_methods,
1908 sizeof(struct gicv3_its_softc), gicv3_its_driver);
1909 #undef its_baseclasses
1910 static devclass_t gicv3_its_fdt_devclass;
1912 EARLY_DRIVER_MODULE(its_fdt, gic, gicv3_its_fdt_driver,
1913 gicv3_its_fdt_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
1916 gicv3_its_fdt_probe(device_t dev)
1919 if (!ofw_bus_status_okay(dev))
1922 if (!ofw_bus_is_compatible(dev, "arm,gic-v3-its"))
1925 device_set_desc(dev, "ARM GIC Interrupt Translation Service");
1926 return (BUS_PROBE_DEFAULT);
1930 gicv3_its_fdt_attach(device_t dev)
1932 struct gicv3_its_softc *sc;
1936 sc = device_get_softc(dev);
1938 err = gicv3_its_attach(dev);
1942 /* Register this device as a interrupt controller */
1943 xref = OF_xref_from_node(ofw_bus_get_node(dev));
1944 sc->sc_pic = intr_pic_register(dev, xref);
1945 intr_pic_add_handler(device_get_parent(dev), sc->sc_pic,
1946 gicv3_its_intr, sc, sc->sc_irq_base, sc->sc_irq_length);
1948 /* Register this device to handle MSI interrupts */
1949 intr_msi_register(dev, xref);
1956 static device_probe_t gicv3_its_acpi_probe;
1957 static device_attach_t gicv3_its_acpi_attach;
1959 static device_method_t gicv3_its_acpi_methods[] = {
1960 /* Device interface */
1961 DEVMETHOD(device_probe, gicv3_its_acpi_probe),
1962 DEVMETHOD(device_attach, gicv3_its_acpi_attach),
1968 #define its_baseclasses its_acpi_baseclasses
1969 DEFINE_CLASS_1(its, gicv3_its_acpi_driver, gicv3_its_acpi_methods,
1970 sizeof(struct gicv3_its_softc), gicv3_its_driver);
1971 #undef its_baseclasses
1972 static devclass_t gicv3_its_acpi_devclass;
1974 EARLY_DRIVER_MODULE(its_acpi, gic, gicv3_its_acpi_driver,
1975 gicv3_its_acpi_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
1978 gicv3_its_acpi_probe(device_t dev)
1981 if (gic_get_bus(dev) != GIC_BUS_ACPI)
1984 if (gic_get_hw_rev(dev) < 3)
1987 device_set_desc(dev, "ARM GIC Interrupt Translation Service");
1988 return (BUS_PROBE_DEFAULT);
1992 gicv3_its_acpi_attach(device_t dev)
1994 struct gicv3_its_softc *sc;
1995 struct gic_v3_devinfo *di;
1998 sc = device_get_softc(dev);
2000 err = gicv3_its_attach(dev);
2004 di = device_get_ivars(dev);
2005 sc->sc_pic = intr_pic_register(dev, di->msi_xref);
2006 intr_pic_add_handler(device_get_parent(dev), sc->sc_pic,
2007 gicv3_its_intr, sc, sc->sc_irq_base, sc->sc_irq_length);
2009 /* Register this device to handle MSI interrupts */
2010 intr_msi_register(dev, di->msi_xref);