sys/arm64/arm64/identcpu.c

   1 /*-
   2  * Copyright (c) 2014 Andrew Turner
   3  * Copyright (c) 2014 The FreeBSD Foundation
   4  * All rights reserved.
   5  *
   6  * Portions of this software were developed by Semihalf
   7  * under sponsorship of the FreeBSD Foundation.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  */
  31
  32 #include <sys/cdefs.h>
  33 __FBSDID("$FreeBSD$");
  34
  35 #include <sys/param.h>
  36 #include <sys/kernel.h>
  37 #include <sys/pcpu.h>
  38 #include <sys/sbuf.h>
  39 #include <sys/smp.h>
  40 #include <sys/sysctl.h>
  41 #include <sys/systm.h>
  42
  43 #include <machine/atomic.h>
  44 #include <machine/cpu.h>
  45 #include <machine/cpufunc.h>
  46 #include <machine/undefined.h>
  47
  48 static int ident_lock;
  49
  50 char machine[] = "arm64";
  51
  52 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0,
  53     "Machine class");
  54
  55 static char cpu_model[64];
  56 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
  57         cpu_model, sizeof(cpu_model), "Machine model");
  58
  59 /*
  60  * Per-CPU affinity as provided in MPIDR_EL1
  61  * Indexed by CPU number in logical order selected by the system.
  62  * Relevant fields can be extracted using CPU_AFFn macros,
  63  * Aff3.Aff2.Aff1.Aff0 construct a unique CPU address in the system.
  64  *
  65  * Fields used by us:
  66  * Aff1 - Cluster number
  67  * Aff0 - CPU number in Aff1 cluster
  68  */
  69 uint64_t __cpu_affinity[MAXCPU];
  70 static u_int cpu_aff_levels;
  71
  72 struct cpu_desc {
  73         u_int           cpu_impl;
  74         u_int           cpu_part_num;
  75         u_int           cpu_variant;
  76         u_int           cpu_revision;
  77         const char      *cpu_impl_name;
  78         const char      *cpu_part_name;
  79
  80         uint64_t        mpidr;
  81         uint64_t        id_aa64afr0;
  82         uint64_t        id_aa64afr1;
  83         uint64_t        id_aa64dfr0;
  84         uint64_t        id_aa64dfr1;
  85         uint64_t        id_aa64isar0;
  86         uint64_t        id_aa64isar1;
  87         uint64_t        id_aa64mmfr0;
  88         uint64_t        id_aa64mmfr1;
  89         uint64_t        id_aa64mmfr2;
  90         uint64_t        id_aa64pfr0;
  91         uint64_t        id_aa64pfr1;
  92 };
  93
  94 struct cpu_desc cpu_desc[MAXCPU];
  95 struct cpu_desc user_cpu_desc;
  96 static u_int cpu_print_regs;
  97 #define PRINT_ID_AA64_AFR0      0x00000001
  98 #define PRINT_ID_AA64_AFR1      0x00000002
  99 #define PRINT_ID_AA64_DFR0      0x00000010
 100 #define PRINT_ID_AA64_DFR1      0x00000020
 101 #define PRINT_ID_AA64_ISAR0     0x00000100
 102 #define PRINT_ID_AA64_ISAR1     0x00000200
 103 #define PRINT_ID_AA64_MMFR0     0x00001000
 104 #define PRINT_ID_AA64_MMFR1     0x00002000
 105 #define PRINT_ID_AA64_MMFR2     0x00004000
 106 #define PRINT_ID_AA64_PFR0      0x00010000
 107 #define PRINT_ID_AA64_PFR1      0x00020000
 108
 109 struct cpu_parts {
 110         u_int           part_id;
 111         const char      *part_name;
 112 };
 113 #define CPU_PART_NONE   { 0, "Unknown Processor" }
 114
 115 struct cpu_implementers {
 116         u_int                   impl_id;
 117         const char              *impl_name;
 118         /*
 119          * Part number is implementation defined
 120          * so each vendor will have its own set of values and names.
 121          */
 122         const struct cpu_parts  *cpu_parts;
 123 };
 124 #define CPU_IMPLEMENTER_NONE    { 0, "Unknown Implementer", cpu_parts_none }
 125
 126 /*
 127  * Per-implementer table of (PartNum, CPU Name) pairs.
 128  */
 129 /* ARM Ltd. */
 130 static const struct cpu_parts cpu_parts_arm[] = {
 131         { CPU_PART_FOUNDATION, "Foundation-Model" },
 132         { CPU_PART_CORTEX_A35, "Cortex-A35" },
 133         { CPU_PART_CORTEX_A53, "Cortex-A53" },
 134         { CPU_PART_CORTEX_A55, "Cortex-A55" },
 135         { CPU_PART_CORTEX_A57, "Cortex-A57" },
 136         { CPU_PART_CORTEX_A72, "Cortex-A72" },
 137         { CPU_PART_CORTEX_A73, "Cortex-A73" },
 138         { CPU_PART_CORTEX_A75, "Cortex-A75" },
 139         CPU_PART_NONE,
 140 };
 141 /* Cavium */
 142 static const struct cpu_parts cpu_parts_cavium[] = {
 143         { CPU_PART_THUNDERX, "ThunderX" },
 144         { CPU_PART_THUNDERX2, "ThunderX2" },
 145         CPU_PART_NONE,
 146 };
 147
 148 /* Unknown */
 149 static const struct cpu_parts cpu_parts_none[] = {
 150         CPU_PART_NONE,
 151 };
 152
 153 /*
 154  * Implementers table.
 155  */
 156 const struct cpu_implementers cpu_implementers[] = {
 157         { CPU_IMPL_ARM,         "ARM",          cpu_parts_arm },
 158         { CPU_IMPL_BROADCOM,    "Broadcom",     cpu_parts_none },
 159         { CPU_IMPL_CAVIUM,      "Cavium",       cpu_parts_cavium },
 160         { CPU_IMPL_DEC,         "DEC",          cpu_parts_none },
 161         { CPU_IMPL_INFINEON,    "IFX",          cpu_parts_none },
 162         { CPU_IMPL_FREESCALE,   "Freescale",    cpu_parts_none },
 163         { CPU_IMPL_NVIDIA,      "NVIDIA",       cpu_parts_none },
 164         { CPU_IMPL_APM,         "APM",          cpu_parts_none },
 165         { CPU_IMPL_QUALCOMM,    "Qualcomm",     cpu_parts_none },
 166         { CPU_IMPL_MARVELL,     "Marvell",      cpu_parts_none },
 167         { CPU_IMPL_INTEL,       "Intel",        cpu_parts_none },
 168         CPU_IMPLEMENTER_NONE,
 169 };
 170
 171 #define MRS_TYPE_MASK           0xf
 172 #define MRS_INVALID             0
 173 #define MRS_EXACT               1
 174 #define MRS_EXACT_VAL(x)        (MRS_EXACT | ((x) << 4))
 175 #define MRS_EXACT_FIELD(x)      ((x) >> 4)
 176 #define MRS_LOWER               2
 177
 178 struct mrs_field {
 179         bool            sign;
 180         u_int           type;
 181         u_int           shift;
 182 };
 183
 184 #define MRS_FIELD(_sign, _type, _shift)                                 \
 185         {                                                               \
 186                 .sign = (_sign),                                        \
 187                 .type = (_type),                                        \
 188                 .shift = (_shift),                                      \
 189         }
 190
 191 #define MRS_FIELD_END   { .type = MRS_INVALID, }
 192
 193 static struct mrs_field id_aa64isar0_fields[] = {
 194         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_DP_SHIFT),
 195         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_SM4_SHIFT),
 196         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_SM3_SHIFT),
 197         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_SHA3_SHIFT),
 198         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_RDM_SHIFT),
 199         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_Atomic_SHIFT),
 200         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_CRC32_SHIFT),
 201         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_SHA2_SHIFT),
 202         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_SHA1_SHIFT),
 203         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_AES_SHIFT),
 204         MRS_FIELD_END,
 205 };
 206
 207 static struct mrs_field id_aa64isar1_fields[] = {
 208         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR1_GPI_SHIFT),
 209         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR1_GPA_SHIFT),
 210         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR1_LRCPC_SHIFT),
 211         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR1_FCMA_SHIFT),
 212         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR1_JSCVT_SHIFT),
 213         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR1_API_SHIFT),
 214         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR1_APA_SHIFT),
 215         MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR1_DPB_SHIFT),
 216         MRS_FIELD_END,
 217 };
 218
 219 static struct mrs_field id_aa64pfr0_fields[] = {
 220         MRS_FIELD(false, MRS_EXACT, ID_AA64PFR0_SVE_SHIFT),
 221         MRS_FIELD(false, MRS_EXACT, ID_AA64PFR0_RAS_SHIFT),
 222         MRS_FIELD(false, MRS_EXACT, ID_AA64PFR0_GIC_SHIFT),
 223         MRS_FIELD(true,  MRS_LOWER, ID_AA64PFR0_AdvSIMD_SHIFT),
 224         MRS_FIELD(true,  MRS_LOWER, ID_AA64PFR0_FP_SHIFT),
 225         MRS_FIELD(false, MRS_EXACT, ID_AA64PFR0_EL3_SHIFT),
 226         MRS_FIELD(false, MRS_EXACT, ID_AA64PFR0_EL2_SHIFT),
 227         MRS_FIELD(false, MRS_LOWER, ID_AA64PFR0_EL1_SHIFT),
 228         MRS_FIELD(false, MRS_LOWER, ID_AA64PFR0_EL0_SHIFT),
 229         MRS_FIELD_END,
 230 };
 231
 232 static struct mrs_field id_aa64dfr0_fields[] = {
 233         MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_PMSVer_SHIFT),
 234         MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_CTX_CMPs_SHIFT),
 235         MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_WRPs_SHIFT),
 236         MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_BRPs_SHIFT),
 237         MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_PMUVer_SHIFT),
 238         MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_TraceVer_SHIFT),
 239         MRS_FIELD(false, MRS_EXACT_VAL(0x6), ID_AA64DFR0_DebugVer_SHIFT),
 240         MRS_FIELD_END,
 241 };
 242
 243 struct mrs_user_reg {
 244         u_int           CRm;
 245         u_int           Op2;
 246         size_t          offset;
 247         struct mrs_field *fields;
 248 };
 249
 250 static struct mrs_user_reg user_regs[] = {
 251         {       /* id_aa64isar0_el1 */
 252                 .CRm = 6,
 253                 .Op2 = 0,
 254                 .offset = __offsetof(struct cpu_desc, id_aa64isar0),
 255                 .fields = id_aa64isar0_fields,
 256         },
 257         {       /* id_aa64isar1_el1 */
 258                 .CRm = 6,
 259                 .Op2 = 1,
 260                 .offset = __offsetof(struct cpu_desc, id_aa64isar1),
 261                 .fields = id_aa64isar1_fields,
 262         },
 263         {       /* id_aa64pfr0_el1 */
 264                 .CRm = 4,
 265                 .Op2 = 0,
 266                 .offset = __offsetof(struct cpu_desc, id_aa64pfr0),
 267                 .fields = id_aa64pfr0_fields,
 268         },
 269         {       /* id_aa64dfr0_el1 */
 270                 .CRm = 5,
 271                 .Op2 = 0,
 272                 .offset = __offsetof(struct cpu_desc, id_aa64dfr0),
 273                 .fields = id_aa64dfr0_fields,
 274         },
 275 };
 276
 277 #define CPU_DESC_FIELD(desc, idx)                                       \
 278     *(uint64_t *)((char *)&(desc) + user_regs[(idx)].offset)
 279
 280 static int
 281 user_mrs_handler(vm_offset_t va, uint32_t insn, struct trapframe *frame,
 282     uint32_t esr)
 283 {
 284         uint64_t value;
 285         int CRm, Op2, i, reg;
 286
 287         if ((insn & MRS_MASK) != MRS_VALUE)
 288                 return (0);
 289
 290         /*
 291          * We only emulate Op0 == 3, Op1 == 0, CRn == 0, CRm == {0, 4-7}.
 292          * These are in the EL1 CPU identification space.
 293          * CRm == 0 holds MIDR_EL1, MPIDR_EL1, and REVID_EL1.
 294          * CRm == {4-7} holds the ID_AA64 registers.
 295          *
 296          * For full details see the ARMv8 ARM (ARM DDI 0487C.a)
 297          * Table D9-2 System instruction encodings for non-Debug System
 298          * register accesses.
 299          */
 300         if (mrs_Op0(insn) != 3 || mrs_Op1(insn) != 0 || mrs_CRn(insn) != 0)
 301                 return (0);
 302
 303         CRm = mrs_CRm(insn);
 304         if (CRm > 7 || (CRm < 4 && CRm != 0))
 305                 return (0);
 306
 307         Op2 = mrs_Op2(insn);
 308         value = 0;
 309
 310         for (i = 0; i < nitems(user_regs); i++) {
 311                 if (user_regs[i].CRm == CRm && user_regs[i].Op2 == Op2) {
 312                         value = CPU_DESC_FIELD(user_cpu_desc, i);
 313                         break;
 314                 }
 315         }
 316
 317         if (CRm == 0) {
 318                 switch (Op2) {
 319                 case 0:
 320                         value = READ_SPECIALREG(midr_el1);
 321                         break;
 322                 case 5:
 323                         value = READ_SPECIALREG(mpidr_el1);
 324                         break;
 325                 case 6:
 326                         value = READ_SPECIALREG(revidr_el1);
 327                         break;
 328                 default:
 329                         return (0);
 330                 }
 331         }
 332
 333         /*
 334          * We will handle this instruction, move to the next so we
 335          * don't trap here again.
 336          */
 337         frame->tf_elr += INSN_SIZE;
 338
 339         reg = MRS_REGISTER(insn);
 340         /* If reg is 31 then write to xzr, i.e. do nothing */
 341         if (reg == 31)
 342                 return (1);
 343
 344         if (reg < nitems(frame->tf_x))
 345                 frame->tf_x[reg] = value;
 346         else if (reg == 30)
 347                 frame->tf_lr = value;
 348
 349         return (1);
 350 }
 351
 352 static void
 353 update_user_regs(u_int cpu)
 354 {
 355         struct mrs_field *fields;
 356         uint64_t cur, value;
 357         int i, j, cur_field, new_field;
 358
 359         for (i = 0; i < nitems(user_regs); i++) {
 360                 value = CPU_DESC_FIELD(cpu_desc[cpu], i);
 361                 if (cpu == 0)
 362                         cur = value;
 363                 else
 364                         cur = CPU_DESC_FIELD(user_cpu_desc, i);
 365
 366                 fields = user_regs[i].fields;
 367                 for (j = 0; fields[j].type != 0; j++) {
 368                         switch (fields[j].type & MRS_TYPE_MASK) {
 369                         case MRS_EXACT:
 370                                 cur &= ~(0xfu << fields[j].shift);
 371                                 cur |=
 372                                     (uint64_t)MRS_EXACT_FIELD(fields[j].type) <<
 373                                     fields[j].shift;
 374                                 break;
 375                         case MRS_LOWER:
 376                                 new_field = (value >> fields[j].shift) & 0xf;
 377                                 cur_field = (cur >> fields[j].shift) & 0xf;
 378                                 if ((fields[j].sign &&
 379                                      (int)new_field < (int)cur_field) ||
 380                                     (!fields[j].sign &&
 381                                      (u_int)new_field < (u_int)cur_field)) {
 382                                         cur &= ~(0xfu << fields[j].shift);
 383                                         cur |= new_field << fields[j].shift;
 384                                 }
 385                                 break;
 386                         default:
 387                                 panic("Invalid field type: %d", fields[j].type);
 388                         }
 389                 }
 390
 391                 CPU_DESC_FIELD(user_cpu_desc, i) = cur;
 392         }
 393 }
 394
 395 static void
 396 identify_cpu_sysinit(void *dummy __unused)
 397 {
 398         int cpu;
 399
 400         /* Create a user visible cpu description with safe values */
 401         memset(&user_cpu_desc, 0, sizeof(user_cpu_desc));
 402         /* Safe values for these registers */
 403         user_cpu_desc.id_aa64pfr0 = ID_AA64PFR0_AdvSIMD_NONE |
 404             ID_AA64PFR0_FP_NONE | ID_AA64PFR0_EL1_64 | ID_AA64PFR0_EL0_64;
 405         user_cpu_desc.id_aa64dfr0 = ID_AA64DFR0_DebugVer_8;
 406
 407
 408         CPU_FOREACH(cpu) {
 409                 print_cpu_features(cpu);
 410                 update_user_regs(cpu);
 411         }
 412
 413         install_undef_handler(true, user_mrs_handler);
 414 }
 415 SYSINIT(idenrity_cpu, SI_SUB_SMP, SI_ORDER_ANY, identify_cpu_sysinit, NULL);
 416
 417 void
 418 print_cpu_features(u_int cpu)
 419 {
 420         struct sbuf *sb;
 421         int printed;
 422
 423         sb = sbuf_new_auto();
 424         sbuf_printf(sb, "CPU%3d: %s %s r%dp%d", cpu,
 425             cpu_desc[cpu].cpu_impl_name, cpu_desc[cpu].cpu_part_name,
 426             cpu_desc[cpu].cpu_variant, cpu_desc[cpu].cpu_revision);
 427
 428         sbuf_cat(sb, " affinity:");
 429         switch(cpu_aff_levels) {
 430         default:
 431         case 4:
 432                 sbuf_printf(sb, " %2d", CPU_AFF3(cpu_desc[cpu].mpidr));
 433                 /* FALLTHROUGH */
 434         case 3:
 435                 sbuf_printf(sb, " %2d", CPU_AFF2(cpu_desc[cpu].mpidr));
 436                 /* FALLTHROUGH */
 437         case 2:
 438                 sbuf_printf(sb, " %2d", CPU_AFF1(cpu_desc[cpu].mpidr));
 439                 /* FALLTHROUGH */
 440         case 1:
 441         case 0: /* On UP this will be zero */
 442                 sbuf_printf(sb, " %2d", CPU_AFF0(cpu_desc[cpu].mpidr));
 443                 break;
 444         }
 445         sbuf_finish(sb);
 446         printf("%s\n", sbuf_data(sb));
 447         sbuf_clear(sb);
 448
 449         /*
 450          * There is a hardware errata where, if one CPU is performing a TLB
 451          * invalidation while another is performing a store-exclusive the
 452          * store-exclusive may return the wrong status. A workaround seems
 453          * to be to use an IPI to invalidate on each CPU, however given the
 454          * limited number of affected units (pass 1.1 is the evaluation
 455          * hardware revision), and the lack of information from Cavium
 456          * this has not been implemented.
 457          *
 458          * At the time of writing this the only information is from:
 459          * https://lkml.org/lkml/2016/8/4/722
 460          */
 461         /*
 462          * XXX: CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 on its own also
 463          * triggers on pass 2.0+.
 464          */
 465         if (cpu == 0 && CPU_VAR(PCPU_GET(midr)) == 0 &&
 466             CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1)
 467                 printf("WARNING: ThunderX Pass 1.1 detected.\nThis has known "
 468                     "hardware bugs that may cause the incorrect operation of "
 469                     "atomic operations.\n");
 470
 471         if (cpu != 0 && cpu_print_regs == 0)
 472                 return;
 473
 474 #define SEP_STR ((printed++) == 0) ? "" : ","
 475
 476         /* AArch64 Instruction Set Attribute Register 0 */
 477         if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR0) != 0) {
 478                 printed = 0;
 479                 sbuf_printf(sb, " Instruction Set Attributes 0 = <");
 480
 481                 switch (ID_AA64ISAR0_DP(cpu_desc[cpu].id_aa64isar0)) {
 482                 case ID_AA64ISAR0_DP_NONE:
 483                         break;
 484                 case ID_AA64ISAR0_DP_IMPL:
 485                         sbuf_printf(sb, "%sDotProd", SEP_STR);
 486                         break;
 487                 default:
 488                         sbuf_printf(sb, "%sUnknown DP", SEP_STR);
 489                         break;
 490                 }
 491
 492                 switch (ID_AA64ISAR0_SM4(cpu_desc[cpu].id_aa64isar0)) {
 493                 case ID_AA64ISAR0_SM4_NONE:
 494                         break;
 495                 case ID_AA64ISAR0_SM4_IMPL:
 496                         sbuf_printf(sb, "%sSM4", SEP_STR);
 497                         break;
 498                 default:
 499                         sbuf_printf(sb, "%sUnknown SM4", SEP_STR);
 500                         break;
 501                 }
 502
 503                 switch (ID_AA64ISAR0_SM3(cpu_desc[cpu].id_aa64isar0)) {
 504                 case ID_AA64ISAR0_SM3_NONE:
 505                         break;
 506                 case ID_AA64ISAR0_SM3_IMPL:
 507                         sbuf_printf(sb, "%sSM3", SEP_STR);
 508                         break;
 509                 default:
 510                         sbuf_printf(sb, "%sUnknown SM3", SEP_STR);
 511                         break;
 512                 }
 513
 514                 switch (ID_AA64ISAR0_SHA3(cpu_desc[cpu].id_aa64isar0)) {
 515                 case ID_AA64ISAR0_SHA3_NONE:
 516                         break;
 517                 case ID_AA64ISAR0_SHA3_IMPL:
 518                         sbuf_printf(sb, "%sSHA3", SEP_STR);
 519                         break;
 520                 default:
 521                         sbuf_printf(sb, "%sUnknown SHA3", SEP_STR);
 522                         break;
 523                 }
 524
 525                 switch (ID_AA64ISAR0_RDM(cpu_desc[cpu].id_aa64isar0)) {
 526                 case ID_AA64ISAR0_RDM_NONE:
 527                         break;
 528                 case ID_AA64ISAR0_RDM_IMPL:
 529                         sbuf_printf(sb, "%sRDM", SEP_STR);
 530                         break;
 531                 default:
 532                         sbuf_printf(sb, "%sUnknown RDM", SEP_STR);
 533                 }
 534
 535                 switch (ID_AA64ISAR0_Atomic(cpu_desc[cpu].id_aa64isar0)) {
 536                 case ID_AA64ISAR0_Atomic_NONE:
 537                         break;
 538                 case ID_AA64ISAR0_Atomic_IMPL:
 539                         sbuf_printf(sb, "%sAtomic", SEP_STR);
 540                         break;
 541                 default:
 542                         sbuf_printf(sb, "%sUnknown Atomic", SEP_STR);
 543                 }
 544
 545                 switch (ID_AA64ISAR0_CRC32(cpu_desc[cpu].id_aa64isar0)) {
 546                 case ID_AA64ISAR0_CRC32_NONE:
 547                         break;
 548                 case ID_AA64ISAR0_CRC32_BASE:
 549                         sbuf_printf(sb, "%sCRC32", SEP_STR);
 550                         break;
 551                 default:
 552                         sbuf_printf(sb, "%sUnknown CRC32", SEP_STR);
 553                         break;
 554                 }
 555
 556                 switch (ID_AA64ISAR0_SHA2(cpu_desc[cpu].id_aa64isar0)) {
 557                 case ID_AA64ISAR0_SHA2_NONE:
 558                         break;
 559                 case ID_AA64ISAR0_SHA2_BASE:
 560                         sbuf_printf(sb, "%sSHA2", SEP_STR);
 561                         break;
 562                 case ID_AA64ISAR0_SHA2_512:
 563                         sbuf_printf(sb, "%sSHA2+SHA512", SEP_STR);
 564                         break;
 565                 default:
 566                         sbuf_printf(sb, "%sUnknown SHA2", SEP_STR);
 567                         break;
 568                 }
 569
 570                 switch (ID_AA64ISAR0_SHA1(cpu_desc[cpu].id_aa64isar0)) {
 571                 case ID_AA64ISAR0_SHA1_NONE:
 572                         break;
 573                 case ID_AA64ISAR0_SHA1_BASE:
 574                         sbuf_printf(sb, "%sSHA1", SEP_STR);
 575                         break;
 576                 default:
 577                         sbuf_printf(sb, "%sUnknown SHA1", SEP_STR);
 578                         break;
 579                 }
 580
 581                 switch (ID_AA64ISAR0_AES(cpu_desc[cpu].id_aa64isar0)) {
 582                 case ID_AA64ISAR0_AES_NONE:
 583                         break;
 584                 case ID_AA64ISAR0_AES_BASE:
 585                         sbuf_printf(sb, "%sAES", SEP_STR);
 586                         break;
 587                 case ID_AA64ISAR0_AES_PMULL:
 588                         sbuf_printf(sb, "%sAES+PMULL", SEP_STR);
 589                         break;
 590                 default:
 591                         sbuf_printf(sb, "%sUnknown AES", SEP_STR);
 592                         break;
 593                 }
 594
 595                 if ((cpu_desc[cpu].id_aa64isar0 & ~ID_AA64ISAR0_MASK) != 0)
 596                         sbuf_printf(sb, "%s%#lx", SEP_STR,
 597                             cpu_desc[cpu].id_aa64isar0 & ~ID_AA64ISAR0_MASK);
 598
 599                 sbuf_finish(sb);
 600                 printf("%s>\n", sbuf_data(sb));
 601                 sbuf_clear(sb);
 602         }
 603
 604         /* AArch64 Instruction Set Attribute Register 1 */
 605         if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR1) != 0) {
 606                 printed = 0;
 607                 sbuf_printf(sb, " Instruction Set Attributes 1 = <");
 608
 609                 switch (ID_AA64ISAR1_GPI(cpu_desc[cpu].id_aa64isar1)) {
 610                 case ID_AA64ISAR1_GPI_NONE:
 611                         break;
 612                 case ID_AA64ISAR1_GPI_IMPL:
 613                         sbuf_printf(sb, "%sImpl GenericAuth", SEP_STR);
 614                         break;
 615                 default:
 616                         sbuf_printf(sb, "%sUnknown GenericAuth", SEP_STR);
 617                         break;
 618                 }
 619
 620                 switch (ID_AA64ISAR1_GPA(cpu_desc[cpu].id_aa64isar1)) {
 621                 case ID_AA64ISAR1_GPA_NONE:
 622                         break;
 623                 case ID_AA64ISAR1_GPA_IMPL:
 624                         sbuf_printf(sb, "%sPrince GenericAuth", SEP_STR);
 625                         break;
 626                 default:
 627                         sbuf_printf(sb, "%sUnknown GenericAuth", SEP_STR);
 628                         break;
 629                 }
 630
 631                 switch (ID_AA64ISAR1_LRCPC(cpu_desc[cpu].id_aa64isar1)) {
 632                 case ID_AA64ISAR1_LRCPC_NONE:
 633                         break;
 634                 case ID_AA64ISAR1_LRCPC_IMPL:
 635                         sbuf_printf(sb, "%sRCpc", SEP_STR);
 636                         break;
 637                 default:
 638                         sbuf_printf(sb, "%sUnknown RCpc", SEP_STR);
 639                         break;
 640                 }
 641
 642                 switch (ID_AA64ISAR1_FCMA(cpu_desc[cpu].id_aa64isar1)) {
 643                 case ID_AA64ISAR1_FCMA_NONE:
 644                         break;
 645                 case ID_AA64ISAR1_FCMA_IMPL:
 646                         sbuf_printf(sb, "%sFCMA", SEP_STR);
 647                         break;
 648                 default:
 649                         sbuf_printf(sb, "%sUnknown FCMA", SEP_STR);
 650                         break;
 651                 }
 652
 653                 switch (ID_AA64ISAR1_JSCVT(cpu_desc[cpu].id_aa64isar1)) {
 654                 case ID_AA64ISAR1_JSCVT_NONE:
 655                         break;
 656                 case ID_AA64ISAR1_JSCVT_IMPL:
 657                         sbuf_printf(sb, "%sJS Conv", SEP_STR);
 658                         break;
 659                 default:
 660                         sbuf_printf(sb, "%sUnknown JS Conv", SEP_STR);
 661                         break;
 662                 }
 663
 664                 switch (ID_AA64ISAR1_API(cpu_desc[cpu].id_aa64isar1)) {
 665                 case ID_AA64ISAR1_API_NONE:
 666                         break;
 667                 case ID_AA64ISAR1_API_IMPL:
 668                         sbuf_printf(sb, "%sImpl AddrAuth", SEP_STR);
 669                         break;
 670                 default:
 671                         sbuf_printf(sb, "%sUnknown Impl AddrAuth", SEP_STR);
 672                         break;
 673                 }
 674
 675                 switch (ID_AA64ISAR1_APA(cpu_desc[cpu].id_aa64isar1)) {
 676                 case ID_AA64ISAR1_APA_NONE:
 677                         break;
 678                 case ID_AA64ISAR1_APA_IMPL:
 679                         sbuf_printf(sb, "%sPrince AddrAuth", SEP_STR);
 680                         break;
 681                 default:
 682                         sbuf_printf(sb, "%sUnknown Prince AddrAuth", SEP_STR);
 683                         break;
 684                 }
 685
 686                 switch (ID_AA64ISAR1_DPB(cpu_desc[cpu].id_aa64isar1)) {
 687                 case ID_AA64ISAR1_DPB_NONE:
 688                         break;
 689                 case ID_AA64ISAR1_DPB_IMPL:
 690                         sbuf_printf(sb, "%sDC CVAP", SEP_STR);
 691                         break;
 692                 default:
 693                         sbuf_printf(sb, "%sUnknown DC CVAP", SEP_STR);
 694                         break;
 695                 }
 696
 697                 if ((cpu_desc[cpu].id_aa64isar1 & ~ID_AA64ISAR1_MASK) != 0)
 698                         sbuf_printf(sb, "%s%#lx", SEP_STR,
 699                             cpu_desc[cpu].id_aa64isar1 & ~ID_AA64ISAR1_MASK);
 700                 sbuf_finish(sb);
 701                 printf("%s>\n", sbuf_data(sb));
 702                 sbuf_clear(sb);
 703         }
 704
 705         /* AArch64 Processor Feature Register 0 */
 706         if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_PFR0) != 0) {
 707                 printed = 0;
 708                 sbuf_printf(sb, "         Processor Features 0 = <");
 709
 710                 switch (ID_AA64PFR0_SVE(cpu_desc[cpu].id_aa64pfr0)) {
 711                 case ID_AA64PFR0_SVE_NONE:
 712                         break;
 713                 case ID_AA64PFR0_SVE_IMPL:
 714                         sbuf_printf(sb, "%sSVE", SEP_STR);
 715                         break;
 716                 default:
 717                         sbuf_printf(sb, "%sUnknown SVE", SEP_STR);
 718                         break;
 719                 }
 720
 721                 switch (ID_AA64PFR0_RAS(cpu_desc[cpu].id_aa64pfr0)) {
 722                 case ID_AA64PFR0_RAS_NONE:
 723                         break;
 724                 case ID_AA64PFR0_RAS_V1:
 725                         sbuf_printf(sb, "%sRASv1", SEP_STR);
 726                         break;
 727                 default:
 728                         sbuf_printf(sb, "%sUnknown RAS", SEP_STR);
 729                         break;
 730                 }
 731
 732                 switch (ID_AA64PFR0_GIC(cpu_desc[cpu].id_aa64pfr0)) {
 733                 case ID_AA64PFR0_GIC_CPUIF_NONE:
 734                         break;
 735                 case ID_AA64PFR0_GIC_CPUIF_EN:
 736                         sbuf_printf(sb, "%sGIC", SEP_STR);
 737                         break;
 738                 default:
 739                         sbuf_printf(sb, "%sUnknown GIC interface", SEP_STR);
 740                         break;
 741                 }
 742
 743                 switch (ID_AA64PFR0_AdvSIMD(cpu_desc[cpu].id_aa64pfr0)) {
 744                 case ID_AA64PFR0_AdvSIMD_NONE:
 745                         break;
 746                 case ID_AA64PFR0_AdvSIMD_IMPL:
 747                         sbuf_printf(sb, "%sAdvSIMD", SEP_STR);
 748                         break;
 749                 case ID_AA64PFR0_AdvSIMD_HP:
 750                         sbuf_printf(sb, "%sAdvSIMD+HP", SEP_STR);
 751                         break;
 752                 default:
 753                         sbuf_printf(sb, "%sUnknown AdvSIMD", SEP_STR);
 754                         break;
 755                 }
 756
 757                 switch (ID_AA64PFR0_FP(cpu_desc[cpu].id_aa64pfr0)) {
 758                 case ID_AA64PFR0_FP_NONE:
 759                         break;
 760                 case ID_AA64PFR0_FP_IMPL:
 761                         sbuf_printf(sb, "%sFloat", SEP_STR);
 762                         break;
 763                 case ID_AA64PFR0_FP_HP:
 764                         sbuf_printf(sb, "%sFloat+HP", SEP_STR);
 765                         break;
 766                 default:
 767                         sbuf_printf(sb, "%sUnknown Float", SEP_STR);
 768                         break;
 769                 }
 770
 771                 switch (ID_AA64PFR0_EL3(cpu_desc[cpu].id_aa64pfr0)) {
 772                 case ID_AA64PFR0_EL3_NONE:
 773                         sbuf_printf(sb, "%sNo EL3", SEP_STR);
 774                         break;
 775                 case ID_AA64PFR0_EL3_64:
 776                         sbuf_printf(sb, "%sEL3", SEP_STR);
 777                         break;
 778                 case ID_AA64PFR0_EL3_64_32:
 779                         sbuf_printf(sb, "%sEL3 32", SEP_STR);
 780                         break;
 781                 default:
 782                         sbuf_printf(sb, "%sUnknown EL3", SEP_STR);
 783                         break;
 784                 }
 785
 786                 switch (ID_AA64PFR0_EL2(cpu_desc[cpu].id_aa64pfr0)) {
 787                 case ID_AA64PFR0_EL2_NONE:
 788                         sbuf_printf(sb, "%sNo EL2", SEP_STR);
 789                         break;
 790                 case ID_AA64PFR0_EL2_64:
 791                         sbuf_printf(sb, "%sEL2", SEP_STR);
 792                         break;
 793                 case ID_AA64PFR0_EL2_64_32:
 794                         sbuf_printf(sb, "%sEL2 32", SEP_STR);
 795                         break;
 796                 default:
 797                         sbuf_printf(sb, "%sUnknown EL2", SEP_STR);
 798                         break;
 799                 }
 800
 801                 switch (ID_AA64PFR0_EL1(cpu_desc[cpu].id_aa64pfr0)) {
 802                 case ID_AA64PFR0_EL1_64:
 803                         sbuf_printf(sb, "%sEL1", SEP_STR);
 804                         break;
 805                 case ID_AA64PFR0_EL1_64_32:
 806                         sbuf_printf(sb, "%sEL1 32", SEP_STR);
 807                         break;
 808                 default:
 809                         sbuf_printf(sb, "%sUnknown EL1", SEP_STR);
 810                         break;
 811                 }
 812
 813                 switch (ID_AA64PFR0_EL0(cpu_desc[cpu].id_aa64pfr0)) {
 814                 case ID_AA64PFR0_EL0_64:
 815                         sbuf_printf(sb, "%sEL0", SEP_STR);
 816                         break;
 817                 case ID_AA64PFR0_EL0_64_32:
 818                         sbuf_printf(sb, "%sEL0 32", SEP_STR);
 819                         break;
 820                 default:
 821                         sbuf_printf(sb, "%sUnknown EL0", SEP_STR);
 822                         break;
 823                 }
 824
 825                 if ((cpu_desc[cpu].id_aa64pfr0 & ~ID_AA64PFR0_MASK) != 0)
 826                         sbuf_printf(sb, "%s%#lx", SEP_STR,
 827                             cpu_desc[cpu].id_aa64pfr0 & ~ID_AA64PFR0_MASK);
 828
 829                 sbuf_finish(sb);
 830                 printf("%s>\n", sbuf_data(sb));
 831                 sbuf_clear(sb);
 832         }
 833
 834         /* AArch64 Processor Feature Register 1 */
 835         if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_PFR1) != 0) {
 836                 printf("         Processor Features 1 = <%#lx>\n",
 837                     cpu_desc[cpu].id_aa64pfr1);
 838         }
 839
 840         /* AArch64 Memory Model Feature Register 0 */
 841         if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR0) != 0) {
 842                 printed = 0;
 843                 sbuf_printf(sb, "      Memory Model Features 0 = <");
 844                 switch (ID_AA64MMFR0_TGran4(cpu_desc[cpu].id_aa64mmfr0)) {
 845                 case ID_AA64MMFR0_TGran4_NONE:
 846                         break;
 847                 case ID_AA64MMFR0_TGran4_IMPL:
 848                         sbuf_printf(sb, "%s4k Granule", SEP_STR);
 849                         break;
 850                 default:
 851                         sbuf_printf(sb, "%sUnknown 4k Granule", SEP_STR);
 852                         break;
 853                 }
 854
 855                 switch (ID_AA64MMFR0_TGran64(cpu_desc[cpu].id_aa64mmfr0)) {
 856                 case ID_AA64MMFR0_TGran64_NONE:
 857                         break;
 858                 case ID_AA64MMFR0_TGran64_IMPL:
 859                         sbuf_printf(sb, "%s64k Granule", SEP_STR);
 860                         break;
 861                 default:
 862                         sbuf_printf(sb, "%sUnknown 64k Granule", SEP_STR);
 863                         break;
 864                 }
 865
 866                 switch (ID_AA64MMFR0_TGran16(cpu_desc[cpu].id_aa64mmfr0)) {
 867                 case ID_AA64MMFR0_TGran16_NONE:
 868                         break;
 869                 case ID_AA64MMFR0_TGran16_IMPL:
 870                         sbuf_printf(sb, "%s16k Granule", SEP_STR);
 871                         break;
 872                 default:
 873                         sbuf_printf(sb, "%sUnknown 16k Granule", SEP_STR);
 874                         break;
 875                 }
 876
 877                 switch (ID_AA64MMFR0_BigEndEL0(cpu_desc[cpu].id_aa64mmfr0)) {
 878                 case ID_AA64MMFR0_BigEndEL0_FIXED:
 879                         break;
 880                 case ID_AA64MMFR0_BigEndEL0_MIXED:
 881                         sbuf_printf(sb, "%sEL0 MixEndian", SEP_STR);
 882                         break;
 883                 default:
 884                         sbuf_printf(sb, "%sUnknown EL0 Endian switching", SEP_STR);
 885                         break;
 886                 }
 887
 888                 switch (ID_AA64MMFR0_SNSMem(cpu_desc[cpu].id_aa64mmfr0)) {
 889                 case ID_AA64MMFR0_SNSMem_NONE:
 890                         break;
 891                 case ID_AA64MMFR0_SNSMem_DISTINCT:
 892                         sbuf_printf(sb, "%sS/NS Mem", SEP_STR);
 893                         break;
 894                 default:
 895                         sbuf_printf(sb, "%sUnknown S/NS Mem", SEP_STR);
 896                         break;
 897                 }
 898
 899                 switch (ID_AA64MMFR0_BigEnd(cpu_desc[cpu].id_aa64mmfr0)) {
 900                 case ID_AA64MMFR0_BigEnd_FIXED:
 901                         break;
 902                 case ID_AA64MMFR0_BigEnd_MIXED:
 903                         sbuf_printf(sb, "%sMixedEndian", SEP_STR);
 904                         break;
 905                 default:
 906                         sbuf_printf(sb, "%sUnknown Endian switching", SEP_STR);
 907                         break;
 908                 }
 909
 910                 switch (ID_AA64MMFR0_ASIDBits(cpu_desc[cpu].id_aa64mmfr0)) {
 911                 case ID_AA64MMFR0_ASIDBits_8:
 912                         sbuf_printf(sb, "%s8bit ASID", SEP_STR);
 913                         break;
 914                 case ID_AA64MMFR0_ASIDBits_16:
 915                         sbuf_printf(sb, "%s16bit ASID", SEP_STR);
 916                         break;
 917                 default:
 918                         sbuf_printf(sb, "%sUnknown ASID", SEP_STR);
 919                         break;
 920                 }
 921
 922                 switch (ID_AA64MMFR0_PARange(cpu_desc[cpu].id_aa64mmfr0)) {
 923                 case ID_AA64MMFR0_PARange_4G:
 924                         sbuf_printf(sb, "%s4GB PA", SEP_STR);
 925                         break;
 926                 case ID_AA64MMFR0_PARange_64G:
 927                         sbuf_printf(sb, "%s64GB PA", SEP_STR);
 928                         break;
 929                 case ID_AA64MMFR0_PARange_1T:
 930                         sbuf_printf(sb, "%s1TB PA", SEP_STR);
 931                         break;
 932                 case ID_AA64MMFR0_PARange_4T:
 933                         sbuf_printf(sb, "%s4TB PA", SEP_STR);
 934                         break;
 935                 case ID_AA64MMFR0_PARange_16T:
 936                         sbuf_printf(sb, "%s16TB PA", SEP_STR);
 937                         break;
 938                 case ID_AA64MMFR0_PARange_256T:
 939                         sbuf_printf(sb, "%s256TB PA", SEP_STR);
 940                         break;
 941                 case ID_AA64MMFR0_PARange_4P:
 942                         sbuf_printf(sb, "%s4PB PA", SEP_STR);
 943                         break;
 944                 default:
 945                         sbuf_printf(sb, "%sUnknown PA Range", SEP_STR);
 946                         break;
 947                 }
 948
 949                 if ((cpu_desc[cpu].id_aa64mmfr0 & ~ID_AA64MMFR0_MASK) != 0)
 950                         sbuf_printf(sb, "%s%#lx", SEP_STR,
 951                             cpu_desc[cpu].id_aa64mmfr0 & ~ID_AA64MMFR0_MASK);
 952                 sbuf_finish(sb);
 953                 printf("%s>\n", sbuf_data(sb));
 954                 sbuf_clear(sb);
 955         }
 956
 957         /* AArch64 Memory Model Feature Register 1 */
 958         if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR1) != 0) {
 959                 printed = 0;
 960                 sbuf_printf(sb, "      Memory Model Features 1 = <");
 961
 962                 switch (ID_AA64MMFR1_XNX(cpu_desc[cpu].id_aa64mmfr1)) {
 963                 case ID_AA64MMFR1_XNX_NONE:
 964                         break;
 965                 case ID_AA64MMFR1_XNX_IMPL:
 966                         sbuf_printf(sb, "%sEL2 XN", SEP_STR);
 967                         break;
 968                 default:
 969                         sbuf_printf(sb, "%sUnknown XNX", SEP_STR);
 970                         break;
 971                 }
 972
 973                 switch (ID_AA64MMFR1_SpecSEI(cpu_desc[cpu].id_aa64mmfr1)) {
 974                 case ID_AA64MMFR1_SpecSEI_NONE:
 975                         break;
 976                 case ID_AA64MMFR1_SpecSEI_IMPL:
 977                         sbuf_printf(sb, "%sSpecSEI", SEP_STR);
 978                         break;
 979                 default:
 980                         sbuf_printf(sb, "%sUnknown SpecSEI", SEP_STR);
 981                         break;
 982                 }
 983
 984                 switch (ID_AA64MMFR1_PAN(cpu_desc[cpu].id_aa64mmfr1)) {
 985                 case ID_AA64MMFR1_PAN_NONE:
 986                         break;
 987                 case ID_AA64MMFR1_PAN_IMPL:
 988                         sbuf_printf(sb, "%sPAN", SEP_STR);
 989                         break;
 990                 case ID_AA64MMFR1_PAN_ATS1E1:
 991                         sbuf_printf(sb, "%sPAN+AT", SEP_STR);
 992                         break;
 993                 default:
 994                         sbuf_printf(sb, "%sUnknown PAN", SEP_STR);
 995                         break;
 996                 }
 997
 998                 switch (ID_AA64MMFR1_LO(cpu_desc[cpu].id_aa64mmfr1)) {
 999                 case ID_AA64MMFR1_LO_NONE:
1000                         break;
1001                 case ID_AA64MMFR1_LO_IMPL:
1002                         sbuf_printf(sb, "%sLO", SEP_STR);
1003                         break;
1004                 default:
1005                         sbuf_printf(sb, "%sUnknown LO", SEP_STR);
1006                         break;
1007                 }
1008
1009                 switch (ID_AA64MMFR1_HPDS(cpu_desc[cpu].id_aa64mmfr1)) {
1010                 case ID_AA64MMFR1_HPDS_NONE:
1011                         break;
1012                 case ID_AA64MMFR1_HPDS_HPD:
1013                         sbuf_printf(sb, "%sHPDS", SEP_STR);
1014                         break;
1015                 case ID_AA64MMFR1_HPDS_TTPBHA:
1016                         sbuf_printf(sb, "%sTTPBHA", SEP_STR);
1017                         break;
1018                 default:
1019                         sbuf_printf(sb, "%sUnknown HPDS", SEP_STR);
1020                         break;
1021                 }
1022
1023                 switch (ID_AA64MMFR1_VH(cpu_desc[cpu].id_aa64mmfr1)) {
1024                 case ID_AA64MMFR1_VH_NONE:
1025                         break;
1026                 case ID_AA64MMFR1_VH_IMPL:
1027                         sbuf_printf(sb, "%sVHE", SEP_STR);
1028                         break;
1029                 default:
1030                         sbuf_printf(sb, "%sUnknown VHE", SEP_STR);
1031                         break;
1032                 }
1033
1034                 switch (ID_AA64MMFR1_VMIDBits(cpu_desc[cpu].id_aa64mmfr1)) {
1035                 case ID_AA64MMFR1_VMIDBits_8:
1036                         break;
1037                 case ID_AA64MMFR1_VMIDBits_16:
1038                         sbuf_printf(sb, "%s16 VMID bits", SEP_STR);
1039                         break;
1040                 default:
1041                         sbuf_printf(sb, "%sUnknown VMID bits", SEP_STR);
1042                         break;
1043                 }
1044
1045                 switch (ID_AA64MMFR1_HAFDBS(cpu_desc[cpu].id_aa64mmfr1)) {
1046                 case ID_AA64MMFR1_HAFDBS_NONE:
1047                         break;
1048                 case ID_AA64MMFR1_HAFDBS_AF:
1049                         sbuf_printf(sb, "%sAF", SEP_STR);
1050                         break;
1051                 case ID_AA64MMFR1_HAFDBS_AF_DBS:
1052                         sbuf_printf(sb, "%sAF+DBS", SEP_STR);
1053                         break;
1054                 default:
1055                         sbuf_printf(sb, "%sUnknown Hardware update AF/DBS", SEP_STR);
1056                         break;
1057                 }
1058
1059                 if ((cpu_desc[cpu].id_aa64mmfr1 & ~ID_AA64MMFR1_MASK) != 0)
1060                         sbuf_printf(sb, "%s%#lx", SEP_STR,
1061                             cpu_desc[cpu].id_aa64mmfr1 & ~ID_AA64MMFR1_MASK);
1062                 sbuf_finish(sb);
1063                 printf("%s>\n", sbuf_data(sb));
1064                 sbuf_clear(sb);
1065         }
1066
1067         /* AArch64 Memory Model Feature Register 2 */
1068         if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR2) != 0) {
1069                 printed = 0;
1070                 sbuf_printf(sb, "      Memory Model Features 2 = <");
1071
1072                 switch (ID_AA64MMFR2_NV(cpu_desc[cpu].id_aa64mmfr2)) {
1073                 case ID_AA64MMFR2_NV_NONE:
1074                         break;
1075                 case ID_AA64MMFR2_NV_IMPL:
1076                         sbuf_printf(sb, "%sNestedVirt", SEP_STR);
1077                         break;
1078                 default:
1079                         sbuf_printf(sb, "%sUnknown NestedVirt", SEP_STR);
1080                         break;
1081                 }
1082
1083                 switch (ID_AA64MMFR2_CCIDX(cpu_desc[cpu].id_aa64mmfr2)) {
1084                 case ID_AA64MMFR2_CCIDX_32:
1085                         sbuf_printf(sb, "%s32b CCIDX", SEP_STR);
1086                         break;
1087                 case ID_AA64MMFR2_CCIDX_64:
1088                         sbuf_printf(sb, "%s64b CCIDX", SEP_STR);
1089                         break;
1090                 default:
1091                         sbuf_printf(sb, "%sUnknown CCIDX", SEP_STR);
1092                         break;
1093                 }
1094
1095                 switch (ID_AA64MMFR2_VARange(cpu_desc[cpu].id_aa64mmfr2)) {
1096                 case ID_AA64MMFR2_VARange_48:
1097                         sbuf_printf(sb, "%s48b VA", SEP_STR);
1098                         break;
1099                 case ID_AA64MMFR2_VARange_52:
1100                         sbuf_printf(sb, "%s52b VA", SEP_STR);
1101                         break;
1102                 default:
1103                         sbuf_printf(sb, "%sUnknown VA Range", SEP_STR);
1104                         break;
1105                 }
1106
1107                 switch (ID_AA64MMFR2_IESB(cpu_desc[cpu].id_aa64mmfr2)) {
1108                 case ID_AA64MMFR2_IESB_NONE:
1109                         break;
1110                 case ID_AA64MMFR2_IESB_IMPL:
1111                         sbuf_printf(sb, "%sIESB", SEP_STR);
1112                         break;
1113                 default:
1114                         sbuf_printf(sb, "%sUnknown IESB", SEP_STR);
1115                         break;
1116                 }
1117
1118                 switch (ID_AA64MMFR2_LSM(cpu_desc[cpu].id_aa64mmfr2)) {
1119                 case ID_AA64MMFR2_LSM_NONE:
1120                         break;
1121                 case ID_AA64MMFR2_LSM_IMPL:
1122                         sbuf_printf(sb, "%sLSM", SEP_STR);
1123                         break;
1124                 default:
1125                         sbuf_printf(sb, "%sUnknown LSM", SEP_STR);
1126                         break;
1127                 }
1128
1129                 switch (ID_AA64MMFR2_UAO(cpu_desc[cpu].id_aa64mmfr2)) {
1130                 case ID_AA64MMFR2_UAO_NONE:
1131                         break;
1132                 case ID_AA64MMFR2_UAO_IMPL:
1133                         sbuf_printf(sb, "%sUAO", SEP_STR);
1134                         break;
1135                 default:
1136                         sbuf_printf(sb, "%sUnknown UAO", SEP_STR);
1137                         break;
1138                 }
1139
1140                 switch (ID_AA64MMFR2_CnP(cpu_desc[cpu].id_aa64mmfr2)) {
1141                 case ID_AA64MMFR2_CnP_NONE:
1142                         break;
1143                 case ID_AA64MMFR2_CnP_IMPL:
1144                         sbuf_printf(sb, "%sCnP", SEP_STR);
1145                         break;
1146                 default:
1147                         sbuf_printf(sb, "%sUnknown CnP", SEP_STR);
1148                         break;
1149                 }
1150
1151                 if ((cpu_desc[cpu].id_aa64mmfr2 & ~ID_AA64MMFR2_MASK) != 0)
1152                         sbuf_printf(sb, "%s%#lx", SEP_STR,
1153                             cpu_desc[cpu].id_aa64mmfr2 & ~ID_AA64MMFR2_MASK);
1154                 sbuf_finish(sb);
1155                 printf("%s>\n", sbuf_data(sb));
1156                 sbuf_clear(sb);
1157         }
1158
1159         /* AArch64 Debug Feature Register 0 */
1160         if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_DFR0) != 0) {
1161                 printed = 0;
1162                 sbuf_printf(sb, "             Debug Features 0 = <");
1163                 switch(ID_AA64DFR0_PMSVer(cpu_desc[cpu].id_aa64dfr0)) {
1164                 case ID_AA64DFR0_PMSVer_NONE:
1165                         break;
1166                 case ID_AA64DFR0_PMSVer_V1:
1167                         sbuf_printf(sb, "%sSPE v1", SEP_STR);
1168                         break;
1169                 default:
1170                         sbuf_printf(sb, "%sUnknown SPE", SEP_STR);
1171                         break;
1172                 }
1173
1174                 sbuf_printf(sb, "%s%lu CTX Breakpoints", SEP_STR,
1175                     ID_AA64DFR0_CTX_CMPs(cpu_desc[cpu].id_aa64dfr0));
1176
1177                 sbuf_printf(sb, "%s%lu Watchpoints", SEP_STR,
1178                     ID_AA64DFR0_WRPs(cpu_desc[cpu].id_aa64dfr0));
1179
1180                 sbuf_printf(sb, "%s%lu Breakpoints", SEP_STR,
1181                     ID_AA64DFR0_BRPs(cpu_desc[cpu].id_aa64dfr0));
1182
1183                 switch (ID_AA64DFR0_PMUVer(cpu_desc[cpu].id_aa64dfr0)) {
1184                 case ID_AA64DFR0_PMUVer_NONE:
1185                         break;
1186                 case ID_AA64DFR0_PMUVer_3:
1187                         sbuf_printf(sb, "%sPMUv3", SEP_STR);
1188                         break;
1189                 case ID_AA64DFR0_PMUVer_3_1:
1190                         sbuf_printf(sb, "%sPMUv3+16 bit evtCount", SEP_STR);
1191                         break;
1192                 case ID_AA64DFR0_PMUVer_IMPL:
1193                         sbuf_printf(sb, "%sImplementation defined PMU", SEP_STR);
1194                         break;
1195                 default:
1196                         sbuf_printf(sb, "%sUnknown PMU", SEP_STR);
1197                         break;
1198                 }
1199
1200                 switch (ID_AA64DFR0_TraceVer(cpu_desc[cpu].id_aa64dfr0)) {
1201                 case ID_AA64DFR0_TraceVer_NONE:
1202                         break;
1203                 case ID_AA64DFR0_TraceVer_IMPL:
1204                         sbuf_printf(sb, "%sTrace", SEP_STR);
1205                         break;
1206                 default:
1207                         sbuf_printf(sb, "%sUnknown Trace", SEP_STR);
1208                         break;
1209                 }
1210
1211                 switch (ID_AA64DFR0_DebugVer(cpu_desc[cpu].id_aa64dfr0)) {
1212                 case ID_AA64DFR0_DebugVer_8:
1213                         sbuf_printf(sb, "%sDebug v8", SEP_STR);
1214                         break;
1215                 case ID_AA64DFR0_DebugVer_8_VHE:
1216                         sbuf_printf(sb, "%sDebug v8+VHE", SEP_STR);
1217                         break;
1218                 case ID_AA64DFR0_DebugVer_8_2:
1219                         sbuf_printf(sb, "%sDebug v8.2", SEP_STR);
1220                         break;
1221                 default:
1222                         sbuf_printf(sb, "%sUnknown Debug", SEP_STR);
1223                         break;
1224                 }
1225
1226                 if (cpu_desc[cpu].id_aa64dfr0 & ~ID_AA64DFR0_MASK)
1227                         sbuf_printf(sb, "%s%#lx", SEP_STR,
1228                             cpu_desc[cpu].id_aa64dfr0 & ~ID_AA64DFR0_MASK);
1229                 sbuf_finish(sb);
1230                 printf("%s>\n", sbuf_data(sb));
1231                 sbuf_clear(sb);
1232         }
1233
1234         /* AArch64 Memory Model Feature Register 1 */
1235         if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_DFR1) != 0) {
1236                 printf("             Debug Features 1 = <%#lx>\n",
1237                     cpu_desc[cpu].id_aa64dfr1);
1238         }
1239
1240         /* AArch64 Auxiliary Feature Register 0 */
1241         if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_AFR0) != 0) {
1242                 printf("         Auxiliary Features 0 = <%#lx>\n",
1243                     cpu_desc[cpu].id_aa64afr0);
1244         }
1245
1246         /* AArch64 Auxiliary Feature Register 1 */
1247         if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_AFR1) != 0) {
1248                 printf("         Auxiliary Features 1 = <%#lx>\n",
1249                     cpu_desc[cpu].id_aa64afr1);
1250         }
1251
1252         sbuf_delete(sb);
1253         sb = NULL;
1254 #undef SEP_STR
1255 }
1256
1257 void
1258 identify_cpu(void)
1259 {
1260         u_int midr;
1261         u_int impl_id;
1262         u_int part_id;
1263         u_int cpu;
1264         size_t i;
1265         const struct cpu_parts *cpu_partsp = NULL;
1266
1267         cpu = PCPU_GET(cpuid);
1268         midr = get_midr();
1269
1270         /*
1271          * Store midr to pcpu to allow fast reading
1272          * from EL0, EL1 and assembly code.
1273          */
1274         PCPU_SET(midr, midr);
1275
1276         impl_id = CPU_IMPL(midr);
1277         for (i = 0; i < nitems(cpu_implementers); i++) {
1278                 if (impl_id == cpu_implementers[i].impl_id ||
1279                     cpu_implementers[i].impl_id == 0) {
1280                         cpu_desc[cpu].cpu_impl = impl_id;
1281                         cpu_desc[cpu].cpu_impl_name = cpu_implementers[i].impl_name;
1282                         cpu_partsp = cpu_implementers[i].cpu_parts;
1283                         break;
1284                 }
1285         }
1286
1287         part_id = CPU_PART(midr);
1288         for (i = 0; &cpu_partsp[i] != NULL; i++) {
1289                 if (part_id == cpu_partsp[i].part_id ||
1290                     cpu_partsp[i].part_id == 0) {
1291                         cpu_desc[cpu].cpu_part_num = part_id;
1292                         cpu_desc[cpu].cpu_part_name = cpu_partsp[i].part_name;
1293                         break;
1294                 }
1295         }
1296
1297         cpu_desc[cpu].cpu_revision = CPU_REV(midr);
1298         cpu_desc[cpu].cpu_variant = CPU_VAR(midr);
1299
1300         snprintf(cpu_model, sizeof(cpu_model), "%s %s r%dp%d",
1301             cpu_desc[cpu].cpu_impl_name, cpu_desc[cpu].cpu_part_name,
1302             cpu_desc[cpu].cpu_variant, cpu_desc[cpu].cpu_revision);
1303
1304         /* Save affinity for current CPU */
1305         cpu_desc[cpu].mpidr = get_mpidr();
1306         CPU_AFFINITY(cpu) = cpu_desc[cpu].mpidr & CPU_AFF_MASK;
1307
1308         cpu_desc[cpu].id_aa64dfr0 = READ_SPECIALREG(ID_AA64DFR0_EL1);
1309         cpu_desc[cpu].id_aa64dfr1 = READ_SPECIALREG(ID_AA64DFR1_EL1);
1310         cpu_desc[cpu].id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
1311         cpu_desc[cpu].id_aa64isar1 = READ_SPECIALREG(ID_AA64ISAR1_EL1);
1312         cpu_desc[cpu].id_aa64mmfr0 = READ_SPECIALREG(ID_AA64MMFR0_EL1);
1313         cpu_desc[cpu].id_aa64mmfr1 = READ_SPECIALREG(ID_AA64MMFR1_EL1);
1314         cpu_desc[cpu].id_aa64mmfr2 = READ_SPECIALREG(ID_AA64MMFR2_EL1);
1315         cpu_desc[cpu].id_aa64pfr0 = READ_SPECIALREG(ID_AA64PFR0_EL1);
1316         cpu_desc[cpu].id_aa64pfr1 = READ_SPECIALREG(ID_AA64PFR1_EL1);
1317
1318         if (cpu != 0) {
1319                 /*
1320                  * This code must run on one cpu at a time, but we are
1321                  * not scheduling on the current core so implement a
1322                  * simple spinlock.
1323                  */
1324                 while (atomic_cmpset_acq_int(&ident_lock, 0, 1) == 0)
1325                         __asm __volatile("wfe" ::: "memory");
1326
1327                 switch (cpu_aff_levels) {
1328                 case 0:
1329                         if (CPU_AFF0(cpu_desc[cpu].mpidr) !=
1330                             CPU_AFF0(cpu_desc[0].mpidr))
1331                                 cpu_aff_levels = 1;
1332                         /* FALLTHROUGH */
1333                 case 1:
1334                         if (CPU_AFF1(cpu_desc[cpu].mpidr) !=
1335                             CPU_AFF1(cpu_desc[0].mpidr))
1336                                 cpu_aff_levels = 2;
1337                         /* FALLTHROUGH */
1338                 case 2:
1339                         if (CPU_AFF2(cpu_desc[cpu].mpidr) !=
1340                             CPU_AFF2(cpu_desc[0].mpidr))
1341                                 cpu_aff_levels = 3;
1342                         /* FALLTHROUGH */
1343                 case 3:
1344                         if (CPU_AFF3(cpu_desc[cpu].mpidr) !=
1345                             CPU_AFF3(cpu_desc[0].mpidr))
1346                                 cpu_aff_levels = 4;
1347                         break;
1348                 }
1349
1350                 if (cpu_desc[cpu].id_aa64afr0 != cpu_desc[0].id_aa64afr0)
1351                         cpu_print_regs |= PRINT_ID_AA64_AFR0;
1352                 if (cpu_desc[cpu].id_aa64afr1 != cpu_desc[0].id_aa64afr1)
1353                         cpu_print_regs |= PRINT_ID_AA64_AFR1;
1354
1355                 if (cpu_desc[cpu].id_aa64dfr0 != cpu_desc[0].id_aa64dfr0)
1356                         cpu_print_regs |= PRINT_ID_AA64_DFR0;
1357                 if (cpu_desc[cpu].id_aa64dfr1 != cpu_desc[0].id_aa64dfr1)
1358                         cpu_print_regs |= PRINT_ID_AA64_DFR1;
1359
1360                 if (cpu_desc[cpu].id_aa64isar0 != cpu_desc[0].id_aa64isar0)
1361                         cpu_print_regs |= PRINT_ID_AA64_ISAR0;
1362                 if (cpu_desc[cpu].id_aa64isar1 != cpu_desc[0].id_aa64isar1)
1363                         cpu_print_regs |= PRINT_ID_AA64_ISAR1;
1364
1365                 if (cpu_desc[cpu].id_aa64mmfr0 != cpu_desc[0].id_aa64mmfr0)
1366                         cpu_print_regs |= PRINT_ID_AA64_MMFR0;
1367                 if (cpu_desc[cpu].id_aa64mmfr1 != cpu_desc[0].id_aa64mmfr1)
1368                         cpu_print_regs |= PRINT_ID_AA64_MMFR1;
1369                 if (cpu_desc[cpu].id_aa64mmfr2 != cpu_desc[0].id_aa64mmfr2)
1370                         cpu_print_regs |= PRINT_ID_AA64_MMFR2;
1371
1372                 if (cpu_desc[cpu].id_aa64pfr0 != cpu_desc[0].id_aa64pfr0)
1373                         cpu_print_regs |= PRINT_ID_AA64_PFR0;
1374                 if (cpu_desc[cpu].id_aa64pfr1 != cpu_desc[0].id_aa64pfr1)
1375                         cpu_print_regs |= PRINT_ID_AA64_PFR1;
1376
1377                 /* Wake up the other CPUs */
1378                 atomic_store_rel_int(&ident_lock, 0);
1379                 __asm __volatile("sev" ::: "memory");
1380         }
1381 }