2 * Copyright (c) 2012-2014 Andrew Turner
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include "opt_kstack_pages.h"
31 #include <sys/syscall.h>
32 #include <machine/asm.h>
33 #include <machine/armreg.h>
34 #include <machine/hypervisor.h>
35 #include <machine/param.h>
36 #include <machine/pte.h>
37 #include <machine/vm.h>
38 #include <machine/vmparam.h>
41 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
44 .set kernbase, KERNBASE
47 /* U-Boot booti related constants. */
48 #if defined(LINUX_BOOT_ABI)
49 #define FDT_MAGIC 0xEDFE0DD0 /* FDT blob Magic */
51 #ifndef UBOOT_IMAGE_OFFSET
52 #define UBOOT_IMAGE_OFFSET 0 /* Image offset from start of */
53 #endif /* 2 MiB page */
55 #ifndef UBOOT_IMAGE_SIZE /* Total size of image */
56 #define UBOOT_IMAGE_SIZE _end - _start
59 #ifndef UBOOT_IMAGE_FLAGS
60 #define UBOOT_IMAGE_FLAGS 0 /* LE kernel, unspecified */
61 #endif /* page size */
62 #endif /* defined(LINUX_BOOT_ABI) */
66 * MMU on with an identity map, or off
69 * We are loaded at a 2MiB aligned address
75 #if defined(LINUX_BOOT_ABI)
76 /* U-boot image header */
79 .quad UBOOT_IMAGE_OFFSET /* Image offset in 2 MiB page, LE */
80 .quad UBOOT_IMAGE_SIZE /* Image size, LE */
81 .quad UBOOT_IMAGE_FLAGS /* Flags for kernel. LE */
82 .quad 0 /* Reserved */
83 .quad 0 /* Reserved */
84 .quad 0 /* Reserved */
85 .long 0x644d5241 /* Magic "ARM\x64", LE */
86 .long 0 /* Reserved for PE COFF offset*/
88 #endif /* defined(LINUX_BOOT_ABI) */
94 * Disable the MMU. We may have entered the kernel with it on and
95 * will need to update the tables later. If this has been set up
96 * with anything other than a VA == PA map then this will fail,
97 * but in this case the code to find where we are running from
98 * would have also failed.
106 /* Set the context id */
107 msr contextidr_el1, xzr
109 /* Get the virt -> phys offset */
115 * x28 = Our physical load address
118 /* Create the page tables */
124 * x26 = Kernel L1 table
131 /* Jump to the virtual address space */
136 /* Set up the stack */
137 adr x25, initstack_end
139 sub sp, sp, #PCB_SIZE
149 /* Backup the module pointer */
152 /* Make the page table base a virtual address */
156 sub sp, sp, #BOOTPARAMS_SIZE
159 /* Degate the delda so it is VA -> PA */
162 str x1, [x0, #BP_MODULEP]
163 str x26, [x0, #BP_KERN_L1PT]
164 str x29, [x0, #BP_KERN_DELTA]
166 str x25, [x0, #BP_KERN_STACK]
167 str x24, [x0, #BP_KERN_L0PT]
168 str x23, [x0, #BP_BOOT_EL]
170 /* trace back starts here */
172 /* Branch to C code */
176 /* We should not get here */
189 * mpentry(unsigned long)
191 * Called by a core when it is being brought online.
192 * The data in x0 is passed straight to init_secondary.
195 /* Disable interrupts */
201 /* Set the context id */
202 msr contextidr_el1, xzr
204 /* Load the kernel page table */
205 adr x24, pagetable_l0_ttbr1
206 /* Load the identity page table */
207 adr x27, pagetable_l0_ttbr0
212 /* Jump to the virtual address space */
213 ldr x15, =mp_virtdone
217 /* Start using the AP boot stack */
226 * If we are started in EL2, configure the required hypervisor
227 * registers and drop to EL1.
236 /* Configure the Hypervisor */
240 /* Load the Virtualization Process ID Register */
244 /* Load the Virtualization Multiprocess ID Register */
248 /* Set the bits that need to be 1 in sctlr_el1 */
252 /* Don't trap to EL2 for exceptions */
256 /* Don't trap to EL2 for CP15 traps */
259 /* Enable access to the physical timers at EL1 */
261 orr x2, x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN)
264 /* Set the counter offset to a known value */
267 /* Hypervisor trap functions */
271 mov x2, #(PSR_F | PSR_I | PSR_A | PSR_D | PSR_M_EL1h)
274 /* Configure GICv3 CPU interface */
275 mrs x2, id_aa64pfr0_el1
276 /* Extract GIC bits from the register */
277 ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS
278 /* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */
279 cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT)
283 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */
284 orr x2, x2, #ICC_SRE_EL2_SRE /* Enable system registers */
288 /* Set the address to return to our return address */
304 VECT_EMPTY /* Synchronous EL2t */
305 VECT_EMPTY /* IRQ EL2t */
306 VECT_EMPTY /* FIQ EL2t */
307 VECT_EMPTY /* Error EL2t */
309 VECT_EMPTY /* Synchronous EL2h */
310 VECT_EMPTY /* IRQ EL2h */
311 VECT_EMPTY /* FIQ EL2h */
312 VECT_EMPTY /* Error EL2h */
314 VECT_EMPTY /* Synchronous 64-bit EL1 */
315 VECT_EMPTY /* IRQ 64-bit EL1 */
316 VECT_EMPTY /* FIQ 64-bit EL1 */
317 VECT_EMPTY /* Error 64-bit EL1 */
319 VECT_EMPTY /* Synchronous 32-bit EL1 */
320 VECT_EMPTY /* IRQ 32-bit EL1 */
321 VECT_EMPTY /* FIQ 32-bit EL1 */
322 VECT_EMPTY /* Error 32-bit EL1 */
325 * Get the delta between the physical address we were loaded to and the
326 * virtual address we expect to run from. This is used when building the
327 * initial page table.
330 /* Load the physical address of virt_map */
332 /* Load the virtual address of virt_map stored in virt_map */
334 /* Find PA - VA as PA' = VA' - VA + PA = VA' + (PA - VA) = VA' + x29 */
336 /* Find the load address for the kernel */
346 * This builds the page tables containing the identity map, and the kernel
350 * We were loaded to an address that is on a 2MiB boundary
351 * All the memory must not cross a 1GiB boundaty
352 * x28 contains the physical address we were loaded from
354 * TODO: This is out of date.
355 * There are at least 5 pages before that address for the page tables
356 * The pages used are:
357 * - The Kernel L2 table
358 * - The Kernel L1 table
359 * - The Kernel L0 table (TTBR1)
360 * - The identity (PA = VA) L1 table
361 * - The identity (PA = VA) L0 table (TTBR0)
362 * - The DMAP L1 tables
365 /* Save the Link register */
368 /* Clean the page table */
371 adr x27, pagetable_end
373 stp xzr, xzr, [x6], #16
374 stp xzr, xzr, [x6], #16
375 stp xzr, xzr, [x6], #16
376 stp xzr, xzr, [x6], #16
381 * Build the TTBR1 maps.
384 /* Find the size of the kernel */
387 #if defined(LINUX_BOOT_ABI)
388 /* X19 is used as 'map FDT data' flag */
391 /* No modules or FDT pointer ? */
394 /* Test if modulep points to modules descriptor or to FDT */
401 /* Booted with modules pointer */
402 /* Find modulep - begin */
404 /* Add two 2MiB pages for the module data and round up */
405 ldr x7, =(3 * L2_SIZE - 1)
409 #if defined(LINUX_BOOT_ABI)
411 /* Booted by U-Boot booti with FDT data */
412 /* Set 'map FDT data' flag */
416 /* Booted by U-Boot booti without FTD data */
417 /* Find the end - begin */
422 * Add one 2MiB page for copy of FDT data (maximum FDT size),
423 * one for metadata and round up
425 ldr x7, =(3 * L2_SIZE - 1)
430 /* Get the number of l2 pages to allocate, rounded down */
431 lsr x10, x8, #(L2_SHIFT)
433 /* Create the kernel space L2 table */
435 mov x7, #VM_MEMATTR_WRITE_BACK
436 mov x8, #(KERNBASE & L2_BLOCK_MASK)
438 bl build_l2_block_pagetable
440 /* Move to the l1 table */
441 add x26, x26, #PAGE_SIZE
443 /* Link the l1 -> l2 table */
448 /* Move to the l0 table */
449 add x24, x26, #PAGE_SIZE
451 /* Link the l0 -> l1 table */
457 /* Link the DMAP tables */
458 ldr x8, =DMAP_MIN_ADDRESS
459 adr x9, pagetable_dmap;
460 mov x10, #DMAP_TABLES
464 * Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_S1_nG.
465 * They are only needed early on, so the VA = PA map is uncached.
467 add x27, x24, #PAGE_SIZE
469 mov x6, x27 /* The initial page table */
470 #if defined(SOCDEV_PA) && defined(SOCDEV_VA)
471 /* Create a table for the UART */
472 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_DEVICE))
473 mov x8, #(SOCDEV_VA) /* VA start */
474 mov x9, #(SOCDEV_PA) /* PA start */
476 bl build_l1_block_pagetable
479 #if defined(LINUX_BOOT_ABI)
483 /* Create the identity mapping for FDT data (2 MiB max) */
484 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE))
486 mov x8, x0 /* VA start (== PA start) */
488 bl build_l1_block_pagetable
493 /* Create the VA = PA map */
494 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE))
496 mov x8, x9 /* VA start (== PA start) */
498 bl build_l1_block_pagetable
500 /* Move to the l0 table */
501 add x27, x27, #PAGE_SIZE
503 /* Link the l0 -> l1 table */
509 /* Restore the Link register */
514 * Builds an L0 -> L1 table descriptor
516 * This is a link for a 512GiB block of memory with up to 1GiB regions mapped
517 * within it by build_l1_block_pagetable.
520 * x8 = Virtual Address
521 * x9 = L1 PA (trashed)
523 * x11, x12 and x13 are trashed
527 * Link an L0 -> L1 table entry.
529 /* Find the table index */
530 lsr x11, x8, #L0_SHIFT
531 and x11, x11, #L0_ADDR_MASK
533 /* Build the L0 block entry */
536 /* Only use the output address bits */
537 lsr x9, x9, #PAGE_SHIFT
538 1: orr x13, x12, x9, lsl #PAGE_SHIFT
540 /* Store the entry */
541 str x13, [x6, x11, lsl #3]
551 * Builds an L1 -> L2 table descriptor
553 * This is a link for a 1GiB block of memory with up to 2MiB regions mapped
554 * within it by build_l2_block_pagetable.
557 * x8 = Virtual Address
558 * x9 = L2 PA (trashed)
559 * x11, x12 and x13 are trashed
563 * Link an L1 -> L2 table entry.
565 /* Find the table index */
566 lsr x11, x8, #L1_SHIFT
567 and x11, x11, #Ln_ADDR_MASK
569 /* Build the L1 block entry */
572 /* Only use the output address bits */
573 lsr x9, x9, #PAGE_SHIFT
574 orr x13, x12, x9, lsl #PAGE_SHIFT
576 /* Store the entry */
577 str x13, [x6, x11, lsl #3]
582 * Builds count 1 GiB page table entry
584 * x7 = Variable lower block attributes
586 * x9 = PA start (trashed)
588 * x11, x12 and x13 are trashed
590 build_l1_block_pagetable:
592 * Build the L1 table entry.
594 /* Find the table index */
595 lsr x11, x8, #L1_SHIFT
596 and x11, x11, #Ln_ADDR_MASK
598 /* Build the L1 block entry */
599 orr x12, x7, #L1_BLOCK
600 orr x12, x12, #(ATTR_AF)
602 orr x12, x12, ATTR_SH(ATTR_SH_IS)
605 /* Only use the output address bits */
606 lsr x9, x9, #L1_SHIFT
608 /* Set the physical address for this virtual address */
609 1: orr x13, x12, x9, lsl #L1_SHIFT
611 /* Store the entry */
612 str x13, [x6, x11, lsl #3]
622 * Builds count 2 MiB page table entry
624 * x7 = Type (0 = Device, 1 = Normal)
626 * x9 = PA start (trashed)
628 * x11, x12 and x13 are trashed
630 build_l2_block_pagetable:
632 * Build the L2 table entry.
634 /* Find the table index */
635 lsr x11, x8, #L2_SHIFT
636 and x11, x11, #Ln_ADDR_MASK
638 /* Build the L2 block entry */
640 orr x12, x12, #L2_BLOCK
641 orr x12, x12, #(ATTR_AF)
642 orr x12, x12, #(ATTR_S1_UXN)
644 orr x12, x12, ATTR_SH(ATTR_SH_IS)
647 /* Only use the output address bits */
648 lsr x9, x9, #L2_SHIFT
650 /* Set the physical address for this virtual address */
651 1: orr x13, x12, x9, lsl #L2_SHIFT
653 /* Store the entry */
654 str x13, [x6, x11, lsl #3]
666 /* Load the exception vectors */
667 ldr x2, =exception_vectors
670 /* Load ttbr0 and ttbr1 */
675 /* Clear the Monitor Debug System control register */
678 /* Invalidate the TLB */
685 * Setup TCR according to the PARange and ASIDBits fields
686 * from ID_AA64MMFR0_EL1 and the HAFDBS field from the
687 * ID_AA64MMFR1_EL1. More precisely, set TCR_EL1.AS
688 * to 1 only if the ASIDBits field equals 0b0010.
691 mrs x3, id_aa64mmfr0_el1
693 /* Copy the bottom 3 bits from id_aa64mmfr0_el1 into TCR.IPS */
694 bfi x2, x3, #(TCR_IPS_SHIFT), #(TCR_IPS_WIDTH)
695 and x3, x3, #(ID_AA64MMFR0_ASIDBits_MASK)
697 /* Check if the HW supports 16 bit ASIDS */
698 cmp x3, #(ID_AA64MMFR0_ASIDBits_16)
699 /* If so x3 == 1, else x3 == 0 */
701 /* Set TCR.AS with x3 */
702 bfi x2, x3, #(TCR_ASID_SHIFT), #(TCR_ASID_WIDTH)
705 * Check if the HW supports access flag and dirty state updates,
706 * and set TCR_EL1.HA and TCR_EL1.HD accordingly.
708 mrs x3, id_aa64mmfr1_el1
709 and x3, x3, #(ID_AA64MMFR1_HAFDBS_MASK)
712 orr x2, x2, #(TCR_HA)
717 orr x2, x2, #(TCR_HA | TCR_HD)
727 bic x1, x1, x3 /* Clear the required bits */
728 orr x1, x1, x2 /* Set the required bits */
736 .quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE) | \
737 MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) | \
738 MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | \
739 MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH)
741 .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG1_4K | \
742 TCR_CACHE_ATTRS | TCR_SMP_ATTRS)
745 .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \
746 SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \
747 SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \
748 SCTLR_M | SCTLR_CP15BEN)
751 .quad (SCTLR_EE | SCTLR_EOE | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \
758 //.section .init_pagetable
759 .align 12 /* 4KiB aligned */
761 * 3 initial tables (in the following order):
762 * L2 for kernel (High addresses)
764 * L1 for user (Low addresses)
777 .globl pagetable_dmap
779 .space PAGE_SIZE * DMAP_TABLES
787 .quad pagetable /* XXX: Keep page tables VA */
791 .space (PAGE_SIZE * KSTACK_PAGES)
800 mov x8, #SYS_sigreturn
803 /* sigreturn failed, exit */
809 /* This may be copied to the stack, keep it 16-byte aligned */
817 .quad esigcode - sigcode
819 ENTRY(aarch32_sigcode)
820 .word 0xe1a0000d // mov r0, sp
821 .word 0xe2800040 // add r0, r0, #SIGF_UC
822 .word 0xe59f700c // ldr r7, [pc, #12]
823 .word 0xef000000 // swi #0
824 .word 0xe59f7008 // ldr r7, [pc, #8]
825 .word 0xef000000 // swi #0
826 .word 0xeafffffa // b . - 16
833 .global sz_aarch32_sigcode
835 .quad aarch32_esigcode - aarch32_sigcode