2 * Copyright (c) 2012-2014 Andrew Turner
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include "opt_kstack_pages.h"
31 #include <sys/syscall.h>
32 #include <machine/asm.h>
33 #include <machine/armreg.h>
34 #include <machine/hypervisor.h>
35 #include <machine/param.h>
36 #include <machine/pte.h>
37 #include <machine/vm.h>
38 #include <machine/vmparam.h>
43 .set kernbase, KERNBASE
47 * MMU on with an identity map, or off
50 * We are loaded at a 2MiB aligned address
58 * Disable the MMU. We may have entered the kernel with it on and
59 * will need to update the tables later. If this has been set up
60 * with anything other than a VA == PA map then this will fail,
61 * but in this case the code to find where we are running from
62 * would have also failed.
70 /* Set the context id */
71 msr contextidr_el1, xzr
73 /* Get the virt -> phys offset */
79 * x28 = Our physical load address
82 /* Create the page tables */
88 * x26 = Kernel L1 table
95 /* Load the new ttbr0 pagetable */
96 adrp x27, pagetable_l0_ttbr0
97 add x27, x27, :lo12:pagetable_l0_ttbr0
99 /* Jump to the virtual address space */
104 /* Set up the stack */
105 adrp x25, initstack_end
106 add x25, x25, :lo12:initstack_end
108 sub sp, sp, #PCB_SIZE
118 #if defined(PERTHREAD_SSP)
119 /* Set sp_el0 to the boot canary for early per-thread SSP to work */
120 adrp x15, boot_canary
121 add x15, x15, :lo12:boot_canary
125 /* Backup the module pointer */
128 /* Make the page table base a virtual address */
132 sub sp, sp, #BOOTPARAMS_SIZE
135 /* Degate the delda so it is VA -> PA */
138 str x1, [x0, #BP_MODULEP]
139 str x26, [x0, #BP_KERN_L1PT]
140 str x29, [x0, #BP_KERN_DELTA]
142 add x25, x25, :lo12:initstack
143 str x25, [x0, #BP_KERN_STACK]
144 str x24, [x0, #BP_KERN_L0PT]
145 str x27, [x0, #BP_KERN_TTBR0]
146 str x23, [x0, #BP_BOOT_EL]
148 /* trace back starts here */
150 /* Branch to C code */
152 /* We are done with the boot params */
153 add sp, sp, #BOOTPARAMS_SIZE
156 /* We should not get here */
170 * mpentry(unsigned long)
172 * Called by a core when it is being brought online.
173 * The data in x0 is passed straight to init_secondary.
176 /* Disable interrupts */
177 msr daifset, #DAIF_INTR
182 /* Set the context id */
183 msr contextidr_el1, xzr
185 /* Load the kernel page table */
186 adrp x24, pagetable_l0_ttbr1
187 add x24, x24, :lo12:pagetable_l0_ttbr1
188 /* Load the identity page table */
189 adrp x27, pagetable_l0_ttbr0_boostrap
190 add x27, x27, :lo12:pagetable_l0_ttbr0_boostrap
195 /* Load the new ttbr0 pagetable */
196 adrp x27, pagetable_l0_ttbr0
197 add x27, x27, :lo12:pagetable_l0_ttbr0
199 /* Jump to the virtual address space */
200 ldr x15, =mp_virtdone
204 /* Start using the AP boot stack */
209 #if defined(PERTHREAD_SSP)
210 /* Set sp_el0 to the boot canary for early per-thread SSP to work */
211 adrp x15, boot_canary
212 add x15, x15, :lo12:boot_canary
216 /* Load the kernel ttbr0 pagetable */
220 /* Invalidate the TLB */
230 * If we are started in EL2, configure the required hypervisor
231 * registers and drop to EL1.
240 /* Configure the Hypervisor */
244 /* Load the Virtualization Process ID Register */
248 /* Load the Virtualization Multiprocess ID Register */
252 /* Set the bits that need to be 1 in sctlr_el1 */
256 /* Don't trap to EL2 for exceptions */
260 /* Don't trap to EL2 for CP15 traps */
263 /* Enable access to the physical timers at EL1 */
265 orr x2, x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN)
268 /* Set the counter offset to a known value */
271 /* Hypervisor trap functions */
273 add x2, x2, :lo12:hyp_vectors
276 mov x2, #(PSR_F | PSR_I | PSR_A | PSR_D | PSR_M_EL1h)
279 /* Configure GICv3 CPU interface */
280 mrs x2, id_aa64pfr0_el1
281 /* Extract GIC bits from the register */
282 ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS
283 /* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */
284 cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT)
288 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */
289 orr x2, x2, #ICC_SRE_EL2_SRE /* Enable system registers */
293 /* Set the address to return to our return address */
310 VECT_EMPTY /* Synchronous EL2t */
311 VECT_EMPTY /* IRQ EL2t */
312 VECT_EMPTY /* FIQ EL2t */
313 VECT_EMPTY /* Error EL2t */
315 VECT_EMPTY /* Synchronous EL2h */
316 VECT_EMPTY /* IRQ EL2h */
317 VECT_EMPTY /* FIQ EL2h */
318 VECT_EMPTY /* Error EL2h */
320 VECT_EMPTY /* Synchronous 64-bit EL1 */
321 VECT_EMPTY /* IRQ 64-bit EL1 */
322 VECT_EMPTY /* FIQ 64-bit EL1 */
323 VECT_EMPTY /* Error 64-bit EL1 */
325 VECT_EMPTY /* Synchronous 32-bit EL1 */
326 VECT_EMPTY /* IRQ 32-bit EL1 */
327 VECT_EMPTY /* FIQ 32-bit EL1 */
328 VECT_EMPTY /* Error 32-bit EL1 */
331 * Get the delta between the physical address we were loaded to and the
332 * virtual address we expect to run from. This is used when building the
333 * initial page table.
335 LENTRY(get_virt_delta)
336 /* Load the physical address of virt_map */
338 add x29, x29, :lo12:virt_map
339 /* Load the virtual address of virt_map stored in virt_map */
341 /* Find PA - VA as PA' = VA' - VA + PA = VA' + (PA - VA) = VA' + x29 */
343 /* Find the load address for the kernel */
354 * This builds the page tables containing the identity map, and the kernel
358 * We were loaded to an address that is on a 2MiB boundary
359 * All the memory must not cross a 1GiB boundaty
360 * x28 contains the physical address we were loaded from
362 * TODO: This is out of date.
363 * There are at least 5 pages before that address for the page tables
364 * The pages used are:
365 * - The Kernel L2 table
366 * - The Kernel L1 table
367 * - The Kernel L0 table (TTBR1)
368 * - The identity (PA = VA) L1 table
369 * - The identity (PA = VA) L0 table (TTBR0)
371 LENTRY(create_pagetables)
372 /* Save the Link register */
375 /* Clean the page table */
377 add x6, x6, :lo12:pagetable
379 adrp x27, pagetable_end
380 add x27, x27, :lo12:pagetable_end
382 stp xzr, xzr, [x6], #16
383 stp xzr, xzr, [x6], #16
384 stp xzr, xzr, [x6], #16
385 stp xzr, xzr, [x6], #16
390 * Build the TTBR1 maps.
393 /* Find the size of the kernel */
396 #if defined(LINUX_BOOT_ABI)
397 /* X19 is used as 'map FDT data' flag */
400 /* No modules or FDT pointer ? */
404 * Test if x0 points to modules descriptor(virtual address) or
405 * to FDT (physical address)
407 cmp x0, x6 /* x6 is #(KERNBASE) */
411 /* Booted with modules pointer */
412 /* Find modulep - begin */
414 /* Add two 2MiB pages for the module data and round up */
415 ldr x7, =(3 * L2_SIZE - 1)
419 #if defined(LINUX_BOOT_ABI)
421 /* Booted by U-Boot booti with FDT data */
422 /* Set 'map FDT data' flag */
426 /* Booted by U-Boot booti without FTD data */
427 /* Find the end - begin */
432 * Add one 2MiB page for copy of FDT data (maximum FDT size),
433 * one for metadata and round up
435 ldr x7, =(3 * L2_SIZE - 1)
440 /* Get the number of l2 pages to allocate, rounded down */
441 lsr x10, x8, #(L2_SHIFT)
443 /* Create the kernel space L2 table */
445 mov x7, #VM_MEMATTR_WRITE_BACK
446 mov x8, #(KERNBASE & L2_BLOCK_MASK)
448 bl build_l2_block_pagetable
450 /* Move to the l1 table */
451 add x26, x26, #PAGE_SIZE
453 /* Link the l1 -> l2 table */
458 /* Move to the l0 table */
459 add x24, x26, #PAGE_SIZE
461 /* Link the l0 -> l1 table */
468 * Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_S1_nG.
469 * They are only needed early on, so the VA = PA map is uncached.
471 add x27, x24, #PAGE_SIZE
473 mov x6, x27 /* The initial page table */
474 #if defined(SOCDEV_PA) && defined(SOCDEV_VA)
475 /* Create a table for the UART */
476 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_DEVICE))
477 mov x8, #(SOCDEV_VA) /* VA start */
478 mov x9, #(SOCDEV_PA) /* PA start */
480 bl build_l1_block_pagetable
483 #if defined(LINUX_BOOT_ABI)
487 /* Create the identity mapping for FDT data (2 MiB max) */
488 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK))
490 mov x8, x0 /* VA start (== PA start) */
492 bl build_l1_block_pagetable
497 /* Create the VA = PA map */
498 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK))
500 mov x8, x9 /* VA start (== PA start) */
502 bl build_l1_block_pagetable
504 /* Move to the l0 table */
505 add x27, x27, #PAGE_SIZE
507 /* Link the l0 -> l1 table */
513 /* Restore the Link register */
516 LEND(create_pagetables)
519 * Builds an L0 -> L1 table descriptor
521 * This is a link for a 512GiB block of memory with up to 1GiB regions mapped
522 * within it by build_l1_block_pagetable.
525 * x8 = Virtual Address
526 * x9 = L1 PA (trashed)
528 * x11, x12 and x13 are trashed
530 LENTRY(link_l0_pagetable)
532 * Link an L0 -> L1 table entry.
534 /* Find the table index */
535 lsr x11, x8, #L0_SHIFT
536 and x11, x11, #L0_ADDR_MASK
538 /* Build the L0 block entry */
540 orr x12, x12, #(TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0)
542 /* Only use the output address bits */
543 lsr x9, x9, #PAGE_SHIFT
544 1: orr x13, x12, x9, lsl #PAGE_SHIFT
546 /* Store the entry */
547 str x13, [x6, x11, lsl #3]
555 LEND(link_l0_pagetable)
558 * Builds an L1 -> L2 table descriptor
560 * This is a link for a 1GiB block of memory with up to 2MiB regions mapped
561 * within it by build_l2_block_pagetable.
564 * x8 = Virtual Address
565 * x9 = L2 PA (trashed)
566 * x11, x12 and x13 are trashed
568 LENTRY(link_l1_pagetable)
570 * Link an L1 -> L2 table entry.
572 /* Find the table index */
573 lsr x11, x8, #L1_SHIFT
574 and x11, x11, #Ln_ADDR_MASK
576 /* Build the L1 block entry */
579 /* Only use the output address bits */
580 lsr x9, x9, #PAGE_SHIFT
581 orr x13, x12, x9, lsl #PAGE_SHIFT
583 /* Store the entry */
584 str x13, [x6, x11, lsl #3]
587 LEND(link_l1_pagetable)
590 * Builds count 1 GiB page table entry
592 * x7 = Variable lower block attributes
594 * x9 = PA start (trashed)
596 * x11, x12 and x13 are trashed
598 LENTRY(build_l1_block_pagetable)
600 * Build the L1 table entry.
602 /* Find the table index */
603 lsr x11, x8, #L1_SHIFT
604 and x11, x11, #Ln_ADDR_MASK
606 /* Build the L1 block entry */
607 orr x12, x7, #L1_BLOCK
608 orr x12, x12, #(ATTR_DEFAULT)
610 /* Only use the output address bits */
611 lsr x9, x9, #L1_SHIFT
613 /* Set the physical address for this virtual address */
614 1: orr x13, x12, x9, lsl #L1_SHIFT
616 /* Store the entry */
617 str x13, [x6, x11, lsl #3]
625 LEND(build_l1_block_pagetable)
628 * Builds count 2 MiB page table entry
630 * x7 = Type (0 = Device, 1 = Normal)
632 * x9 = PA start (trashed)
634 * x11, x12 and x13 are trashed
636 LENTRY(build_l2_block_pagetable)
638 * Build the L2 table entry.
640 /* Find the table index */
641 lsr x11, x8, #L2_SHIFT
642 and x11, x11, #Ln_ADDR_MASK
644 /* Build the L2 block entry */
646 orr x12, x12, #L2_BLOCK
647 orr x12, x12, #(ATTR_DEFAULT)
648 orr x12, x12, #(ATTR_S1_UXN)
650 /* Only use the output address bits */
651 lsr x9, x9, #L2_SHIFT
653 /* Set the physical address for this virtual address */
654 1: orr x13, x12, x9, lsl #L2_SHIFT
656 /* Store the entry */
657 str x13, [x6, x11, lsl #3]
665 LEND(build_l2_block_pagetable)
670 /* Load the exception vectors */
671 ldr x2, =exception_vectors
674 /* Load ttbr0 and ttbr1 */
679 /* Clear the Monitor Debug System control register */
682 /* Invalidate the TLB */
691 * Setup TCR according to the PARange and ASIDBits fields
692 * from ID_AA64MMFR0_EL1 and the HAFDBS field from the
693 * ID_AA64MMFR1_EL1. More precisely, set TCR_EL1.AS
694 * to 1 only if the ASIDBits field equals 0b0010.
697 mrs x3, id_aa64mmfr0_el1
699 /* Copy the bottom 3 bits from id_aa64mmfr0_el1 into TCR.IPS */
700 bfi x2, x3, #(TCR_IPS_SHIFT), #(TCR_IPS_WIDTH)
701 and x3, x3, #(ID_AA64MMFR0_ASIDBits_MASK)
703 /* Check if the HW supports 16 bit ASIDS */
704 cmp x3, #(ID_AA64MMFR0_ASIDBits_16)
705 /* If so x3 == 1, else x3 == 0 */
707 /* Set TCR.AS with x3 */
708 bfi x2, x3, #(TCR_ASID_SHIFT), #(TCR_ASID_WIDTH)
711 * Check if the HW supports access flag and dirty state updates,
712 * and set TCR_EL1.HA and TCR_EL1.HD accordingly.
714 mrs x3, id_aa64mmfr1_el1
715 and x3, x3, #(ID_AA64MMFR1_HAFDBS_MASK)
718 orr x2, x2, #(TCR_HA)
723 orr x2, x2, #(TCR_HA | TCR_HD)
733 bic x1, x1, x3 /* Clear the required bits */
734 orr x1, x1, x2 /* Set the required bits */
742 .quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE_nGnRnE) | \
743 MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) | \
744 MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | \
745 MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH) | \
746 MAIR_ATTR(MAIR_DEVICE_nGnRE, VM_MEMATTR_DEVICE_nGnRE)
748 .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG1_4K | TCR_TG0_4K | \
749 TCR_CACHE_ATTRS | TCR_SMP_ATTRS)
752 .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \
753 SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \
754 SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \
755 SCTLR_M | SCTLR_CP15BEN)
758 .quad (SCTLR_EE | SCTLR_E0E | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \
766 .section .init_pagetable, "aw", %nobits
769 * 6 initial tables (in the following order):
770 * L2 for kernel (High addresses)
773 * L1 bootstrap for user (Low addresses)
774 * L0 bootstrap for user
777 .globl pagetable_l0_ttbr1
784 pagetable_l1_ttbr0_bootstrap:
786 pagetable_l0_ttbr0_boostrap:
798 .space (PAGE_SIZE * KSTACK_PAGES)
803 EENTRY(aarch32_sigcode)
804 .word 0xe1a0000d // mov r0, sp
805 .word 0xe2800040 // add r0, r0, #SIGF_UC
806 .word 0xe59f700c // ldr r7, [pc, #12]
807 .word 0xef000000 // swi #0
808 .word 0xe59f7008 // ldr r7, [pc, #8]
809 .word 0xef000000 // swi #0
810 .word 0xeafffffa // b . - 16
811 EEND(aarch32_sigcode)
817 .global sz_aarch32_sigcode
819 .quad aarch32_esigcode - aarch32_sigcode