2 * Copyright (c) 2012-2014 Andrew Turner
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include "opt_kstack_pages.h"
29 #include <sys/syscall.h>
30 #include <machine/asm.h>
31 #include <machine/armreg.h>
32 #include <machine/hypervisor.h>
33 #include <machine/param.h>
34 #include <machine/pte.h>
35 #include <machine/vm.h>
36 #include <machine/vmparam.h>
40 #if PAGE_SIZE == PAGE_SIZE_16K
42 * The number of level 3 tables to create. 32 will allow for 1G of address
43 * space, the same as a single level 2 page with 4k pages.
45 #define L3_PAGE_COUNT 32
49 .set kernbase, KERNBASE
53 * MMU on with an identity map, or off
56 * We are loaded at a 2MiB aligned address
64 * Disable the MMU. We may have entered the kernel with it on and
65 * will need to update the tables later. If this has been set up
66 * with anything other than a VA == PA map then this will fail,
67 * but in this case the code to find where we are running from
68 * would have also failed.
76 /* Set the context id */
77 msr contextidr_el1, xzr
79 /* Get the virt -> phys offset */
84 * x28 = Our physical load address
87 /* Create the page tables */
93 * x26 = Kernel L1 table
100 /* Load the new ttbr0 pagetable */
101 adrp x27, pagetable_l0_ttbr0
102 add x27, x27, :lo12:pagetable_l0_ttbr0
104 /* Jump to the virtual address space */
111 /* Set up the stack */
112 adrp x25, initstack_end
113 add x25, x25, :lo12:initstack_end
114 sub sp, x25, #PCB_SIZE
124 #if defined(PERTHREAD_SSP)
125 /* Set sp_el0 to the boot canary for early per-thread SSP to work */
126 adrp x15, boot_canary
127 add x15, x15, :lo12:boot_canary
131 /* Backup the module pointer */
134 sub sp, sp, #BOOTPARAMS_SIZE
137 str x1, [x0, #BP_MODULEP]
139 add x25, x25, :lo12:initstack
140 str x25, [x0, #BP_KERN_STACK]
141 str x27, [x0, #BP_KERN_TTBR0]
142 str x23, [x0, #BP_BOOT_EL]
143 str x4, [x0, #BP_HCR_EL2]
146 /* Save bootparams */
149 /* Bootstrap an early shadow map for the boot stack. */
150 bl pmap_san_bootstrap
152 /* Restore bootparams */
156 /* trace back starts here */
158 /* Branch to C code */
160 /* We are done with the boot params */
161 add sp, sp, #BOOTPARAMS_SIZE
164 * Enable pointer authentication in the kernel. We set the keys for
165 * thread0 in initarm so have to wait until it returns to enable it.
166 * If we were to enable it in initarm then any authentication when
167 * returning would fail as it was called with pointer authentication
174 /* We should not get here */
188 * mpentry(unsigned long)
190 * Called by a core when it is being brought online.
191 * The data in x0 is passed straight to init_secondary.
194 /* Disable interrupts */
195 msr daifset, #DAIF_INTR
200 /* Set the context id */
201 msr contextidr_el1, xzr
203 /* Load the kernel page table */
204 adrp x24, pagetable_l0_ttbr1
205 add x24, x24, :lo12:pagetable_l0_ttbr1
206 /* Load the identity page table */
207 adrp x27, pagetable_l0_ttbr0_boostrap
208 add x27, x27, :lo12:pagetable_l0_ttbr0_boostrap
213 /* Load the new ttbr0 pagetable */
214 adrp x27, pagetable_l0_ttbr0
215 add x27, x27, :lo12:pagetable_l0_ttbr0
217 /* Jump to the virtual address space */
218 ldr x15, =mp_virtdone
224 /* Start using the AP boot stack */
226 ldr x4, [x4, :lo12:bootstack]
229 #if defined(PERTHREAD_SSP)
230 /* Set sp_el0 to the boot canary for early per-thread SSP to work */
231 adrp x15, boot_canary
232 add x15, x15, :lo12:boot_canary
236 /* Load the kernel ttbr0 pagetable */
240 /* Invalidate the TLB */
246 * Initialize the per-CPU pointer before calling into C code, for the
247 * benefit of kernel sanitizers.
250 ldr x18, [x18, :lo12:bootpcpu]
258 * If we are started in EL2, configure the required hypervisor
259 * registers and drop to EL1.
269 * Disable the MMU. If the HCR_EL2.E2H field is set we will clear it
270 * which may break address translation.
278 /* Configure the Hypervisor */
279 ldr x2, =(HCR_RW | HCR_APK | HCR_API)
282 /* Stash value of HCR_EL2 for later */
286 /* Load the Virtualization Process ID Register */
290 /* Load the Virtualization Multiprocess ID Register */
294 /* Set the bits that need to be 1 in sctlr_el1 */
299 * On some hardware, e.g., Apple M1, we can't clear E2H, so make sure we
300 * don't trap to EL2 for SIMD register usage to have at least a
301 * minimally usable system.
304 mov x3, #CPTR_RES1 /* HCR_E2H == 0 */
305 mov x5, #CPTR_FPEN /* HCR_E2H == 1 */
309 /* Don't trap to EL2 for CP15 traps */
312 /* Enable access to the physical timers at EL1 */
314 orr x2, x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN)
317 /* Set the counter offset to a known value */
320 /* Hypervisor trap functions */
321 adrp x2, hyp_stub_vectors
322 add x2, x2, :lo12:hyp_stub_vectors
325 /* Zero vttbr_el2 so a hypervisor can tell the host and guest apart */
328 mov x2, #(PSR_DAIF | PSR_M_EL1h)
331 /* Configure GICv3 CPU interface */
332 mrs x2, id_aa64pfr0_el1
333 /* Extract GIC bits from the register */
334 ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS
335 /* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */
336 cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT)
340 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */
341 orr x2, x2, #ICC_SRE_EL2_SRE /* Enable system registers */
345 /* Set the address to return to our return address */
357 * Get the physical address the kernel was loaded at.
359 LENTRY(get_load_phys_addr)
360 /* Load the offset of get_load_phys_addr from KERNBASE */
361 ldr x28, =(get_load_phys_addr - KERNBASE)
362 /* Load the physical address of get_load_phys_addr */
363 adr x29, get_load_phys_addr
364 /* Find the physical address of KERNBASE, i.e. our load address */
367 LEND(get_load_phys_addr)
370 * This builds the page tables containing the identity map, and the kernel
374 * We were loaded to an address that is on a 2MiB boundary
375 * All the memory must not cross a 1GiB boundaty
376 * x28 contains the physical address we were loaded from
378 * TODO: This is out of date.
379 * There are at least 5 pages before that address for the page tables
380 * The pages used are:
381 * - The Kernel L2 table
382 * - The Kernel L1 table
383 * - The Kernel L0 table (TTBR1)
384 * - The identity (PA = VA) L1 table
385 * - The identity (PA = VA) L0 table (TTBR0)
387 LENTRY(create_pagetables)
388 /* Save the Link register */
391 /* Clean the page table */
393 add x6, x6, :lo12:pagetable
395 adrp x27, pagetable_end
396 add x27, x27, :lo12:pagetable_end
398 stp xzr, xzr, [x6], #16
399 stp xzr, xzr, [x6], #16
400 stp xzr, xzr, [x6], #16
401 stp xzr, xzr, [x6], #16
406 * Build the TTBR1 maps.
409 /* Find the size of the kernel */
412 #if defined(LINUX_BOOT_ABI)
413 /* X19 is used as 'map FDT data' flag */
416 /* No modules or FDT pointer ? */
420 * Test if x0 points to modules descriptor(virtual address) or
421 * to FDT (physical address)
423 cmp x0, x6 /* x6 is #(KERNBASE) */
427 /* Booted with modules pointer */
428 /* Find modulep - begin */
431 * Add space for the module data. When PAGE_SIZE is 4k this will
432 * add at least 2 level 2 blocks (2 * 2MiB). When PAGE_SIZE is
433 * larger it will be at least as large as we use smaller level 3
436 ldr x7, =((6 * 1024 * 1024) - 1)
440 #if defined(LINUX_BOOT_ABI)
442 /* Booted by U-Boot booti with FDT data */
443 /* Set 'map FDT data' flag */
447 /* Booted by U-Boot booti without FTD data */
448 /* Find the end - begin */
453 * Add one 2MiB page for copy of FDT data (maximum FDT size),
454 * one for metadata and round up
456 ldr x7, =(3 * L2_SIZE - 1)
461 #if PAGE_SIZE != PAGE_SIZE_4K
463 * Create L3 pages. The kernel will be loaded at a 2M aligned
464 * address, however L2 blocks are too large when the page size is
465 * not 4k to map the kernel with such an aligned address. However,
466 * when the page size is larger than 4k, L2 blocks are too large to
467 * map the kernel with such an alignment.
470 /* Get the number of l3 pages to allocate, rounded down */
471 lsr x10, x8, #(L3_SHIFT)
473 /* Create the kernel space L2 table */
475 mov x7, #(ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK))
478 bl build_l3_page_pagetable
480 /* Move to the l2 table */
481 ldr x9, =(PAGE_SIZE * L3_PAGE_COUNT)
484 /* Link the l2 -> l3 table */
489 /* Get the number of l2 pages to allocate, rounded down */
490 lsr x10, x8, #(L2_SHIFT)
492 /* Create the kernel space L2 table */
494 mov x7, #(ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK))
497 bl build_l2_block_pagetable
500 /* Move to the l1 table */
501 add x26, x26, #PAGE_SIZE
503 /* Link the l1 -> l2 table */
508 /* Move to the l0 table */
509 add x24, x26, #PAGE_SIZE
511 /* Link the l0 -> l1 table */
518 * Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_S1_nG.
519 * They are only needed early on, so the VA = PA map is uncached.
521 add x27, x24, #PAGE_SIZE
523 mov x6, x27 /* The initial page table */
525 /* Create the VA = PA map */
526 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK))
528 and x16, x16, #(~L2_OFFSET)
529 mov x9, x16 /* PA start */
530 mov x8, x16 /* VA start (== PA start) */
532 bl build_l2_block_pagetable
534 #if defined(SOCDEV_PA)
535 /* Create a table for the UART */
536 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_DEVICE))
538 add x16, x16, x9 /* VA start */
541 /* Store the socdev virtual address */
542 add x17, x8, #(SOCDEV_PA & L2_OFFSET)
544 str x17, [x9, :lo12:socdev_va]
546 mov x9, #(SOCDEV_PA & ~L2_OFFSET) /* PA start */
548 bl build_l2_block_pagetable
551 #if defined(LINUX_BOOT_ABI)
555 /* Create the mapping for FDT data (2 MiB max) */
556 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK))
558 add x16, x16, x9 /* VA start */
560 mov x9, x0 /* PA start */
561 /* Update the module pointer to point at the allocated memory */
562 and x0, x0, #(L2_OFFSET) /* Keep the lower bits */
563 add x0, x0, x8 /* Add the aligned virtual address */
566 bl build_l2_block_pagetable
571 /* Move to the l1 table */
572 add x27, x27, #PAGE_SIZE
574 /* Link the l1 -> l2 table */
579 /* Move to the l0 table */
580 add x27, x27, #PAGE_SIZE
582 /* Link the l0 -> l1 table */
588 /* Restore the Link register */
591 LEND(create_pagetables)
594 * Builds an L0 -> L1 table descriptor
597 * x8 = Virtual Address
598 * x9 = L1 PA (trashed)
599 * x10 = Entry count (trashed)
600 * x11, x12 and x13 are trashed
602 LENTRY(link_l0_pagetable)
604 * Link an L0 -> L1 table entry.
606 /* Find the table index */
607 lsr x11, x8, #L0_SHIFT
608 and x11, x11, #L0_ADDR_MASK
610 /* Build the L0 block entry */
612 orr x12, x12, #(TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0)
614 /* Only use the output address bits */
615 lsr x9, x9, #PAGE_SHIFT
616 1: orr x13, x12, x9, lsl #PAGE_SHIFT
618 /* Store the entry */
619 str x13, [x6, x11, lsl #3]
627 LEND(link_l0_pagetable)
630 * Builds an L1 -> L2 table descriptor
633 * x8 = Virtual Address
634 * x9 = L2 PA (trashed)
635 * x11, x12 and x13 are trashed
637 LENTRY(link_l1_pagetable)
639 * Link an L1 -> L2 table entry.
641 /* Find the table index */
642 lsr x11, x8, #L1_SHIFT
643 and x11, x11, #Ln_ADDR_MASK
645 /* Build the L1 block entry */
648 /* Only use the output address bits */
649 lsr x9, x9, #PAGE_SHIFT
650 orr x13, x12, x9, lsl #PAGE_SHIFT
652 /* Store the entry */
653 str x13, [x6, x11, lsl #3]
656 LEND(link_l1_pagetable)
659 * Builds count 2 MiB page table entry
661 * x7 = Block attributes
663 * x9 = PA start (trashed)
664 * x10 = Entry count (trashed)
665 * x11, x12 and x13 are trashed
667 LENTRY(build_l2_block_pagetable)
669 * Build the L2 table entry.
671 /* Find the table index */
672 lsr x11, x8, #L2_SHIFT
673 and x11, x11, #Ln_ADDR_MASK
675 /* Build the L2 block entry */
676 orr x12, x7, #L2_BLOCK
677 orr x12, x12, #(ATTR_DEFAULT)
678 orr x12, x12, #(ATTR_S1_UXN)
679 #ifdef __ARM_FEATURE_BTI_DEFAULT
680 orr x12, x12, #(ATTR_S1_GP)
683 /* Only use the output address bits */
684 lsr x9, x9, #L2_SHIFT
686 /* Set the physical address for this virtual address */
687 1: orr x13, x12, x9, lsl #L2_SHIFT
689 /* Store the entry */
690 str x13, [x6, x11, lsl #3]
698 LEND(build_l2_block_pagetable)
700 #if PAGE_SIZE != PAGE_SIZE_4K
702 * Builds an L2 -> L3 table descriptor
705 * x8 = Virtual Address
706 * x9 = L3 PA (trashed)
707 * x11, x12 and x13 are trashed
709 LENTRY(link_l2_pagetable)
711 * Link an L2 -> L3 table entry.
713 /* Find the table index */
714 lsr x11, x8, #L2_SHIFT
715 and x11, x11, #Ln_ADDR_MASK
717 /* Build the L1 block entry */
720 /* Only use the output address bits */
721 lsr x9, x9, #PAGE_SHIFT
722 orr x13, x12, x9, lsl #PAGE_SHIFT
724 /* Store the entry */
725 str x13, [x6, x11, lsl #3]
728 LEND(link_l2_pagetable)
731 * Builds count level 3 page table entries
733 * x7 = Block attributes
735 * x9 = PA start (trashed)
736 * x10 = Entry count (trashed)
737 * x11, x12 and x13 are trashed
739 LENTRY(build_l3_page_pagetable)
741 * Build the L3 table entry.
743 /* Find the table index */
744 lsr x11, x8, #L3_SHIFT
745 and x11, x11, #Ln_ADDR_MASK
747 /* Build the L3 page entry */
748 orr x12, x7, #L3_PAGE
749 orr x12, x12, #(ATTR_DEFAULT)
750 orr x12, x12, #(ATTR_S1_UXN)
751 #ifdef __ARM_FEATURE_BTI_DEFAULT
752 orr x12, x12, #(ATTR_S1_GP)
755 /* Only use the output address bits */
756 lsr x9, x9, #L3_SHIFT
758 /* Set the physical address for this virtual address */
759 1: orr x13, x12, x9, lsl #L3_SHIFT
761 /* Store the entry */
762 str x13, [x6, x11, lsl #3]
770 LEND(build_l3_page_pagetable)
776 /* Load the exception vectors */
777 ldr x2, =exception_vectors
780 /* Load ttbr0 and ttbr1 */
785 /* Clear the Monitor Debug System control register */
788 /* Invalidate the TLB */
797 * Setup TCR according to the PARange and ASIDBits fields
798 * from ID_AA64MMFR0_EL1 and the HAFDBS field from the
799 * ID_AA64MMFR1_EL1. More precisely, set TCR_EL1.AS
800 * to 1 only if the ASIDBits field equals 0b0010.
803 mrs x3, id_aa64mmfr0_el1
805 /* Copy the bottom 3 bits from id_aa64mmfr0_el1 into TCR.IPS */
806 bfi x2, x3, #(TCR_IPS_SHIFT), #(TCR_IPS_WIDTH)
807 and x3, x3, #(ID_AA64MMFR0_ASIDBits_MASK)
809 /* Check if the HW supports 16 bit ASIDS */
810 cmp x3, #(ID_AA64MMFR0_ASIDBits_16)
811 /* If so x3 == 1, else x3 == 0 */
813 /* Set TCR.AS with x3 */
814 bfi x2, x3, #(TCR_ASID_SHIFT), #(TCR_ASID_WIDTH)
817 * Check if the HW supports access flag and dirty state updates,
818 * and set TCR_EL1.HA and TCR_EL1.HD accordingly.
820 mrs x3, id_aa64mmfr1_el1
821 and x3, x3, #(ID_AA64MMFR1_HAFDBS_MASK)
824 orr x2, x2, #(TCR_HA)
829 orr x2, x2, #(TCR_HA | TCR_HD)
839 bic x1, x1, x3 /* Clear the required bits */
840 orr x1, x1, x2 /* Set the required bits */
848 .quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE_nGnRnE) | \
849 MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) | \
850 MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | \
851 MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH) | \
852 MAIR_ATTR(MAIR_DEVICE_nGnRE, VM_MEMATTR_DEVICE_nGnRE)
854 #if PAGE_SIZE == PAGE_SIZE_4K
855 #define TCR_TG (TCR_TG1_4K | TCR_TG0_4K)
856 #elif PAGE_SIZE == PAGE_SIZE_16K
857 #define TCR_TG (TCR_TG1_16K | TCR_TG0_16K)
859 #error Unsupported page size
862 .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG | \
863 TCR_CACHE_ATTRS | TCR_SMP_ATTRS)
866 .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \
867 SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \
868 SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \
869 SCTLR_M | SCTLR_CP15BEN | SCTLR_BT1 | SCTLR_BT0)
872 .quad (SCTLR_EE | SCTLR_E0E | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \
883 .space (PAGE_SIZE * KSTACK_PAGES)
886 .section .init_pagetable, "aw", %nobits
889 * 6 initial tables (in the following order):
890 * L2 for kernel (High addresses)
893 * L1 bootstrap for user (Low addresses)
894 * L0 bootstrap for user
897 .globl pagetable_l0_ttbr1
899 #if PAGE_SIZE != PAGE_SIZE_4K
900 .space (PAGE_SIZE * L3_PAGE_COUNT)
908 pagetable_l2_ttbr0_bootstrap:
910 pagetable_l1_ttbr0_bootstrap:
912 pagetable_l0_ttbr0_boostrap:
921 .section .rodata, "a", %progbits
922 .globl aarch32_sigcode
925 .word 0xe1a0000d // mov r0, sp
926 .word 0xe2800040 // add r0, r0, #SIGF_UC
927 .word 0xe59f700c // ldr r7, [pc, #12]
928 .word 0xef000000 // swi #0
929 .word 0xe59f7008 // ldr r7, [pc, #8]
930 .word 0xef000000 // swi #0
931 .word 0xeafffffa // b . - 16
935 .size aarch32_sigcode, . - aarch32_sigcode
938 .global sz_aarch32_sigcode
940 .quad aarch32_esigcode - aarch32_sigcode