2 * Copyright (c) 2012-2014 Andrew Turner
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include "opt_kstack_pages.h"
31 #include <sys/syscall.h>
32 #include <machine/asm.h>
33 #include <machine/armreg.h>
34 #include <machine/hypervisor.h>
35 #include <machine/param.h>
36 #include <machine/pte.h>
37 #include <machine/vm.h>
38 #include <machine/vmparam.h>
42 #if PAGE_SIZE == PAGE_SIZE_16K
44 * The number of level 3 tables to create. 32 will allow for 1G of address
45 * space, the same as a single level 2 page with 4k pages.
47 #define L3_PAGE_COUNT 32
51 .set kernbase, KERNBASE
55 * MMU on with an identity map, or off
58 * We are loaded at a 2MiB aligned address
66 * Disable the MMU. We may have entered the kernel with it on and
67 * will need to update the tables later. If this has been set up
68 * with anything other than a VA == PA map then this will fail,
69 * but in this case the code to find where we are running from
70 * would have also failed.
78 /* Set the context id */
79 msr contextidr_el1, xzr
81 /* Get the virt -> phys offset */
87 * x28 = Our physical load address
90 /* Create the page tables */
96 * x26 = Kernel L1 table
103 /* Load the new ttbr0 pagetable */
104 adrp x27, pagetable_l0_ttbr0
105 add x27, x27, :lo12:pagetable_l0_ttbr0
107 /* Jump to the virtual address space */
112 /* Set up the stack */
113 adrp x25, initstack_end
114 add x25, x25, :lo12:initstack_end
116 sub sp, sp, #PCB_SIZE
126 #if defined(PERTHREAD_SSP)
127 /* Set sp_el0 to the boot canary for early per-thread SSP to work */
128 adrp x15, boot_canary
129 add x15, x15, :lo12:boot_canary
133 /* Backup the module pointer */
136 sub sp, sp, #BOOTPARAMS_SIZE
139 /* Degate the delda so it is VA -> PA */
142 str x1, [x0, #BP_MODULEP]
143 str x29, [x0, #BP_KERN_DELTA]
145 add x25, x25, :lo12:initstack
146 str x25, [x0, #BP_KERN_STACK]
147 str x27, [x0, #BP_KERN_TTBR0]
148 str x23, [x0, #BP_BOOT_EL]
149 str x4, [x0, #BP_HCR_EL2]
151 /* trace back starts here */
153 /* Branch to C code */
155 /* We are done with the boot params */
156 add sp, sp, #BOOTPARAMS_SIZE
159 * Enable pointer authentication in the kernel. We set the keys for
160 * thread0 in initarm so have to wait until it returns to enable it.
161 * If we were to enable it in initarm then any authentication when
162 * returning would fail as it was called with pointer authentication
169 /* We should not get here */
183 * mpentry(unsigned long)
185 * Called by a core when it is being brought online.
186 * The data in x0 is passed straight to init_secondary.
189 /* Disable interrupts */
190 msr daifset, #DAIF_INTR
195 /* Set the context id */
196 msr contextidr_el1, xzr
198 /* Load the kernel page table */
199 adrp x24, pagetable_l0_ttbr1
200 add x24, x24, :lo12:pagetable_l0_ttbr1
201 /* Load the identity page table */
202 adrp x27, pagetable_l0_ttbr0_boostrap
203 add x27, x27, :lo12:pagetable_l0_ttbr0_boostrap
208 /* Load the new ttbr0 pagetable */
209 adrp x27, pagetable_l0_ttbr0
210 add x27, x27, :lo12:pagetable_l0_ttbr0
212 /* Jump to the virtual address space */
213 ldr x15, =mp_virtdone
217 /* Start using the AP boot stack */
222 #if defined(PERTHREAD_SSP)
223 /* Set sp_el0 to the boot canary for early per-thread SSP to work */
224 adrp x15, boot_canary
225 add x15, x15, :lo12:boot_canary
229 /* Load the kernel ttbr0 pagetable */
233 /* Invalidate the TLB */
243 * If we are started in EL2, configure the required hypervisor
244 * registers and drop to EL1.
254 * Disable the MMU. If the HCR_EL2.E2H field is set we will clear it
255 * which may break address translation.
263 /* Configure the Hypervisor */
264 ldr x2, =(HCR_RW | HCR_APK | HCR_API)
267 /* Stash value of HCR_EL2 for later */
271 /* Load the Virtualization Process ID Register */
275 /* Load the Virtualization Multiprocess ID Register */
279 /* Set the bits that need to be 1 in sctlr_el1 */
284 * On some hardware, e.g., Apple M1, we can't clear E2H, so make sure we
285 * don't trap to EL2 for SIMD register usage to have at least a
286 * minimally usable system.
289 mov x3, #CPTR_RES1 /* HCR_E2H == 0 */
290 mov x5, #CPTR_FPEN /* HCR_E2H == 1 */
294 /* Don't trap to EL2 for CP15 traps */
297 /* Enable access to the physical timers at EL1 */
299 orr x2, x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN)
302 /* Set the counter offset to a known value */
305 /* Hypervisor trap functions */
306 adrp x2, hyp_stub_vectors
307 add x2, x2, :lo12:hyp_stub_vectors
310 /* Zero vttbr_el2 so a hypervisor can tell the host and guest apart */
313 mov x2, #(PSR_F | PSR_I | PSR_A | PSR_D | PSR_M_EL1h)
316 /* Configure GICv3 CPU interface */
317 mrs x2, id_aa64pfr0_el1
318 /* Extract GIC bits from the register */
319 ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS
320 /* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */
321 cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT)
325 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */
326 orr x2, x2, #ICC_SRE_EL2_SRE /* Enable system registers */
330 /* Set the address to return to our return address */
342 * Get the delta between the physical address we were loaded to and the
343 * virtual address we expect to run from. This is used when building the
344 * initial page table.
346 LENTRY(get_virt_delta)
347 /* Load the physical address of virt_map */
349 add x29, x29, :lo12:virt_map
350 /* Load the virtual address of virt_map stored in virt_map */
352 /* Find PA - VA as PA' = VA' - VA + PA = VA' + (PA - VA) = VA' + x29 */
354 /* Find the load address for the kernel */
365 * This builds the page tables containing the identity map, and the kernel
369 * We were loaded to an address that is on a 2MiB boundary
370 * All the memory must not cross a 1GiB boundaty
371 * x28 contains the physical address we were loaded from
373 * TODO: This is out of date.
374 * There are at least 5 pages before that address for the page tables
375 * The pages used are:
376 * - The Kernel L2 table
377 * - The Kernel L1 table
378 * - The Kernel L0 table (TTBR1)
379 * - The identity (PA = VA) L1 table
380 * - The identity (PA = VA) L0 table (TTBR0)
382 LENTRY(create_pagetables)
383 /* Save the Link register */
386 /* Clean the page table */
388 add x6, x6, :lo12:pagetable
390 adrp x27, pagetable_end
391 add x27, x27, :lo12:pagetable_end
393 stp xzr, xzr, [x6], #16
394 stp xzr, xzr, [x6], #16
395 stp xzr, xzr, [x6], #16
396 stp xzr, xzr, [x6], #16
401 * Build the TTBR1 maps.
404 /* Find the size of the kernel */
407 #if defined(LINUX_BOOT_ABI)
408 /* X19 is used as 'map FDT data' flag */
411 /* No modules or FDT pointer ? */
415 * Test if x0 points to modules descriptor(virtual address) or
416 * to FDT (physical address)
418 cmp x0, x6 /* x6 is #(KERNBASE) */
422 /* Booted with modules pointer */
423 /* Find modulep - begin */
426 * Add space for the module data. When PAGE_SIZE is 4k this will
427 * add at least 2 level 2 blocks (2 * 2MiB). When PAGE_SIZE is
428 * larger it will be at least as large as we use smaller level 3
431 ldr x7, =((6 * 1024 * 1024) - 1)
435 #if defined(LINUX_BOOT_ABI)
437 /* Booted by U-Boot booti with FDT data */
438 /* Set 'map FDT data' flag */
442 /* Booted by U-Boot booti without FTD data */
443 /* Find the end - begin */
448 * Add one 2MiB page for copy of FDT data (maximum FDT size),
449 * one for metadata and round up
451 ldr x7, =(3 * L2_SIZE - 1)
456 #if PAGE_SIZE != PAGE_SIZE_4K
458 * Create L3 pages. The kernel will be loaded at a 2M aligned
459 * address, however L2 blocks are too large when the page size is
460 * not 4k to map the kernel with such an aligned address. However,
461 * when the page size is larger than 4k, L2 blocks are too large to
462 * map the kernel with such an alignment.
465 /* Get the number of l3 pages to allocate, rounded down */
466 lsr x10, x8, #(L3_SHIFT)
468 /* Create the kernel space L2 table */
470 mov x7, #(ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK))
473 bl build_l3_page_pagetable
475 /* Move to the l2 table */
476 ldr x9, =(PAGE_SIZE * L3_PAGE_COUNT)
479 /* Link the l2 -> l3 table */
484 /* Get the number of l2 pages to allocate, rounded down */
485 lsr x10, x8, #(L2_SHIFT)
487 /* Create the kernel space L2 table */
489 mov x7, #(ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK))
492 bl build_l2_block_pagetable
495 /* Move to the l1 table */
496 add x26, x26, #PAGE_SIZE
498 /* Link the l1 -> l2 table */
503 /* Move to the l0 table */
504 add x24, x26, #PAGE_SIZE
506 /* Link the l0 -> l1 table */
513 * Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_S1_nG.
514 * They are only needed early on, so the VA = PA map is uncached.
516 add x27, x24, #PAGE_SIZE
518 mov x6, x27 /* The initial page table */
520 /* Create the VA = PA map */
521 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK))
523 and x16, x16, #(~L2_OFFSET)
524 mov x9, x16 /* PA start */
525 mov x8, x16 /* VA start (== PA start) */
527 bl build_l2_block_pagetable
529 #if defined(SOCDEV_PA)
530 /* Create a table for the UART */
531 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_DEVICE))
533 add x16, x16, x9 /* VA start */
536 /* Store the socdev virtual address */
537 add x17, x8, #(SOCDEV_PA & L2_OFFSET)
539 str x17, [x9, :lo12:socdev_va]
541 mov x9, #(SOCDEV_PA & ~L2_OFFSET) /* PA start */
543 bl build_l2_block_pagetable
546 #if defined(LINUX_BOOT_ABI)
550 /* Create the mapping for FDT data (2 MiB max) */
551 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK))
553 add x16, x16, x9 /* VA start */
555 mov x9, x0 /* PA start */
556 /* Update the module pointer to point at the allocated memory */
557 and x0, x0, #(L2_OFFSET) /* Keep the lower bits */
558 add x0, x0, x8 /* Add the aligned virtual address */
561 bl build_l2_block_pagetable
566 /* Move to the l1 table */
567 add x27, x27, #PAGE_SIZE
569 /* Link the l1 -> l2 table */
574 /* Move to the l0 table */
575 add x27, x27, #PAGE_SIZE
577 /* Link the l0 -> l1 table */
583 /* Restore the Link register */
586 LEND(create_pagetables)
589 * Builds an L0 -> L1 table descriptor
592 * x8 = Virtual Address
593 * x9 = L1 PA (trashed)
594 * x10 = Entry count (trashed)
595 * x11, x12 and x13 are trashed
597 LENTRY(link_l0_pagetable)
599 * Link an L0 -> L1 table entry.
601 /* Find the table index */
602 lsr x11, x8, #L0_SHIFT
603 and x11, x11, #L0_ADDR_MASK
605 /* Build the L0 block entry */
607 orr x12, x12, #(TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0)
609 /* Only use the output address bits */
610 lsr x9, x9, #PAGE_SHIFT
611 1: orr x13, x12, x9, lsl #PAGE_SHIFT
613 /* Store the entry */
614 str x13, [x6, x11, lsl #3]
622 LEND(link_l0_pagetable)
625 * Builds an L1 -> L2 table descriptor
628 * x8 = Virtual Address
629 * x9 = L2 PA (trashed)
630 * x11, x12 and x13 are trashed
632 LENTRY(link_l1_pagetable)
634 * Link an L1 -> L2 table entry.
636 /* Find the table index */
637 lsr x11, x8, #L1_SHIFT
638 and x11, x11, #Ln_ADDR_MASK
640 /* Build the L1 block entry */
643 /* Only use the output address bits */
644 lsr x9, x9, #PAGE_SHIFT
645 orr x13, x12, x9, lsl #PAGE_SHIFT
647 /* Store the entry */
648 str x13, [x6, x11, lsl #3]
651 LEND(link_l1_pagetable)
654 * Builds count 2 MiB page table entry
656 * x7 = Block attributes
658 * x9 = PA start (trashed)
659 * x10 = Entry count (trashed)
660 * x11, x12 and x13 are trashed
662 LENTRY(build_l2_block_pagetable)
664 * Build the L2 table entry.
666 /* Find the table index */
667 lsr x11, x8, #L2_SHIFT
668 and x11, x11, #Ln_ADDR_MASK
670 /* Build the L2 block entry */
671 orr x12, x7, #L2_BLOCK
672 orr x12, x12, #(ATTR_DEFAULT)
673 orr x12, x12, #(ATTR_S1_UXN)
675 /* Only use the output address bits */
676 lsr x9, x9, #L2_SHIFT
678 /* Set the physical address for this virtual address */
679 1: orr x13, x12, x9, lsl #L2_SHIFT
681 /* Store the entry */
682 str x13, [x6, x11, lsl #3]
690 LEND(build_l2_block_pagetable)
692 #if PAGE_SIZE != PAGE_SIZE_4K
694 * Builds an L2 -> L3 table descriptor
697 * x8 = Virtual Address
698 * x9 = L3 PA (trashed)
699 * x11, x12 and x13 are trashed
701 LENTRY(link_l2_pagetable)
703 * Link an L2 -> L3 table entry.
705 /* Find the table index */
706 lsr x11, x8, #L2_SHIFT
707 and x11, x11, #Ln_ADDR_MASK
709 /* Build the L1 block entry */
712 /* Only use the output address bits */
713 lsr x9, x9, #PAGE_SHIFT
714 orr x13, x12, x9, lsl #PAGE_SHIFT
716 /* Store the entry */
717 str x13, [x6, x11, lsl #3]
720 LEND(link_l2_pagetable)
723 * Builds count level 3 page table entries
725 * x7 = Block attributes
727 * x9 = PA start (trashed)
728 * x10 = Entry count (trashed)
729 * x11, x12 and x13 are trashed
731 LENTRY(build_l3_page_pagetable)
733 * Build the L3 table entry.
735 /* Find the table index */
736 lsr x11, x8, #L3_SHIFT
737 and x11, x11, #Ln_ADDR_MASK
739 /* Build the L3 page entry */
740 orr x12, x7, #L3_PAGE
741 orr x12, x12, #(ATTR_DEFAULT)
742 orr x12, x12, #(ATTR_S1_UXN)
744 /* Only use the output address bits */
745 lsr x9, x9, #L3_SHIFT
747 /* Set the physical address for this virtual address */
748 1: orr x13, x12, x9, lsl #L3_SHIFT
750 /* Store the entry */
751 str x13, [x6, x11, lsl #3]
759 LEND(build_l3_page_pagetable)
765 /* Load the exception vectors */
766 ldr x2, =exception_vectors
769 /* Load ttbr0 and ttbr1 */
774 /* Clear the Monitor Debug System control register */
777 /* Invalidate the TLB */
786 * Setup TCR according to the PARange and ASIDBits fields
787 * from ID_AA64MMFR0_EL1 and the HAFDBS field from the
788 * ID_AA64MMFR1_EL1. More precisely, set TCR_EL1.AS
789 * to 1 only if the ASIDBits field equals 0b0010.
792 mrs x3, id_aa64mmfr0_el1
794 /* Copy the bottom 3 bits from id_aa64mmfr0_el1 into TCR.IPS */
795 bfi x2, x3, #(TCR_IPS_SHIFT), #(TCR_IPS_WIDTH)
796 and x3, x3, #(ID_AA64MMFR0_ASIDBits_MASK)
798 /* Check if the HW supports 16 bit ASIDS */
799 cmp x3, #(ID_AA64MMFR0_ASIDBits_16)
800 /* If so x3 == 1, else x3 == 0 */
802 /* Set TCR.AS with x3 */
803 bfi x2, x3, #(TCR_ASID_SHIFT), #(TCR_ASID_WIDTH)
806 * Check if the HW supports access flag and dirty state updates,
807 * and set TCR_EL1.HA and TCR_EL1.HD accordingly.
809 mrs x3, id_aa64mmfr1_el1
810 and x3, x3, #(ID_AA64MMFR1_HAFDBS_MASK)
813 orr x2, x2, #(TCR_HA)
818 orr x2, x2, #(TCR_HA | TCR_HD)
828 bic x1, x1, x3 /* Clear the required bits */
829 orr x1, x1, x2 /* Set the required bits */
837 .quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE_nGnRnE) | \
838 MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) | \
839 MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | \
840 MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH) | \
841 MAIR_ATTR(MAIR_DEVICE_nGnRE, VM_MEMATTR_DEVICE_nGnRE)
843 #if PAGE_SIZE == PAGE_SIZE_4K
844 #define TCR_TG (TCR_TG1_4K | TCR_TG0_4K)
845 #elif PAGE_SIZE == PAGE_SIZE_16K
846 #define TCR_TG (TCR_TG1_16K | TCR_TG0_16K)
848 #error Unsupported page size
851 .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG | \
852 TCR_CACHE_ATTRS | TCR_SMP_ATTRS)
855 .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \
856 SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \
857 SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \
858 SCTLR_M | SCTLR_CP15BEN)
861 .quad (SCTLR_EE | SCTLR_E0E | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \
869 .section .init_pagetable, "aw", %nobits
872 * 6 initial tables (in the following order):
873 * L2 for kernel (High addresses)
876 * L1 bootstrap for user (Low addresses)
877 * L0 bootstrap for user
880 .globl pagetable_l0_ttbr1
882 #if PAGE_SIZE != PAGE_SIZE_4K
883 .space (PAGE_SIZE * L3_PAGE_COUNT)
891 pagetable_l2_ttbr0_bootstrap:
893 pagetable_l1_ttbr0_bootstrap:
895 pagetable_l0_ttbr0_boostrap:
907 .space (PAGE_SIZE * KSTACK_PAGES)
912 EENTRY(aarch32_sigcode)
913 .word 0xe1a0000d // mov r0, sp
914 .word 0xe2800040 // add r0, r0, #SIGF_UC
915 .word 0xe59f700c // ldr r7, [pc, #12]
916 .word 0xef000000 // swi #0
917 .word 0xe59f7008 // ldr r7, [pc, #8]
918 .word 0xef000000 // swi #0
919 .word 0xeafffffa // b . - 16
920 EEND(aarch32_sigcode)
926 .global sz_aarch32_sigcode
928 .quad aarch32_esigcode - aarch32_sigcode