2 * Copyright (c) 2015-2016 The FreeBSD Foundation
4 * This software was developed by Andrew Turner under
5 * sponsorship from the FreeBSD Foundation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include "opt_kstack_pages.h"
33 #include "opt_platform.h"
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/systm.h>
43 #include <sys/domainset.h>
44 #include <sys/kernel.h>
46 #include <sys/malloc.h>
47 #include <sys/module.h>
48 #include <sys/mutex.h>
51 #include <sys/sched.h>
56 #include <vm/vm_extern.h>
57 #include <vm/vm_kern.h>
58 #include <vm/vm_map.h>
60 #include <machine/machdep.h>
61 #include <machine/debug_monitor.h>
62 #include <machine/intr.h>
63 #include <machine/smp.h>
65 #include <machine/vfp.h>
69 #include <contrib/dev/acpica/include/acpi.h>
70 #include <dev/acpica/acpivar.h>
74 #include <dev/ofw/openfirm.h>
75 #include <dev/ofw/ofw_bus.h>
76 #include <dev/ofw/ofw_bus_subr.h>
77 #include <dev/ofw/ofw_cpu.h>
80 #include <dev/psci/psci.h>
84 #define MP_BOOTSTACK_SIZE (kstack_pages * PAGE_SIZE)
86 #define MP_QUIRK_CPULIST 0x01 /* The list of cpus may be wrong, */
87 /* don't panic if one fails to start */
88 static uint32_t mp_quirks;
95 { "arm,foundation-aarch64", MP_QUIRK_CPULIST },
96 { "arm,fvp-base", MP_QUIRK_CPULIST },
97 /* This is incorrect in some DTS files */
98 { "arm,vfp-base", MP_QUIRK_CPULIST },
103 typedef void intr_ipi_send_t(void *, cpuset_t, u_int);
104 typedef void intr_ipi_handler_t(void *);
106 #define INTR_IPI_NAMELEN (MAXCOMLEN + 1)
108 intr_ipi_handler_t * ii_handler;
109 void * ii_handler_arg;
110 intr_ipi_send_t * ii_send;
112 char ii_name[INTR_IPI_NAMELEN];
116 static struct intr_ipi ipi_sources[INTR_IPI_COUNT];
118 static struct intr_ipi *intr_ipi_lookup(u_int);
119 static void intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *,
122 static void ipi_ast(void *);
123 static void ipi_hardclock(void *);
124 static void ipi_preempt(void *);
125 static void ipi_rendezvous(void *);
126 static void ipi_stop(void *);
128 struct pcb stoppcbs[MAXCPU];
131 static u_int fdt_cpuid;
134 void mpentry(unsigned long cpuid);
135 void init_secondary(uint64_t);
137 /* Synchronize AP startup. */
138 static struct mtx ap_boot_mtx;
140 /* Stacks for AP initialization, discarded once idle threads are started. */
142 static void *bootstacks[MAXCPU];
144 /* Count of started APs, used to synchronize access to bootstack. */
145 static volatile int aps_started;
147 /* Set to 1 once we're ready to let the APs out of the pen. */
148 static volatile int aps_ready;
150 /* Temporary variables for init_secondary() */
151 void *dpcpu[MAXCPU - 1];
154 is_boot_cpu(uint64_t target_cpu)
157 return (PCPU_GET_MPIDR(cpuid_to_pcpu[0]) == (target_cpu & CPU_AFF_MASK));
161 release_aps(void *dummy __unused)
165 /* Only release CPUs if they exist */
169 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
170 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
171 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
172 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
173 intr_pic_ipi_setup(IPI_STOP_HARD, "stop hard", ipi_stop, NULL);
174 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
176 atomic_store_rel_int(&aps_ready, 1);
177 /* Wake up the other CPUs */
183 printf("Release APs...");
186 for (i = 0; i < 2000; i++) {
187 if (atomic_load_acq_int(&smp_started) != 0) {
192 * Don't time out while we are making progress. Some large
193 * systems can take a while to start all CPUs.
195 if (smp_cpus > started) {
202 printf("APs not started\n");
204 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
207 init_secondary(uint64_t cpu)
214 * Verify that the value passed in 'cpu' argument (aka context_id) is
215 * valid. Some older U-Boot based PSCI implementations are buggy,
216 * they can pass random value in it.
218 mpidr = READ_SPECIALREG(mpidr_el1) & CPU_AFF_MASK;
219 if (cpu >= MAXCPU || cpuid_to_pcpu[cpu] == NULL ||
220 PCPU_GET_MPIDR(cpuid_to_pcpu[cpu]) != mpidr) {
221 for (cpu = 0; cpu < mp_maxid; cpu++)
222 if (cpuid_to_pcpu[cpu] != NULL &&
223 PCPU_GET_MPIDR(cpuid_to_pcpu[cpu]) == mpidr)
226 panic("MPIDR for this CPU is not in pcpu table");
229 pcpup = cpuid_to_pcpu[cpu];
231 * Set the pcpu pointer with a backup in tpidr_el1 to be
232 * loaded when entering the kernel from userland.
236 "msr tpidr_el1, %0" :: "r"(pcpup));
239 * Identify current CPU. This is necessary to setup
240 * affinity registers and to provide support for
241 * runtime chip identification.
243 * We need this before signalling the CPU is ready to
244 * let the boot CPU use the results.
246 pcpup->pc_midr = get_midr();
249 /* Ensure the stores in identify_cpu have completed */
250 atomic_thread_fence_acq_rel();
252 /* Signal the BSP and spin until it has released all APs. */
253 atomic_add_int(&aps_started, 1);
254 while (!atomic_load_int(&aps_ready))
255 __asm __volatile("wfe");
257 /* Initialize curthread */
258 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
259 pcpup->pc_curthread = pcpup->pc_idlethread;
262 /* Initialize curpmap to match TTBR0's current setting. */
263 pmap0 = vmspace_pmap(&vmspace0);
264 KASSERT(pmap_to_ttbr0(pmap0) == READ_SPECIALREG(ttbr0_el1),
265 ("pmap0 doesn't match cpu %ld's ttbr0", cpu));
266 pcpup->pc_curpmap = pmap0;
268 install_cpu_errata();
270 intr_pic_init_secondary();
272 /* Start per-CPU event timers. */
282 mtx_lock_spin(&ap_boot_mtx);
283 atomic_add_rel_32(&smp_cpus, 1);
284 if (smp_cpus == mp_ncpus) {
285 /* enable IPI's, tlb shootdown, freezes etc */
286 atomic_store_rel_int(&smp_started, 1);
288 mtx_unlock_spin(&ap_boot_mtx);
292 /* Enter the scheduler */
295 panic("scheduler returned us to init_secondary");
300 smp_after_idle_runnable(void *arg __unused)
307 KASSERT(smp_started != 0, ("%s: SMP not started yet", __func__));
310 * Wait for all APs to handle an interrupt. After that, we know that
311 * the APs have entered the scheduler at least once, so the boot stacks
314 smp_rendezvous(smp_no_rendezvous_barrier, NULL,
315 smp_no_rendezvous_barrier, NULL);
317 for (cpu = 1; cpu < mp_ncpus; cpu++) {
318 if (bootstacks[cpu] != NULL)
319 kmem_free((vm_offset_t)bootstacks[cpu],
323 SYSINIT(smp_after_idle_runnable, SI_SUB_SMP, SI_ORDER_ANY,
324 smp_after_idle_runnable, NULL);
327 * Send IPI thru interrupt controller.
330 pic_ipi_send(void *arg, cpuset_t cpus, u_int ipi)
333 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
336 * Ensure that this CPU's stores will be visible to IPI
337 * recipients before starting to send the interrupts.
341 PIC_IPI_SEND(intr_irq_root_dev, arg, cpus, ipi);
345 * Setup IPI handler on interrupt controller.
350 intr_pic_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand,
353 struct intr_irqsrc *isrc;
357 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
358 KASSERT(hand != NULL, ("%s: ipi %u no handler", __func__, ipi));
360 error = PIC_IPI_SETUP(intr_irq_root_dev, ipi, &isrc);
364 isrc->isrc_handlers++;
366 ii = intr_ipi_lookup(ipi);
367 KASSERT(ii->ii_count == NULL, ("%s: ipi %u reused", __func__, ipi));
369 ii->ii_handler = hand;
370 ii->ii_handler_arg = arg;
371 ii->ii_send = pic_ipi_send;
372 ii->ii_send_arg = isrc;
373 strlcpy(ii->ii_name, name, INTR_IPI_NAMELEN);
374 ii->ii_count = intr_ipi_setup_counters(name);
376 PIC_ENABLE_INTR(intr_irq_root_dev, isrc);
380 intr_ipi_send(cpuset_t cpus, u_int ipi)
384 ii = intr_ipi_lookup(ipi);
385 if (ii->ii_count == NULL)
386 panic("%s: not setup IPI %u", __func__, ipi);
388 ii->ii_send(ii->ii_send_arg, cpus, ipi);
392 ipi_ast(void *dummy __unused)
395 CTR0(KTR_SMP, "IPI_AST");
399 ipi_hardclock(void *dummy __unused)
402 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
407 ipi_preempt(void *dummy __unused)
409 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
410 sched_preempt(curthread);
414 ipi_rendezvous(void *dummy __unused)
417 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
418 smp_rendezvous_action();
422 ipi_stop(void *dummy __unused)
426 CTR0(KTR_SMP, "IPI_STOP");
428 cpu = PCPU_GET(cpuid);
429 savectx(&stoppcbs[cpu]);
431 /* Indicate we are stopped */
432 CPU_SET_ATOMIC(cpu, &stopped_cpus);
434 /* Wait for restart */
435 while (!CPU_ISSET(cpu, &started_cpus))
439 dbg_register_sync(NULL);
442 CPU_CLR_ATOMIC(cpu, &started_cpus);
443 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
444 CTR0(KTR_SMP, "IPI_STOP (restart)");
450 struct cpu_group *dom, *root;
453 root = smp_topo_alloc(1);
454 dom = smp_topo_alloc(vm_ndomains);
456 root->cg_parent = NULL;
457 root->cg_child = dom;
458 CPU_COPY(&all_cpus, &root->cg_mask);
459 root->cg_count = mp_ncpus;
460 root->cg_children = vm_ndomains;
461 root->cg_level = CG_SHARE_NONE;
465 * Redundant layers will be collapsed by the caller so we don't need a
466 * special case for a single domain.
468 for (i = 0; i < vm_ndomains; i++, dom++) {
469 dom->cg_parent = root;
470 dom->cg_child = NULL;
471 CPU_COPY(&cpuset_domain[i], &dom->cg_mask);
472 dom->cg_count = CPU_COUNT(&dom->cg_mask);
473 dom->cg_children = 0;
474 dom->cg_level = CG_SHARE_L3;
481 /* Determine if we running MP machine */
486 /* ARM64TODO: Read the u bit of mpidr_el1 to determine this */
491 enable_cpu_psci(uint64_t target_cpu, vm_paddr_t entry, u_int cpuid)
495 err = psci_cpu_on(target_cpu, entry, cpuid);
496 if (err != PSCI_RETVAL_SUCCESS) {
498 * Panic here if INVARIANTS are enabled and PSCI failed to
499 * start the requested CPU. psci_cpu_on() returns PSCI_MISSING
500 * to indicate we are unable to use it to start the given CPU.
502 KASSERT(err == PSCI_MISSING ||
503 (mp_quirks & MP_QUIRK_CPULIST) == MP_QUIRK_CPULIST,
504 ("Failed to start CPU %u (%lx), error %d\n",
505 cpuid, target_cpu, err));
513 enable_cpu_spin(uint64_t cpu, vm_paddr_t entry, vm_paddr_t release_paddr)
515 vm_paddr_t *release_addr;
517 release_addr = pmap_mapdev(release_paddr, sizeof(*release_addr));
518 if (release_addr == NULL)
521 *release_addr = entry;
522 pmap_unmapdev((vm_offset_t)release_addr, sizeof(*release_addr));
533 * Starts a given CPU. If the CPU is already running, i.e. it is the boot CPU,
534 * do nothing. Returns true if the CPU is present and running.
537 start_cpu(u_int cpuid, uint64_t target_cpu, int domain, vm_paddr_t release_addr)
540 vm_offset_t pcpu_mem;
545 /* Check we are able to start this cpu */
546 if (cpuid > mp_maxid)
550 if (is_boot_cpu(target_cpu))
553 KASSERT(cpuid < MAXCPU, ("Too many CPUs"));
555 size = round_page(sizeof(*pcpup) + DPCPU_SIZE);
556 pcpu_mem = kmem_malloc_domainset(DOMAINSET_PREF(domain), size,
558 pmap_disable_promotion(pcpu_mem, size);
560 pcpup = (struct pcpu *)pcpu_mem;
561 pcpu_init(pcpup, cpuid, sizeof(struct pcpu));
562 pcpup->pc_mpidr_low = target_cpu & CPU_AFF_MASK;
563 pcpup->pc_mpidr_high = (target_cpu & CPU_AFF_MASK) >> 32;
565 dpcpu[cpuid - 1] = (void *)(pcpup + 1);
566 dpcpu_init(dpcpu[cpuid - 1], cpuid);
568 bootstacks[cpuid] = (void *)kmem_malloc_domainset(
569 DOMAINSET_PREF(domain), MP_BOOTSTACK_SIZE, M_WAITOK | M_ZERO);
571 naps = atomic_load_int(&aps_started);
572 bootstack = (char *)bootstacks[cpuid] + MP_BOOTSTACK_SIZE;
574 printf("Starting CPU %u (%lx)\n", cpuid, target_cpu);
575 pa = pmap_extract(kernel_pmap, (vm_offset_t)mpentry);
578 * A limited set of hardware we support can only do spintables and
579 * remain useful, due to lack of EL3. Thus, we'll usually fall into the
582 MPASS(release_addr == 0 || !psci_present);
583 if (release_addr != 0)
584 err = enable_cpu_spin(target_cpu, pa, release_addr);
586 err = enable_cpu_psci(target_cpu, pa, cpuid);
590 dpcpu[cpuid - 1] = NULL;
591 kmem_free((vm_offset_t)bootstacks[cpuid], MP_BOOTSTACK_SIZE);
592 kmem_free(pcpu_mem, size);
593 bootstacks[cpuid] = NULL;
598 /* Wait for the AP to switch to its boot stack. */
599 while (atomic_load_int(&aps_started) < naps + 1)
601 CPU_SET(cpuid, &all_cpus);
608 madt_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
610 ACPI_MADT_GENERIC_INTERRUPT *intr;
615 switch(entry->Type) {
616 case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
617 intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
620 if (is_boot_cpu(intr->ArmMpidr))
628 domain = acpi_pxm_get_cpu_locality(intr->Uid);
630 if (start_cpu(id, intr->ArmMpidr, domain, 0)) {
631 MPASS(cpuid_to_pcpu[id] != NULL);
632 cpuid_to_pcpu[id]->pc_acpi_id = intr->Uid;
634 * Don't increment for the boot CPU, its CPU ID is
637 if (!is_boot_cpu(intr->ArmMpidr))
650 ACPI_TABLE_MADT *madt;
654 physaddr = acpi_find_table(ACPI_SIG_MADT);
658 madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
660 printf("Unable to map the MADT, not starting APs\n");
663 /* Boot CPU is always 0 */
665 acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
666 madt_handler, &cpuid);
668 acpi_unmap_table(madt);
671 acpi_pxm_set_cpu_locality();
678 * Failure is indicated by failing to populate *release_addr.
681 populate_release_addr(phandle_t node, vm_paddr_t *release_addr)
685 if (OF_getencprop(node, "cpu-release-addr", buf, sizeof(buf)) !=
689 *release_addr = (((uintptr_t)buf[0] << 32) | buf[1]);
693 start_cpu_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
696 vm_paddr_t release_addr;
702 if (addr_size == 2) {
704 target_cpu |= reg[1];
707 if (is_boot_cpu(target_cpu))
713 * If PSCI is present, we'll always use that -- the cpu_on method is
714 * mandated in both v0.1 and v0.2. We'll check the enable-method if
715 * we don't have PSCI and use spin table if it's provided.
718 if (!psci_present && cpuid != 0) {
719 if (OF_getprop_alloc(node, "enable-method",
720 (void **)&enable_method) <= 0)
723 if (strcmp(enable_method, "spin-table") != 0) {
724 OF_prop_free(enable_method);
728 OF_prop_free(enable_method);
729 populate_release_addr(node, &release_addr);
730 if (release_addr == 0) {
731 printf("Failed to fetch release address for CPU %u",
737 if (!start_cpu(cpuid, target_cpu, 0, release_addr))
741 * Don't increment for the boot CPU, its CPU ID is reserved.
743 if (!is_boot_cpu(target_cpu))
746 /* Try to read the numa node of this cpu */
747 if (vm_ndomains == 1 ||
748 OF_getencprop(node, "numa-node-id", &domain, sizeof(domain)) <= 0)
750 cpuid_to_pcpu[cpuid]->pc_domain = domain;
751 if (domain < MAXMEMDOM)
752 CPU_SET(cpuid, &cpuset_domain[domain]);
762 for (i = 0; fdt_quirks[i].compat != NULL; i++) {
763 if (ofw_bus_node_is_compatible(node,
764 fdt_quirks[i].compat) != 0) {
765 mp_quirks = fdt_quirks[i].quirks;
769 ofw_cpu_early_foreach(start_cpu_fdt, true);
773 /* Initialize and fire up non-boot processors */
779 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
781 /* CPU 0 is always boot CPU. */
782 CPU_SET(0, &all_cpus);
783 mpidr = READ_SPECIALREG(mpidr_el1) & CPU_AFF_MASK;
784 cpuid_to_pcpu[0]->pc_mpidr_low = mpidr;
785 cpuid_to_pcpu[0]->pc_mpidr_high = mpidr >> 32;
787 switch(arm64_bus_method) {
790 mp_quirks = MP_QUIRK_CPULIST;
804 /* Introduce rest of cores to the world */
806 cpu_mp_announce(void)
812 cpu_count_acpi_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
814 ACPI_MADT_GENERIC_INTERRUPT *intr;
817 switch(entry->Type) {
818 case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
819 intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
830 ACPI_TABLE_MADT *madt;
834 physaddr = acpi_find_table(ACPI_SIG_MADT);
838 madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
840 printf("Unable to map the MADT, not starting APs\n");
845 acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
846 cpu_count_acpi_handler, &cores);
848 acpi_unmap_table(madt);
855 cpu_mp_setmaxid(void)
862 switch(arm64_bus_method) {
865 cores = cpu_count_acpi();
867 cores = MIN(cores, MAXCPU);
869 printf("Found %d CPUs in the ACPI tables\n",
872 mp_maxid = cores - 1;
878 cores = ofw_cpu_early_foreach(NULL, false);
880 cores = MIN(cores, MAXCPU);
882 printf("Found %d CPUs in the device tree\n",
885 mp_maxid = cores - 1;
891 printf("No CPU data, limiting to 1 core\n");
895 if (TUNABLE_INT_FETCH("hw.ncpu", &cores)) {
896 if (cores > 0 && cores < mp_ncpus) {
898 mp_maxid = cores - 1;
906 static struct intr_ipi *
907 intr_ipi_lookup(u_int ipi)
910 if (ipi >= INTR_IPI_COUNT)
911 panic("%s: no such IPI %u", __func__, ipi);
913 return (&ipi_sources[ipi]);
917 * interrupt controller dispatch function for IPIs. It should
918 * be called straight from the interrupt controller, when associated
919 * interrupt source is learned. Or from anybody who has an interrupt
923 intr_ipi_dispatch(u_int ipi, struct trapframe *tf)
928 ii = intr_ipi_lookup(ipi);
929 if (ii->ii_count == NULL)
930 panic("%s: not setup IPI %u", __func__, ipi);
932 intr_ipi_increment_count(ii->ii_count, PCPU_GET(cpuid));
935 * Supply ipi filter with trapframe argument
936 * if none is registered.
938 arg = ii->ii_handler_arg != NULL ? ii->ii_handler_arg : tf;
944 * Map IPI into interrupt controller.
949 ipi_map(struct intr_irqsrc *isrc, u_int ipi)
954 if (ipi >= INTR_IPI_COUNT)
955 panic("%s: no such IPI %u", __func__, ipi);
957 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
959 isrc->isrc_type = INTR_ISRCT_NAMESPACE;
960 isrc->isrc_nspc_type = INTR_IRQ_NSPC_IPI;
961 isrc->isrc_nspc_num = ipi_next_num;
963 error = PIC_REGISTER(intr_irq_root_dev, isrc, &is_percpu);
965 isrc->isrc_dev = intr_irq_root_dev;
972 * Setup IPI handler to interrupt source.
974 * Note that there could be more ways how to send and receive IPIs
975 * on a platform like fast interrupts for example. In that case,
976 * one can call this function with ASIF_NOALLOC flag set and then
977 * call intr_ipi_dispatch() when appropriate.
982 intr_ipi_set_handler(u_int ipi, const char *name, intr_ipi_filter_t *filter,
983 void *arg, u_int flags)
985 struct intr_irqsrc *isrc;
991 isrc = intr_ipi_lookup(ipi);
992 if (isrc->isrc_ipifilter != NULL)
995 if ((flags & AISHF_NOALLOC) == 0) {
996 error = ipi_map(isrc, ipi);
1001 isrc->isrc_ipifilter = filter;
1002 isrc->isrc_arg = arg;
1003 isrc->isrc_handlers = 1;
1004 isrc->isrc_count = intr_ipi_setup_counters(name);
1005 isrc->isrc_index = 0; /* it should not be used in IPI case */
1007 if (isrc->isrc_dev != NULL) {
1008 PIC_ENABLE_INTR(isrc->isrc_dev, isrc);
1009 PIC_ENABLE_SOURCE(isrc->isrc_dev, isrc);
1017 ipi_all_but_self(u_int ipi)
1022 CPU_CLR(PCPU_GET(cpuid), &cpus);
1023 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1024 intr_ipi_send(cpus, ipi);
1028 ipi_cpu(int cpu, u_int ipi)
1033 CPU_SET(cpu, &cpus);
1035 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
1036 intr_ipi_send(cpus, ipi);
1040 ipi_selected(cpuset_t cpus, u_int ipi)
1043 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1044 intr_ipi_send(cpus, ipi);