2 * Copyright (c) 2015-2016 The FreeBSD Foundation
5 * This software was developed by Andrew Turner under
6 * sponsorship from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include "opt_kstack_pages.h"
32 #include "opt_platform.h"
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/malloc.h>
43 #include <sys/module.h>
44 #include <sys/mutex.h>
46 #include <sys/sched.h>
51 #include <vm/vm_extern.h>
52 #include <vm/vm_kern.h>
54 #include <machine/debug_monitor.h>
55 #include <machine/intr.h>
56 #include <machine/smp.h>
58 #include <machine/vfp.h>
62 #include <dev/ofw/openfirm.h>
63 #include <dev/ofw/ofw_cpu.h>
66 #include <dev/psci/psci.h>
70 typedef void intr_ipi_send_t(void *, cpuset_t, u_int);
71 typedef void intr_ipi_handler_t(void *);
73 #define INTR_IPI_NAMELEN (MAXCOMLEN + 1)
75 intr_ipi_handler_t * ii_handler;
76 void * ii_handler_arg;
77 intr_ipi_send_t * ii_send;
79 char ii_name[INTR_IPI_NAMELEN];
83 static struct intr_ipi ipi_sources[INTR_IPI_COUNT];
85 static struct intr_ipi *intr_ipi_lookup(u_int);
86 static void intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *,
89 boolean_t ofw_cpu_reg(phandle_t node, u_int, cell_t *);
91 extern struct pcpu __pcpu[];
100 static device_identify_t arm64_cpu_identify;
101 static device_probe_t arm64_cpu_probe;
102 static device_attach_t arm64_cpu_attach;
104 static void ipi_ast(void *);
105 static void ipi_hardclock(void *);
106 static void ipi_preempt(void *);
107 static void ipi_rendezvous(void *);
108 static void ipi_stop(void *);
110 static int ipi_handler(void *arg);
112 struct mtx ap_boot_mtx;
113 struct pcb stoppcbs[MAXCPU];
116 static uint32_t cpu_reg[MAXCPU][2];
118 static device_t cpu_list[MAXCPU];
121 * Not all systems boot from the first CPU in the device tree. To work around
122 * this we need to find which CPU we have booted from so when we later
123 * enable the secondary CPUs we skip this one.
125 static int cpu0 = -1;
127 void mpentry(unsigned long cpuid);
128 void init_secondary(uint64_t);
130 uint8_t secondary_stacks[MAXCPU - 1][PAGE_SIZE * KSTACK_PAGES] __aligned(16);
132 /* Set to 1 once we're ready to let the APs out of the pen. */
133 volatile int aps_ready = 0;
135 /* Temporary variables for init_secondary() */
136 void *dpcpu[MAXCPU - 1];
138 static device_method_t arm64_cpu_methods[] = {
139 /* Device interface */
140 DEVMETHOD(device_identify, arm64_cpu_identify),
141 DEVMETHOD(device_probe, arm64_cpu_probe),
142 DEVMETHOD(device_attach, arm64_cpu_attach),
147 static devclass_t arm64_cpu_devclass;
148 static driver_t arm64_cpu_driver = {
154 DRIVER_MODULE(arm64_cpu, cpu, arm64_cpu_driver, arm64_cpu_devclass, 0, 0);
157 arm64_cpu_identify(driver_t *driver, device_t parent)
160 if (device_find_child(parent, "arm64_cpu", -1) != NULL)
162 if (BUS_ADD_CHILD(parent, 0, "arm64_cpu", -1) == NULL)
163 device_printf(parent, "add child failed\n");
167 arm64_cpu_probe(device_t dev)
171 cpuid = device_get_unit(dev);
172 if (cpuid >= MAXCPU || cpuid > mp_maxid)
180 arm64_cpu_attach(device_t dev)
187 cpuid = device_get_unit(dev);
189 if (cpuid >= MAXCPU || cpuid > mp_maxid)
191 KASSERT(cpu_list[cpuid] == NULL, ("Already have cpu %u", cpuid));
193 reg = cpu_get_cpuid(dev, ®_size);
198 device_printf(dev, "register <");
199 for (i = 0; i < reg_size; i++)
200 printf("%s%x", (i == 0) ? "" : " ", reg[i]);
204 /* Set the device to start it later */
205 cpu_list[cpuid] = dev;
211 release_aps(void *dummy __unused)
215 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
216 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
217 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
218 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
219 intr_pic_ipi_setup(IPI_STOP_HARD, "stop hard", ipi_stop, NULL);
220 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
222 atomic_store_rel_int(&aps_ready, 1);
223 /* Wake up the other CPUs */
224 __asm __volatile("sev");
226 printf("Release APs\n");
228 for (i = 0; i < 2000; i++) {
230 for (cpu = 0; cpu <= mp_maxid; cpu++) {
233 print_cpu_features(cpu);
240 printf("APs not started\n");
242 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
245 init_secondary(uint64_t cpu)
249 pcpup = &__pcpu[cpu];
251 * Set the pcpu pointer with a backup in tpidr_el1 to be
252 * loaded when entering the kernel from userland.
256 "msr tpidr_el1, %0" :: "r"(pcpup));
258 /* Spin until the BSP releases the APs */
260 __asm __volatile("wfe");
262 /* Initialize curthread */
263 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
264 pcpup->pc_curthread = pcpup->pc_idlethread;
265 pcpup->pc_curpcb = pcpup->pc_idlethread->td_pcb;
268 * Identify current CPU. This is necessary to setup
269 * affinity registers and to provide support for
270 * runtime chip identification.
274 intr_pic_init_secondary();
276 /* Start per-CPU event timers. */
285 /* Enable interrupts */
288 mtx_lock_spin(&ap_boot_mtx);
290 atomic_add_rel_32(&smp_cpus, 1);
292 if (smp_cpus == mp_ncpus) {
293 /* enable IPI's, tlb shootdown, freezes etc */
294 atomic_store_rel_int(&smp_started, 1);
297 mtx_unlock_spin(&ap_boot_mtx);
299 /* Enter the scheduler */
302 panic("scheduler returned us to init_secondary");
307 * Send IPI thru interrupt controller.
310 pic_ipi_send(void *arg, cpuset_t cpus, u_int ipi)
313 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
314 PIC_IPI_SEND(intr_irq_root_dev, arg, cpus, ipi);
318 * Setup IPI handler on interrupt controller.
323 intr_pic_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand,
326 struct intr_irqsrc *isrc;
330 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
331 KASSERT(hand != NULL, ("%s: ipi %u no handler", __func__, ipi));
333 error = PIC_IPI_SETUP(intr_irq_root_dev, ipi, &isrc);
337 isrc->isrc_handlers++;
339 ii = intr_ipi_lookup(ipi);
340 KASSERT(ii->ii_count == NULL, ("%s: ipi %u reused", __func__, ipi));
342 ii->ii_handler = hand;
343 ii->ii_handler_arg = arg;
344 ii->ii_send = pic_ipi_send;
345 ii->ii_send_arg = isrc;
346 strlcpy(ii->ii_name, name, INTR_IPI_NAMELEN);
347 ii->ii_count = intr_ipi_setup_counters(name);
351 intr_ipi_send(cpuset_t cpus, u_int ipi)
355 ii = intr_ipi_lookup(ipi);
356 if (ii->ii_count == NULL)
357 panic("%s: not setup IPI %u", __func__, ipi);
359 ii->ii_send(ii->ii_send_arg, cpus, ipi);
363 ipi_ast(void *dummy __unused)
366 CTR0(KTR_SMP, "IPI_AST");
370 ipi_hardclock(void *dummy __unused)
373 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
378 ipi_preempt(void *dummy __unused)
380 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
381 sched_preempt(curthread);
385 ipi_rendezvous(void *dummy __unused)
388 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
389 smp_rendezvous_action();
393 ipi_stop(void *dummy __unused)
397 CTR0(KTR_SMP, "IPI_STOP");
399 cpu = PCPU_GET(cpuid);
400 savectx(&stoppcbs[cpu]);
402 /* Indicate we are stopped */
403 CPU_SET_ATOMIC(cpu, &stopped_cpus);
405 /* Wait for restart */
406 while (!CPU_ISSET(cpu, &started_cpus))
409 CPU_CLR_ATOMIC(cpu, &started_cpus);
410 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
411 CTR0(KTR_SMP, "IPI_STOP (restart)");
418 return (smp_topo_none());
421 /* Determine if we running MP machine */
426 /* ARM64TODO: Read the u bit of mpidr_el1 to determine this */
432 cpu_init_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
440 /* Check we are able to start this cpu */
444 KASSERT(id < MAXCPU, ("Too many CPUs"));
446 KASSERT(addr_size == 1 || addr_size == 2, ("Invalid register size"));
448 cpu_reg[id][0] = reg[0];
450 cpu_reg[id][1] = reg[1];
453 /* We are already running on cpu 0 */
458 * Rotate the CPU IDs to put the boot CPU as CPU 0. We keep the other
459 * CPUs ordered as the are likely grouped into clusters so it can be
460 * useful to keep that property, e.g. for the GICv3 driver to send
461 * an IPI to all CPUs in the cluster.
465 cpuid += mp_maxid + 1;
468 pcpup = &__pcpu[cpuid];
469 pcpu_init(pcpup, cpuid, sizeof(struct pcpu));
471 dpcpu[cpuid - 1] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
473 dpcpu_init(dpcpu[cpuid - 1], cpuid);
476 if (addr_size == 2) {
478 target_cpu |= reg[1];
481 printf("Starting CPU %u (%lx)\n", cpuid, target_cpu);
482 pa = pmap_extract(kernel_pmap, (vm_offset_t)mpentry);
484 err = psci_cpu_on(target_cpu, pa, cpuid);
485 if (err != PSCI_RETVAL_SUCCESS) {
486 /* Panic here if INVARIANTS are enabled */
487 KASSERT(0, ("Failed to start CPU %u (%lx)\n", id,
491 kmem_free(kernel_arena, (vm_offset_t)dpcpu[cpuid - 1],
493 dpcpu[cpuid - 1] = NULL;
494 /* Notify the user that the CPU failed to start */
495 printf("Failed to start CPU %u (%lx)\n", id, target_cpu);
497 CPU_SET(cpuid, &all_cpus);
503 /* Initialize and fire up non-boot processors */
508 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
510 CPU_SET(0, &all_cpus);
512 switch(cpu_enum_method) {
515 KASSERT(cpu0 >= 0, ("Current CPU was not found"));
516 ofw_cpu_early_foreach(cpu_init_fdt, true);
524 /* Introduce rest of cores to the world */
526 cpu_mp_announce(void)
531 cpu_find_cpu0_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
533 uint64_t mpidr_fdt, mpidr_reg;
537 if (addr_size == 2) {
542 mpidr_reg = READ_SPECIALREG(mpidr_el1);
544 if ((mpidr_reg & 0xff00fffffful) == mpidr_fdt)
552 cpu_mp_setmaxid(void)
557 cores = ofw_cpu_early_foreach(cpu_find_cpu0_fdt, false);
559 cores = MIN(cores, MAXCPU);
561 printf("Found %d CPUs in the device tree\n", cores);
563 mp_maxid = cores - 1;
564 cpu_enum_method = CPUS_FDT;
570 printf("No CPU data, limiting to 1 core\n");
578 static struct intr_ipi *
579 intr_ipi_lookup(u_int ipi)
582 if (ipi >= INTR_IPI_COUNT)
583 panic("%s: no such IPI %u", __func__, ipi);
585 return (&ipi_sources[ipi]);
589 * interrupt controller dispatch function for IPIs. It should
590 * be called straight from the interrupt controller, when associated
591 * interrupt source is learned. Or from anybody who has an interrupt
595 intr_ipi_dispatch(u_int ipi, struct trapframe *tf)
600 ii = intr_ipi_lookup(ipi);
601 if (ii->ii_count == NULL)
602 panic("%s: not setup IPI %u", __func__, ipi);
604 intr_ipi_increment_count(ii->ii_count, PCPU_GET(cpuid));
607 * Supply ipi filter with trapframe argument
608 * if none is registered.
610 arg = ii->ii_handler_arg != NULL ? ii->ii_handler_arg : tf;
616 * Map IPI into interrupt controller.
621 ipi_map(struct intr_irqsrc *isrc, u_int ipi)
626 if (ipi >= INTR_IPI_COUNT)
627 panic("%s: no such IPI %u", __func__, ipi);
629 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
631 isrc->isrc_type = INTR_ISRCT_NAMESPACE;
632 isrc->isrc_nspc_type = INTR_IRQ_NSPC_IPI;
633 isrc->isrc_nspc_num = ipi_next_num;
635 error = PIC_REGISTER(intr_irq_root_dev, isrc, &is_percpu);
637 isrc->isrc_dev = intr_irq_root_dev;
644 * Setup IPI handler to interrupt source.
646 * Note that there could be more ways how to send and receive IPIs
647 * on a platform like fast interrupts for example. In that case,
648 * one can call this function with ASIF_NOALLOC flag set and then
649 * call intr_ipi_dispatch() when appropriate.
654 intr_ipi_set_handler(u_int ipi, const char *name, intr_ipi_filter_t *filter,
655 void *arg, u_int flags)
657 struct intr_irqsrc *isrc;
663 isrc = intr_ipi_lookup(ipi);
664 if (isrc->isrc_ipifilter != NULL)
667 if ((flags & AISHF_NOALLOC) == 0) {
668 error = ipi_map(isrc, ipi);
673 isrc->isrc_ipifilter = filter;
674 isrc->isrc_arg = arg;
675 isrc->isrc_handlers = 1;
676 isrc->isrc_count = intr_ipi_setup_counters(name);
677 isrc->isrc_index = 0; /* it should not be used in IPI case */
679 if (isrc->isrc_dev != NULL) {
680 PIC_ENABLE_INTR(isrc->isrc_dev, isrc);
681 PIC_ENABLE_SOURCE(isrc->isrc_dev, isrc);
689 ipi_all_but_self(u_int ipi)
694 CPU_CLR(PCPU_GET(cpuid), &cpus);
695 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
696 intr_ipi_send(cpus, ipi);
700 ipi_cpu(int cpu, u_int ipi)
707 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
708 intr_ipi_send(cpus, ipi);
712 ipi_selected(cpuset_t cpus, u_int ipi)
715 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
716 intr_ipi_send(cpus, ipi);