2 * Copyright (c) 2015-2016 The FreeBSD Foundation
4 * This software was developed by Andrew Turner under
5 * sponsorship from the FreeBSD Foundation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include "opt_kstack_pages.h"
33 #include "opt_platform.h"
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/systm.h>
43 #include <sys/domainset.h>
44 #include <sys/kernel.h>
46 #include <sys/malloc.h>
47 #include <sys/module.h>
48 #include <sys/mutex.h>
51 #include <sys/sched.h>
56 #include <vm/vm_extern.h>
57 #include <vm/vm_kern.h>
58 #include <vm/vm_map.h>
60 #include <machine/machdep.h>
61 #include <machine/cpu.h>
62 #include <machine/debug_monitor.h>
63 #include <machine/intr.h>
64 #include <machine/smp.h>
66 #include <machine/vfp.h>
70 #include <contrib/dev/acpica/include/acpi.h>
71 #include <dev/acpica/acpivar.h>
75 #include <dev/ofw/openfirm.h>
76 #include <dev/ofw/ofw_bus.h>
77 #include <dev/ofw/ofw_bus_subr.h>
78 #include <dev/ofw/ofw_cpu.h>
81 #include <dev/psci/psci.h>
85 #define MP_BOOTSTACK_SIZE (kstack_pages * PAGE_SIZE)
87 #define MP_QUIRK_CPULIST 0x01 /* The list of cpus may be wrong, */
88 /* don't panic if one fails to start */
89 static uint32_t mp_quirks;
96 { "arm,foundation-aarch64", MP_QUIRK_CPULIST },
97 { "arm,fvp-base", MP_QUIRK_CPULIST },
98 /* This is incorrect in some DTS files */
99 { "arm,vfp-base", MP_QUIRK_CPULIST },
104 typedef void intr_ipi_send_t(void *, cpuset_t, u_int);
105 typedef void intr_ipi_handler_t(void *);
107 #define INTR_IPI_NAMELEN (MAXCOMLEN + 1)
109 intr_ipi_handler_t * ii_handler;
110 void * ii_handler_arg;
111 intr_ipi_send_t * ii_send;
113 char ii_name[INTR_IPI_NAMELEN];
117 static struct intr_ipi ipi_sources[INTR_IPI_COUNT];
119 static struct intr_ipi *intr_ipi_lookup(u_int);
120 static void intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *,
123 static void ipi_ast(void *);
124 static void ipi_hardclock(void *);
125 static void ipi_preempt(void *);
126 static void ipi_rendezvous(void *);
127 static void ipi_stop(void *);
129 struct pcb stoppcbs[MAXCPU];
132 static u_int fdt_cpuid;
135 void mpentry(unsigned long cpuid);
136 void init_secondary(uint64_t);
138 /* Synchronize AP startup. */
139 static struct mtx ap_boot_mtx;
141 /* Stacks for AP initialization, discarded once idle threads are started. */
143 static void *bootstacks[MAXCPU];
145 /* Count of started APs, used to synchronize access to bootstack. */
146 static volatile int aps_started;
148 /* Set to 1 once we're ready to let the APs out of the pen. */
149 static volatile int aps_ready;
151 /* Temporary variables for init_secondary() */
152 void *dpcpu[MAXCPU - 1];
155 is_boot_cpu(uint64_t target_cpu)
158 return (PCPU_GET_MPIDR(cpuid_to_pcpu[0]) == (target_cpu & CPU_AFF_MASK));
162 release_aps(void *dummy __unused)
166 /* Only release CPUs if they exist */
170 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
171 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
172 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
173 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
174 intr_pic_ipi_setup(IPI_STOP_HARD, "stop hard", ipi_stop, NULL);
175 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
177 atomic_store_rel_int(&aps_ready, 1);
178 /* Wake up the other CPUs */
184 printf("Release APs...");
187 for (i = 0; i < 2000; i++) {
188 if (atomic_load_acq_int(&smp_started) != 0) {
193 * Don't time out while we are making progress. Some large
194 * systems can take a while to start all CPUs.
196 if (smp_cpus > started) {
203 printf("APs not started\n");
205 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
208 init_secondary(uint64_t cpu)
214 ptrauth_mp_start(cpu);
217 * Verify that the value passed in 'cpu' argument (aka context_id) is
218 * valid. Some older U-Boot based PSCI implementations are buggy,
219 * they can pass random value in it.
221 mpidr = READ_SPECIALREG(mpidr_el1) & CPU_AFF_MASK;
222 if (cpu >= MAXCPU || cpuid_to_pcpu[cpu] == NULL ||
223 PCPU_GET_MPIDR(cpuid_to_pcpu[cpu]) != mpidr) {
224 for (cpu = 0; cpu < mp_maxid; cpu++)
225 if (cpuid_to_pcpu[cpu] != NULL &&
226 PCPU_GET_MPIDR(cpuid_to_pcpu[cpu]) == mpidr)
229 panic("MPIDR for this CPU is not in pcpu table");
232 pcpup = cpuid_to_pcpu[cpu];
234 * Set the pcpu pointer with a backup in tpidr_el1 to be
235 * loaded when entering the kernel from userland.
239 "msr tpidr_el1, %0" :: "r"(pcpup));
242 * Identify current CPU. This is necessary to setup
243 * affinity registers and to provide support for
244 * runtime chip identification.
246 * We need this before signalling the CPU is ready to
247 * let the boot CPU use the results.
249 pcpup->pc_midr = get_midr();
252 /* Ensure the stores in identify_cpu have completed */
253 atomic_thread_fence_acq_rel();
255 /* Signal the BSP and spin until it has released all APs. */
256 atomic_add_int(&aps_started, 1);
257 while (!atomic_load_int(&aps_ready))
258 __asm __volatile("wfe");
260 /* Initialize curthread */
261 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
262 pcpup->pc_curthread = pcpup->pc_idlethread;
265 /* Initialize curpmap to match TTBR0's current setting. */
266 pmap0 = vmspace_pmap(&vmspace0);
267 KASSERT(pmap_to_ttbr0(pmap0) == READ_SPECIALREG(ttbr0_el1),
268 ("pmap0 doesn't match cpu %ld's ttbr0", cpu));
269 pcpup->pc_curpmap = pmap0;
271 install_cpu_errata();
273 intr_pic_init_secondary();
275 /* Start per-CPU event timers. */
285 mtx_lock_spin(&ap_boot_mtx);
286 atomic_add_rel_32(&smp_cpus, 1);
287 if (smp_cpus == mp_ncpus) {
288 /* enable IPI's, tlb shootdown, freezes etc */
289 atomic_store_rel_int(&smp_started, 1);
291 mtx_unlock_spin(&ap_boot_mtx);
295 /* Enter the scheduler */
298 panic("scheduler returned us to init_secondary");
303 smp_after_idle_runnable(void *arg __unused)
310 KASSERT(smp_started != 0, ("%s: SMP not started yet", __func__));
313 * Wait for all APs to handle an interrupt. After that, we know that
314 * the APs have entered the scheduler at least once, so the boot stacks
317 smp_rendezvous(smp_no_rendezvous_barrier, NULL,
318 smp_no_rendezvous_barrier, NULL);
320 for (cpu = 1; cpu < mp_ncpus; cpu++) {
321 if (bootstacks[cpu] != NULL)
322 kmem_free(bootstacks[cpu], MP_BOOTSTACK_SIZE);
325 SYSINIT(smp_after_idle_runnable, SI_SUB_SMP, SI_ORDER_ANY,
326 smp_after_idle_runnable, NULL);
329 * Send IPI thru interrupt controller.
332 pic_ipi_send(void *arg, cpuset_t cpus, u_int ipi)
335 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
338 * Ensure that this CPU's stores will be visible to IPI
339 * recipients before starting to send the interrupts.
343 PIC_IPI_SEND(intr_irq_root_dev, arg, cpus, ipi);
347 * Setup IPI handler on interrupt controller.
352 intr_pic_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand,
355 struct intr_irqsrc *isrc;
359 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
360 KASSERT(hand != NULL, ("%s: ipi %u no handler", __func__, ipi));
362 error = PIC_IPI_SETUP(intr_irq_root_dev, ipi, &isrc);
366 isrc->isrc_handlers++;
368 ii = intr_ipi_lookup(ipi);
369 KASSERT(ii->ii_count == NULL, ("%s: ipi %u reused", __func__, ipi));
371 ii->ii_handler = hand;
372 ii->ii_handler_arg = arg;
373 ii->ii_send = pic_ipi_send;
374 ii->ii_send_arg = isrc;
375 strlcpy(ii->ii_name, name, INTR_IPI_NAMELEN);
376 ii->ii_count = intr_ipi_setup_counters(name);
378 PIC_ENABLE_INTR(intr_irq_root_dev, isrc);
382 intr_ipi_send(cpuset_t cpus, u_int ipi)
386 ii = intr_ipi_lookup(ipi);
387 if (ii->ii_count == NULL)
388 panic("%s: not setup IPI %u", __func__, ipi);
390 ii->ii_send(ii->ii_send_arg, cpus, ipi);
394 ipi_ast(void *dummy __unused)
397 CTR0(KTR_SMP, "IPI_AST");
401 ipi_hardclock(void *dummy __unused)
404 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
409 ipi_preempt(void *dummy __unused)
411 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
412 sched_preempt(curthread);
416 ipi_rendezvous(void *dummy __unused)
419 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
420 smp_rendezvous_action();
424 ipi_stop(void *dummy __unused)
428 CTR0(KTR_SMP, "IPI_STOP");
430 cpu = PCPU_GET(cpuid);
431 savectx(&stoppcbs[cpu]);
433 /* Indicate we are stopped */
434 CPU_SET_ATOMIC(cpu, &stopped_cpus);
436 /* Wait for restart */
437 while (!CPU_ISSET(cpu, &started_cpus))
441 dbg_register_sync(NULL);
444 CPU_CLR_ATOMIC(cpu, &started_cpus);
445 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
446 CTR0(KTR_SMP, "IPI_STOP (restart)");
452 struct cpu_group *dom, *root;
455 root = smp_topo_alloc(1);
456 dom = smp_topo_alloc(vm_ndomains);
458 root->cg_parent = NULL;
459 root->cg_child = dom;
460 CPU_COPY(&all_cpus, &root->cg_mask);
461 root->cg_count = mp_ncpus;
462 root->cg_children = vm_ndomains;
463 root->cg_level = CG_SHARE_NONE;
467 * Redundant layers will be collapsed by the caller so we don't need a
468 * special case for a single domain.
470 for (i = 0; i < vm_ndomains; i++, dom++) {
471 dom->cg_parent = root;
472 dom->cg_child = NULL;
473 CPU_COPY(&cpuset_domain[i], &dom->cg_mask);
474 dom->cg_count = CPU_COUNT(&dom->cg_mask);
475 dom->cg_children = 0;
476 dom->cg_level = CG_SHARE_L3;
483 /* Determine if we running MP machine */
488 /* ARM64TODO: Read the u bit of mpidr_el1 to determine this */
493 * Starts a given CPU. If the CPU is already running, i.e. it is the boot CPU,
494 * do nothing. Returns true if the CPU is present and running.
497 start_cpu(u_int cpuid, uint64_t target_cpu, int domain)
504 /* Check we are able to start this cpu */
505 if (cpuid > mp_maxid)
509 if (is_boot_cpu(target_cpu))
512 KASSERT(cpuid < MAXCPU, ("Too many CPUs"));
514 size = round_page(sizeof(*pcpup) + DPCPU_SIZE);
515 pcpup = kmem_malloc_domainset(DOMAINSET_PREF(domain), size,
517 pmap_disable_promotion((vm_offset_t)pcpup, size);
518 pcpu_init(pcpup, cpuid, sizeof(struct pcpu));
519 pcpup->pc_mpidr_low = target_cpu & CPU_AFF_MASK;
520 pcpup->pc_mpidr_high = (target_cpu & CPU_AFF_MASK) >> 32;
522 dpcpu[cpuid - 1] = (void *)(pcpup + 1);
523 dpcpu_init(dpcpu[cpuid - 1], cpuid);
525 bootstacks[cpuid] = kmem_malloc_domainset(DOMAINSET_PREF(domain),
526 MP_BOOTSTACK_SIZE, M_WAITOK | M_ZERO);
528 naps = atomic_load_int(&aps_started);
529 bootstack = (char *)bootstacks[cpuid] + MP_BOOTSTACK_SIZE;
531 printf("Starting CPU %u (%lx)\n", cpuid, target_cpu);
532 pa = pmap_extract(kernel_pmap, (vm_offset_t)mpentry);
533 err = psci_cpu_on(target_cpu, pa, cpuid);
534 if (err != PSCI_RETVAL_SUCCESS) {
536 * Panic here if INVARIANTS are enabled and PSCI failed to
537 * start the requested CPU. psci_cpu_on() returns PSCI_MISSING
538 * to indicate we are unable to use it to start the given CPU.
540 KASSERT(err == PSCI_MISSING ||
541 (mp_quirks & MP_QUIRK_CPULIST) == MP_QUIRK_CPULIST,
542 ("Failed to start CPU %u (%lx), error %d\n",
543 cpuid, target_cpu, err));
546 dpcpu[cpuid - 1] = NULL;
547 kmem_free(bootstacks[cpuid], MP_BOOTSTACK_SIZE);
548 kmem_free(pcpup, size);
549 bootstacks[cpuid] = NULL;
554 /* Wait for the AP to switch to its boot stack. */
555 while (atomic_load_int(&aps_started) < naps + 1)
557 CPU_SET(cpuid, &all_cpus);
564 madt_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
566 ACPI_MADT_GENERIC_INTERRUPT *intr;
571 switch(entry->Type) {
572 case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
573 intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
576 if (is_boot_cpu(intr->ArmMpidr))
584 domain = acpi_pxm_get_cpu_locality(intr->Uid);
586 if (start_cpu(id, intr->ArmMpidr, domain)) {
587 MPASS(cpuid_to_pcpu[id] != NULL);
588 cpuid_to_pcpu[id]->pc_acpi_id = intr->Uid;
590 * Don't increment for the boot CPU, its CPU ID is
593 if (!is_boot_cpu(intr->ArmMpidr))
606 ACPI_TABLE_MADT *madt;
610 physaddr = acpi_find_table(ACPI_SIG_MADT);
614 madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
616 printf("Unable to map the MADT, not starting APs\n");
619 /* Boot CPU is always 0 */
621 acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
622 madt_handler, &cpuid);
624 acpi_unmap_table(madt);
627 acpi_pxm_set_cpu_locality();
634 start_cpu_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
641 if (addr_size == 2) {
643 target_cpu |= reg[1];
646 if (is_boot_cpu(target_cpu))
651 if (!start_cpu(cpuid, target_cpu, 0))
655 * Don't increment for the boot CPU, its CPU ID is reserved.
657 if (!is_boot_cpu(target_cpu))
660 /* Try to read the numa node of this cpu */
661 if (vm_ndomains == 1 ||
662 OF_getencprop(node, "numa-node-id", &domain, sizeof(domain)) <= 0)
664 cpuid_to_pcpu[cpuid]->pc_domain = domain;
665 if (domain < MAXMEMDOM)
666 CPU_SET(cpuid, &cpuset_domain[domain]);
676 for (i = 0; fdt_quirks[i].compat != NULL; i++) {
677 if (ofw_bus_node_is_compatible(node,
678 fdt_quirks[i].compat) != 0) {
679 mp_quirks = fdt_quirks[i].quirks;
683 ofw_cpu_early_foreach(start_cpu_fdt, true);
687 /* Initialize and fire up non-boot processors */
693 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
695 /* CPU 0 is always boot CPU. */
696 CPU_SET(0, &all_cpus);
697 mpidr = READ_SPECIALREG(mpidr_el1) & CPU_AFF_MASK;
698 cpuid_to_pcpu[0]->pc_mpidr_low = mpidr;
699 cpuid_to_pcpu[0]->pc_mpidr_high = mpidr >> 32;
701 switch(arm64_bus_method) {
704 mp_quirks = MP_QUIRK_CPULIST;
718 /* Introduce rest of cores to the world */
720 cpu_mp_announce(void)
726 cpu_count_acpi_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
730 switch(entry->Type) {
731 case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
742 ACPI_TABLE_MADT *madt;
746 physaddr = acpi_find_table(ACPI_SIG_MADT);
750 madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
752 printf("Unable to map the MADT, not starting APs\n");
757 acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
758 cpu_count_acpi_handler, &cores);
760 acpi_unmap_table(madt);
767 cpu_mp_setmaxid(void)
774 switch(arm64_bus_method) {
777 cores = cpu_count_acpi();
779 cores = MIN(cores, MAXCPU);
781 printf("Found %d CPUs in the ACPI tables\n",
784 mp_maxid = cores - 1;
790 cores = ofw_cpu_early_foreach(NULL, false);
792 cores = MIN(cores, MAXCPU);
794 printf("Found %d CPUs in the device tree\n",
797 mp_maxid = cores - 1;
803 printf("No CPU data, limiting to 1 core\n");
807 if (TUNABLE_INT_FETCH("hw.ncpu", &cores)) {
808 if (cores > 0 && cores < mp_ncpus) {
810 mp_maxid = cores - 1;
818 static struct intr_ipi *
819 intr_ipi_lookup(u_int ipi)
822 if (ipi >= INTR_IPI_COUNT)
823 panic("%s: no such IPI %u", __func__, ipi);
825 return (&ipi_sources[ipi]);
829 * interrupt controller dispatch function for IPIs. It should
830 * be called straight from the interrupt controller, when associated
831 * interrupt source is learned. Or from anybody who has an interrupt
835 intr_ipi_dispatch(u_int ipi, struct trapframe *tf)
840 ii = intr_ipi_lookup(ipi);
841 if (ii->ii_count == NULL)
842 panic("%s: not setup IPI %u", __func__, ipi);
844 intr_ipi_increment_count(ii->ii_count, PCPU_GET(cpuid));
847 * Supply ipi filter with trapframe argument
848 * if none is registered.
850 arg = ii->ii_handler_arg != NULL ? ii->ii_handler_arg : tf;
856 * Map IPI into interrupt controller.
861 ipi_map(struct intr_irqsrc *isrc, u_int ipi)
866 if (ipi >= INTR_IPI_COUNT)
867 panic("%s: no such IPI %u", __func__, ipi);
869 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
871 isrc->isrc_type = INTR_ISRCT_NAMESPACE;
872 isrc->isrc_nspc_type = INTR_IRQ_NSPC_IPI;
873 isrc->isrc_nspc_num = ipi_next_num;
875 error = PIC_REGISTER(intr_irq_root_dev, isrc, &is_percpu);
877 isrc->isrc_dev = intr_irq_root_dev;
884 * Setup IPI handler to interrupt source.
886 * Note that there could be more ways how to send and receive IPIs
887 * on a platform like fast interrupts for example. In that case,
888 * one can call this function with ASIF_NOALLOC flag set and then
889 * call intr_ipi_dispatch() when appropriate.
894 intr_ipi_set_handler(u_int ipi, const char *name, intr_ipi_filter_t *filter,
895 void *arg, u_int flags)
897 struct intr_irqsrc *isrc;
903 isrc = intr_ipi_lookup(ipi);
904 if (isrc->isrc_ipifilter != NULL)
907 if ((flags & AISHF_NOALLOC) == 0) {
908 error = ipi_map(isrc, ipi);
913 isrc->isrc_ipifilter = filter;
914 isrc->isrc_arg = arg;
915 isrc->isrc_handlers = 1;
916 isrc->isrc_count = intr_ipi_setup_counters(name);
917 isrc->isrc_index = 0; /* it should not be used in IPI case */
919 if (isrc->isrc_dev != NULL) {
920 PIC_ENABLE_INTR(isrc->isrc_dev, isrc);
921 PIC_ENABLE_SOURCE(isrc->isrc_dev, isrc);
929 ipi_all_but_self(u_int ipi)
934 CPU_CLR(PCPU_GET(cpuid), &cpus);
935 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
936 intr_ipi_send(cpus, ipi);
940 ipi_cpu(int cpu, u_int ipi)
947 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
948 intr_ipi_send(cpus, ipi);
952 ipi_selected(cpuset_t cpus, u_int ipi)
955 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
956 intr_ipi_send(cpus, ipi);