2 * Copyright (c) 2015-2016 The FreeBSD Foundation
5 * This software was developed by Andrew Turner under
6 * sponsorship from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include "opt_kstack_pages.h"
34 #include "opt_platform.h"
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include <sys/param.h>
40 #include <sys/systm.h>
44 #include <sys/kernel.h>
46 #include <sys/malloc.h>
47 #include <sys/module.h>
48 #include <sys/mutex.h>
51 #include <sys/sched.h>
56 #include <vm/vm_extern.h>
57 #include <vm/vm_kern.h>
58 #include <vm/vm_map.h>
60 #include <machine/machdep.h>
61 #include <machine/debug_monitor.h>
62 #include <machine/intr.h>
63 #include <machine/smp.h>
65 #include <machine/vfp.h>
69 #include <contrib/dev/acpica/include/acpi.h>
70 #include <dev/acpica/acpivar.h>
74 #include <dev/ofw/openfirm.h>
75 #include <dev/ofw/ofw_bus.h>
76 #include <dev/ofw/ofw_bus_subr.h>
77 #include <dev/ofw/ofw_cpu.h>
80 #include <dev/psci/psci.h>
84 #define MP_QUIRK_CPULIST 0x01 /* The list of cpus may be wrong, */
85 /* don't panic if one fails to start */
86 static uint32_t mp_quirks;
93 { "arm,foundation-aarch64", MP_QUIRK_CPULIST },
94 { "arm,fvp-base", MP_QUIRK_CPULIST },
95 /* This is incorrect in some DTS files */
96 { "arm,vfp-base", MP_QUIRK_CPULIST },
101 typedef void intr_ipi_send_t(void *, cpuset_t, u_int);
102 typedef void intr_ipi_handler_t(void *);
104 #define INTR_IPI_NAMELEN (MAXCOMLEN + 1)
106 intr_ipi_handler_t * ii_handler;
107 void * ii_handler_arg;
108 intr_ipi_send_t * ii_send;
110 char ii_name[INTR_IPI_NAMELEN];
114 static struct intr_ipi ipi_sources[INTR_IPI_COUNT];
116 static struct intr_ipi *intr_ipi_lookup(u_int);
117 static void intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *,
120 static void ipi_ast(void *);
121 static void ipi_hardclock(void *);
122 static void ipi_preempt(void *);
123 static void ipi_rendezvous(void *);
124 static void ipi_stop(void *);
126 struct pcb stoppcbs[MAXCPU];
129 * Not all systems boot from the first CPU in the device tree. To work around
130 * this we need to find which CPU we have booted from so when we later
131 * enable the secondary CPUs we skip this one.
133 static int cpu0 = -1;
135 void mpentry(unsigned long cpuid);
136 void init_secondary(uint64_t);
138 /* Synchronize AP startup. */
139 static struct mtx ap_boot_mtx;
141 /* Stacks for AP initialization, discarded once idle threads are started. */
143 static void *bootstacks[MAXCPU];
145 /* Count of started APs, used to synchronize access to bootstack. */
146 static volatile int aps_started;
148 /* Set to 1 once we're ready to let the APs out of the pen. */
149 static volatile int aps_ready;
151 /* Temporary variables for init_secondary() */
152 void *dpcpu[MAXCPU - 1];
155 release_aps(void *dummy __unused)
159 /* Only release CPUs if they exist */
163 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
164 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
165 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
166 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
167 intr_pic_ipi_setup(IPI_STOP_HARD, "stop hard", ipi_stop, NULL);
168 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
170 atomic_store_rel_int(&aps_ready, 1);
171 /* Wake up the other CPUs */
177 printf("Release APs...");
180 for (i = 0; i < 2000; i++) {
186 * Don't time out while we are making progress. Some large
187 * systems can take a while to start all CPUs.
189 if (smp_cpus > started) {
196 printf("APs not started\n");
198 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
201 init_secondary(uint64_t cpu)
206 pcpup = &__pcpu[cpu];
208 * Set the pcpu pointer with a backup in tpidr_el1 to be
209 * loaded when entering the kernel from userland.
213 "msr tpidr_el1, %0" :: "r"(pcpup));
216 * Identify current CPU. This is necessary to setup
217 * affinity registers and to provide support for
218 * runtime chip identification.
220 * We need this before signalling the CPU is ready to
221 * let the boot CPU use the results.
225 /* Ensure the stores in identify_cpu have completed */
226 atomic_thread_fence_acq_rel();
228 /* Signal the BSP and spin until it has released all APs. */
229 atomic_add_int(&aps_started, 1);
230 while (!atomic_load_int(&aps_ready))
231 __asm __volatile("wfe");
233 pcpup->pc_midr = get_midr();
235 /* Initialize curthread */
236 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
237 pcpup->pc_curthread = pcpup->pc_idlethread;
239 /* Initialize curpmap to match TTBR0's current setting. */
240 pmap0 = vmspace_pmap(&vmspace0);
241 KASSERT(pmap_to_ttbr0(pmap0) == READ_SPECIALREG(ttbr0_el1),
242 ("pmap0 doesn't match cpu %ld's ttbr0", cpu));
243 pcpup->pc_curpmap = pmap0;
245 install_cpu_errata();
247 intr_pic_init_secondary();
249 /* Start per-CPU event timers. */
259 mtx_lock_spin(&ap_boot_mtx);
260 atomic_add_rel_32(&smp_cpus, 1);
261 if (smp_cpus == mp_ncpus) {
262 /* enable IPI's, tlb shootdown, freezes etc */
263 atomic_store_rel_int(&smp_started, 1);
265 mtx_unlock_spin(&ap_boot_mtx);
270 * Assert that smp_after_idle_runnable condition is reasonable.
272 MPASS(PCPU_GET(curpcb) == NULL);
274 /* Enter the scheduler */
277 panic("scheduler returned us to init_secondary");
282 smp_after_idle_runnable(void *arg __unused)
287 for (cpu = 1; cpu < mp_ncpus; cpu++) {
288 if (bootstacks[cpu] != NULL) {
290 while (atomic_load_ptr(&pc->pc_curpcb) == NULL)
292 kmem_free((vm_offset_t)bootstacks[cpu], PAGE_SIZE);
296 SYSINIT(smp_after_idle_runnable, SI_SUB_SMP, SI_ORDER_ANY,
297 smp_after_idle_runnable, NULL);
300 * Send IPI thru interrupt controller.
303 pic_ipi_send(void *arg, cpuset_t cpus, u_int ipi)
306 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
307 PIC_IPI_SEND(intr_irq_root_dev, arg, cpus, ipi);
311 * Setup IPI handler on interrupt controller.
316 intr_pic_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand,
319 struct intr_irqsrc *isrc;
323 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
324 KASSERT(hand != NULL, ("%s: ipi %u no handler", __func__, ipi));
326 error = PIC_IPI_SETUP(intr_irq_root_dev, ipi, &isrc);
330 isrc->isrc_handlers++;
332 ii = intr_ipi_lookup(ipi);
333 KASSERT(ii->ii_count == NULL, ("%s: ipi %u reused", __func__, ipi));
335 ii->ii_handler = hand;
336 ii->ii_handler_arg = arg;
337 ii->ii_send = pic_ipi_send;
338 ii->ii_send_arg = isrc;
339 strlcpy(ii->ii_name, name, INTR_IPI_NAMELEN);
340 ii->ii_count = intr_ipi_setup_counters(name);
344 intr_ipi_send(cpuset_t cpus, u_int ipi)
348 ii = intr_ipi_lookup(ipi);
349 if (ii->ii_count == NULL)
350 panic("%s: not setup IPI %u", __func__, ipi);
352 ii->ii_send(ii->ii_send_arg, cpus, ipi);
356 ipi_ast(void *dummy __unused)
359 CTR0(KTR_SMP, "IPI_AST");
363 ipi_hardclock(void *dummy __unused)
366 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
371 ipi_preempt(void *dummy __unused)
373 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
374 sched_preempt(curthread);
378 ipi_rendezvous(void *dummy __unused)
381 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
382 smp_rendezvous_action();
386 ipi_stop(void *dummy __unused)
390 CTR0(KTR_SMP, "IPI_STOP");
392 cpu = PCPU_GET(cpuid);
393 savectx(&stoppcbs[cpu]);
395 /* Indicate we are stopped */
396 CPU_SET_ATOMIC(cpu, &stopped_cpus);
398 /* Wait for restart */
399 while (!CPU_ISSET(cpu, &started_cpus))
403 dbg_register_sync(NULL);
406 CPU_CLR_ATOMIC(cpu, &started_cpus);
407 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
408 CTR0(KTR_SMP, "IPI_STOP (restart)");
415 return (smp_topo_none());
418 /* Determine if we running MP machine */
423 /* ARM64TODO: Read the u bit of mpidr_el1 to determine this */
428 start_cpu(u_int id, uint64_t target_cpu)
435 /* Check we are able to start this cpu */
439 KASSERT(id < MAXCPU, ("Too many CPUs"));
441 /* We are already running on cpu 0 */
446 * Rotate the CPU IDs to put the boot CPU as CPU 0. We keep the other
447 * CPUs ordered as they are likely grouped into clusters so it can be
448 * useful to keep that property, e.g. for the GICv3 driver to send
449 * an IPI to all CPUs in the cluster.
453 cpuid += mp_maxid + 1;
456 pcpup = &__pcpu[cpuid];
457 pcpu_init(pcpup, cpuid, sizeof(struct pcpu));
459 dpcpu[cpuid - 1] = (void *)kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO);
460 dpcpu_init(dpcpu[cpuid - 1], cpuid);
462 bootstacks[cpuid] = (void *)kmem_malloc(PAGE_SIZE, M_WAITOK | M_ZERO);
464 naps = atomic_load_int(&aps_started);
465 bootstack = (char *)bootstacks[cpuid] + PAGE_SIZE;
467 printf("Starting CPU %u (%lx)\n", cpuid, target_cpu);
468 pa = pmap_extract(kernel_pmap, (vm_offset_t)mpentry);
469 err = psci_cpu_on(target_cpu, pa, cpuid);
470 if (err != PSCI_RETVAL_SUCCESS) {
472 * Panic here if INVARIANTS are enabled and PSCI failed to
473 * start the requested CPU. psci_cpu_on() returns PSCI_MISSING
474 * to indicate we are unable to use it to start the given CPU.
476 KASSERT(err == PSCI_MISSING ||
477 (mp_quirks & MP_QUIRK_CPULIST) == MP_QUIRK_CPULIST,
478 ("Failed to start CPU %u (%lx), error %d\n",
479 id, target_cpu, err));
482 kmem_free((vm_offset_t)dpcpu[cpuid - 1], DPCPU_SIZE);
483 dpcpu[cpuid - 1] = NULL;
484 kmem_free((vm_offset_t)bootstacks[cpuid], PAGE_SIZE);
485 bootstacks[cpuid] = NULL;
488 /* Notify the user that the CPU failed to start */
489 printf("Failed to start CPU %u (%lx), error %d\n",
490 id, target_cpu, err);
492 /* Wait for the AP to switch to its boot stack. */
493 while (atomic_load_int(&aps_started) < naps + 1)
495 CPU_SET(cpuid, &all_cpus);
503 madt_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
505 ACPI_MADT_GENERIC_INTERRUPT *intr;
509 switch(entry->Type) {
510 case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
511 intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
514 start_cpu(id, intr->ArmMpidr);
515 __pcpu[id].pc_acpi_id = intr->Uid;
526 ACPI_TABLE_MADT *madt;
530 physaddr = acpi_find_table(ACPI_SIG_MADT);
534 madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
536 printf("Unable to map the MADT, not starting APs\n");
541 acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
542 madt_handler, &cpuid);
544 acpi_unmap_table(madt);
547 acpi_pxm_set_cpu_locality();
554 cpu_init_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
560 if (addr_size == 2) {
562 target_cpu |= reg[1];
565 if (!start_cpu(id, target_cpu))
568 /* Try to read the numa node of this cpu */
569 if (vm_ndomains == 1 ||
570 OF_getencprop(node, "numa-node-id", &domain, sizeof(domain)) <= 0)
572 __pcpu[id].pc_domain = domain;
573 if (domain < MAXMEMDOM)
574 CPU_SET(id, &cpuset_domain[domain]);
580 /* Initialize and fire up non-boot processors */
589 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
591 CPU_SET(0, &all_cpus);
593 switch(arm64_bus_method) {
596 mp_quirks = MP_QUIRK_CPULIST;
597 KASSERT(cpu0 >= 0, ("Current CPU was not found"));
604 for (i = 0; fdt_quirks[i].compat != NULL; i++) {
605 if (ofw_bus_node_is_compatible(node,
606 fdt_quirks[i].compat) != 0) {
607 mp_quirks = fdt_quirks[i].quirks;
610 KASSERT(cpu0 >= 0, ("Current CPU was not found"));
611 ofw_cpu_early_foreach(cpu_init_fdt, true);
619 /* Introduce rest of cores to the world */
621 cpu_mp_announce(void)
627 cpu_count_acpi_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
629 ACPI_MADT_GENERIC_INTERRUPT *intr;
633 switch(entry->Type) {
634 case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
635 intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
637 mpidr_reg = READ_SPECIALREG(mpidr_el1);
638 if ((mpidr_reg & 0xff00fffffful) == intr->ArmMpidr)
651 ACPI_TABLE_MADT *madt;
655 physaddr = acpi_find_table(ACPI_SIG_MADT);
659 madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
661 printf("Unable to map the MADT, not starting APs\n");
666 acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
667 cpu_count_acpi_handler, &cores);
669 acpi_unmap_table(madt);
677 cpu_find_cpu0_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
679 uint64_t mpidr_fdt, mpidr_reg;
683 if (addr_size == 2) {
688 mpidr_reg = READ_SPECIALREG(mpidr_el1);
690 if ((mpidr_reg & 0xff00fffffful) == mpidr_fdt)
699 cpu_mp_setmaxid(void)
706 switch(arm64_bus_method) {
709 cores = cpu_count_acpi();
711 cores = MIN(cores, MAXCPU);
713 printf("Found %d CPUs in the ACPI tables\n",
716 mp_maxid = cores - 1;
722 cores = ofw_cpu_early_foreach(cpu_find_cpu0_fdt, false);
724 cores = MIN(cores, MAXCPU);
726 printf("Found %d CPUs in the device tree\n",
729 mp_maxid = cores - 1;
735 printf("No CPU data, limiting to 1 core\n");
739 if (TUNABLE_INT_FETCH("hw.ncpu", &cores)) {
740 if (cores > 0 && cores < mp_ncpus) {
742 mp_maxid = cores - 1;
750 static struct intr_ipi *
751 intr_ipi_lookup(u_int ipi)
754 if (ipi >= INTR_IPI_COUNT)
755 panic("%s: no such IPI %u", __func__, ipi);
757 return (&ipi_sources[ipi]);
761 * interrupt controller dispatch function for IPIs. It should
762 * be called straight from the interrupt controller, when associated
763 * interrupt source is learned. Or from anybody who has an interrupt
767 intr_ipi_dispatch(u_int ipi, struct trapframe *tf)
772 ii = intr_ipi_lookup(ipi);
773 if (ii->ii_count == NULL)
774 panic("%s: not setup IPI %u", __func__, ipi);
776 intr_ipi_increment_count(ii->ii_count, PCPU_GET(cpuid));
779 * Supply ipi filter with trapframe argument
780 * if none is registered.
782 arg = ii->ii_handler_arg != NULL ? ii->ii_handler_arg : tf;
788 * Map IPI into interrupt controller.
793 ipi_map(struct intr_irqsrc *isrc, u_int ipi)
798 if (ipi >= INTR_IPI_COUNT)
799 panic("%s: no such IPI %u", __func__, ipi);
801 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
803 isrc->isrc_type = INTR_ISRCT_NAMESPACE;
804 isrc->isrc_nspc_type = INTR_IRQ_NSPC_IPI;
805 isrc->isrc_nspc_num = ipi_next_num;
807 error = PIC_REGISTER(intr_irq_root_dev, isrc, &is_percpu);
809 isrc->isrc_dev = intr_irq_root_dev;
816 * Setup IPI handler to interrupt source.
818 * Note that there could be more ways how to send and receive IPIs
819 * on a platform like fast interrupts for example. In that case,
820 * one can call this function with ASIF_NOALLOC flag set and then
821 * call intr_ipi_dispatch() when appropriate.
826 intr_ipi_set_handler(u_int ipi, const char *name, intr_ipi_filter_t *filter,
827 void *arg, u_int flags)
829 struct intr_irqsrc *isrc;
835 isrc = intr_ipi_lookup(ipi);
836 if (isrc->isrc_ipifilter != NULL)
839 if ((flags & AISHF_NOALLOC) == 0) {
840 error = ipi_map(isrc, ipi);
845 isrc->isrc_ipifilter = filter;
846 isrc->isrc_arg = arg;
847 isrc->isrc_handlers = 1;
848 isrc->isrc_count = intr_ipi_setup_counters(name);
849 isrc->isrc_index = 0; /* it should not be used in IPI case */
851 if (isrc->isrc_dev != NULL) {
852 PIC_ENABLE_INTR(isrc->isrc_dev, isrc);
853 PIC_ENABLE_SOURCE(isrc->isrc_dev, isrc);
861 ipi_all_but_self(u_int ipi)
866 CPU_CLR(PCPU_GET(cpuid), &cpus);
867 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
868 intr_ipi_send(cpus, ipi);
872 ipi_cpu(int cpu, u_int ipi)
879 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
880 intr_ipi_send(cpus, ipi);
884 ipi_selected(cpuset_t cpus, u_int ipi)
887 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
888 intr_ipi_send(cpus, ipi);