2 * Copyright (c) 2015-2016 The FreeBSD Foundation
5 * This software was developed by Andrew Turner under
6 * sponsorship from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include "opt_kstack_pages.h"
34 #include "opt_platform.h"
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include <sys/param.h>
40 #include <sys/systm.h>
44 #include <sys/kernel.h>
46 #include <sys/malloc.h>
47 #include <sys/module.h>
48 #include <sys/mutex.h>
51 #include <sys/sched.h>
56 #include <vm/vm_extern.h>
57 #include <vm/vm_kern.h>
58 #include <vm/vm_map.h>
60 #include <machine/machdep.h>
61 #include <machine/debug_monitor.h>
62 #include <machine/intr.h>
63 #include <machine/smp.h>
65 #include <machine/vfp.h>
69 #include <contrib/dev/acpica/include/acpi.h>
70 #include <dev/acpica/acpivar.h>
74 #include <dev/ofw/openfirm.h>
75 #include <dev/ofw/ofw_bus.h>
76 #include <dev/ofw/ofw_bus_subr.h>
77 #include <dev/ofw/ofw_cpu.h>
80 #include <dev/psci/psci.h>
84 #define MP_QUIRK_CPULIST 0x01 /* The list of cpus may be wrong, */
85 /* don't panic if one fails to start */
86 static uint32_t mp_quirks;
93 { "arm,foundation-aarch64", MP_QUIRK_CPULIST },
94 { "arm,fvp-base", MP_QUIRK_CPULIST },
95 /* This is incorrect in some DTS files */
96 { "arm,vfp-base", MP_QUIRK_CPULIST },
101 typedef void intr_ipi_send_t(void *, cpuset_t, u_int);
102 typedef void intr_ipi_handler_t(void *);
104 #define INTR_IPI_NAMELEN (MAXCOMLEN + 1)
106 intr_ipi_handler_t * ii_handler;
107 void * ii_handler_arg;
108 intr_ipi_send_t * ii_send;
110 char ii_name[INTR_IPI_NAMELEN];
114 static struct intr_ipi ipi_sources[INTR_IPI_COUNT];
116 static struct intr_ipi *intr_ipi_lookup(u_int);
117 static void intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *,
120 static void ipi_ast(void *);
121 static void ipi_hardclock(void *);
122 static void ipi_preempt(void *);
123 static void ipi_rendezvous(void *);
124 static void ipi_stop(void *);
126 struct pcb stoppcbs[MAXCPU];
129 static u_int fdt_cpuid;
132 void mpentry(unsigned long cpuid);
133 void init_secondary(uint64_t);
135 /* Synchronize AP startup. */
136 static struct mtx ap_boot_mtx;
138 /* Stacks for AP initialization, discarded once idle threads are started. */
140 static void *bootstacks[MAXCPU];
142 /* Count of started APs, used to synchronize access to bootstack. */
143 static volatile int aps_started;
145 /* Set to 1 once we're ready to let the APs out of the pen. */
146 static volatile int aps_ready;
148 /* Temporary variables for init_secondary() */
149 void *dpcpu[MAXCPU - 1];
152 release_aps(void *dummy __unused)
156 /* Only release CPUs if they exist */
160 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
161 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
162 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
163 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
164 intr_pic_ipi_setup(IPI_STOP_HARD, "stop hard", ipi_stop, NULL);
165 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
167 atomic_store_rel_int(&aps_ready, 1);
168 /* Wake up the other CPUs */
174 printf("Release APs...");
177 for (i = 0; i < 2000; i++) {
183 * Don't time out while we are making progress. Some large
184 * systems can take a while to start all CPUs.
186 if (smp_cpus > started) {
193 printf("APs not started\n");
195 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
198 init_secondary(uint64_t cpu)
203 pcpup = &__pcpu[cpu];
205 * Set the pcpu pointer with a backup in tpidr_el1 to be
206 * loaded when entering the kernel from userland.
210 "msr tpidr_el1, %0" :: "r"(pcpup));
213 * Identify current CPU. This is necessary to setup
214 * affinity registers and to provide support for
215 * runtime chip identification.
217 * We need this before signalling the CPU is ready to
218 * let the boot CPU use the results.
222 /* Ensure the stores in identify_cpu have completed */
223 atomic_thread_fence_acq_rel();
225 /* Signal the BSP and spin until it has released all APs. */
226 atomic_add_int(&aps_started, 1);
227 while (!atomic_load_int(&aps_ready))
228 __asm __volatile("wfe");
230 pcpup->pc_midr = get_midr();
232 /* Initialize curthread */
233 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
234 pcpup->pc_curthread = pcpup->pc_idlethread;
236 /* Initialize curpmap to match TTBR0's current setting. */
237 pmap0 = vmspace_pmap(&vmspace0);
238 KASSERT(pmap_to_ttbr0(pmap0) == READ_SPECIALREG(ttbr0_el1),
239 ("pmap0 doesn't match cpu %ld's ttbr0", cpu));
240 pcpup->pc_curpmap = pmap0;
242 install_cpu_errata();
244 intr_pic_init_secondary();
246 /* Start per-CPU event timers. */
256 mtx_lock_spin(&ap_boot_mtx);
257 atomic_add_rel_32(&smp_cpus, 1);
258 if (smp_cpus == mp_ncpus) {
259 /* enable IPI's, tlb shootdown, freezes etc */
260 atomic_store_rel_int(&smp_started, 1);
262 mtx_unlock_spin(&ap_boot_mtx);
267 * Assert that smp_after_idle_runnable condition is reasonable.
269 MPASS(PCPU_GET(curpcb) == NULL);
271 /* Enter the scheduler */
274 panic("scheduler returned us to init_secondary");
279 smp_after_idle_runnable(void *arg __unused)
284 for (cpu = 1; cpu < mp_ncpus; cpu++) {
285 if (bootstacks[cpu] != NULL) {
287 while (atomic_load_ptr(&pc->pc_curpcb) == NULL)
289 kmem_free((vm_offset_t)bootstacks[cpu], PAGE_SIZE);
293 SYSINIT(smp_after_idle_runnable, SI_SUB_SMP, SI_ORDER_ANY,
294 smp_after_idle_runnable, NULL);
297 * Send IPI thru interrupt controller.
300 pic_ipi_send(void *arg, cpuset_t cpus, u_int ipi)
303 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
306 * Ensure that this CPU's stores will be visible to IPI
307 * recipients before starting to send the interrupts.
311 PIC_IPI_SEND(intr_irq_root_dev, arg, cpus, ipi);
315 * Setup IPI handler on interrupt controller.
320 intr_pic_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand,
323 struct intr_irqsrc *isrc;
327 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
328 KASSERT(hand != NULL, ("%s: ipi %u no handler", __func__, ipi));
330 error = PIC_IPI_SETUP(intr_irq_root_dev, ipi, &isrc);
334 isrc->isrc_handlers++;
336 ii = intr_ipi_lookup(ipi);
337 KASSERT(ii->ii_count == NULL, ("%s: ipi %u reused", __func__, ipi));
339 ii->ii_handler = hand;
340 ii->ii_handler_arg = arg;
341 ii->ii_send = pic_ipi_send;
342 ii->ii_send_arg = isrc;
343 strlcpy(ii->ii_name, name, INTR_IPI_NAMELEN);
344 ii->ii_count = intr_ipi_setup_counters(name);
348 intr_ipi_send(cpuset_t cpus, u_int ipi)
352 ii = intr_ipi_lookup(ipi);
353 if (ii->ii_count == NULL)
354 panic("%s: not setup IPI %u", __func__, ipi);
356 ii->ii_send(ii->ii_send_arg, cpus, ipi);
360 ipi_ast(void *dummy __unused)
363 CTR0(KTR_SMP, "IPI_AST");
367 ipi_hardclock(void *dummy __unused)
370 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
375 ipi_preempt(void *dummy __unused)
377 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
378 sched_preempt(curthread);
382 ipi_rendezvous(void *dummy __unused)
385 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
386 smp_rendezvous_action();
390 ipi_stop(void *dummy __unused)
394 CTR0(KTR_SMP, "IPI_STOP");
396 cpu = PCPU_GET(cpuid);
397 savectx(&stoppcbs[cpu]);
399 /* Indicate we are stopped */
400 CPU_SET_ATOMIC(cpu, &stopped_cpus);
402 /* Wait for restart */
403 while (!CPU_ISSET(cpu, &started_cpus))
407 dbg_register_sync(NULL);
410 CPU_CLR_ATOMIC(cpu, &started_cpus);
411 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
412 CTR0(KTR_SMP, "IPI_STOP (restart)");
419 return (smp_topo_none());
422 /* Determine if we running MP machine */
427 /* ARM64TODO: Read the u bit of mpidr_el1 to determine this */
432 start_cpu(u_int cpuid, uint64_t target_cpu)
438 /* Check we are able to start this cpu */
439 if (cpuid > mp_maxid)
442 KASSERT(cpuid < MAXCPU, ("Too many CPUs"));
443 KASSERT(__pcpu[0].pc_mpidr != (target_cpu & CPU_AFF_MASK),
444 ("Start_cpu() was called on the boot CPU"));
446 pcpup = &__pcpu[cpuid];
447 pcpu_init(pcpup, cpuid, sizeof(struct pcpu));
448 pcpup->pc_mpidr = target_cpu & CPU_AFF_MASK;
450 dpcpu[cpuid - 1] = (void *)kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO);
451 dpcpu_init(dpcpu[cpuid - 1], cpuid);
453 bootstacks[cpuid] = (void *)kmem_malloc(PAGE_SIZE, M_WAITOK | M_ZERO);
455 naps = atomic_load_int(&aps_started);
456 bootstack = (char *)bootstacks[cpuid] + PAGE_SIZE;
458 printf("Starting CPU %u (%lx)\n", cpuid, target_cpu);
459 pa = pmap_extract(kernel_pmap, (vm_offset_t)mpentry);
460 err = psci_cpu_on(target_cpu, pa, cpuid);
461 if (err != PSCI_RETVAL_SUCCESS) {
463 * Panic here if INVARIANTS are enabled and PSCI failed to
464 * start the requested CPU. psci_cpu_on() returns PSCI_MISSING
465 * to indicate we are unable to use it to start the given CPU.
467 KASSERT(err == PSCI_MISSING ||
468 (mp_quirks & MP_QUIRK_CPULIST) == MP_QUIRK_CPULIST,
469 ("Failed to start CPU %u (%lx), error %d\n",
470 cpuid, target_cpu, err));
473 kmem_free((vm_offset_t)dpcpu[cpuid - 1], DPCPU_SIZE);
474 dpcpu[cpuid - 1] = NULL;
475 kmem_free((vm_offset_t)bootstacks[cpuid], PAGE_SIZE);
476 bootstacks[cpuid] = NULL;
480 /* Wait for the AP to switch to its boot stack. */
481 while (atomic_load_int(&aps_started) < naps + 1)
483 CPU_SET(cpuid, &all_cpus);
491 madt_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
493 ACPI_MADT_GENERIC_INTERRUPT *intr;
497 switch(entry->Type) {
498 case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
499 intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
503 /* Skip the boot CPU, but save its ACPI id. */
504 if (__pcpu[0].pc_mpidr == (intr->ArmMpidr & CPU_AFF_MASK)) {
505 __pcpu[0].pc_acpi_id = intr->Uid;
509 start_cpu(id, intr->ArmMpidr);
510 __pcpu[id].pc_acpi_id = intr->Uid;
521 ACPI_TABLE_MADT *madt;
525 physaddr = acpi_find_table(ACPI_SIG_MADT);
529 madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
531 printf("Unable to map the MADT, not starting APs\n");
534 /* Boot CPU is always 0 */
536 acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
537 madt_handler, &cpuid);
539 acpi_unmap_table(madt);
542 acpi_pxm_set_cpu_locality();
549 cpu_init_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
555 if (addr_size == 2) {
557 target_cpu |= reg[1];
561 if (__pcpu[0].pc_mpidr == (target_cpu & CPU_AFF_MASK))
564 if (!start_cpu(fdt_cpuid, target_cpu))
568 /* Try to read the numa node of this cpu */
569 if (vm_ndomains == 1 ||
570 OF_getencprop(node, "numa-node-id", &domain, sizeof(domain)) <= 0)
572 __pcpu[fdt_cpuid].pc_domain = domain;
573 if (domain < MAXMEMDOM)
574 CPU_SET(fdt_cpuid, &cpuset_domain[domain]);
580 /* Initialize and fire up non-boot processors */
589 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
591 /* CPU 0 is always boot CPU. */
592 CPU_SET(0, &all_cpus);
593 __pcpu[0].pc_mpidr = READ_SPECIALREG(mpidr_el1) & CPU_AFF_MASK;
595 switch(arm64_bus_method) {
598 mp_quirks = MP_QUIRK_CPULIST;
605 for (i = 0; fdt_quirks[i].compat != NULL; i++) {
606 if (ofw_bus_node_is_compatible(node,
607 fdt_quirks[i].compat) != 0) {
608 mp_quirks = fdt_quirks[i].quirks;
612 ofw_cpu_early_foreach(cpu_init_fdt, true);
620 /* Introduce rest of cores to the world */
622 cpu_mp_announce(void)
628 cpu_count_acpi_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
630 ACPI_MADT_GENERIC_INTERRUPT *intr;
633 switch(entry->Type) {
634 case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
635 intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
646 ACPI_TABLE_MADT *madt;
650 physaddr = acpi_find_table(ACPI_SIG_MADT);
654 madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
656 printf("Unable to map the MADT, not starting APs\n");
661 acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
662 cpu_count_acpi_handler, &cores);
664 acpi_unmap_table(madt);
671 cpu_mp_setmaxid(void)
678 switch(arm64_bus_method) {
681 cores = cpu_count_acpi();
683 cores = MIN(cores, MAXCPU);
685 printf("Found %d CPUs in the ACPI tables\n",
688 mp_maxid = cores - 1;
694 cores = ofw_cpu_early_foreach(NULL, false);
696 cores = MIN(cores, MAXCPU);
698 printf("Found %d CPUs in the device tree\n",
701 mp_maxid = cores - 1;
707 printf("No CPU data, limiting to 1 core\n");
711 if (TUNABLE_INT_FETCH("hw.ncpu", &cores)) {
712 if (cores > 0 && cores < mp_ncpus) {
714 mp_maxid = cores - 1;
722 static struct intr_ipi *
723 intr_ipi_lookup(u_int ipi)
726 if (ipi >= INTR_IPI_COUNT)
727 panic("%s: no such IPI %u", __func__, ipi);
729 return (&ipi_sources[ipi]);
733 * interrupt controller dispatch function for IPIs. It should
734 * be called straight from the interrupt controller, when associated
735 * interrupt source is learned. Or from anybody who has an interrupt
739 intr_ipi_dispatch(u_int ipi, struct trapframe *tf)
744 ii = intr_ipi_lookup(ipi);
745 if (ii->ii_count == NULL)
746 panic("%s: not setup IPI %u", __func__, ipi);
748 intr_ipi_increment_count(ii->ii_count, PCPU_GET(cpuid));
751 * Supply ipi filter with trapframe argument
752 * if none is registered.
754 arg = ii->ii_handler_arg != NULL ? ii->ii_handler_arg : tf;
760 * Map IPI into interrupt controller.
765 ipi_map(struct intr_irqsrc *isrc, u_int ipi)
770 if (ipi >= INTR_IPI_COUNT)
771 panic("%s: no such IPI %u", __func__, ipi);
773 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
775 isrc->isrc_type = INTR_ISRCT_NAMESPACE;
776 isrc->isrc_nspc_type = INTR_IRQ_NSPC_IPI;
777 isrc->isrc_nspc_num = ipi_next_num;
779 error = PIC_REGISTER(intr_irq_root_dev, isrc, &is_percpu);
781 isrc->isrc_dev = intr_irq_root_dev;
788 * Setup IPI handler to interrupt source.
790 * Note that there could be more ways how to send and receive IPIs
791 * on a platform like fast interrupts for example. In that case,
792 * one can call this function with ASIF_NOALLOC flag set and then
793 * call intr_ipi_dispatch() when appropriate.
798 intr_ipi_set_handler(u_int ipi, const char *name, intr_ipi_filter_t *filter,
799 void *arg, u_int flags)
801 struct intr_irqsrc *isrc;
807 isrc = intr_ipi_lookup(ipi);
808 if (isrc->isrc_ipifilter != NULL)
811 if ((flags & AISHF_NOALLOC) == 0) {
812 error = ipi_map(isrc, ipi);
817 isrc->isrc_ipifilter = filter;
818 isrc->isrc_arg = arg;
819 isrc->isrc_handlers = 1;
820 isrc->isrc_count = intr_ipi_setup_counters(name);
821 isrc->isrc_index = 0; /* it should not be used in IPI case */
823 if (isrc->isrc_dev != NULL) {
824 PIC_ENABLE_INTR(isrc->isrc_dev, isrc);
825 PIC_ENABLE_SOURCE(isrc->isrc_dev, isrc);
833 ipi_all_but_self(u_int ipi)
838 CPU_CLR(PCPU_GET(cpuid), &cpus);
839 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
840 intr_ipi_send(cpus, ipi);
844 ipi_cpu(int cpu, u_int ipi)
851 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
852 intr_ipi_send(cpus, ipi);
856 ipi_selected(cpuset_t cpus, u_int ipi)
859 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
860 intr_ipi_send(cpus, ipi);