2 * Copyright (c) 2015-2016 The FreeBSD Foundation
5 * This software was developed by Andrew Turner under
6 * sponsorship from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include "opt_kstack_pages.h"
33 #include "opt_platform.h"
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/malloc.h>
44 #include <sys/module.h>
45 #include <sys/mutex.h>
47 #include <sys/sched.h>
52 #include <vm/vm_extern.h>
53 #include <vm/vm_kern.h>
55 #include <machine/debug_monitor.h>
56 #include <machine/machdep.h>
57 #include <machine/intr.h>
58 #include <machine/smp.h>
60 #include <machine/vfp.h>
64 #include <contrib/dev/acpica/include/acpi.h>
65 #include <dev/acpica/acpivar.h>
69 #include <dev/ofw/openfirm.h>
70 #include <dev/ofw/ofw_cpu.h>
73 #include <dev/psci/psci.h>
77 typedef void intr_ipi_send_t(void *, cpuset_t, u_int);
78 typedef void intr_ipi_handler_t(void *);
80 #define INTR_IPI_NAMELEN (MAXCOMLEN + 1)
82 intr_ipi_handler_t * ii_handler;
83 void * ii_handler_arg;
84 intr_ipi_send_t * ii_send;
86 char ii_name[INTR_IPI_NAMELEN];
90 static struct intr_ipi ipi_sources[INTR_IPI_COUNT];
92 static struct intr_ipi *intr_ipi_lookup(u_int);
93 static void intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *,
96 extern struct pcpu __pcpu[];
98 static device_identify_t arm64_cpu_identify;
99 static device_probe_t arm64_cpu_probe;
100 static device_attach_t arm64_cpu_attach;
102 static void ipi_ast(void *);
103 static void ipi_hardclock(void *);
104 static void ipi_preempt(void *);
105 static void ipi_rendezvous(void *);
106 static void ipi_stop(void *);
108 struct mtx ap_boot_mtx;
109 struct pcb stoppcbs[MAXCPU];
111 static device_t cpu_list[MAXCPU];
114 * Not all systems boot from the first CPU in the device tree. To work around
115 * this we need to find which CPU we have booted from so when we later
116 * enable the secondary CPUs we skip this one.
118 static int cpu0 = -1;
120 void mpentry(unsigned long cpuid);
121 void init_secondary(uint64_t);
123 uint8_t secondary_stacks[MAXCPU - 1][PAGE_SIZE * KSTACK_PAGES] __aligned(16);
125 /* Set to 1 once we're ready to let the APs out of the pen. */
126 volatile int aps_ready = 0;
128 /* Temporary variables for init_secondary() */
129 void *dpcpu[MAXCPU - 1];
131 static device_method_t arm64_cpu_methods[] = {
132 /* Device interface */
133 DEVMETHOD(device_identify, arm64_cpu_identify),
134 DEVMETHOD(device_probe, arm64_cpu_probe),
135 DEVMETHOD(device_attach, arm64_cpu_attach),
140 static devclass_t arm64_cpu_devclass;
141 static driver_t arm64_cpu_driver = {
147 DRIVER_MODULE(arm64_cpu, cpu, arm64_cpu_driver, arm64_cpu_devclass, 0, 0);
150 arm64_cpu_identify(driver_t *driver, device_t parent)
153 if (device_find_child(parent, "arm64_cpu", -1) != NULL)
155 if (BUS_ADD_CHILD(parent, 0, "arm64_cpu", -1) == NULL)
156 device_printf(parent, "add child failed\n");
160 arm64_cpu_probe(device_t dev)
164 cpuid = device_get_unit(dev);
165 if (cpuid >= MAXCPU || cpuid > mp_maxid)
173 arm64_cpu_attach(device_t dev)
180 cpuid = device_get_unit(dev);
182 if (cpuid >= MAXCPU || cpuid > mp_maxid)
184 KASSERT(cpu_list[cpuid] == NULL, ("Already have cpu %u", cpuid));
186 reg = cpu_get_cpuid(dev, ®_size);
191 device_printf(dev, "register <");
192 for (i = 0; i < reg_size; i++)
193 printf("%s%x", (i == 0) ? "" : " ", reg[i]);
197 /* Set the device to start it later */
198 cpu_list[cpuid] = dev;
204 release_aps(void *dummy __unused)
208 /* Only release CPUs if they exist */
212 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
213 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
214 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
215 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
216 intr_pic_ipi_setup(IPI_STOP_HARD, "stop hard", ipi_stop, NULL);
217 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
219 atomic_store_rel_int(&aps_ready, 1);
220 /* Wake up the other CPUs */
221 __asm __volatile("sev");
223 printf("Release APs\n");
225 for (i = 0; i < 2000; i++) {
231 printf("APs not started\n");
233 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
236 init_secondary(uint64_t cpu)
240 pcpup = &__pcpu[cpu];
242 * Set the pcpu pointer with a backup in tpidr_el1 to be
243 * loaded when entering the kernel from userland.
247 "msr tpidr_el1, %0" :: "r"(pcpup));
249 /* Spin until the BSP releases the APs */
251 __asm __volatile("wfe");
253 /* Initialize curthread */
254 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
255 pcpup->pc_curthread = pcpup->pc_idlethread;
256 pcpup->pc_curpcb = pcpup->pc_idlethread->td_pcb;
259 * Identify current CPU. This is necessary to setup
260 * affinity registers and to provide support for
261 * runtime chip identification.
265 intr_pic_init_secondary();
267 /* Start per-CPU event timers. */
276 /* Enable interrupts */
279 mtx_lock_spin(&ap_boot_mtx);
281 atomic_add_rel_32(&smp_cpus, 1);
283 if (smp_cpus == mp_ncpus) {
284 /* enable IPI's, tlb shootdown, freezes etc */
285 atomic_store_rel_int(&smp_started, 1);
288 mtx_unlock_spin(&ap_boot_mtx);
290 /* Enter the scheduler */
293 panic("scheduler returned us to init_secondary");
298 * Send IPI thru interrupt controller.
301 pic_ipi_send(void *arg, cpuset_t cpus, u_int ipi)
304 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
305 PIC_IPI_SEND(intr_irq_root_dev, arg, cpus, ipi);
309 * Setup IPI handler on interrupt controller.
314 intr_pic_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand,
317 struct intr_irqsrc *isrc;
321 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
322 KASSERT(hand != NULL, ("%s: ipi %u no handler", __func__, ipi));
324 error = PIC_IPI_SETUP(intr_irq_root_dev, ipi, &isrc);
328 isrc->isrc_handlers++;
330 ii = intr_ipi_lookup(ipi);
331 KASSERT(ii->ii_count == NULL, ("%s: ipi %u reused", __func__, ipi));
333 ii->ii_handler = hand;
334 ii->ii_handler_arg = arg;
335 ii->ii_send = pic_ipi_send;
336 ii->ii_send_arg = isrc;
337 strlcpy(ii->ii_name, name, INTR_IPI_NAMELEN);
338 ii->ii_count = intr_ipi_setup_counters(name);
342 intr_ipi_send(cpuset_t cpus, u_int ipi)
346 ii = intr_ipi_lookup(ipi);
347 if (ii->ii_count == NULL)
348 panic("%s: not setup IPI %u", __func__, ipi);
350 ii->ii_send(ii->ii_send_arg, cpus, ipi);
354 ipi_ast(void *dummy __unused)
357 CTR0(KTR_SMP, "IPI_AST");
361 ipi_hardclock(void *dummy __unused)
364 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
369 ipi_preempt(void *dummy __unused)
371 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
372 sched_preempt(curthread);
376 ipi_rendezvous(void *dummy __unused)
379 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
380 smp_rendezvous_action();
384 ipi_stop(void *dummy __unused)
388 CTR0(KTR_SMP, "IPI_STOP");
390 cpu = PCPU_GET(cpuid);
391 savectx(&stoppcbs[cpu]);
393 /* Indicate we are stopped */
394 CPU_SET_ATOMIC(cpu, &stopped_cpus);
396 /* Wait for restart */
397 while (!CPU_ISSET(cpu, &started_cpus))
400 CPU_CLR_ATOMIC(cpu, &started_cpus);
401 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
402 CTR0(KTR_SMP, "IPI_STOP (restart)");
409 return (smp_topo_none());
412 /* Determine if we running MP machine */
417 /* ARM64TODO: Read the u bit of mpidr_el1 to determine this */
422 start_cpu(u_int id, uint64_t target_cpu)
429 /* Check we are able to start this cpu */
433 KASSERT(id < MAXCPU, ("Too many CPUs"));
435 /* We are already running on cpu 0 */
440 * Rotate the CPU IDs to put the boot CPU as CPU 0. We keep the other
441 * CPUs ordered as the are likely grouped into clusters so it can be
442 * useful to keep that property, e.g. for the GICv3 driver to send
443 * an IPI to all CPUs in the cluster.
447 cpuid += mp_maxid + 1;
450 pcpup = &__pcpu[cpuid];
451 pcpu_init(pcpup, cpuid, sizeof(struct pcpu));
453 dpcpu[cpuid - 1] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
455 dpcpu_init(dpcpu[cpuid - 1], cpuid);
457 printf("Starting CPU %u (%lx)\n", cpuid, target_cpu);
458 pa = pmap_extract(kernel_pmap, (vm_offset_t)mpentry);
460 err = psci_cpu_on(target_cpu, pa, cpuid);
461 if (err != PSCI_RETVAL_SUCCESS) {
463 * Panic here if INVARIANTS are enabled and PSCI failed to
464 * start the requested CPU. If psci_cpu_on returns PSCI_MISSING
465 * to indicate we are unable to use it to start the given CPU.
467 KASSERT(err == PSCI_MISSING,
468 ("Failed to start CPU %u (%lx)\n", id, target_cpu));
471 kmem_free(kernel_arena, (vm_offset_t)dpcpu[cpuid - 1],
473 dpcpu[cpuid - 1] = NULL;
474 /* Notify the user that the CPU failed to start */
475 printf("Failed to start CPU %u (%lx)\n", id, target_cpu);
477 CPU_SET(cpuid, &all_cpus);
484 madt_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
486 ACPI_MADT_GENERIC_INTERRUPT *intr;
489 switch(entry->Type) {
490 case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
491 intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
494 start_cpu((*cpuid), intr->ArmMpidr);
505 ACPI_TABLE_MADT *madt;
509 physaddr = acpi_find_table(ACPI_SIG_MADT);
513 madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
515 printf("Unable to map the MADT, not starting APs\n");
520 acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
521 madt_handler, &cpuid);
523 acpi_unmap_table(madt);
529 cpu_init_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
534 if (addr_size == 2) {
536 target_cpu |= reg[1];
539 return (start_cpu(id, target_cpu) ? TRUE : FALSE);
543 /* Initialize and fire up non-boot processors */
548 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
550 CPU_SET(0, &all_cpus);
552 switch(arm64_bus_method) {
555 KASSERT(cpu0 >= 0, ("Current CPU was not found"));
561 KASSERT(cpu0 >= 0, ("Current CPU was not found"));
562 ofw_cpu_early_foreach(cpu_init_fdt, true);
570 /* Introduce rest of cores to the world */
572 cpu_mp_announce(void)
578 cpu_count_acpi_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
580 ACPI_MADT_GENERIC_INTERRUPT *intr;
584 switch(entry->Type) {
585 case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
586 intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
588 mpidr_reg = READ_SPECIALREG(mpidr_el1);
589 if ((mpidr_reg & 0xff00fffffful) == intr->ArmMpidr)
602 ACPI_TABLE_MADT *madt;
606 physaddr = acpi_find_table(ACPI_SIG_MADT);
610 madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
612 printf("Unable to map the MADT, not starting APs\n");
617 acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
618 cpu_count_acpi_handler, &cores);
620 acpi_unmap_table(madt);
628 cpu_find_cpu0_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
630 uint64_t mpidr_fdt, mpidr_reg;
634 if (addr_size == 2) {
639 mpidr_reg = READ_SPECIALREG(mpidr_el1);
641 if ((mpidr_reg & 0xff00fffffful) == mpidr_fdt)
650 cpu_mp_setmaxid(void)
652 #if defined(DEV_ACPI) || defined(FDT)
656 switch(arm64_bus_method) {
659 cores = cpu_count_acpi();
661 cores = MIN(cores, MAXCPU);
663 printf("Found %d CPUs in the ACPI tables\n",
666 mp_maxid = cores - 1;
673 cores = ofw_cpu_early_foreach(cpu_find_cpu0_fdt, false);
675 cores = MIN(cores, MAXCPU);
677 printf("Found %d CPUs in the device tree\n",
680 mp_maxid = cores - 1;
690 printf("No CPU data, limiting to 1 core\n");
698 static struct intr_ipi *
699 intr_ipi_lookup(u_int ipi)
702 if (ipi >= INTR_IPI_COUNT)
703 panic("%s: no such IPI %u", __func__, ipi);
705 return (&ipi_sources[ipi]);
709 * interrupt controller dispatch function for IPIs. It should
710 * be called straight from the interrupt controller, when associated
711 * interrupt source is learned. Or from anybody who has an interrupt
715 intr_ipi_dispatch(u_int ipi, struct trapframe *tf)
720 ii = intr_ipi_lookup(ipi);
721 if (ii->ii_count == NULL)
722 panic("%s: not setup IPI %u", __func__, ipi);
724 intr_ipi_increment_count(ii->ii_count, PCPU_GET(cpuid));
727 * Supply ipi filter with trapframe argument
728 * if none is registered.
730 arg = ii->ii_handler_arg != NULL ? ii->ii_handler_arg : tf;
736 * Map IPI into interrupt controller.
741 ipi_map(struct intr_irqsrc *isrc, u_int ipi)
746 if (ipi >= INTR_IPI_COUNT)
747 panic("%s: no such IPI %u", __func__, ipi);
749 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
751 isrc->isrc_type = INTR_ISRCT_NAMESPACE;
752 isrc->isrc_nspc_type = INTR_IRQ_NSPC_IPI;
753 isrc->isrc_nspc_num = ipi_next_num;
755 error = PIC_REGISTER(intr_irq_root_dev, isrc, &is_percpu);
757 isrc->isrc_dev = intr_irq_root_dev;
764 * Setup IPI handler to interrupt source.
766 * Note that there could be more ways how to send and receive IPIs
767 * on a platform like fast interrupts for example. In that case,
768 * one can call this function with ASIF_NOALLOC flag set and then
769 * call intr_ipi_dispatch() when appropriate.
774 intr_ipi_set_handler(u_int ipi, const char *name, intr_ipi_filter_t *filter,
775 void *arg, u_int flags)
777 struct intr_irqsrc *isrc;
783 isrc = intr_ipi_lookup(ipi);
784 if (isrc->isrc_ipifilter != NULL)
787 if ((flags & AISHF_NOALLOC) == 0) {
788 error = ipi_map(isrc, ipi);
793 isrc->isrc_ipifilter = filter;
794 isrc->isrc_arg = arg;
795 isrc->isrc_handlers = 1;
796 isrc->isrc_count = intr_ipi_setup_counters(name);
797 isrc->isrc_index = 0; /* it should not be used in IPI case */
799 if (isrc->isrc_dev != NULL) {
800 PIC_ENABLE_INTR(isrc->isrc_dev, isrc);
801 PIC_ENABLE_SOURCE(isrc->isrc_dev, isrc);
809 ipi_all_but_self(u_int ipi)
814 CPU_CLR(PCPU_GET(cpuid), &cpus);
815 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
816 intr_ipi_send(cpus, ipi);
820 ipi_cpu(int cpu, u_int ipi)
827 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
828 intr_ipi_send(cpus, ipi);
832 ipi_selected(cpuset_t cpus, u_int ipi)
835 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
836 intr_ipi_send(cpus, ipi);