2 * Copyright (c) 2015-2016 The FreeBSD Foundation
5 * This software was developed by Andrew Turner under
6 * sponsorship from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include "opt_kstack_pages.h"
32 #include "opt_platform.h"
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/malloc.h>
43 #include <sys/module.h>
44 #include <sys/mutex.h>
46 #include <sys/sched.h>
51 #include <vm/vm_extern.h>
52 #include <vm/vm_kern.h>
54 #include <machine/debug_monitor.h>
55 #include <machine/intr.h>
56 #include <machine/smp.h>
58 #include <machine/vfp.h>
62 #include <dev/ofw/openfirm.h>
63 #include <dev/ofw/ofw_cpu.h>
66 #include <dev/psci/psci.h>
71 typedef void intr_ipi_send_t(void *, cpuset_t, u_int);
72 typedef void intr_ipi_handler_t(void *);
74 #define INTR_IPI_NAMELEN (MAXCOMLEN + 1)
76 intr_ipi_handler_t * ii_handler;
77 void * ii_handler_arg;
78 intr_ipi_send_t * ii_send;
80 char ii_name[INTR_IPI_NAMELEN];
84 static struct intr_ipi ipi_sources[INTR_IPI_COUNT];
86 static struct intr_ipi *intr_ipi_lookup(u_int);
87 static void intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *,
91 boolean_t ofw_cpu_reg(phandle_t node, u_int, cell_t *);
93 extern struct pcpu __pcpu[];
102 static device_identify_t arm64_cpu_identify;
103 static device_probe_t arm64_cpu_probe;
104 static device_attach_t arm64_cpu_attach;
106 static void ipi_ast(void *);
107 static void ipi_hardclock(void *);
108 static void ipi_preempt(void *);
109 static void ipi_rendezvous(void *);
110 static void ipi_stop(void *);
112 static int ipi_handler(void *arg);
114 struct mtx ap_boot_mtx;
115 struct pcb stoppcbs[MAXCPU];
118 static uint32_t cpu_reg[MAXCPU][2];
120 static device_t cpu_list[MAXCPU];
123 * Not all systems boot from the first CPU in the device tree. To work around
124 * this we need to find which CPU we have booted from so when we later
125 * enable the secondary CPUs we skip this one.
127 static int cpu0 = -1;
129 void mpentry(unsigned long cpuid);
130 void init_secondary(uint64_t);
132 uint8_t secondary_stacks[MAXCPU - 1][PAGE_SIZE * KSTACK_PAGES] __aligned(16);
134 /* Set to 1 once we're ready to let the APs out of the pen. */
135 volatile int aps_ready = 0;
137 /* Temporary variables for init_secondary() */
138 void *dpcpu[MAXCPU - 1];
140 static device_method_t arm64_cpu_methods[] = {
141 /* Device interface */
142 DEVMETHOD(device_identify, arm64_cpu_identify),
143 DEVMETHOD(device_probe, arm64_cpu_probe),
144 DEVMETHOD(device_attach, arm64_cpu_attach),
149 static devclass_t arm64_cpu_devclass;
150 static driver_t arm64_cpu_driver = {
156 DRIVER_MODULE(arm64_cpu, cpu, arm64_cpu_driver, arm64_cpu_devclass, 0, 0);
159 arm64_cpu_identify(driver_t *driver, device_t parent)
162 if (device_find_child(parent, "arm64_cpu", -1) != NULL)
164 if (BUS_ADD_CHILD(parent, 0, "arm64_cpu", -1) == NULL)
165 device_printf(parent, "add child failed\n");
169 arm64_cpu_probe(device_t dev)
173 cpuid = device_get_unit(dev);
174 if (cpuid >= MAXCPU || cpuid > mp_maxid)
182 arm64_cpu_attach(device_t dev)
189 cpuid = device_get_unit(dev);
191 if (cpuid >= MAXCPU || cpuid > mp_maxid)
193 KASSERT(cpu_list[cpuid] == NULL, ("Already have cpu %u", cpuid));
195 reg = cpu_get_cpuid(dev, ®_size);
200 device_printf(dev, "register <");
201 for (i = 0; i < reg_size; i++)
202 printf("%s%x", (i == 0) ? "" : " ", reg[i]);
206 /* Set the device to start it later */
207 cpu_list[cpuid] = dev;
213 release_aps(void *dummy __unused)
218 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
219 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
220 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
221 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
222 intr_pic_ipi_setup(IPI_STOP_HARD, "stop hard", ipi_stop, NULL);
223 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
225 /* Setup the IPI handler */
226 for (i = 0; i < INTR_IPI_COUNT; i++)
227 arm_setup_ipihandler(ipi_handler, i);
230 atomic_store_rel_int(&aps_ready, 1);
231 /* Wake up the other CPUs */
232 __asm __volatile("sev");
234 printf("Release APs\n");
236 for (i = 0; i < 2000; i++) {
238 for (cpu = 0; cpu <= mp_maxid; cpu++) {
241 print_cpu_features(cpu);
248 printf("APs not started\n");
250 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
253 init_secondary(uint64_t cpu)
260 pcpup = &__pcpu[cpu];
262 * Set the pcpu pointer with a backup in tpidr_el1 to be
263 * loaded when entering the kernel from userland.
267 "msr tpidr_el1, %0" :: "r"(pcpup));
269 /* Spin until the BSP releases the APs */
271 __asm __volatile("wfe");
273 /* Initialize curthread */
274 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
275 pcpup->pc_curthread = pcpup->pc_idlethread;
276 pcpup->pc_curpcb = pcpup->pc_idlethread->td_pcb;
279 * Identify current CPU. This is necessary to setup
280 * affinity registers and to provide support for
281 * runtime chip identification.
286 intr_pic_init_secondary();
288 /* Configure the interrupt controller */
289 arm_init_secondary();
291 for (i = 0; i < INTR_IPI_COUNT; i++)
295 /* Start per-CPU event timers. */
304 /* Enable interrupts */
307 mtx_lock_spin(&ap_boot_mtx);
309 atomic_add_rel_32(&smp_cpus, 1);
311 if (smp_cpus == mp_ncpus) {
312 /* enable IPI's, tlb shootdown, freezes etc */
313 atomic_store_rel_int(&smp_started, 1);
316 mtx_unlock_spin(&ap_boot_mtx);
318 /* Enter the scheduler */
321 panic("scheduler returned us to init_secondary");
327 * Send IPI thru interrupt controller.
330 pic_ipi_send(void *arg, cpuset_t cpus, u_int ipi)
333 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
334 PIC_IPI_SEND(intr_irq_root_dev, arg, cpus, ipi);
338 * Setup IPI handler on interrupt controller.
343 intr_pic_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand,
346 struct intr_irqsrc *isrc;
350 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
351 KASSERT(hand != NULL, ("%s: ipi %u no handler", __func__, ipi));
353 error = PIC_IPI_SETUP(intr_irq_root_dev, ipi, &isrc);
357 isrc->isrc_handlers++;
359 ii = intr_ipi_lookup(ipi);
360 KASSERT(ii->ii_count == NULL, ("%s: ipi %u reused", __func__, ipi));
362 ii->ii_handler = hand;
363 ii->ii_handler_arg = arg;
364 ii->ii_send = pic_ipi_send;
365 ii->ii_send_arg = isrc;
366 strlcpy(ii->ii_name, name, INTR_IPI_NAMELEN);
367 ii->ii_count = intr_ipi_setup_counters(name);
371 intr_ipi_send(cpuset_t cpus, u_int ipi)
375 ii = intr_ipi_lookup(ipi);
376 if (ii->ii_count == NULL)
377 panic("%s: not setup IPI %u", __func__, ipi);
379 ii->ii_send(ii->ii_send_arg, cpus, ipi);
384 ipi_ast(void *dummy __unused)
387 CTR0(KTR_SMP, "IPI_AST");
391 ipi_hardclock(void *dummy __unused)
394 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
399 ipi_preempt(void *dummy __unused)
401 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
402 sched_preempt(curthread);
406 ipi_rendezvous(void *dummy __unused)
409 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
410 smp_rendezvous_action();
414 ipi_stop(void *dummy __unused)
418 CTR0(KTR_SMP, "IPI_STOP");
420 cpu = PCPU_GET(cpuid);
421 savectx(&stoppcbs[cpu]);
423 /* Indicate we are stopped */
424 CPU_SET_ATOMIC(cpu, &stopped_cpus);
426 /* Wait for restart */
427 while (!CPU_ISSET(cpu, &started_cpus))
430 CPU_CLR_ATOMIC(cpu, &started_cpus);
431 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
432 CTR0(KTR_SMP, "IPI_STOP (restart)");
437 ipi_handler(void *arg)
441 arg = (void *)((uintptr_t)arg & ~(1 << 16));
442 KASSERT((uintptr_t)arg < INTR_IPI_COUNT,
443 ("Invalid IPI %ju", (uintptr_t)arg));
445 cpu = PCPU_GET(cpuid);
446 ipi = (uintptr_t)arg;
456 ipi_rendezvous(NULL);
466 panic("Unknown IPI %#0x on cpu %d", ipi, curcpu);
469 return (FILTER_HANDLED);
477 return (smp_topo_none());
480 /* Determine if we running MP machine */
485 /* ARM64TODO: Read the u bit of mpidr_el1 to determine this */
491 cpu_init_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
499 /* Check we are able to start this cpu */
503 KASSERT(id < MAXCPU, ("Too mant CPUs"));
505 KASSERT(addr_size == 1 || addr_size == 2, ("Invalid register size"));
507 cpu_reg[id][0] = reg[0];
509 cpu_reg[id][1] = reg[1];
512 /* We are already running on cpu 0 */
520 pcpup = &__pcpu[cpuid];
521 pcpu_init(pcpup, cpuid, sizeof(struct pcpu));
523 dpcpu[cpuid - 1] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
525 dpcpu_init(dpcpu[cpuid - 1], cpuid);
528 if (addr_size == 2) {
530 target_cpu |= reg[1];
533 printf("Starting CPU %u (%lx)\n", cpuid, target_cpu);
534 pa = pmap_extract(kernel_pmap, (vm_offset_t)mpentry);
536 err = psci_cpu_on(target_cpu, pa, cpuid);
537 if (err != PSCI_RETVAL_SUCCESS) {
538 /* Panic here if INVARIANTS are enabled */
539 KASSERT(0, ("Failed to start CPU %u (%lx)\n", id,
543 kmem_free(kernel_arena, (vm_offset_t)dpcpu[cpuid - 1],
545 dpcpu[cpuid - 1] = NULL;
546 /* Notify the user that the CPU failed to start */
547 printf("Failed to start CPU %u (%lx)\n", id, target_cpu);
549 CPU_SET(cpuid, &all_cpus);
555 /* Initialize and fire up non-boot processors */
560 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
562 CPU_SET(0, &all_cpus);
564 switch(cpu_enum_method) {
567 KASSERT(cpu0 >= 0, ("Current CPU was not found"));
568 ofw_cpu_early_foreach(cpu_init_fdt, true);
576 /* Introduce rest of cores to the world */
578 cpu_mp_announce(void)
583 cpu_find_cpu0_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
585 uint64_t mpidr_fdt, mpidr_reg;
589 if (addr_size == 2) {
594 mpidr_reg = READ_SPECIALREG(mpidr_el1);
596 if ((mpidr_reg & 0xff00fffffful) == mpidr_fdt)
604 cpu_mp_setmaxid(void)
609 cores = ofw_cpu_early_foreach(cpu_find_cpu0_fdt, false);
611 cores = MIN(cores, MAXCPU);
613 printf("Found %d CPUs in the device tree\n", cores);
615 mp_maxid = cores - 1;
616 cpu_enum_method = CPUS_FDT;
622 printf("No CPU data, limiting to 1 core\n");
631 static struct intr_ipi *
632 intr_ipi_lookup(u_int ipi)
635 if (ipi >= INTR_IPI_COUNT)
636 panic("%s: no such IPI %u", __func__, ipi);
638 return (&ipi_sources[ipi]);
642 * interrupt controller dispatch function for IPIs. It should
643 * be called straight from the interrupt controller, when associated
644 * interrupt source is learned. Or from anybody who has an interrupt
648 intr_ipi_dispatch(u_int ipi, struct trapframe *tf)
653 ii = intr_ipi_lookup(ipi);
654 if (ii->ii_count == NULL)
655 panic("%s: not setup IPI %u", __func__, ipi);
657 intr_ipi_increment_count(ii->ii_count, PCPU_GET(cpuid));
660 * Supply ipi filter with trapframe argument
661 * if none is registered.
663 arg = ii->ii_handler_arg != NULL ? ii->ii_handler_arg : tf;
669 * Map IPI into interrupt controller.
674 ipi_map(struct intr_irqsrc *isrc, u_int ipi)
679 if (ipi >= INTR_IPI_COUNT)
680 panic("%s: no such IPI %u", __func__, ipi);
682 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
684 isrc->isrc_type = INTR_ISRCT_NAMESPACE;
685 isrc->isrc_nspc_type = INTR_IRQ_NSPC_IPI;
686 isrc->isrc_nspc_num = ipi_next_num;
688 error = PIC_REGISTER(intr_irq_root_dev, isrc, &is_percpu);
690 isrc->isrc_dev = intr_irq_root_dev;
697 * Setup IPI handler to interrupt source.
699 * Note that there could be more ways how to send and receive IPIs
700 * on a platform like fast interrupts for example. In that case,
701 * one can call this function with ASIF_NOALLOC flag set and then
702 * call intr_ipi_dispatch() when appropriate.
707 intr_ipi_set_handler(u_int ipi, const char *name, intr_ipi_filter_t *filter,
708 void *arg, u_int flags)
710 struct intr_irqsrc *isrc;
716 isrc = intr_ipi_lookup(ipi);
717 if (isrc->isrc_ipifilter != NULL)
720 if ((flags & AISHF_NOALLOC) == 0) {
721 error = ipi_map(isrc, ipi);
726 isrc->isrc_ipifilter = filter;
727 isrc->isrc_arg = arg;
728 isrc->isrc_handlers = 1;
729 isrc->isrc_count = intr_ipi_setup_counters(name);
730 isrc->isrc_index = 0; /* it should not be used in IPI case */
732 if (isrc->isrc_dev != NULL) {
733 PIC_ENABLE_INTR(isrc->isrc_dev, isrc);
734 PIC_ENABLE_SOURCE(isrc->isrc_dev, isrc);
742 ipi_all_but_self(u_int ipi)
747 CPU_CLR(PCPU_GET(cpuid), &cpus);
748 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
749 intr_ipi_send(cpus, ipi);
753 ipi_cpu(int cpu, u_int ipi)
760 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
761 intr_ipi_send(cpus, ipi);
765 ipi_selected(cpuset_t cpus, u_int ipi)
768 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
769 intr_ipi_send(cpus, ipi);