2 * Copyright (c) 2015-2016 The FreeBSD Foundation
5 * This software was developed by Andrew Turner under
6 * sponsorship from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include "opt_kstack_pages.h"
34 #include "opt_platform.h"
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include <sys/param.h>
40 #include <sys/systm.h>
44 #include <sys/kernel.h>
46 #include <sys/malloc.h>
47 #include <sys/module.h>
48 #include <sys/mutex.h>
51 #include <sys/sched.h>
56 #include <vm/vm_extern.h>
57 #include <vm/vm_kern.h>
58 #include <vm/vm_map.h>
60 #include <machine/machdep.h>
61 #include <machine/debug_monitor.h>
62 #include <machine/intr.h>
63 #include <machine/smp.h>
65 #include <machine/vfp.h>
69 #include <contrib/dev/acpica/include/acpi.h>
70 #include <dev/acpica/acpivar.h>
74 #include <dev/ofw/openfirm.h>
75 #include <dev/ofw/ofw_bus.h>
76 #include <dev/ofw/ofw_bus_subr.h>
77 #include <dev/ofw/ofw_cpu.h>
80 #include <dev/psci/psci.h>
84 #define MP_QUIRK_CPULIST 0x01 /* The list of cpus may be wrong, */
85 /* don't panic if one fails to start */
86 static uint32_t mp_quirks;
93 { "arm,foundation-aarch64", MP_QUIRK_CPULIST },
94 { "arm,fvp-base", MP_QUIRK_CPULIST },
95 /* This is incorrect in some DTS files */
96 { "arm,vfp-base", MP_QUIRK_CPULIST },
101 typedef void intr_ipi_send_t(void *, cpuset_t, u_int);
102 typedef void intr_ipi_handler_t(void *);
104 #define INTR_IPI_NAMELEN (MAXCOMLEN + 1)
106 intr_ipi_handler_t * ii_handler;
107 void * ii_handler_arg;
108 intr_ipi_send_t * ii_send;
110 char ii_name[INTR_IPI_NAMELEN];
114 static struct intr_ipi ipi_sources[INTR_IPI_COUNT];
116 static struct intr_ipi *intr_ipi_lookup(u_int);
117 static void intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *,
120 static void ipi_ast(void *);
121 static void ipi_hardclock(void *);
122 static void ipi_preempt(void *);
123 static void ipi_rendezvous(void *);
124 static void ipi_stop(void *);
126 struct pcb stoppcbs[MAXCPU];
129 static u_int fdt_cpuid;
132 void mpentry(unsigned long cpuid);
133 void init_secondary(uint64_t);
135 /* Synchronize AP startup. */
136 static struct mtx ap_boot_mtx;
138 /* Stacks for AP initialization, discarded once idle threads are started. */
140 static void *bootstacks[MAXCPU];
142 /* Count of started APs, used to synchronize access to bootstack. */
143 static volatile int aps_started;
145 /* Set to 1 once we're ready to let the APs out of the pen. */
146 static volatile int aps_ready;
148 /* Temporary variables for init_secondary() */
149 void *dpcpu[MAXCPU - 1];
152 is_boot_cpu(uint64_t target_cpu)
155 return (__pcpu[0].pc_mpidr == (target_cpu & CPU_AFF_MASK));
159 release_aps(void *dummy __unused)
163 /* Only release CPUs if they exist */
167 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
168 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
169 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
170 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
171 intr_pic_ipi_setup(IPI_STOP_HARD, "stop hard", ipi_stop, NULL);
172 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
174 atomic_store_rel_int(&aps_ready, 1);
175 /* Wake up the other CPUs */
181 printf("Release APs...");
184 for (i = 0; i < 2000; i++) {
190 * Don't time out while we are making progress. Some large
191 * systems can take a while to start all CPUs.
193 if (smp_cpus > started) {
200 printf("APs not started\n");
202 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
205 init_secondary(uint64_t cpu)
210 pcpup = &__pcpu[cpu];
212 * Set the pcpu pointer with a backup in tpidr_el1 to be
213 * loaded when entering the kernel from userland.
217 "msr tpidr_el1, %0" :: "r"(pcpup));
220 * Identify current CPU. This is necessary to setup
221 * affinity registers and to provide support for
222 * runtime chip identification.
224 * We need this before signalling the CPU is ready to
225 * let the boot CPU use the results.
229 /* Ensure the stores in identify_cpu have completed */
230 atomic_thread_fence_acq_rel();
232 /* Signal the BSP and spin until it has released all APs. */
233 atomic_add_int(&aps_started, 1);
234 while (!atomic_load_int(&aps_ready))
235 __asm __volatile("wfe");
237 pcpup->pc_midr = get_midr();
239 /* Initialize curthread */
240 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
241 pcpup->pc_curthread = pcpup->pc_idlethread;
243 /* Initialize curpmap to match TTBR0's current setting. */
244 pmap0 = vmspace_pmap(&vmspace0);
245 KASSERT(pmap_to_ttbr0(pmap0) == READ_SPECIALREG(ttbr0_el1),
246 ("pmap0 doesn't match cpu %ld's ttbr0", cpu));
247 pcpup->pc_curpmap = pmap0;
249 install_cpu_errata();
251 intr_pic_init_secondary();
253 /* Start per-CPU event timers. */
263 mtx_lock_spin(&ap_boot_mtx);
264 atomic_add_rel_32(&smp_cpus, 1);
265 if (smp_cpus == mp_ncpus) {
266 /* enable IPI's, tlb shootdown, freezes etc */
267 atomic_store_rel_int(&smp_started, 1);
269 mtx_unlock_spin(&ap_boot_mtx);
274 * Assert that smp_after_idle_runnable condition is reasonable.
276 MPASS(PCPU_GET(curpcb) == NULL);
278 /* Enter the scheduler */
281 panic("scheduler returned us to init_secondary");
286 smp_after_idle_runnable(void *arg __unused)
291 for (cpu = 1; cpu < mp_ncpus; cpu++) {
292 if (bootstacks[cpu] != NULL) {
294 while (atomic_load_ptr(&pc->pc_curpcb) == NULL)
296 kmem_free((vm_offset_t)bootstacks[cpu], PAGE_SIZE);
300 SYSINIT(smp_after_idle_runnable, SI_SUB_SMP, SI_ORDER_ANY,
301 smp_after_idle_runnable, NULL);
304 * Send IPI thru interrupt controller.
307 pic_ipi_send(void *arg, cpuset_t cpus, u_int ipi)
310 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
313 * Ensure that this CPU's stores will be visible to IPI
314 * recipients before starting to send the interrupts.
318 PIC_IPI_SEND(intr_irq_root_dev, arg, cpus, ipi);
322 * Setup IPI handler on interrupt controller.
327 intr_pic_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand,
330 struct intr_irqsrc *isrc;
334 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
335 KASSERT(hand != NULL, ("%s: ipi %u no handler", __func__, ipi));
337 error = PIC_IPI_SETUP(intr_irq_root_dev, ipi, &isrc);
341 isrc->isrc_handlers++;
343 ii = intr_ipi_lookup(ipi);
344 KASSERT(ii->ii_count == NULL, ("%s: ipi %u reused", __func__, ipi));
346 ii->ii_handler = hand;
347 ii->ii_handler_arg = arg;
348 ii->ii_send = pic_ipi_send;
349 ii->ii_send_arg = isrc;
350 strlcpy(ii->ii_name, name, INTR_IPI_NAMELEN);
351 ii->ii_count = intr_ipi_setup_counters(name);
355 intr_ipi_send(cpuset_t cpus, u_int ipi)
359 ii = intr_ipi_lookup(ipi);
360 if (ii->ii_count == NULL)
361 panic("%s: not setup IPI %u", __func__, ipi);
363 ii->ii_send(ii->ii_send_arg, cpus, ipi);
367 ipi_ast(void *dummy __unused)
370 CTR0(KTR_SMP, "IPI_AST");
374 ipi_hardclock(void *dummy __unused)
377 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
382 ipi_preempt(void *dummy __unused)
384 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
385 sched_preempt(curthread);
389 ipi_rendezvous(void *dummy __unused)
392 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
393 smp_rendezvous_action();
397 ipi_stop(void *dummy __unused)
401 CTR0(KTR_SMP, "IPI_STOP");
403 cpu = PCPU_GET(cpuid);
404 savectx(&stoppcbs[cpu]);
406 /* Indicate we are stopped */
407 CPU_SET_ATOMIC(cpu, &stopped_cpus);
409 /* Wait for restart */
410 while (!CPU_ISSET(cpu, &started_cpus))
414 dbg_register_sync(NULL);
417 CPU_CLR_ATOMIC(cpu, &started_cpus);
418 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
419 CTR0(KTR_SMP, "IPI_STOP (restart)");
426 return (smp_topo_none());
429 /* Determine if we running MP machine */
434 /* ARM64TODO: Read the u bit of mpidr_el1 to determine this */
439 * Starts a given CPU. If the CPU is already running, i.e. it is the boot CPU,
440 * do nothing. Returns true if the CPU is present and running.
443 start_cpu(u_int cpuid, uint64_t target_cpu)
449 /* Check we are able to start this cpu */
450 if (cpuid > mp_maxid)
454 if (is_boot_cpu(target_cpu))
457 KASSERT(cpuid < MAXCPU, ("Too many CPUs"));
459 pcpup = &__pcpu[cpuid];
460 pcpu_init(pcpup, cpuid, sizeof(struct pcpu));
461 pcpup->pc_mpidr = target_cpu & CPU_AFF_MASK;
463 dpcpu[cpuid - 1] = (void *)kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO);
464 dpcpu_init(dpcpu[cpuid - 1], cpuid);
466 bootstacks[cpuid] = (void *)kmem_malloc(PAGE_SIZE, M_WAITOK | M_ZERO);
468 naps = atomic_load_int(&aps_started);
469 bootstack = (char *)bootstacks[cpuid] + PAGE_SIZE;
471 printf("Starting CPU %u (%lx)\n", cpuid, target_cpu);
472 pa = pmap_extract(kernel_pmap, (vm_offset_t)mpentry);
473 err = psci_cpu_on(target_cpu, pa, cpuid);
474 if (err != PSCI_RETVAL_SUCCESS) {
476 * Panic here if INVARIANTS are enabled and PSCI failed to
477 * start the requested CPU. psci_cpu_on() returns PSCI_MISSING
478 * to indicate we are unable to use it to start the given CPU.
480 KASSERT(err == PSCI_MISSING ||
481 (mp_quirks & MP_QUIRK_CPULIST) == MP_QUIRK_CPULIST,
482 ("Failed to start CPU %u (%lx), error %d\n",
483 cpuid, target_cpu, err));
486 kmem_free((vm_offset_t)dpcpu[cpuid - 1], DPCPU_SIZE);
487 dpcpu[cpuid - 1] = NULL;
488 kmem_free((vm_offset_t)bootstacks[cpuid], PAGE_SIZE);
489 bootstacks[cpuid] = NULL;
494 /* Wait for the AP to switch to its boot stack. */
495 while (atomic_load_int(&aps_started) < naps + 1)
497 CPU_SET(cpuid, &all_cpus);
504 madt_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
506 ACPI_MADT_GENERIC_INTERRUPT *intr;
510 switch(entry->Type) {
511 case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
512 intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
515 if (is_boot_cpu(intr->ArmMpidr))
520 if (start_cpu(id, intr->ArmMpidr)) {
521 __pcpu[id].pc_acpi_id = intr->Uid;
523 * Don't increment for the boot CPU, its CPU ID is
526 if (!is_boot_cpu(intr->ArmMpidr))
539 ACPI_TABLE_MADT *madt;
543 physaddr = acpi_find_table(ACPI_SIG_MADT);
547 madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
549 printf("Unable to map the MADT, not starting APs\n");
552 /* Boot CPU is always 0 */
554 acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
555 madt_handler, &cpuid);
557 acpi_unmap_table(madt);
560 acpi_pxm_set_cpu_locality();
567 start_cpu_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
574 if (addr_size == 2) {
576 target_cpu |= reg[1];
579 if (is_boot_cpu(target_cpu))
584 if (!start_cpu(cpuid, target_cpu))
588 * Don't increment for the boot CPU, its CPU ID is reserved.
590 if (!is_boot_cpu(target_cpu))
593 /* Try to read the numa node of this cpu */
594 if (vm_ndomains == 1 ||
595 OF_getencprop(node, "numa-node-id", &domain, sizeof(domain)) <= 0)
597 __pcpu[cpuid].pc_domain = domain;
598 if (domain < MAXMEMDOM)
599 CPU_SET(cpuid, &cpuset_domain[domain]);
609 for (i = 0; fdt_quirks[i].compat != NULL; i++) {
610 if (ofw_bus_node_is_compatible(node,
611 fdt_quirks[i].compat) != 0) {
612 mp_quirks = fdt_quirks[i].quirks;
616 ofw_cpu_early_foreach(start_cpu_fdt, true);
620 /* Initialize and fire up non-boot processors */
624 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
626 /* CPU 0 is always boot CPU. */
627 CPU_SET(0, &all_cpus);
628 __pcpu[0].pc_mpidr = READ_SPECIALREG(mpidr_el1) & CPU_AFF_MASK;
630 switch(arm64_bus_method) {
633 mp_quirks = MP_QUIRK_CPULIST;
647 /* Introduce rest of cores to the world */
649 cpu_mp_announce(void)
655 cpu_count_acpi_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
657 ACPI_MADT_GENERIC_INTERRUPT *intr;
660 switch(entry->Type) {
661 case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
662 intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
673 ACPI_TABLE_MADT *madt;
677 physaddr = acpi_find_table(ACPI_SIG_MADT);
681 madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
683 printf("Unable to map the MADT, not starting APs\n");
688 acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
689 cpu_count_acpi_handler, &cores);
691 acpi_unmap_table(madt);
698 cpu_mp_setmaxid(void)
705 switch(arm64_bus_method) {
708 cores = cpu_count_acpi();
710 cores = MIN(cores, MAXCPU);
712 printf("Found %d CPUs in the ACPI tables\n",
715 mp_maxid = cores - 1;
721 cores = ofw_cpu_early_foreach(NULL, false);
723 cores = MIN(cores, MAXCPU);
725 printf("Found %d CPUs in the device tree\n",
728 mp_maxid = cores - 1;
734 printf("No CPU data, limiting to 1 core\n");
738 if (TUNABLE_INT_FETCH("hw.ncpu", &cores)) {
739 if (cores > 0 && cores < mp_ncpus) {
741 mp_maxid = cores - 1;
749 static struct intr_ipi *
750 intr_ipi_lookup(u_int ipi)
753 if (ipi >= INTR_IPI_COUNT)
754 panic("%s: no such IPI %u", __func__, ipi);
756 return (&ipi_sources[ipi]);
760 * interrupt controller dispatch function for IPIs. It should
761 * be called straight from the interrupt controller, when associated
762 * interrupt source is learned. Or from anybody who has an interrupt
766 intr_ipi_dispatch(u_int ipi, struct trapframe *tf)
771 ii = intr_ipi_lookup(ipi);
772 if (ii->ii_count == NULL)
773 panic("%s: not setup IPI %u", __func__, ipi);
775 intr_ipi_increment_count(ii->ii_count, PCPU_GET(cpuid));
778 * Supply ipi filter with trapframe argument
779 * if none is registered.
781 arg = ii->ii_handler_arg != NULL ? ii->ii_handler_arg : tf;
787 * Map IPI into interrupt controller.
792 ipi_map(struct intr_irqsrc *isrc, u_int ipi)
797 if (ipi >= INTR_IPI_COUNT)
798 panic("%s: no such IPI %u", __func__, ipi);
800 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
802 isrc->isrc_type = INTR_ISRCT_NAMESPACE;
803 isrc->isrc_nspc_type = INTR_IRQ_NSPC_IPI;
804 isrc->isrc_nspc_num = ipi_next_num;
806 error = PIC_REGISTER(intr_irq_root_dev, isrc, &is_percpu);
808 isrc->isrc_dev = intr_irq_root_dev;
815 * Setup IPI handler to interrupt source.
817 * Note that there could be more ways how to send and receive IPIs
818 * on a platform like fast interrupts for example. In that case,
819 * one can call this function with ASIF_NOALLOC flag set and then
820 * call intr_ipi_dispatch() when appropriate.
825 intr_ipi_set_handler(u_int ipi, const char *name, intr_ipi_filter_t *filter,
826 void *arg, u_int flags)
828 struct intr_irqsrc *isrc;
834 isrc = intr_ipi_lookup(ipi);
835 if (isrc->isrc_ipifilter != NULL)
838 if ((flags & AISHF_NOALLOC) == 0) {
839 error = ipi_map(isrc, ipi);
844 isrc->isrc_ipifilter = filter;
845 isrc->isrc_arg = arg;
846 isrc->isrc_handlers = 1;
847 isrc->isrc_count = intr_ipi_setup_counters(name);
848 isrc->isrc_index = 0; /* it should not be used in IPI case */
850 if (isrc->isrc_dev != NULL) {
851 PIC_ENABLE_INTR(isrc->isrc_dev, isrc);
852 PIC_ENABLE_SOURCE(isrc->isrc_dev, isrc);
860 ipi_all_but_self(u_int ipi)
865 CPU_CLR(PCPU_GET(cpuid), &cpus);
866 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
867 intr_ipi_send(cpus, ipi);
871 ipi_cpu(int cpu, u_int ipi)
878 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
879 intr_ipi_send(cpus, ipi);
883 ipi_selected(cpuset_t cpus, u_int ipi)
886 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
887 intr_ipi_send(cpus, ipi);