2 * Copyright (c) 2015-2016 The FreeBSD Foundation
5 * This software was developed by Andrew Turner under
6 * sponsorship from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include "opt_kstack_pages.h"
33 #include "opt_platform.h"
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/malloc.h>
44 #include <sys/module.h>
45 #include <sys/mutex.h>
47 #include <sys/sched.h>
52 #include <vm/vm_extern.h>
53 #include <vm/vm_kern.h>
55 #include <machine/machdep.h>
56 #include <machine/intr.h>
57 #include <machine/smp.h>
59 #include <machine/vfp.h>
63 #include <contrib/dev/acpica/include/acpi.h>
64 #include <dev/acpica/acpivar.h>
68 #include <dev/ofw/openfirm.h>
69 #include <dev/ofw/ofw_bus.h>
70 #include <dev/ofw/ofw_bus_subr.h>
71 #include <dev/ofw/ofw_cpu.h>
74 #include <dev/psci/psci.h>
78 #define MP_QUIRK_CPULIST 0x01 /* The list of cpus may be wrong, */
79 /* don't panic if one fails to start */
80 static uint32_t mp_quirks;
87 { "arm,foundation-aarch64", MP_QUIRK_CPULIST },
88 { "arm,fvp-base", MP_QUIRK_CPULIST },
89 /* This is incorrect in some DTS files */
90 { "arm,vfp-base", MP_QUIRK_CPULIST },
95 typedef void intr_ipi_send_t(void *, cpuset_t, u_int);
96 typedef void intr_ipi_handler_t(void *);
98 #define INTR_IPI_NAMELEN (MAXCOMLEN + 1)
100 intr_ipi_handler_t * ii_handler;
101 void * ii_handler_arg;
102 intr_ipi_send_t * ii_send;
104 char ii_name[INTR_IPI_NAMELEN];
108 static struct intr_ipi ipi_sources[INTR_IPI_COUNT];
110 static struct intr_ipi *intr_ipi_lookup(u_int);
111 static void intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *,
114 extern struct pcpu __pcpu[];
116 static device_identify_t arm64_cpu_identify;
117 static device_probe_t arm64_cpu_probe;
118 static device_attach_t arm64_cpu_attach;
120 static void ipi_ast(void *);
121 static void ipi_hardclock(void *);
122 static void ipi_preempt(void *);
123 static void ipi_rendezvous(void *);
124 static void ipi_stop(void *);
126 struct mtx ap_boot_mtx;
127 struct pcb stoppcbs[MAXCPU];
129 static device_t cpu_list[MAXCPU];
132 * Not all systems boot from the first CPU in the device tree. To work around
133 * this we need to find which CPU we have booted from so when we later
134 * enable the secondary CPUs we skip this one.
136 static int cpu0 = -1;
138 void mpentry(unsigned long cpuid);
139 void init_secondary(uint64_t);
141 uint8_t secondary_stacks[MAXCPU - 1][PAGE_SIZE * KSTACK_PAGES] __aligned(16);
143 /* Set to 1 once we're ready to let the APs out of the pen. */
144 volatile int aps_ready = 0;
146 /* Temporary variables for init_secondary() */
147 void *dpcpu[MAXCPU - 1];
149 static device_method_t arm64_cpu_methods[] = {
150 /* Device interface */
151 DEVMETHOD(device_identify, arm64_cpu_identify),
152 DEVMETHOD(device_probe, arm64_cpu_probe),
153 DEVMETHOD(device_attach, arm64_cpu_attach),
158 static devclass_t arm64_cpu_devclass;
159 static driver_t arm64_cpu_driver = {
165 DRIVER_MODULE(arm64_cpu, cpu, arm64_cpu_driver, arm64_cpu_devclass, 0, 0);
168 arm64_cpu_identify(driver_t *driver, device_t parent)
171 if (device_find_child(parent, "arm64_cpu", -1) != NULL)
173 if (BUS_ADD_CHILD(parent, 0, "arm64_cpu", -1) == NULL)
174 device_printf(parent, "add child failed\n");
178 arm64_cpu_probe(device_t dev)
182 cpuid = device_get_unit(dev);
183 if (cpuid >= MAXCPU || cpuid > mp_maxid)
191 arm64_cpu_attach(device_t dev)
198 cpuid = device_get_unit(dev);
200 if (cpuid >= MAXCPU || cpuid > mp_maxid)
202 KASSERT(cpu_list[cpuid] == NULL, ("Already have cpu %u", cpuid));
204 reg = cpu_get_cpuid(dev, ®_size);
209 device_printf(dev, "register <");
210 for (i = 0; i < reg_size; i++)
211 printf("%s%x", (i == 0) ? "" : " ", reg[i]);
215 /* Set the device to start it later */
216 cpu_list[cpuid] = dev;
222 release_aps(void *dummy __unused)
226 /* Only release CPUs if they exist */
230 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
231 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
232 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
233 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
234 intr_pic_ipi_setup(IPI_STOP_HARD, "stop hard", ipi_stop, NULL);
235 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
237 atomic_store_rel_int(&aps_ready, 1);
238 /* Wake up the other CPUs */
244 printf("Release APs\n");
246 for (i = 0; i < 2000; i++) {
252 printf("APs not started\n");
254 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
257 init_secondary(uint64_t cpu)
261 pcpup = &__pcpu[cpu];
263 * Set the pcpu pointer with a backup in tpidr_el1 to be
264 * loaded when entering the kernel from userland.
268 "msr tpidr_el1, %0" :: "r"(pcpup));
270 /* Spin until the BSP releases the APs */
272 __asm __volatile("wfe");
274 /* Initialize curthread */
275 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
276 pcpup->pc_curthread = pcpup->pc_idlethread;
277 pcpup->pc_curpcb = pcpup->pc_idlethread->td_pcb;
280 * Identify current CPU. This is necessary to setup
281 * affinity registers and to provide support for
282 * runtime chip identification.
285 install_cpu_errata();
287 intr_pic_init_secondary();
289 /* Start per-CPU event timers. */
299 /* Enable interrupts */
302 mtx_lock_spin(&ap_boot_mtx);
304 atomic_add_rel_32(&smp_cpus, 1);
306 if (smp_cpus == mp_ncpus) {
307 /* enable IPI's, tlb shootdown, freezes etc */
308 atomic_store_rel_int(&smp_started, 1);
311 mtx_unlock_spin(&ap_boot_mtx);
313 /* Enter the scheduler */
316 panic("scheduler returned us to init_secondary");
321 * Send IPI thru interrupt controller.
324 pic_ipi_send(void *arg, cpuset_t cpus, u_int ipi)
327 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
328 PIC_IPI_SEND(intr_irq_root_dev, arg, cpus, ipi);
332 * Setup IPI handler on interrupt controller.
337 intr_pic_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand,
340 struct intr_irqsrc *isrc;
344 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
345 KASSERT(hand != NULL, ("%s: ipi %u no handler", __func__, ipi));
347 error = PIC_IPI_SETUP(intr_irq_root_dev, ipi, &isrc);
351 isrc->isrc_handlers++;
353 ii = intr_ipi_lookup(ipi);
354 KASSERT(ii->ii_count == NULL, ("%s: ipi %u reused", __func__, ipi));
356 ii->ii_handler = hand;
357 ii->ii_handler_arg = arg;
358 ii->ii_send = pic_ipi_send;
359 ii->ii_send_arg = isrc;
360 strlcpy(ii->ii_name, name, INTR_IPI_NAMELEN);
361 ii->ii_count = intr_ipi_setup_counters(name);
365 intr_ipi_send(cpuset_t cpus, u_int ipi)
369 ii = intr_ipi_lookup(ipi);
370 if (ii->ii_count == NULL)
371 panic("%s: not setup IPI %u", __func__, ipi);
373 ii->ii_send(ii->ii_send_arg, cpus, ipi);
377 ipi_ast(void *dummy __unused)
380 CTR0(KTR_SMP, "IPI_AST");
384 ipi_hardclock(void *dummy __unused)
387 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
392 ipi_preempt(void *dummy __unused)
394 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
395 sched_preempt(curthread);
399 ipi_rendezvous(void *dummy __unused)
402 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
403 smp_rendezvous_action();
407 ipi_stop(void *dummy __unused)
411 CTR0(KTR_SMP, "IPI_STOP");
413 cpu = PCPU_GET(cpuid);
414 savectx(&stoppcbs[cpu]);
416 /* Indicate we are stopped */
417 CPU_SET_ATOMIC(cpu, &stopped_cpus);
419 /* Wait for restart */
420 while (!CPU_ISSET(cpu, &started_cpus))
423 CPU_CLR_ATOMIC(cpu, &started_cpus);
424 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
425 CTR0(KTR_SMP, "IPI_STOP (restart)");
432 return (smp_topo_none());
435 /* Determine if we running MP machine */
440 /* ARM64TODO: Read the u bit of mpidr_el1 to determine this */
445 start_cpu(u_int id, uint64_t target_cpu)
452 /* Check we are able to start this cpu */
456 KASSERT(id < MAXCPU, ("Too many CPUs"));
458 /* We are already running on cpu 0 */
463 * Rotate the CPU IDs to put the boot CPU as CPU 0. We keep the other
464 * CPUs ordered as the are likely grouped into clusters so it can be
465 * useful to keep that property, e.g. for the GICv3 driver to send
466 * an IPI to all CPUs in the cluster.
470 cpuid += mp_maxid + 1;
473 pcpup = &__pcpu[cpuid];
474 pcpu_init(pcpup, cpuid, sizeof(struct pcpu));
476 dpcpu[cpuid - 1] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
478 dpcpu_init(dpcpu[cpuid - 1], cpuid);
480 printf("Starting CPU %u (%lx)\n", cpuid, target_cpu);
481 pa = pmap_extract(kernel_pmap, (vm_offset_t)mpentry);
483 err = psci_cpu_on(target_cpu, pa, cpuid);
484 if (err != PSCI_RETVAL_SUCCESS) {
486 * Panic here if INVARIANTS are enabled and PSCI failed to
487 * start the requested CPU. If psci_cpu_on returns PSCI_MISSING
488 * to indicate we are unable to use it to start the given CPU.
490 KASSERT(err == PSCI_MISSING ||
491 (mp_quirks & MP_QUIRK_CPULIST) == MP_QUIRK_CPULIST,
492 ("Failed to start CPU %u (%lx)\n", id, target_cpu));
495 kmem_free(kernel_arena, (vm_offset_t)dpcpu[cpuid - 1],
497 dpcpu[cpuid - 1] = NULL;
500 /* Notify the user that the CPU failed to start */
501 printf("Failed to start CPU %u (%lx)\n", id, target_cpu);
503 CPU_SET(cpuid, &all_cpus);
510 madt_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
512 ACPI_MADT_GENERIC_INTERRUPT *intr;
515 switch(entry->Type) {
516 case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
517 intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
520 start_cpu((*cpuid), intr->ArmMpidr);
531 ACPI_TABLE_MADT *madt;
535 physaddr = acpi_find_table(ACPI_SIG_MADT);
539 madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
541 printf("Unable to map the MADT, not starting APs\n");
546 acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
547 madt_handler, &cpuid);
549 acpi_unmap_table(madt);
555 cpu_init_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
561 if (addr_size == 2) {
563 target_cpu |= reg[1];
566 if (!start_cpu(id, target_cpu))
569 /* Try to read the numa node of this cpu */
570 if (OF_getencprop(node, "numa-node-id", &domain, sizeof(domain)) > 0) {
571 __pcpu[id].pc_domain = domain;
572 if (domain < MAXMEMDOM)
573 CPU_SET(id, &cpuset_domain[domain]);
580 /* Initialize and fire up non-boot processors */
589 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
591 CPU_SET(0, &all_cpus);
593 switch(arm64_bus_method) {
596 KASSERT(cpu0 >= 0, ("Current CPU was not found"));
603 for (i = 0; fdt_quirks[i].compat != NULL; i++) {
604 if (ofw_bus_node_is_compatible(node,
605 fdt_quirks[i].compat) != 0) {
606 mp_quirks = fdt_quirks[i].quirks;
609 KASSERT(cpu0 >= 0, ("Current CPU was not found"));
610 ofw_cpu_early_foreach(cpu_init_fdt, true);
618 /* Introduce rest of cores to the world */
620 cpu_mp_announce(void)
626 cpu_count_acpi_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
628 ACPI_MADT_GENERIC_INTERRUPT *intr;
632 switch(entry->Type) {
633 case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
634 intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
636 mpidr_reg = READ_SPECIALREG(mpidr_el1);
637 if ((mpidr_reg & 0xff00fffffful) == intr->ArmMpidr)
650 ACPI_TABLE_MADT *madt;
654 physaddr = acpi_find_table(ACPI_SIG_MADT);
658 madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
660 printf("Unable to map the MADT, not starting APs\n");
665 acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
666 cpu_count_acpi_handler, &cores);
668 acpi_unmap_table(madt);
676 cpu_find_cpu0_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
678 uint64_t mpidr_fdt, mpidr_reg;
682 if (addr_size == 2) {
687 mpidr_reg = READ_SPECIALREG(mpidr_el1);
689 if ((mpidr_reg & 0xff00fffffful) == mpidr_fdt)
698 cpu_mp_setmaxid(void)
700 #if defined(DEV_ACPI) || defined(FDT)
704 switch(arm64_bus_method) {
707 cores = cpu_count_acpi();
709 cores = MIN(cores, MAXCPU);
711 printf("Found %d CPUs in the ACPI tables\n",
714 mp_maxid = cores - 1;
721 cores = ofw_cpu_early_foreach(cpu_find_cpu0_fdt, false);
723 cores = MIN(cores, MAXCPU);
725 printf("Found %d CPUs in the device tree\n",
728 mp_maxid = cores - 1;
738 printf("No CPU data, limiting to 1 core\n");
746 static struct intr_ipi *
747 intr_ipi_lookup(u_int ipi)
750 if (ipi >= INTR_IPI_COUNT)
751 panic("%s: no such IPI %u", __func__, ipi);
753 return (&ipi_sources[ipi]);
757 * interrupt controller dispatch function for IPIs. It should
758 * be called straight from the interrupt controller, when associated
759 * interrupt source is learned. Or from anybody who has an interrupt
763 intr_ipi_dispatch(u_int ipi, struct trapframe *tf)
768 ii = intr_ipi_lookup(ipi);
769 if (ii->ii_count == NULL)
770 panic("%s: not setup IPI %u", __func__, ipi);
772 intr_ipi_increment_count(ii->ii_count, PCPU_GET(cpuid));
775 * Supply ipi filter with trapframe argument
776 * if none is registered.
778 arg = ii->ii_handler_arg != NULL ? ii->ii_handler_arg : tf;
784 * Map IPI into interrupt controller.
789 ipi_map(struct intr_irqsrc *isrc, u_int ipi)
794 if (ipi >= INTR_IPI_COUNT)
795 panic("%s: no such IPI %u", __func__, ipi);
797 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
799 isrc->isrc_type = INTR_ISRCT_NAMESPACE;
800 isrc->isrc_nspc_type = INTR_IRQ_NSPC_IPI;
801 isrc->isrc_nspc_num = ipi_next_num;
803 error = PIC_REGISTER(intr_irq_root_dev, isrc, &is_percpu);
805 isrc->isrc_dev = intr_irq_root_dev;
812 * Setup IPI handler to interrupt source.
814 * Note that there could be more ways how to send and receive IPIs
815 * on a platform like fast interrupts for example. In that case,
816 * one can call this function with ASIF_NOALLOC flag set and then
817 * call intr_ipi_dispatch() when appropriate.
822 intr_ipi_set_handler(u_int ipi, const char *name, intr_ipi_filter_t *filter,
823 void *arg, u_int flags)
825 struct intr_irqsrc *isrc;
831 isrc = intr_ipi_lookup(ipi);
832 if (isrc->isrc_ipifilter != NULL)
835 if ((flags & AISHF_NOALLOC) == 0) {
836 error = ipi_map(isrc, ipi);
841 isrc->isrc_ipifilter = filter;
842 isrc->isrc_arg = arg;
843 isrc->isrc_handlers = 1;
844 isrc->isrc_count = intr_ipi_setup_counters(name);
845 isrc->isrc_index = 0; /* it should not be used in IPI case */
847 if (isrc->isrc_dev != NULL) {
848 PIC_ENABLE_INTR(isrc->isrc_dev, isrc);
849 PIC_ENABLE_SOURCE(isrc->isrc_dev, isrc);
857 ipi_all_but_self(u_int ipi)
862 CPU_CLR(PCPU_GET(cpuid), &cpus);
863 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
864 intr_ipi_send(cpus, ipi);
868 ipi_cpu(int cpu, u_int ipi)
875 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
876 intr_ipi_send(cpus, ipi);
880 ipi_selected(cpuset_t cpus, u_int ipi)
883 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
884 intr_ipi_send(cpus, ipi);