2 * Copyright (c) 2015-2016 The FreeBSD Foundation
5 * This software was developed by Andrew Turner under
6 * sponsorship from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include "opt_kstack_pages.h"
34 #include "opt_platform.h"
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include <sys/param.h>
40 #include <sys/systm.h>
44 #include <sys/kernel.h>
46 #include <sys/malloc.h>
47 #include <sys/module.h>
48 #include <sys/mutex.h>
51 #include <sys/sched.h>
56 #include <vm/vm_extern.h>
57 #include <vm/vm_kern.h>
58 #include <vm/vm_map.h>
60 #include <machine/machdep.h>
61 #include <machine/debug_monitor.h>
62 #include <machine/intr.h>
63 #include <machine/smp.h>
65 #include <machine/vfp.h>
69 #include <contrib/dev/acpica/include/acpi.h>
70 #include <dev/acpica/acpivar.h>
74 #include <dev/ofw/openfirm.h>
75 #include <dev/ofw/ofw_bus.h>
76 #include <dev/ofw/ofw_bus_subr.h>
77 #include <dev/ofw/ofw_cpu.h>
80 #include <dev/psci/psci.h>
84 #define MP_QUIRK_CPULIST 0x01 /* The list of cpus may be wrong, */
85 /* don't panic if one fails to start */
86 static uint32_t mp_quirks;
93 { "arm,foundation-aarch64", MP_QUIRK_CPULIST },
94 { "arm,fvp-base", MP_QUIRK_CPULIST },
95 /* This is incorrect in some DTS files */
96 { "arm,vfp-base", MP_QUIRK_CPULIST },
101 typedef void intr_ipi_send_t(void *, cpuset_t, u_int);
102 typedef void intr_ipi_handler_t(void *);
104 #define INTR_IPI_NAMELEN (MAXCOMLEN + 1)
106 intr_ipi_handler_t * ii_handler;
107 void * ii_handler_arg;
108 intr_ipi_send_t * ii_send;
110 char ii_name[INTR_IPI_NAMELEN];
114 static struct intr_ipi ipi_sources[INTR_IPI_COUNT];
116 static struct intr_ipi *intr_ipi_lookup(u_int);
117 static void intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *,
120 static void ipi_ast(void *);
121 static void ipi_hardclock(void *);
122 static void ipi_preempt(void *);
123 static void ipi_rendezvous(void *);
124 static void ipi_stop(void *);
126 struct pcb stoppcbs[MAXCPU];
129 * Not all systems boot from the first CPU in the device tree. To work around
130 * this we need to find which CPU we have booted from so when we later
131 * enable the secondary CPUs we skip this one.
133 static int cpu0 = -1;
135 void mpentry(unsigned long cpuid);
136 void init_secondary(uint64_t);
138 /* Synchronize AP startup. */
139 static struct mtx ap_boot_mtx;
141 /* Stacks for AP initialization, discarded once idle threads are started. */
143 static void *bootstacks[MAXCPU];
145 /* Count of started APs, used to synchronize access to bootstack. */
146 static volatile int aps_started;
148 /* Set to 1 once we're ready to let the APs out of the pen. */
149 static volatile int aps_ready;
151 /* Temporary variables for init_secondary() */
152 void *dpcpu[MAXCPU - 1];
155 release_aps(void *dummy __unused)
159 /* Only release CPUs if they exist */
163 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
164 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
165 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
166 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
167 intr_pic_ipi_setup(IPI_STOP_HARD, "stop hard", ipi_stop, NULL);
168 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
170 atomic_store_rel_int(&aps_ready, 1);
171 /* Wake up the other CPUs */
177 printf("Release APs...");
180 for (i = 0; i < 2000; i++) {
186 * Don't time out while we are making progress. Some large
187 * systems can take a while to start all CPUs.
189 if (smp_cpus > started) {
196 printf("APs not started\n");
198 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
201 init_secondary(uint64_t cpu)
206 pcpup = &__pcpu[cpu];
208 * Set the pcpu pointer with a backup in tpidr_el1 to be
209 * loaded when entering the kernel from userland.
213 "msr tpidr_el1, %0" :: "r"(pcpup));
215 /* Signal the BSP and spin until it has released all APs. */
216 atomic_add_int(&aps_started, 1);
217 while (!atomic_load_int(&aps_ready))
218 __asm __volatile("wfe");
220 /* Initialize curthread */
221 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
222 pcpup->pc_curthread = pcpup->pc_idlethread;
224 /* Initialize curpmap to match TTBR0's current setting. */
225 pmap0 = vmspace_pmap(&vmspace0);
226 KASSERT(pmap_to_ttbr0(pmap0) == READ_SPECIALREG(ttbr0_el1),
227 ("pmap0 doesn't match cpu %ld's ttbr0", cpu));
228 pcpup->pc_curpmap = pmap0;
231 * Identify current CPU. This is necessary to setup
232 * affinity registers and to provide support for
233 * runtime chip identification.
236 install_cpu_errata();
238 intr_pic_init_secondary();
240 /* Start per-CPU event timers. */
250 mtx_lock_spin(&ap_boot_mtx);
251 atomic_add_rel_32(&smp_cpus, 1);
252 if (smp_cpus == mp_ncpus) {
253 /* enable IPI's, tlb shootdown, freezes etc */
254 atomic_store_rel_int(&smp_started, 1);
256 mtx_unlock_spin(&ap_boot_mtx);
261 * Assert that smp_after_idle_runnable condition is reasonable.
263 MPASS(PCPU_GET(curpcb) == NULL);
265 /* Enter the scheduler */
268 panic("scheduler returned us to init_secondary");
273 smp_after_idle_runnable(void *arg __unused)
278 for (cpu = 1; cpu < mp_ncpus; cpu++) {
279 if (bootstacks[cpu] != NULL) {
281 while (atomic_load_ptr(&pc->pc_curpcb) == NULL)
283 kmem_free((vm_offset_t)bootstacks[cpu], PAGE_SIZE);
287 SYSINIT(smp_after_idle_runnable, SI_SUB_SMP, SI_ORDER_ANY,
288 smp_after_idle_runnable, NULL);
291 * Send IPI thru interrupt controller.
294 pic_ipi_send(void *arg, cpuset_t cpus, u_int ipi)
297 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
298 PIC_IPI_SEND(intr_irq_root_dev, arg, cpus, ipi);
302 * Setup IPI handler on interrupt controller.
307 intr_pic_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand,
310 struct intr_irqsrc *isrc;
314 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
315 KASSERT(hand != NULL, ("%s: ipi %u no handler", __func__, ipi));
317 error = PIC_IPI_SETUP(intr_irq_root_dev, ipi, &isrc);
321 isrc->isrc_handlers++;
323 ii = intr_ipi_lookup(ipi);
324 KASSERT(ii->ii_count == NULL, ("%s: ipi %u reused", __func__, ipi));
326 ii->ii_handler = hand;
327 ii->ii_handler_arg = arg;
328 ii->ii_send = pic_ipi_send;
329 ii->ii_send_arg = isrc;
330 strlcpy(ii->ii_name, name, INTR_IPI_NAMELEN);
331 ii->ii_count = intr_ipi_setup_counters(name);
335 intr_ipi_send(cpuset_t cpus, u_int ipi)
339 ii = intr_ipi_lookup(ipi);
340 if (ii->ii_count == NULL)
341 panic("%s: not setup IPI %u", __func__, ipi);
343 ii->ii_send(ii->ii_send_arg, cpus, ipi);
347 ipi_ast(void *dummy __unused)
350 CTR0(KTR_SMP, "IPI_AST");
354 ipi_hardclock(void *dummy __unused)
357 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
362 ipi_preempt(void *dummy __unused)
364 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
365 sched_preempt(curthread);
369 ipi_rendezvous(void *dummy __unused)
372 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
373 smp_rendezvous_action();
377 ipi_stop(void *dummy __unused)
381 CTR0(KTR_SMP, "IPI_STOP");
383 cpu = PCPU_GET(cpuid);
384 savectx(&stoppcbs[cpu]);
386 /* Indicate we are stopped */
387 CPU_SET_ATOMIC(cpu, &stopped_cpus);
389 /* Wait for restart */
390 while (!CPU_ISSET(cpu, &started_cpus))
394 dbg_register_sync(NULL);
397 CPU_CLR_ATOMIC(cpu, &started_cpus);
398 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
399 CTR0(KTR_SMP, "IPI_STOP (restart)");
406 return (smp_topo_none());
409 /* Determine if we running MP machine */
414 /* ARM64TODO: Read the u bit of mpidr_el1 to determine this */
419 start_cpu(u_int id, uint64_t target_cpu)
426 /* Check we are able to start this cpu */
430 KASSERT(id < MAXCPU, ("Too many CPUs"));
432 /* We are already running on cpu 0 */
437 * Rotate the CPU IDs to put the boot CPU as CPU 0. We keep the other
438 * CPUs ordered as they are likely grouped into clusters so it can be
439 * useful to keep that property, e.g. for the GICv3 driver to send
440 * an IPI to all CPUs in the cluster.
444 cpuid += mp_maxid + 1;
447 pcpup = &__pcpu[cpuid];
448 pcpu_init(pcpup, cpuid, sizeof(struct pcpu));
450 dpcpu[cpuid - 1] = (void *)kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO);
451 dpcpu_init(dpcpu[cpuid - 1], cpuid);
453 bootstacks[cpuid] = (void *)kmem_malloc(PAGE_SIZE, M_WAITOK | M_ZERO);
455 naps = atomic_load_int(&aps_started);
456 bootstack = (char *)bootstacks[cpuid] + PAGE_SIZE;
458 printf("Starting CPU %u (%lx)\n", cpuid, target_cpu);
459 pa = pmap_extract(kernel_pmap, (vm_offset_t)mpentry);
460 err = psci_cpu_on(target_cpu, pa, cpuid);
461 if (err != PSCI_RETVAL_SUCCESS) {
463 * Panic here if INVARIANTS are enabled and PSCI failed to
464 * start the requested CPU. psci_cpu_on() returns PSCI_MISSING
465 * to indicate we are unable to use it to start the given CPU.
467 KASSERT(err == PSCI_MISSING ||
468 (mp_quirks & MP_QUIRK_CPULIST) == MP_QUIRK_CPULIST,
469 ("Failed to start CPU %u (%lx), error %d\n",
470 id, target_cpu, err));
473 kmem_free((vm_offset_t)dpcpu[cpuid - 1], DPCPU_SIZE);
474 dpcpu[cpuid - 1] = NULL;
475 kmem_free((vm_offset_t)bootstacks[cpuid], PAGE_SIZE);
476 bootstacks[cpuid] = NULL;
479 /* Notify the user that the CPU failed to start */
480 printf("Failed to start CPU %u (%lx), error %d\n",
481 id, target_cpu, err);
483 /* Wait for the AP to switch to its boot stack. */
484 while (atomic_load_int(&aps_started) < naps + 1)
486 CPU_SET(cpuid, &all_cpus);
494 madt_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
496 ACPI_MADT_GENERIC_INTERRUPT *intr;
500 switch(entry->Type) {
501 case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
502 intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
505 start_cpu(id, intr->ArmMpidr);
506 __pcpu[id].pc_acpi_id = intr->Uid;
517 ACPI_TABLE_MADT *madt;
521 physaddr = acpi_find_table(ACPI_SIG_MADT);
525 madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
527 printf("Unable to map the MADT, not starting APs\n");
532 acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
533 madt_handler, &cpuid);
535 acpi_unmap_table(madt);
538 /* set proximity info */
539 acpi_pxm_set_cpu_locality();
547 cpu_init_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
553 if (addr_size == 2) {
555 target_cpu |= reg[1];
558 if (!start_cpu(id, target_cpu))
561 /* Try to read the numa node of this cpu */
562 if (vm_ndomains == 1 ||
563 OF_getencprop(node, "numa-node-id", &domain, sizeof(domain)) <= 0)
565 __pcpu[id].pc_domain = domain;
566 if (domain < MAXMEMDOM)
567 CPU_SET(id, &cpuset_domain[domain]);
573 /* Initialize and fire up non-boot processors */
582 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
584 CPU_SET(0, &all_cpus);
586 switch(arm64_bus_method) {
589 mp_quirks = MP_QUIRK_CPULIST;
590 KASSERT(cpu0 >= 0, ("Current CPU was not found"));
597 for (i = 0; fdt_quirks[i].compat != NULL; i++) {
598 if (ofw_bus_node_is_compatible(node,
599 fdt_quirks[i].compat) != 0) {
600 mp_quirks = fdt_quirks[i].quirks;
603 KASSERT(cpu0 >= 0, ("Current CPU was not found"));
604 ofw_cpu_early_foreach(cpu_init_fdt, true);
612 /* Introduce rest of cores to the world */
614 cpu_mp_announce(void)
620 cpu_count_acpi_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
622 ACPI_MADT_GENERIC_INTERRUPT *intr;
626 switch(entry->Type) {
627 case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
628 intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
630 mpidr_reg = READ_SPECIALREG(mpidr_el1);
631 if ((mpidr_reg & 0xff00fffffful) == intr->ArmMpidr)
644 ACPI_TABLE_MADT *madt;
648 physaddr = acpi_find_table(ACPI_SIG_MADT);
652 madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
654 printf("Unable to map the MADT, not starting APs\n");
659 acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
660 cpu_count_acpi_handler, &cores);
662 acpi_unmap_table(madt);
670 cpu_find_cpu0_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
672 uint64_t mpidr_fdt, mpidr_reg;
676 if (addr_size == 2) {
681 mpidr_reg = READ_SPECIALREG(mpidr_el1);
683 if ((mpidr_reg & 0xff00fffffful) == mpidr_fdt)
692 cpu_mp_setmaxid(void)
699 switch(arm64_bus_method) {
702 cores = cpu_count_acpi();
704 cores = MIN(cores, MAXCPU);
706 printf("Found %d CPUs in the ACPI tables\n",
709 mp_maxid = cores - 1;
715 cores = ofw_cpu_early_foreach(cpu_find_cpu0_fdt, false);
717 cores = MIN(cores, MAXCPU);
719 printf("Found %d CPUs in the device tree\n",
722 mp_maxid = cores - 1;
728 printf("No CPU data, limiting to 1 core\n");
732 if (TUNABLE_INT_FETCH("hw.ncpu", &cores)) {
733 if (cores > 0 && cores < mp_ncpus) {
735 mp_maxid = cores - 1;
743 static struct intr_ipi *
744 intr_ipi_lookup(u_int ipi)
747 if (ipi >= INTR_IPI_COUNT)
748 panic("%s: no such IPI %u", __func__, ipi);
750 return (&ipi_sources[ipi]);
754 * interrupt controller dispatch function for IPIs. It should
755 * be called straight from the interrupt controller, when associated
756 * interrupt source is learned. Or from anybody who has an interrupt
760 intr_ipi_dispatch(u_int ipi, struct trapframe *tf)
765 ii = intr_ipi_lookup(ipi);
766 if (ii->ii_count == NULL)
767 panic("%s: not setup IPI %u", __func__, ipi);
769 intr_ipi_increment_count(ii->ii_count, PCPU_GET(cpuid));
772 * Supply ipi filter with trapframe argument
773 * if none is registered.
775 arg = ii->ii_handler_arg != NULL ? ii->ii_handler_arg : tf;
781 * Map IPI into interrupt controller.
786 ipi_map(struct intr_irqsrc *isrc, u_int ipi)
791 if (ipi >= INTR_IPI_COUNT)
792 panic("%s: no such IPI %u", __func__, ipi);
794 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
796 isrc->isrc_type = INTR_ISRCT_NAMESPACE;
797 isrc->isrc_nspc_type = INTR_IRQ_NSPC_IPI;
798 isrc->isrc_nspc_num = ipi_next_num;
800 error = PIC_REGISTER(intr_irq_root_dev, isrc, &is_percpu);
802 isrc->isrc_dev = intr_irq_root_dev;
809 * Setup IPI handler to interrupt source.
811 * Note that there could be more ways how to send and receive IPIs
812 * on a platform like fast interrupts for example. In that case,
813 * one can call this function with ASIF_NOALLOC flag set and then
814 * call intr_ipi_dispatch() when appropriate.
819 intr_ipi_set_handler(u_int ipi, const char *name, intr_ipi_filter_t *filter,
820 void *arg, u_int flags)
822 struct intr_irqsrc *isrc;
828 isrc = intr_ipi_lookup(ipi);
829 if (isrc->isrc_ipifilter != NULL)
832 if ((flags & AISHF_NOALLOC) == 0) {
833 error = ipi_map(isrc, ipi);
838 isrc->isrc_ipifilter = filter;
839 isrc->isrc_arg = arg;
840 isrc->isrc_handlers = 1;
841 isrc->isrc_count = intr_ipi_setup_counters(name);
842 isrc->isrc_index = 0; /* it should not be used in IPI case */
844 if (isrc->isrc_dev != NULL) {
845 PIC_ENABLE_INTR(isrc->isrc_dev, isrc);
846 PIC_ENABLE_SOURCE(isrc->isrc_dev, isrc);
854 ipi_all_but_self(u_int ipi)
859 CPU_CLR(PCPU_GET(cpuid), &cpus);
860 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
861 intr_ipi_send(cpus, ipi);
865 ipi_cpu(int cpu, u_int ipi)
872 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
873 intr_ipi_send(cpus, ipi);
877 ipi_selected(cpuset_t cpus, u_int ipi)
880 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
881 intr_ipi_send(cpus, ipi);