2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/msgbuf.h>
120 #include <sys/mutex.h>
121 #include <sys/proc.h>
122 #include <sys/rwlock.h>
124 #include <sys/vmem.h>
125 #include <sys/vmmeter.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/_unrhdr.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/vm_pager.h>
140 #include <vm/vm_phys.h>
141 #include <vm/vm_radix.h>
142 #include <vm/vm_reserv.h>
145 #include <machine/machdep.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
149 #include <arm/include/physmem.h>
151 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
152 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
153 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
154 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
156 #define NUL0E L0_ENTRIES
157 #define NUL1E (NUL0E * NL1PG)
158 #define NUL2E (NUL1E * NL2PG)
160 #if !defined(DIAGNOSTIC)
161 #ifdef __GNUC_GNU_INLINE__
162 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
164 #define PMAP_INLINE extern inline
171 * These are configured by the mair_el1 register. This is set up in locore.S
173 #define DEVICE_MEMORY 0
174 #define UNCACHED_MEMORY 1
175 #define CACHED_MEMORY 2
179 #define PV_STAT(x) do { x ; } while (0)
181 #define PV_STAT(x) do { } while (0)
184 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
185 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
187 #define NPV_LIST_LOCKS MAXCPU
189 #define PHYS_TO_PV_LIST_LOCK(pa) \
190 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
192 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
193 struct rwlock **_lockp = (lockp); \
194 struct rwlock *_new_lock; \
196 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
197 if (_new_lock != *_lockp) { \
198 if (*_lockp != NULL) \
199 rw_wunlock(*_lockp); \
200 *_lockp = _new_lock; \
205 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
206 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
208 #define RELEASE_PV_LIST_LOCK(lockp) do { \
209 struct rwlock **_lockp = (lockp); \
211 if (*_lockp != NULL) { \
212 rw_wunlock(*_lockp); \
217 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
218 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
220 struct pmap kernel_pmap_store;
222 /* Used for mapping ACPI memory before VM is initialized */
223 #define PMAP_PREINIT_MAPPING_COUNT 32
224 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
225 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
226 static int vm_initialized = 0; /* No need to use pre-init maps when set */
229 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
230 * Always map entire L2 block for simplicity.
231 * VA of L2 block = preinit_map_va + i * L2_SIZE
233 static struct pmap_preinit_mapping {
237 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
239 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
240 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
241 vm_offset_t kernel_vm_end = 0;
244 * Data for the pv entry allocation mechanism.
246 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
247 static struct mtx pv_chunks_mutex;
248 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
249 static struct md_page *pv_table;
250 static struct md_page pv_dummy;
252 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
253 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
254 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
256 /* This code assumes all L1 DMAP entries will be used */
257 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
258 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
260 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
261 extern pt_entry_t pagetable_dmap[];
263 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
264 static vm_paddr_t physmap[PHYSMAP_SIZE];
265 static u_int physmap_idx;
267 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
269 static int superpages_enabled = 1;
270 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
271 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
272 "Are large page mappings enabled?");
275 * Internal flags for pmap_enter()'s helper functions.
277 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
278 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
280 static void free_pv_chunk(struct pv_chunk *pc);
281 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
282 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
283 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
284 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
285 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
288 static int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode);
289 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
290 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
291 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
292 vm_offset_t va, struct rwlock **lockp);
293 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
294 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
295 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
296 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
297 u_int flags, vm_page_t m, struct rwlock **lockp);
298 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
299 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
300 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
301 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
302 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
303 vm_page_t m, struct rwlock **lockp);
305 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
306 struct rwlock **lockp);
308 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
309 struct spglist *free);
310 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
311 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
314 * These load the old table data and store the new value.
315 * They need to be atomic as the System MMU may write to the table at
316 * the same time as the CPU.
318 #define pmap_clear(table) atomic_store_64(table, 0)
319 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
320 #define pmap_set(table, mask) atomic_set_64(table, mask)
321 #define pmap_load_clear(table) atomic_swap_64(table, 0)
322 #define pmap_load(table) (*table)
324 /********************/
325 /* Inline functions */
326 /********************/
329 pagecopy(void *s, void *d)
332 memcpy(d, s, PAGE_SIZE);
335 static __inline pd_entry_t *
336 pmap_l0(pmap_t pmap, vm_offset_t va)
339 return (&pmap->pm_l0[pmap_l0_index(va)]);
342 static __inline pd_entry_t *
343 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
347 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
348 return (&l1[pmap_l1_index(va)]);
351 static __inline pd_entry_t *
352 pmap_l1(pmap_t pmap, vm_offset_t va)
356 l0 = pmap_l0(pmap, va);
357 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
360 return (pmap_l0_to_l1(l0, va));
363 static __inline pd_entry_t *
364 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
368 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
369 return (&l2[pmap_l2_index(va)]);
372 static __inline pd_entry_t *
373 pmap_l2(pmap_t pmap, vm_offset_t va)
377 l1 = pmap_l1(pmap, va);
378 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
381 return (pmap_l1_to_l2(l1, va));
384 static __inline pt_entry_t *
385 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
389 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
390 return (&l3[pmap_l3_index(va)]);
394 * Returns the lowest valid pde for a given virtual address.
395 * The next level may or may not point to a valid page or block.
397 static __inline pd_entry_t *
398 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
400 pd_entry_t *l0, *l1, *l2, desc;
402 l0 = pmap_l0(pmap, va);
403 desc = pmap_load(l0) & ATTR_DESCR_MASK;
404 if (desc != L0_TABLE) {
409 l1 = pmap_l0_to_l1(l0, va);
410 desc = pmap_load(l1) & ATTR_DESCR_MASK;
411 if (desc != L1_TABLE) {
416 l2 = pmap_l1_to_l2(l1, va);
417 desc = pmap_load(l2) & ATTR_DESCR_MASK;
418 if (desc != L2_TABLE) {
428 * Returns the lowest valid pte block or table entry for a given virtual
429 * address. If there are no valid entries return NULL and set the level to
430 * the first invalid level.
432 static __inline pt_entry_t *
433 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
435 pd_entry_t *l1, *l2, desc;
438 l1 = pmap_l1(pmap, va);
443 desc = pmap_load(l1) & ATTR_DESCR_MASK;
444 if (desc == L1_BLOCK) {
449 if (desc != L1_TABLE) {
454 l2 = pmap_l1_to_l2(l1, va);
455 desc = pmap_load(l2) & ATTR_DESCR_MASK;
456 if (desc == L2_BLOCK) {
461 if (desc != L2_TABLE) {
467 l3 = pmap_l2_to_l3(l2, va);
468 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
475 pmap_ps_enabled(pmap_t pmap __unused)
478 return (superpages_enabled != 0);
482 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
483 pd_entry_t **l2, pt_entry_t **l3)
485 pd_entry_t *l0p, *l1p, *l2p;
487 if (pmap->pm_l0 == NULL)
490 l0p = pmap_l0(pmap, va);
493 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
496 l1p = pmap_l0_to_l1(l0p, va);
499 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
505 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
508 l2p = pmap_l1_to_l2(l1p, va);
511 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
516 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
519 *l3 = pmap_l2_to_l3(l2p, va);
525 pmap_l3_valid(pt_entry_t l3)
528 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
532 CTASSERT(L1_BLOCK == L2_BLOCK);
535 * Checks if the page is dirty. We currently lack proper tracking of this on
536 * arm64 so for now assume is a page mapped as rw was accessed it is.
539 pmap_page_dirty(pt_entry_t pte)
542 return ((pte & (ATTR_AF | ATTR_AP_RW_BIT)) ==
543 (ATTR_AF | ATTR_AP(ATTR_AP_RW)));
547 pmap_resident_count_inc(pmap_t pmap, int count)
550 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
551 pmap->pm_stats.resident_count += count;
555 pmap_resident_count_dec(pmap_t pmap, int count)
558 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
559 KASSERT(pmap->pm_stats.resident_count >= count,
560 ("pmap %p resident count underflow %ld %d", pmap,
561 pmap->pm_stats.resident_count, count));
562 pmap->pm_stats.resident_count -= count;
566 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
572 l1 = (pd_entry_t *)l1pt;
573 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
575 /* Check locore has used a table L1 map */
576 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
577 ("Invalid bootstrap L1 table"));
578 /* Find the address of the L2 table */
579 l2 = (pt_entry_t *)init_pt_va;
580 *l2_slot = pmap_l2_index(va);
586 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
588 u_int l1_slot, l2_slot;
591 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
593 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
597 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
598 vm_offset_t freemempos)
602 vm_paddr_t l2_pa, pa;
603 u_int l1_slot, l2_slot, prev_l1_slot;
606 dmap_phys_base = min_pa & ~L1_OFFSET;
612 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
613 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
615 for (i = 0; i < (physmap_idx * 2); i += 2) {
616 pa = physmap[i] & ~L2_OFFSET;
617 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
619 /* Create L2 mappings at the start of the region */
620 if ((pa & L1_OFFSET) != 0) {
621 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
622 if (l1_slot != prev_l1_slot) {
623 prev_l1_slot = l1_slot;
624 l2 = (pt_entry_t *)freemempos;
625 l2_pa = pmap_early_vtophys(kern_l1,
627 freemempos += PAGE_SIZE;
629 pmap_load_store(&pagetable_dmap[l1_slot],
630 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
632 memset(l2, 0, PAGE_SIZE);
635 ("pmap_bootstrap_dmap: NULL l2 map"));
636 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
637 pa += L2_SIZE, va += L2_SIZE) {
639 * We are on a boundary, stop to
640 * create a level 1 block
642 if ((pa & L1_OFFSET) == 0)
645 l2_slot = pmap_l2_index(va);
646 KASSERT(l2_slot != 0, ("..."));
647 pmap_load_store(&l2[l2_slot],
648 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
649 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
651 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
655 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
656 (physmap[i + 1] - pa) >= L1_SIZE;
657 pa += L1_SIZE, va += L1_SIZE) {
658 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
659 pmap_load_store(&pagetable_dmap[l1_slot],
660 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
661 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
664 /* Create L2 mappings at the end of the region */
665 if (pa < physmap[i + 1]) {
666 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
667 if (l1_slot != prev_l1_slot) {
668 prev_l1_slot = l1_slot;
669 l2 = (pt_entry_t *)freemempos;
670 l2_pa = pmap_early_vtophys(kern_l1,
672 freemempos += PAGE_SIZE;
674 pmap_load_store(&pagetable_dmap[l1_slot],
675 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
677 memset(l2, 0, PAGE_SIZE);
680 ("pmap_bootstrap_dmap: NULL l2 map"));
681 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
682 pa += L2_SIZE, va += L2_SIZE) {
683 l2_slot = pmap_l2_index(va);
684 pmap_load_store(&l2[l2_slot],
685 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
686 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
690 if (pa > dmap_phys_max) {
702 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
709 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
711 l1 = (pd_entry_t *)l1pt;
712 l1_slot = pmap_l1_index(va);
715 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
716 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
718 pa = pmap_early_vtophys(l1pt, l2pt);
719 pmap_load_store(&l1[l1_slot],
720 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
724 /* Clean the L2 page table */
725 memset((void *)l2_start, 0, l2pt - l2_start);
731 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
738 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
740 l2 = pmap_l2(kernel_pmap, va);
741 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
742 l2_slot = pmap_l2_index(va);
745 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
746 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
748 pa = pmap_early_vtophys(l1pt, l3pt);
749 pmap_load_store(&l2[l2_slot],
750 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
754 /* Clean the L2 page table */
755 memset((void *)l3_start, 0, l3pt - l3_start);
761 * Bootstrap the system enough to run with virtual memory.
764 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
767 u_int l1_slot, l2_slot;
770 vm_offset_t va, freemempos;
771 vm_offset_t dpcpu, msgbufpv;
772 vm_paddr_t start_pa, pa, min_pa;
775 kern_delta = KERNBASE - kernstart;
777 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
778 printf("%lx\n", l1pt);
779 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
781 /* Set this early so we can use the pagetable walking functions */
782 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
783 PMAP_LOCK_INIT(kernel_pmap);
785 /* Assume the address we were loaded to is a valid physical address */
786 min_pa = KERNBASE - kern_delta;
788 physmap_idx = arm_physmem_avail(physmap, nitems(physmap));
792 * Find the minimum physical address. physmap is sorted,
793 * but may contain empty ranges.
795 for (i = 0; i < (physmap_idx * 2); i += 2) {
796 if (physmap[i] == physmap[i + 1])
798 if (physmap[i] <= min_pa)
802 freemempos = KERNBASE + kernlen;
803 freemempos = roundup2(freemempos, PAGE_SIZE);
805 /* Create a direct map region early so we can use it for pa -> va */
806 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
809 start_pa = pa = KERNBASE - kern_delta;
812 * Read the page table to find out what is already mapped.
813 * This assumes we have mapped a block of memory from KERNBASE
814 * using a single L1 entry.
816 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
818 /* Sanity check the index, KERNBASE should be the first VA */
819 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
821 /* Find how many pages we have mapped */
822 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
823 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
826 /* Check locore used L2 blocks */
827 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
828 ("Invalid bootstrap L2 table"));
829 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
830 ("Incorrect PA in L2 table"));
836 va = roundup2(va, L1_SIZE);
838 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
839 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
840 /* And the l3 tables for the early devmap */
841 freemempos = pmap_bootstrap_l3(l1pt,
842 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
846 #define alloc_pages(var, np) \
847 (var) = freemempos; \
848 freemempos += (np * PAGE_SIZE); \
849 memset((char *)(var), 0, ((np) * PAGE_SIZE));
851 /* Allocate dynamic per-cpu area. */
852 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
853 dpcpu_init((void *)dpcpu, 0);
855 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
856 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
857 msgbufp = (void *)msgbufpv;
859 /* Reserve some VA space for early BIOS/ACPI mapping */
860 preinit_map_va = roundup2(freemempos, L2_SIZE);
862 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
863 virtual_avail = roundup2(virtual_avail, L1_SIZE);
864 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
865 kernel_vm_end = virtual_avail;
867 pa = pmap_early_vtophys(l1pt, freemempos);
869 arm_physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
875 * Initialize a vm_page's machine-dependent fields.
878 pmap_page_init(vm_page_t m)
881 TAILQ_INIT(&m->md.pv_list);
882 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
886 * Initialize the pmap module.
887 * Called by vm_init, to initialize any structures that the pmap
888 * system needs to map virtual memory.
897 * Are large page mappings enabled?
899 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
900 if (superpages_enabled) {
901 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
902 ("pmap_init: can't assign to pagesizes[1]"));
903 pagesizes[1] = L2_SIZE;
907 * Initialize the pv chunk list mutex.
909 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
912 * Initialize the pool of pv list locks.
914 for (i = 0; i < NPV_LIST_LOCKS; i++)
915 rw_init(&pv_list_locks[i], "pmap pv list");
918 * Calculate the size of the pv head table for superpages.
920 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
923 * Allocate memory for the pv head table for superpages.
925 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
927 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
928 for (i = 0; i < pv_npg; i++)
929 TAILQ_INIT(&pv_table[i].pv_list);
930 TAILQ_INIT(&pv_dummy.pv_list);
935 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
936 "2MB page mapping counters");
938 static u_long pmap_l2_demotions;
939 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
940 &pmap_l2_demotions, 0, "2MB page demotions");
942 static u_long pmap_l2_mappings;
943 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
944 &pmap_l2_mappings, 0, "2MB page mappings");
946 static u_long pmap_l2_p_failures;
947 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
948 &pmap_l2_p_failures, 0, "2MB page promotion failures");
950 static u_long pmap_l2_promotions;
951 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
952 &pmap_l2_promotions, 0, "2MB page promotions");
955 * Invalidate a single TLB entry.
958 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
964 "tlbi vaae1is, %0 \n"
967 : : "r"(va >> PAGE_SHIFT));
972 pmap_invalidate_range_nopin(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
977 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
979 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
987 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
991 pmap_invalidate_range_nopin(pmap, sva, eva);
996 pmap_invalidate_all(pmap_t pmap)
1009 * Routine: pmap_extract
1011 * Extract the physical page address associated
1012 * with the given map/virtual_address pair.
1015 pmap_extract(pmap_t pmap, vm_offset_t va)
1017 pt_entry_t *pte, tpte;
1024 * Find the block or page map for this virtual address. pmap_pte
1025 * will return either a valid block/page entry, or NULL.
1027 pte = pmap_pte(pmap, va, &lvl);
1029 tpte = pmap_load(pte);
1030 pa = tpte & ~ATTR_MASK;
1033 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1034 ("pmap_extract: Invalid L1 pte found: %lx",
1035 tpte & ATTR_DESCR_MASK));
1036 pa |= (va & L1_OFFSET);
1039 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1040 ("pmap_extract: Invalid L2 pte found: %lx",
1041 tpte & ATTR_DESCR_MASK));
1042 pa |= (va & L2_OFFSET);
1045 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1046 ("pmap_extract: Invalid L3 pte found: %lx",
1047 tpte & ATTR_DESCR_MASK));
1048 pa |= (va & L3_OFFSET);
1057 * Routine: pmap_extract_and_hold
1059 * Atomically extract and hold the physical page
1060 * with the given pmap and virtual address pair
1061 * if that mapping permits the given protection.
1064 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1066 pt_entry_t *pte, tpte;
1076 pte = pmap_pte(pmap, va, &lvl);
1078 tpte = pmap_load(pte);
1080 KASSERT(lvl > 0 && lvl <= 3,
1081 ("pmap_extract_and_hold: Invalid level %d", lvl));
1082 CTASSERT(L1_BLOCK == L2_BLOCK);
1083 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1084 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1085 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1086 tpte & ATTR_DESCR_MASK));
1087 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1088 ((prot & VM_PROT_WRITE) == 0)) {
1091 off = va & L1_OFFSET;
1094 off = va & L2_OFFSET;
1100 if (vm_page_pa_tryrelock(pmap,
1101 (tpte & ~ATTR_MASK) | off, &pa))
1103 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1113 pmap_kextract(vm_offset_t va)
1115 pt_entry_t *pte, tpte;
1119 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1120 pa = DMAP_TO_PHYS(va);
1123 pte = pmap_pte(kernel_pmap, va, &lvl);
1125 tpte = pmap_load(pte);
1126 pa = tpte & ~ATTR_MASK;
1129 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1130 ("pmap_kextract: Invalid L1 pte found: %lx",
1131 tpte & ATTR_DESCR_MASK));
1132 pa |= (va & L1_OFFSET);
1135 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1136 ("pmap_kextract: Invalid L2 pte found: %lx",
1137 tpte & ATTR_DESCR_MASK));
1138 pa |= (va & L2_OFFSET);
1141 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1142 ("pmap_kextract: Invalid L3 pte found: %lx",
1143 tpte & ATTR_DESCR_MASK));
1144 pa |= (va & L3_OFFSET);
1152 /***************************************************
1153 * Low level mapping routines.....
1154 ***************************************************/
1157 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1160 pt_entry_t *pte, attr;
1164 KASSERT((pa & L3_OFFSET) == 0,
1165 ("pmap_kenter: Invalid physical address"));
1166 KASSERT((sva & L3_OFFSET) == 0,
1167 ("pmap_kenter: Invalid virtual address"));
1168 KASSERT((size & PAGE_MASK) == 0,
1169 ("pmap_kenter: Mapping is not page-sized"));
1171 attr = ATTR_DEFAULT | ATTR_IDX(mode) | L3_PAGE;
1172 if (mode == DEVICE_MEMORY)
1177 pde = pmap_pde(kernel_pmap, va, &lvl);
1178 KASSERT(pde != NULL,
1179 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1180 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1182 pte = pmap_l2_to_l3(pde, va);
1183 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1189 pmap_invalidate_range(kernel_pmap, sva, va);
1193 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1196 pmap_kenter(sva, size, pa, DEVICE_MEMORY);
1200 * Remove a page from the kernel pagetables.
1203 pmap_kremove(vm_offset_t va)
1208 pte = pmap_pte(kernel_pmap, va, &lvl);
1209 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1210 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1213 pmap_invalidate_page(kernel_pmap, va);
1217 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1223 KASSERT((sva & L3_OFFSET) == 0,
1224 ("pmap_kremove_device: Invalid virtual address"));
1225 KASSERT((size & PAGE_MASK) == 0,
1226 ("pmap_kremove_device: Mapping is not page-sized"));
1230 pte = pmap_pte(kernel_pmap, va, &lvl);
1231 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1233 ("Invalid device pagetable level: %d != 3", lvl));
1239 pmap_invalidate_range(kernel_pmap, sva, va);
1243 * Used to map a range of physical addresses into kernel
1244 * virtual address space.
1246 * The value passed in '*virt' is a suggested virtual address for
1247 * the mapping. Architectures which can support a direct-mapped
1248 * physical to virtual region can return the appropriate address
1249 * within that region, leaving '*virt' unchanged. Other
1250 * architectures should map the pages starting at '*virt' and
1251 * update '*virt' with the first usable address after the mapped
1255 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1257 return PHYS_TO_DMAP(start);
1262 * Add a list of wired pages to the kva
1263 * this routine is only used for temporary
1264 * kernel mappings that do not need to have
1265 * page modification or references recorded.
1266 * Note that old mappings are simply written
1267 * over. The page *must* be wired.
1268 * Note: SMP coherent. Uses a ranged shootdown IPI.
1271 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1274 pt_entry_t *pte, pa;
1280 for (i = 0; i < count; i++) {
1281 pde = pmap_pde(kernel_pmap, va, &lvl);
1282 KASSERT(pde != NULL,
1283 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1285 ("pmap_qenter: Invalid level %d", lvl));
1288 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1289 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1290 if (m->md.pv_memattr == DEVICE_MEMORY)
1292 pte = pmap_l2_to_l3(pde, va);
1293 pmap_load_store(pte, pa);
1297 pmap_invalidate_range(kernel_pmap, sva, va);
1301 * This routine tears out page mappings from the
1302 * kernel -- it is meant only for temporary mappings.
1305 pmap_qremove(vm_offset_t sva, int count)
1311 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1314 while (count-- > 0) {
1315 pte = pmap_pte(kernel_pmap, va, &lvl);
1317 ("Invalid device pagetable level: %d != 3", lvl));
1324 pmap_invalidate_range(kernel_pmap, sva, va);
1327 /***************************************************
1328 * Page table page management routines.....
1329 ***************************************************/
1331 * Schedule the specified unused page table page to be freed. Specifically,
1332 * add the page to the specified list of pages that will be released to the
1333 * physical memory manager after the TLB has been updated.
1335 static __inline void
1336 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1337 boolean_t set_PG_ZERO)
1341 m->flags |= PG_ZERO;
1343 m->flags &= ~PG_ZERO;
1344 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1348 * Decrements a page table page's wire count, which is used to record the
1349 * number of valid page table entries within the page. If the wire count
1350 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1351 * page table page was unmapped and FALSE otherwise.
1353 static inline boolean_t
1354 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1358 if (m->wire_count == 0) {
1359 _pmap_unwire_l3(pmap, va, m, free);
1366 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1369 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1371 * unmap the page table page
1373 if (m->pindex >= (NUL2E + NUL1E)) {
1377 l0 = pmap_l0(pmap, va);
1379 } else if (m->pindex >= NUL2E) {
1383 l1 = pmap_l1(pmap, va);
1389 l2 = pmap_l2(pmap, va);
1392 pmap_resident_count_dec(pmap, 1);
1393 if (m->pindex < NUL2E) {
1394 /* We just released an l3, unhold the matching l2 */
1395 pd_entry_t *l1, tl1;
1398 l1 = pmap_l1(pmap, va);
1399 tl1 = pmap_load(l1);
1400 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1401 pmap_unwire_l3(pmap, va, l2pg, free);
1402 } else if (m->pindex < (NUL2E + NUL1E)) {
1403 /* We just released an l2, unhold the matching l1 */
1404 pd_entry_t *l0, tl0;
1407 l0 = pmap_l0(pmap, va);
1408 tl0 = pmap_load(l0);
1409 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1410 pmap_unwire_l3(pmap, va, l1pg, free);
1412 pmap_invalidate_page(pmap, va);
1415 * Put page on a list so that it is released after
1416 * *ALL* TLB shootdown is done
1418 pmap_add_delayed_free_list(m, free, TRUE);
1422 * After removing a page table entry, this routine is used to
1423 * conditionally free the page, and manage the hold/wire counts.
1426 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1427 struct spglist *free)
1431 if (va >= VM_MAXUSER_ADDRESS)
1433 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1434 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1435 return (pmap_unwire_l3(pmap, va, mpte, free));
1439 pmap_pinit0(pmap_t pmap)
1442 PMAP_LOCK_INIT(pmap);
1443 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1444 pmap->pm_l0 = kernel_pmap->pm_l0;
1445 pmap->pm_root.rt_root = 0;
1449 pmap_pinit(pmap_t pmap)
1455 * allocate the l0 page
1457 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1458 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1461 l0phys = VM_PAGE_TO_PHYS(l0pt);
1462 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1464 if ((l0pt->flags & PG_ZERO) == 0)
1465 pagezero(pmap->pm_l0);
1467 pmap->pm_root.rt_root = 0;
1468 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1474 * This routine is called if the desired page table page does not exist.
1476 * If page table page allocation fails, this routine may sleep before
1477 * returning NULL. It sleeps only if a lock pointer was given.
1479 * Note: If a page allocation fails at page table level two or three,
1480 * one or two pages may be held during the wait, only to be released
1481 * afterwards. This conservative approach is easily argued to avoid
1485 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1487 vm_page_t m, l1pg, l2pg;
1489 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1492 * Allocate a page table page.
1494 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1495 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1496 if (lockp != NULL) {
1497 RELEASE_PV_LIST_LOCK(lockp);
1504 * Indicate the need to retry. While waiting, the page table
1505 * page may have been allocated.
1509 if ((m->flags & PG_ZERO) == 0)
1513 * Map the pagetable page into the process address space, if
1514 * it isn't already there.
1517 if (ptepindex >= (NUL2E + NUL1E)) {
1519 vm_pindex_t l0index;
1521 l0index = ptepindex - (NUL2E + NUL1E);
1522 l0 = &pmap->pm_l0[l0index];
1523 pmap_load_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1524 } else if (ptepindex >= NUL2E) {
1525 vm_pindex_t l0index, l1index;
1526 pd_entry_t *l0, *l1;
1529 l1index = ptepindex - NUL2E;
1530 l0index = l1index >> L0_ENTRIES_SHIFT;
1532 l0 = &pmap->pm_l0[l0index];
1533 tl0 = pmap_load(l0);
1535 /* recurse for allocating page dir */
1536 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1538 vm_page_unwire_noq(m);
1539 vm_page_free_zero(m);
1543 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1547 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1548 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1549 pmap_load_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1551 vm_pindex_t l0index, l1index;
1552 pd_entry_t *l0, *l1, *l2;
1553 pd_entry_t tl0, tl1;
1555 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1556 l0index = l1index >> L0_ENTRIES_SHIFT;
1558 l0 = &pmap->pm_l0[l0index];
1559 tl0 = pmap_load(l0);
1561 /* recurse for allocating page dir */
1562 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1564 vm_page_unwire_noq(m);
1565 vm_page_free_zero(m);
1568 tl0 = pmap_load(l0);
1569 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1570 l1 = &l1[l1index & Ln_ADDR_MASK];
1572 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1573 l1 = &l1[l1index & Ln_ADDR_MASK];
1574 tl1 = pmap_load(l1);
1576 /* recurse for allocating page dir */
1577 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1579 vm_page_unwire_noq(m);
1580 vm_page_free_zero(m);
1584 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1589 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1590 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1591 pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1594 pmap_resident_count_inc(pmap, 1);
1600 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1604 vm_pindex_t l2pindex;
1607 l1 = pmap_l1(pmap, va);
1608 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1609 /* Add a reference to the L2 page. */
1610 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1613 /* Allocate a L2 page. */
1614 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1615 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1616 if (l2pg == NULL && lockp != NULL)
1623 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1625 vm_pindex_t ptepindex;
1626 pd_entry_t *pde, tpde;
1634 * Calculate pagetable page index
1636 ptepindex = pmap_l2_pindex(va);
1639 * Get the page directory entry
1641 pde = pmap_pde(pmap, va, &lvl);
1644 * If the page table page is mapped, we just increment the hold count,
1645 * and activate it. If we get a level 2 pde it will point to a level 3
1653 pte = pmap_l0_to_l1(pde, va);
1654 KASSERT(pmap_load(pte) == 0,
1655 ("pmap_alloc_l3: TODO: l0 superpages"));
1660 pte = pmap_l1_to_l2(pde, va);
1661 KASSERT(pmap_load(pte) == 0,
1662 ("pmap_alloc_l3: TODO: l1 superpages"));
1666 tpde = pmap_load(pde);
1668 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1674 panic("pmap_alloc_l3: Invalid level %d", lvl);
1678 * Here if the pte page isn't mapped, or if it has been deallocated.
1680 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1681 if (m == NULL && lockp != NULL)
1687 /***************************************************
1688 * Pmap allocation/deallocation routines.
1689 ***************************************************/
1692 * Release any resources held by the given physical map.
1693 * Called when a pmap initialized by pmap_pinit is being released.
1694 * Should only be called if the map contains no valid mappings.
1697 pmap_release(pmap_t pmap)
1701 KASSERT(pmap->pm_stats.resident_count == 0,
1702 ("pmap_release: pmap resident count %ld != 0",
1703 pmap->pm_stats.resident_count));
1704 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1705 ("pmap_release: pmap has reserved page table page(s)"));
1707 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1709 vm_page_unwire_noq(m);
1710 vm_page_free_zero(m);
1714 kvm_size(SYSCTL_HANDLER_ARGS)
1716 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1718 return sysctl_handle_long(oidp, &ksize, 0, req);
1720 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1721 0, 0, kvm_size, "LU", "Size of KVM");
1724 kvm_free(SYSCTL_HANDLER_ARGS)
1726 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1728 return sysctl_handle_long(oidp, &kfree, 0, req);
1730 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1731 0, 0, kvm_free, "LU", "Amount of KVM free");
1734 * grow the number of kernel page table entries, if needed
1737 pmap_growkernel(vm_offset_t addr)
1741 pd_entry_t *l0, *l1, *l2;
1743 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1745 addr = roundup2(addr, L2_SIZE);
1746 if (addr - 1 >= vm_map_max(kernel_map))
1747 addr = vm_map_max(kernel_map);
1748 while (kernel_vm_end < addr) {
1749 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1750 KASSERT(pmap_load(l0) != 0,
1751 ("pmap_growkernel: No level 0 kernel entry"));
1753 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1754 if (pmap_load(l1) == 0) {
1755 /* We need a new PDP entry */
1756 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1757 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1758 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1760 panic("pmap_growkernel: no memory to grow kernel");
1761 if ((nkpg->flags & PG_ZERO) == 0)
1762 pmap_zero_page(nkpg);
1763 paddr = VM_PAGE_TO_PHYS(nkpg);
1764 pmap_load_store(l1, paddr | L1_TABLE);
1765 continue; /* try again */
1767 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1768 if ((pmap_load(l2) & ATTR_AF) != 0) {
1769 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1770 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1771 kernel_vm_end = vm_map_max(kernel_map);
1777 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1778 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1781 panic("pmap_growkernel: no memory to grow kernel");
1782 if ((nkpg->flags & PG_ZERO) == 0)
1783 pmap_zero_page(nkpg);
1784 paddr = VM_PAGE_TO_PHYS(nkpg);
1785 pmap_load_store(l2, paddr | L2_TABLE);
1786 pmap_invalidate_page(kernel_pmap, kernel_vm_end);
1788 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1789 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1790 kernel_vm_end = vm_map_max(kernel_map);
1797 /***************************************************
1798 * page management routines.
1799 ***************************************************/
1801 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1802 CTASSERT(_NPCM == 3);
1803 CTASSERT(_NPCPV == 168);
1805 static __inline struct pv_chunk *
1806 pv_to_chunk(pv_entry_t pv)
1809 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1812 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1814 #define PC_FREE0 0xfffffffffffffffful
1815 #define PC_FREE1 0xfffffffffffffffful
1816 #define PC_FREE2 0x000000fffffffffful
1818 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1822 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1824 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1825 "Current number of pv entry chunks");
1826 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1827 "Current number of pv entry chunks allocated");
1828 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1829 "Current number of pv entry chunks frees");
1830 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1831 "Number of times tried to get a chunk page but failed.");
1833 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1834 static int pv_entry_spare;
1836 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1837 "Current number of pv entry frees");
1838 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1839 "Current number of pv entry allocs");
1840 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1841 "Current number of pv entries");
1842 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1843 "Current number of spare pv entries");
1848 * We are in a serious low memory condition. Resort to
1849 * drastic measures to free some pages so we can allocate
1850 * another pv entry chunk.
1852 * Returns NULL if PV entries were reclaimed from the specified pmap.
1854 * We do not, however, unmap 2mpages because subsequent accesses will
1855 * allocate per-page pv entries until repromotion occurs, thereby
1856 * exacerbating the shortage of free pv entries.
1859 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1861 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
1862 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
1863 struct md_page *pvh;
1865 pmap_t next_pmap, pmap;
1866 pt_entry_t *pte, tpte;
1870 struct spglist free;
1872 int bit, field, freed, lvl;
1873 static int active_reclaims = 0;
1875 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1876 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
1881 bzero(&pc_marker_b, sizeof(pc_marker_b));
1882 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
1883 pc_marker = (struct pv_chunk *)&pc_marker_b;
1884 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
1886 mtx_lock(&pv_chunks_mutex);
1888 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
1889 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
1890 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
1891 SLIST_EMPTY(&free)) {
1892 next_pmap = pc->pc_pmap;
1893 if (next_pmap == NULL) {
1895 * The next chunk is a marker. However, it is
1896 * not our marker, so active_reclaims must be
1897 * > 1. Consequently, the next_chunk code
1898 * will not rotate the pv_chunks list.
1902 mtx_unlock(&pv_chunks_mutex);
1905 * A pv_chunk can only be removed from the pc_lru list
1906 * when both pv_chunks_mutex is owned and the
1907 * corresponding pmap is locked.
1909 if (pmap != next_pmap) {
1910 if (pmap != NULL && pmap != locked_pmap)
1913 /* Avoid deadlock and lock recursion. */
1914 if (pmap > locked_pmap) {
1915 RELEASE_PV_LIST_LOCK(lockp);
1917 mtx_lock(&pv_chunks_mutex);
1919 } else if (pmap != locked_pmap) {
1920 if (PMAP_TRYLOCK(pmap)) {
1921 mtx_lock(&pv_chunks_mutex);
1924 pmap = NULL; /* pmap is not locked */
1925 mtx_lock(&pv_chunks_mutex);
1926 pc = TAILQ_NEXT(pc_marker, pc_lru);
1928 pc->pc_pmap != next_pmap)
1936 * Destroy every non-wired, 4 KB page mapping in the chunk.
1939 for (field = 0; field < _NPCM; field++) {
1940 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1941 inuse != 0; inuse &= ~(1UL << bit)) {
1942 bit = ffsl(inuse) - 1;
1943 pv = &pc->pc_pventry[field * 64 + bit];
1945 pde = pmap_pde(pmap, va, &lvl);
1948 pte = pmap_l2_to_l3(pde, va);
1949 tpte = pmap_load(pte);
1950 if ((tpte & ATTR_SW_WIRED) != 0)
1952 tpte = pmap_load_clear(pte);
1953 pmap_invalidate_page(pmap, va);
1954 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
1955 if (pmap_page_dirty(tpte))
1957 if ((tpte & ATTR_AF) != 0)
1958 vm_page_aflag_set(m, PGA_REFERENCED);
1959 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1960 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
1962 if (TAILQ_EMPTY(&m->md.pv_list) &&
1963 (m->flags & PG_FICTITIOUS) == 0) {
1964 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
1965 if (TAILQ_EMPTY(&pvh->pv_list)) {
1966 vm_page_aflag_clear(m,
1970 pc->pc_map[field] |= 1UL << bit;
1971 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
1976 mtx_lock(&pv_chunks_mutex);
1979 /* Every freed mapping is for a 4 KB page. */
1980 pmap_resident_count_dec(pmap, freed);
1981 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
1982 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
1983 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
1984 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1985 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
1986 pc->pc_map[2] == PC_FREE2) {
1987 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1988 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1989 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1990 /* Entire chunk is free; return it. */
1991 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1992 dump_drop_page(m_pc->phys_addr);
1993 mtx_lock(&pv_chunks_mutex);
1994 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1997 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1998 mtx_lock(&pv_chunks_mutex);
1999 /* One freed pv entry in locked_pmap is sufficient. */
2000 if (pmap == locked_pmap)
2004 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2005 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2006 if (active_reclaims == 1 && pmap != NULL) {
2008 * Rotate the pv chunks list so that we do not
2009 * scan the same pv chunks that could not be
2010 * freed (because they contained a wired
2011 * and/or superpage mapping) on every
2012 * invocation of reclaim_pv_chunk().
2014 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2015 MPASS(pc->pc_pmap != NULL);
2016 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2017 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2021 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2022 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2024 mtx_unlock(&pv_chunks_mutex);
2025 if (pmap != NULL && pmap != locked_pmap)
2027 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2028 m_pc = SLIST_FIRST(&free);
2029 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2030 /* Recycle a freed page table page. */
2031 m_pc->wire_count = 1;
2033 vm_page_free_pages_toq(&free, true);
2038 * free the pv_entry back to the free list
2041 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2043 struct pv_chunk *pc;
2044 int idx, field, bit;
2046 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2047 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2048 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2049 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2050 pc = pv_to_chunk(pv);
2051 idx = pv - &pc->pc_pventry[0];
2054 pc->pc_map[field] |= 1ul << bit;
2055 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2056 pc->pc_map[2] != PC_FREE2) {
2057 /* 98% of the time, pc is already at the head of the list. */
2058 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2059 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2060 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2064 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2069 free_pv_chunk(struct pv_chunk *pc)
2073 mtx_lock(&pv_chunks_mutex);
2074 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2075 mtx_unlock(&pv_chunks_mutex);
2076 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2077 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2078 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2079 /* entire chunk is free, return it */
2080 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2081 dump_drop_page(m->phys_addr);
2082 vm_page_unwire_noq(m);
2087 * Returns a new PV entry, allocating a new PV chunk from the system when
2088 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2089 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2092 * The given PV list lock may be released.
2095 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2099 struct pv_chunk *pc;
2102 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2103 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2105 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2107 for (field = 0; field < _NPCM; field++) {
2108 if (pc->pc_map[field]) {
2109 bit = ffsl(pc->pc_map[field]) - 1;
2113 if (field < _NPCM) {
2114 pv = &pc->pc_pventry[field * 64 + bit];
2115 pc->pc_map[field] &= ~(1ul << bit);
2116 /* If this was the last item, move it to tail */
2117 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2118 pc->pc_map[2] == 0) {
2119 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2120 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2123 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2124 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2128 /* No free items, allocate another chunk */
2129 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2132 if (lockp == NULL) {
2133 PV_STAT(pc_chunk_tryfail++);
2136 m = reclaim_pv_chunk(pmap, lockp);
2140 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2141 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2142 dump_add_page(m->phys_addr);
2143 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2145 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2146 pc->pc_map[1] = PC_FREE1;
2147 pc->pc_map[2] = PC_FREE2;
2148 mtx_lock(&pv_chunks_mutex);
2149 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2150 mtx_unlock(&pv_chunks_mutex);
2151 pv = &pc->pc_pventry[0];
2152 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2153 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2154 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2159 * Ensure that the number of spare PV entries in the specified pmap meets or
2160 * exceeds the given count, "needed".
2162 * The given PV list lock may be released.
2165 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2167 struct pch new_tail;
2168 struct pv_chunk *pc;
2173 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2174 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2177 * Newly allocated PV chunks must be stored in a private list until
2178 * the required number of PV chunks have been allocated. Otherwise,
2179 * reclaim_pv_chunk() could recycle one of these chunks. In
2180 * contrast, these chunks must be added to the pmap upon allocation.
2182 TAILQ_INIT(&new_tail);
2185 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2186 bit_count((bitstr_t *)pc->pc_map, 0,
2187 sizeof(pc->pc_map) * NBBY, &free);
2191 if (avail >= needed)
2194 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2195 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2198 m = reclaim_pv_chunk(pmap, lockp);
2203 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2204 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2205 dump_add_page(m->phys_addr);
2206 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2208 pc->pc_map[0] = PC_FREE0;
2209 pc->pc_map[1] = PC_FREE1;
2210 pc->pc_map[2] = PC_FREE2;
2211 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2212 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2213 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2216 * The reclaim might have freed a chunk from the current pmap.
2217 * If that chunk contained available entries, we need to
2218 * re-count the number of available entries.
2223 if (!TAILQ_EMPTY(&new_tail)) {
2224 mtx_lock(&pv_chunks_mutex);
2225 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2226 mtx_unlock(&pv_chunks_mutex);
2231 * First find and then remove the pv entry for the specified pmap and virtual
2232 * address from the specified pv list. Returns the pv entry if found and NULL
2233 * otherwise. This operation can be performed on pv lists for either 4KB or
2234 * 2MB page mappings.
2236 static __inline pv_entry_t
2237 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2241 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2242 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2243 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2252 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2253 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2254 * entries for each of the 4KB page mappings.
2257 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2258 struct rwlock **lockp)
2260 struct md_page *pvh;
2261 struct pv_chunk *pc;
2263 vm_offset_t va_last;
2267 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2268 KASSERT((va & L2_OFFSET) == 0,
2269 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
2270 KASSERT((pa & L2_OFFSET) == 0,
2271 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2272 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2275 * Transfer the 2mpage's pv entry for this mapping to the first
2276 * page's pv list. Once this transfer begins, the pv list lock
2277 * must not be released until the last pv entry is reinstantiated.
2279 pvh = pa_to_pvh(pa);
2280 pv = pmap_pvh_remove(pvh, pmap, va);
2281 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2282 m = PHYS_TO_VM_PAGE(pa);
2283 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2285 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2286 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2287 va_last = va + L2_SIZE - PAGE_SIZE;
2289 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2290 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2291 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2292 for (field = 0; field < _NPCM; field++) {
2293 while (pc->pc_map[field]) {
2294 bit = ffsl(pc->pc_map[field]) - 1;
2295 pc->pc_map[field] &= ~(1ul << bit);
2296 pv = &pc->pc_pventry[field * 64 + bit];
2300 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2301 ("pmap_pv_demote_l2: page %p is not managed", m));
2302 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2308 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2309 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2312 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2313 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2314 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2316 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2317 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2321 * First find and then destroy the pv entry for the specified pmap and virtual
2322 * address. This operation can be performed on pv lists for either 4KB or 2MB
2326 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2330 pv = pmap_pvh_remove(pvh, pmap, va);
2331 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2332 free_pv_entry(pmap, pv);
2336 * Conditionally create the PV entry for a 4KB page mapping if the required
2337 * memory can be allocated without resorting to reclamation.
2340 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2341 struct rwlock **lockp)
2345 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2346 /* Pass NULL instead of the lock pointer to disable reclamation. */
2347 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2349 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2350 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2358 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2359 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2360 * false if the PV entry cannot be allocated without resorting to reclamation.
2363 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2364 struct rwlock **lockp)
2366 struct md_page *pvh;
2370 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2371 /* Pass NULL instead of the lock pointer to disable reclamation. */
2372 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2373 NULL : lockp)) == NULL)
2376 pa = l2e & ~ATTR_MASK;
2377 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2378 pvh = pa_to_pvh(pa);
2379 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2385 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2387 pt_entry_t newl2, oldl2;
2391 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2392 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2393 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2395 ml3 = pmap_remove_pt_page(pmap, va);
2397 panic("pmap_remove_kernel_l2: Missing pt page");
2399 ml3pa = VM_PAGE_TO_PHYS(ml3);
2400 newl2 = ml3pa | L2_TABLE;
2403 * If this page table page was unmapped by a promotion, then it
2404 * contains valid mappings. Zero it to invalidate those mappings.
2406 if (ml3->valid != 0)
2407 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2410 * Demote the mapping. The caller must have already invalidated the
2411 * mapping (i.e., the "break" in break-before-make).
2413 oldl2 = pmap_load_store(l2, newl2);
2414 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
2415 __func__, l2, oldl2));
2419 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
2422 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2423 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2425 struct md_page *pvh;
2427 vm_offset_t eva, va;
2430 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2431 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2432 old_l2 = pmap_load_clear(l2);
2433 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2434 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2437 * Since a promotion must break the 4KB page mappings before making
2438 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2440 pmap_invalidate_page(pmap, sva);
2442 if (old_l2 & ATTR_SW_WIRED)
2443 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2444 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2445 if (old_l2 & ATTR_SW_MANAGED) {
2446 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2447 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2448 pmap_pvh_free(pvh, pmap, sva);
2449 eva = sva + L2_SIZE;
2450 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2451 va < eva; va += PAGE_SIZE, m++) {
2452 if (pmap_page_dirty(old_l2))
2454 if (old_l2 & ATTR_AF)
2455 vm_page_aflag_set(m, PGA_REFERENCED);
2456 if (TAILQ_EMPTY(&m->md.pv_list) &&
2457 TAILQ_EMPTY(&pvh->pv_list))
2458 vm_page_aflag_clear(m, PGA_WRITEABLE);
2461 if (pmap == kernel_pmap) {
2462 pmap_remove_kernel_l2(pmap, l2, sva);
2464 ml3 = pmap_remove_pt_page(pmap, sva);
2466 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
2467 ("pmap_remove_l2: l3 page not promoted"));
2468 pmap_resident_count_dec(pmap, 1);
2469 KASSERT(ml3->wire_count == NL3PG,
2470 ("pmap_remove_l2: l3 page wire count error"));
2471 ml3->wire_count = 0;
2472 pmap_add_delayed_free_list(ml3, free, FALSE);
2475 return (pmap_unuse_pt(pmap, sva, l1e, free));
2479 * pmap_remove_l3: do the things to unmap a page in a process
2482 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2483 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2485 struct md_page *pvh;
2489 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2490 old_l3 = pmap_load_clear(l3);
2491 pmap_invalidate_page(pmap, va);
2492 if (old_l3 & ATTR_SW_WIRED)
2493 pmap->pm_stats.wired_count -= 1;
2494 pmap_resident_count_dec(pmap, 1);
2495 if (old_l3 & ATTR_SW_MANAGED) {
2496 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2497 if (pmap_page_dirty(old_l3))
2499 if (old_l3 & ATTR_AF)
2500 vm_page_aflag_set(m, PGA_REFERENCED);
2501 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2502 pmap_pvh_free(&m->md, pmap, va);
2503 if (TAILQ_EMPTY(&m->md.pv_list) &&
2504 (m->flags & PG_FICTITIOUS) == 0) {
2505 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2506 if (TAILQ_EMPTY(&pvh->pv_list))
2507 vm_page_aflag_clear(m, PGA_WRITEABLE);
2510 return (pmap_unuse_pt(pmap, va, l2e, free));
2514 * Remove the specified range of addresses from the L3 page table that is
2515 * identified by the given L2 entry.
2518 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
2519 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
2521 struct md_page *pvh;
2522 struct rwlock *new_lock;
2523 pt_entry_t *l3, old_l3;
2527 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2528 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
2529 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
2531 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
2532 if (!pmap_l3_valid(pmap_load(l3))) {
2534 pmap_invalidate_range(pmap, va, sva);
2539 old_l3 = pmap_load_clear(l3);
2540 if ((old_l3 & ATTR_SW_WIRED) != 0)
2541 pmap->pm_stats.wired_count--;
2542 pmap_resident_count_dec(pmap, 1);
2543 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
2544 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2545 if (pmap_page_dirty(old_l3))
2547 if ((old_l3 & ATTR_AF) != 0)
2548 vm_page_aflag_set(m, PGA_REFERENCED);
2549 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
2550 if (new_lock != *lockp) {
2551 if (*lockp != NULL) {
2553 * Pending TLB invalidations must be
2554 * performed before the PV list lock is
2555 * released. Otherwise, a concurrent
2556 * pmap_remove_all() on a physical page
2557 * could return while a stale TLB entry
2558 * still provides access to that page.
2561 pmap_invalidate_range(pmap, va,
2570 pmap_pvh_free(&m->md, pmap, sva);
2571 if (TAILQ_EMPTY(&m->md.pv_list) &&
2572 (m->flags & PG_FICTITIOUS) == 0) {
2573 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2574 if (TAILQ_EMPTY(&pvh->pv_list))
2575 vm_page_aflag_clear(m, PGA_WRITEABLE);
2580 if (pmap_unuse_pt(pmap, sva, l2e, free)) {
2586 pmap_invalidate_range(pmap, va, sva);
2590 * Remove the given range of addresses from the specified map.
2592 * It is assumed that the start and end are properly
2593 * rounded to the page size.
2596 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2598 struct rwlock *lock;
2599 vm_offset_t va_next;
2600 pd_entry_t *l0, *l1, *l2;
2601 pt_entry_t l3_paddr;
2602 struct spglist free;
2605 * Perform an unsynchronized read. This is, however, safe.
2607 if (pmap->pm_stats.resident_count == 0)
2615 for (; sva < eva; sva = va_next) {
2617 if (pmap->pm_stats.resident_count == 0)
2620 l0 = pmap_l0(pmap, sva);
2621 if (pmap_load(l0) == 0) {
2622 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2628 l1 = pmap_l0_to_l1(l0, sva);
2629 if (pmap_load(l1) == 0) {
2630 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2637 * Calculate index for next page table.
2639 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2643 l2 = pmap_l1_to_l2(l1, sva);
2647 l3_paddr = pmap_load(l2);
2649 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2650 if (sva + L2_SIZE == va_next && eva >= va_next) {
2651 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2654 } else if (pmap_demote_l2_locked(pmap, l2, sva,
2657 l3_paddr = pmap_load(l2);
2661 * Weed out invalid mappings.
2663 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2667 * Limit our scan to either the end of the va represented
2668 * by the current page table page, or to the end of the
2669 * range being removed.
2674 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
2680 vm_page_free_pages_toq(&free, true);
2684 * Routine: pmap_remove_all
2686 * Removes this physical page from
2687 * all physical maps in which it resides.
2688 * Reflects back modify bits to the pager.
2691 * Original versions of this routine were very
2692 * inefficient because they iteratively called
2693 * pmap_remove (slow...)
2697 pmap_remove_all(vm_page_t m)
2699 struct md_page *pvh;
2702 struct rwlock *lock;
2703 pd_entry_t *pde, tpde;
2704 pt_entry_t *pte, tpte;
2706 struct spglist free;
2707 int lvl, pvh_gen, md_gen;
2709 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2710 ("pmap_remove_all: page %p is not managed", m));
2712 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2713 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2714 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2717 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2719 if (!PMAP_TRYLOCK(pmap)) {
2720 pvh_gen = pvh->pv_gen;
2724 if (pvh_gen != pvh->pv_gen) {
2731 pte = pmap_pte(pmap, va, &lvl);
2732 KASSERT(pte != NULL,
2733 ("pmap_remove_all: no page table entry found"));
2735 ("pmap_remove_all: invalid pte level %d", lvl));
2737 pmap_demote_l2_locked(pmap, pte, va, &lock);
2740 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2742 if (!PMAP_TRYLOCK(pmap)) {
2743 pvh_gen = pvh->pv_gen;
2744 md_gen = m->md.pv_gen;
2748 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2754 pmap_resident_count_dec(pmap, 1);
2756 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2757 KASSERT(pde != NULL,
2758 ("pmap_remove_all: no page directory entry found"));
2760 ("pmap_remove_all: invalid pde level %d", lvl));
2761 tpde = pmap_load(pde);
2763 pte = pmap_l2_to_l3(pde, pv->pv_va);
2764 tpte = pmap_load_clear(pte);
2765 pmap_invalidate_page(pmap, pv->pv_va);
2766 if (tpte & ATTR_SW_WIRED)
2767 pmap->pm_stats.wired_count--;
2768 if ((tpte & ATTR_AF) != 0)
2769 vm_page_aflag_set(m, PGA_REFERENCED);
2772 * Update the vm_page_t clean and reference bits.
2774 if (pmap_page_dirty(tpte))
2776 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2777 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2779 free_pv_entry(pmap, pv);
2782 vm_page_aflag_clear(m, PGA_WRITEABLE);
2784 vm_page_free_pages_toq(&free, true);
2788 * Set the physical protection on the
2789 * specified range of this map as requested.
2792 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2794 vm_offset_t va, va_next;
2795 pd_entry_t *l0, *l1, *l2;
2796 pt_entry_t *l3p, l3, nbits;
2798 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
2799 if (prot == VM_PROT_NONE) {
2800 pmap_remove(pmap, sva, eva);
2804 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
2805 (VM_PROT_WRITE | VM_PROT_EXECUTE))
2809 for (; sva < eva; sva = va_next) {
2811 l0 = pmap_l0(pmap, sva);
2812 if (pmap_load(l0) == 0) {
2813 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2819 l1 = pmap_l0_to_l1(l0, sva);
2820 if (pmap_load(l1) == 0) {
2821 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2827 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2831 l2 = pmap_l1_to_l2(l1, sva);
2832 if (pmap_load(l2) == 0)
2835 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
2836 l3p = pmap_demote_l2(pmap, l2, sva);
2840 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
2841 ("pmap_protect: Invalid L2 entry after demotion"));
2847 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2849 l3 = pmap_load(l3p);
2850 if (!pmap_l3_valid(l3)) {
2851 if (va != va_next) {
2852 pmap_invalidate_range(pmap, va, sva);
2861 if ((prot & VM_PROT_WRITE) == 0) {
2862 if ((l3 & ATTR_SW_MANAGED) &&
2863 pmap_page_dirty(l3)) {
2864 vm_page_dirty(PHYS_TO_VM_PAGE(l3 &
2867 nbits |= ATTR_AP(ATTR_AP_RO);
2869 if ((prot & VM_PROT_EXECUTE) == 0)
2872 pmap_set(l3p, nbits);
2875 pmap_invalidate_range(pmap, va, sva);
2881 * Inserts the specified page table page into the specified pmap's collection
2882 * of idle page table pages. Each of a pmap's page table pages is responsible
2883 * for mapping a distinct range of virtual addresses. The pmap's collection is
2884 * ordered by this virtual address range.
2886 * If "promoted" is false, then the page table page "mpte" must be zero filled.
2889 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
2892 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2893 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
2894 return (vm_radix_insert(&pmap->pm_root, mpte));
2898 * Removes the page table page mapping the specified virtual address from the
2899 * specified pmap's collection of idle page table pages, and returns it.
2900 * Otherwise, returns NULL if there is no page table page corresponding to the
2901 * specified virtual address.
2903 static __inline vm_page_t
2904 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2907 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2908 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
2912 * Performs a break-before-make update of a pmap entry. This is needed when
2913 * either promoting or demoting pages to ensure the TLB doesn't get into an
2914 * inconsistent state.
2917 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
2918 vm_offset_t va, vm_size_t size)
2922 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2925 * Ensure we don't get switched out with the page table in an
2926 * inconsistent state. We also need to ensure no interrupts fire
2927 * as they may make use of an address we are about to invalidate.
2929 intr = intr_disable();
2932 /* Clear the old mapping */
2934 pmap_invalidate_range_nopin(pmap, va, va + size);
2936 /* Create the new mapping */
2937 pmap_load_store(pte, newpte);
2943 #if VM_NRESERVLEVEL > 0
2945 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
2946 * replace the many pv entries for the 4KB page mappings by a single pv entry
2947 * for the 2MB page mapping.
2950 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2951 struct rwlock **lockp)
2953 struct md_page *pvh;
2955 vm_offset_t va_last;
2958 KASSERT((pa & L2_OFFSET) == 0,
2959 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
2960 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2963 * Transfer the first page's pv entry for this mapping to the 2mpage's
2964 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
2965 * a transfer avoids the possibility that get_pv_entry() calls
2966 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
2967 * mappings that is being promoted.
2969 m = PHYS_TO_VM_PAGE(pa);
2970 va = va & ~L2_OFFSET;
2971 pv = pmap_pvh_remove(&m->md, pmap, va);
2972 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
2973 pvh = pa_to_pvh(pa);
2974 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2976 /* Free the remaining NPTEPG - 1 pv entries. */
2977 va_last = va + L2_SIZE - PAGE_SIZE;
2981 pmap_pvh_free(&m->md, pmap, va);
2982 } while (va < va_last);
2986 * Tries to promote the 512, contiguous 4KB page mappings that are within a
2987 * single level 2 table entry to a single 2MB page mapping. For promotion
2988 * to occur, two conditions must be met: (1) the 4KB page mappings must map
2989 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
2990 * identical characteristics.
2993 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
2994 struct rwlock **lockp)
2996 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
3000 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3002 sva = va & ~L2_OFFSET;
3003 firstl3 = pmap_l2_to_l3(l2, sva);
3004 newl2 = pmap_load(firstl3);
3006 /* Check the alingment is valid */
3007 if (((newl2 & ~ATTR_MASK) & L2_OFFSET) != 0) {
3008 atomic_add_long(&pmap_l2_p_failures, 1);
3009 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3010 " in pmap %p", va, pmap);
3014 pa = newl2 + L2_SIZE - PAGE_SIZE;
3015 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
3016 oldl3 = pmap_load(l3);
3018 atomic_add_long(&pmap_l2_p_failures, 1);
3019 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3020 " in pmap %p", va, pmap);
3027 * Save the page table page in its current state until the L2
3028 * mapping the superpage is demoted by pmap_demote_l2() or
3029 * destroyed by pmap_remove_l3().
3031 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3032 KASSERT(mpte >= vm_page_array &&
3033 mpte < &vm_page_array[vm_page_array_size],
3034 ("pmap_promote_l2: page table page is out of range"));
3035 KASSERT(mpte->pindex == pmap_l2_pindex(va),
3036 ("pmap_promote_l2: page table page's pindex is wrong"));
3037 if (pmap_insert_pt_page(pmap, mpte, true)) {
3038 atomic_add_long(&pmap_l2_p_failures, 1);
3040 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
3045 if ((newl2 & ATTR_SW_MANAGED) != 0)
3046 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
3048 newl2 &= ~ATTR_DESCR_MASK;
3051 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
3053 atomic_add_long(&pmap_l2_promotions, 1);
3054 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
3057 #endif /* VM_NRESERVLEVEL > 0 */
3060 * Insert the given physical page (p) at
3061 * the specified virtual address (v) in the
3062 * target physical map with the protection requested.
3064 * If specified, the page will be wired down, meaning
3065 * that the related pte can not be reclaimed.
3067 * NB: This is the only routine which MAY NOT lazy-evaluate
3068 * or lose information. That is, this routine must actually
3069 * insert this page into the given map NOW.
3072 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3073 u_int flags, int8_t psind)
3075 struct rwlock *lock;
3077 pt_entry_t new_l3, orig_l3;
3078 pt_entry_t *l2, *l3;
3085 va = trunc_page(va);
3086 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3087 VM_OBJECT_ASSERT_LOCKED(m->object);
3088 pa = VM_PAGE_TO_PHYS(m);
3089 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3091 if ((prot & VM_PROT_WRITE) == 0)
3092 new_l3 |= ATTR_AP(ATTR_AP_RO);
3093 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3095 if ((flags & PMAP_ENTER_WIRED) != 0)
3096 new_l3 |= ATTR_SW_WIRED;
3097 if (va < VM_MAXUSER_ADDRESS)
3098 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3099 if ((m->oflags & VPO_UNMANAGED) == 0)
3100 new_l3 |= ATTR_SW_MANAGED;
3102 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3107 /* Assert the required virtual and physical alignment. */
3108 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3109 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3110 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3117 * In the case that a page table page is not
3118 * resident, we are creating it here.
3121 pde = pmap_pde(pmap, va, &lvl);
3122 if (pde != NULL && lvl == 2) {
3123 l3 = pmap_l2_to_l3(pde, va);
3124 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3125 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3129 } else if (pde != NULL && lvl == 1) {
3130 l2 = pmap_l1_to_l2(pde, va);
3131 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3132 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
3133 l3 = &l3[pmap_l3_index(va)];
3134 if (va < VM_MAXUSER_ADDRESS) {
3135 mpte = PHYS_TO_VM_PAGE(
3136 pmap_load(l2) & ~ATTR_MASK);
3141 /* We need to allocate an L3 table. */
3143 if (va < VM_MAXUSER_ADDRESS) {
3144 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
3147 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
3148 * to handle the possibility that a superpage mapping for "va"
3149 * was created while we slept.
3151 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
3152 nosleep ? NULL : &lock);
3153 if (mpte == NULL && nosleep) {
3154 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3155 rv = KERN_RESOURCE_SHORTAGE;
3160 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
3163 orig_l3 = pmap_load(l3);
3164 opa = orig_l3 & ~ATTR_MASK;
3168 * Is the specified virtual address already mapped?
3170 if (pmap_l3_valid(orig_l3)) {
3172 * Wiring change, just update stats. We don't worry about
3173 * wiring PT pages as they remain resident as long as there
3174 * are valid mappings in them. Hence, if a user page is wired,
3175 * the PT page will be also.
3177 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3178 (orig_l3 & ATTR_SW_WIRED) == 0)
3179 pmap->pm_stats.wired_count++;
3180 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3181 (orig_l3 & ATTR_SW_WIRED) != 0)
3182 pmap->pm_stats.wired_count--;
3185 * Remove the extra PT page reference.
3189 KASSERT(mpte->wire_count > 0,
3190 ("pmap_enter: missing reference to page table page,"
3195 * Has the physical page changed?
3199 * No, might be a protection or wiring change.
3201 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3202 if ((new_l3 & ATTR_AP(ATTR_AP_RW)) ==
3203 ATTR_AP(ATTR_AP_RW)) {
3204 vm_page_aflag_set(m, PGA_WRITEABLE);
3211 * The physical page has changed. Temporarily invalidate
3214 orig_l3 = pmap_load_clear(l3);
3215 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
3216 ("pmap_enter: unexpected pa update for %#lx", va));
3217 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3218 om = PHYS_TO_VM_PAGE(opa);
3221 * The pmap lock is sufficient to synchronize with
3222 * concurrent calls to pmap_page_test_mappings() and
3223 * pmap_ts_referenced().
3225 if (pmap_page_dirty(orig_l3))
3227 if ((orig_l3 & ATTR_AF) != 0)
3228 vm_page_aflag_set(om, PGA_REFERENCED);
3229 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3230 pv = pmap_pvh_remove(&om->md, pmap, va);
3231 if ((m->oflags & VPO_UNMANAGED) != 0)
3232 free_pv_entry(pmap, pv);
3233 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3234 TAILQ_EMPTY(&om->md.pv_list) &&
3235 ((om->flags & PG_FICTITIOUS) != 0 ||
3236 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3237 vm_page_aflag_clear(om, PGA_WRITEABLE);
3239 pmap_invalidate_page(pmap, va);
3243 * Increment the counters.
3245 if ((new_l3 & ATTR_SW_WIRED) != 0)
3246 pmap->pm_stats.wired_count++;
3247 pmap_resident_count_inc(pmap, 1);
3250 * Enter on the PV list if part of our managed memory.
3252 if ((m->oflags & VPO_UNMANAGED) == 0) {
3254 pv = get_pv_entry(pmap, &lock);
3257 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3258 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3260 if ((new_l3 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3261 vm_page_aflag_set(m, PGA_WRITEABLE);
3266 * Sync icache if exec permission and attribute VM_MEMATTR_WRITE_BACK
3267 * is set. Do it now, before the mapping is stored and made
3268 * valid for hardware table walk. If done later, then other can
3269 * access this page before caches are properly synced.
3270 * Don't do it for kernel memory which is mapped with exec
3271 * permission even if the memory isn't going to hold executable
3272 * code. The only time when icache sync is needed is after
3273 * kernel module is loaded and the relocation info is processed.
3274 * And it's done in elf_cpu_load_file().
3276 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3277 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3278 (opa != pa || (orig_l3 & ATTR_XN)))
3279 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3282 * Update the L3 entry
3284 if (pmap_l3_valid(orig_l3)) {
3285 KASSERT(opa == pa, ("pmap_enter: invalid update"));
3286 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3287 /* same PA, different attributes */
3288 pmap_load_store(l3, new_l3);
3289 pmap_invalidate_page(pmap, va);
3290 if (pmap_page_dirty(orig_l3) &&
3291 (orig_l3 & ATTR_SW_MANAGED) != 0)
3296 * This can happens if multiple threads simultaneously
3297 * access not yet mapped page. This bad for performance
3298 * since this can cause full demotion-NOP-promotion
3300 * Another possible reasons are:
3301 * - VM and pmap memory layout are diverged
3302 * - tlb flush is missing somewhere and CPU doesn't see
3305 CTR4(KTR_PMAP, "%s: already mapped page - "
3306 "pmap %p va 0x%#lx pte 0x%lx",
3307 __func__, pmap, va, new_l3);
3311 pmap_load_store(l3, new_l3);
3314 #if VM_NRESERVLEVEL > 0
3315 if (pmap != pmap_kernel() &&
3316 (mpte == NULL || mpte->wire_count == NL3PG) &&
3317 pmap_ps_enabled(pmap) &&
3318 (m->flags & PG_FICTITIOUS) == 0 &&
3319 vm_reserv_level_iffullpop(m) == 0) {
3320 pmap_promote_l2(pmap, pde, va, &lock);
3333 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
3334 * if successful. Returns false if (1) a page table page cannot be allocated
3335 * without sleeping, (2) a mapping already exists at the specified virtual
3336 * address, or (3) a PV entry cannot be allocated without reclaiming another
3340 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3341 struct rwlock **lockp)
3345 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3347 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
3348 ATTR_IDX(m->md.pv_memattr) | ATTR_AP(ATTR_AP_RO) | L2_BLOCK);
3349 if ((m->oflags & VPO_UNMANAGED) == 0)
3350 new_l2 |= ATTR_SW_MANAGED;
3351 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3353 if (va < VM_MAXUSER_ADDRESS)
3354 new_l2 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3355 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
3356 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
3361 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
3362 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
3363 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
3364 * a mapping already exists at the specified virtual address. Returns
3365 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
3366 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
3367 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3369 * The parameter "m" is only used when creating a managed, writeable mapping.
3372 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
3373 vm_page_t m, struct rwlock **lockp)
3375 struct spglist free;
3376 pd_entry_t *l2, old_l2;
3379 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3381 if ((l2pg = pmap_alloc_l2(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
3382 NULL : lockp)) == NULL) {
3383 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
3385 return (KERN_RESOURCE_SHORTAGE);
3388 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
3389 l2 = &l2[pmap_l2_index(va)];
3390 if ((old_l2 = pmap_load(l2)) != 0) {
3391 KASSERT(l2pg->wire_count > 1,
3392 ("pmap_enter_l2: l2pg's wire count is too low"));
3393 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3396 "pmap_enter_l2: failure for va %#lx in pmap %p",
3398 return (KERN_FAILURE);
3401 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
3402 (void)pmap_remove_l2(pmap, l2, va,
3403 pmap_load(pmap_l1(pmap, va)), &free, lockp);
3405 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
3407 vm_page_free_pages_toq(&free, true);
3408 if (va >= VM_MAXUSER_ADDRESS) {
3410 * Both pmap_remove_l2() and pmap_remove_l3() will
3411 * leave the kernel page table page zero filled.
3413 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3414 if (pmap_insert_pt_page(pmap, mt, false))
3415 panic("pmap_enter_l2: trie insert failed");
3417 KASSERT(pmap_load(l2) == 0,
3418 ("pmap_enter_l2: non-zero L2 entry %p", l2));
3421 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
3423 * Abort this mapping if its PV entry could not be created.
3425 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
3427 if (pmap_unwire_l3(pmap, va, l2pg, &free)) {
3429 * Although "va" is not mapped, paging-structure
3430 * caches could nonetheless have entries that
3431 * refer to the freed page table pages.
3432 * Invalidate those entries.
3434 pmap_invalidate_page(pmap, va);
3435 vm_page_free_pages_toq(&free, true);
3438 "pmap_enter_l2: failure for va %#lx in pmap %p",
3440 return (KERN_RESOURCE_SHORTAGE);
3442 if ((new_l2 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3443 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3444 vm_page_aflag_set(mt, PGA_WRITEABLE);
3448 * Increment counters.
3450 if ((new_l2 & ATTR_SW_WIRED) != 0)
3451 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
3452 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
3455 * Map the superpage.
3457 (void)pmap_load_store(l2, new_l2);
3459 atomic_add_long(&pmap_l2_mappings, 1);
3460 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
3463 return (KERN_SUCCESS);
3467 * Maps a sequence of resident pages belonging to the same object.
3468 * The sequence begins with the given page m_start. This page is
3469 * mapped at the given virtual address start. Each subsequent page is
3470 * mapped at a virtual address that is offset from start by the same
3471 * amount as the page is offset from m_start within the object. The
3472 * last page in the sequence is the page with the largest offset from
3473 * m_start that can be mapped at a virtual address less than the given
3474 * virtual address end. Not every virtual page between start and end
3475 * is mapped; only those for which a resident page exists with the
3476 * corresponding offset from m_start are mapped.
3479 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3480 vm_page_t m_start, vm_prot_t prot)
3482 struct rwlock *lock;
3485 vm_pindex_t diff, psize;
3487 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3489 psize = atop(end - start);
3494 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3495 va = start + ptoa(diff);
3496 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
3497 m->psind == 1 && pmap_ps_enabled(pmap) &&
3498 pmap_enter_2mpage(pmap, va, m, prot, &lock))
3499 m = &m[L2_SIZE / PAGE_SIZE - 1];
3501 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
3503 m = TAILQ_NEXT(m, listq);
3511 * this code makes some *MAJOR* assumptions:
3512 * 1. Current pmap & pmap exists.
3515 * 4. No page table pages.
3516 * but is *MUCH* faster than pmap_enter...
3520 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3522 struct rwlock *lock;
3526 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3533 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3534 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3536 struct spglist free;
3538 pt_entry_t *l2, *l3, l3_val;
3542 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3543 (m->oflags & VPO_UNMANAGED) != 0,
3544 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3545 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3547 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3549 * In the case that a page table page is not
3550 * resident, we are creating it here.
3552 if (va < VM_MAXUSER_ADDRESS) {
3553 vm_pindex_t l2pindex;
3556 * Calculate pagetable page index
3558 l2pindex = pmap_l2_pindex(va);
3559 if (mpte && (mpte->pindex == l2pindex)) {
3565 pde = pmap_pde(pmap, va, &lvl);
3568 * If the page table page is mapped, we just increment
3569 * the hold count, and activate it. Otherwise, we
3570 * attempt to allocate a page table page. If this
3571 * attempt fails, we don't retry. Instead, we give up.
3574 l2 = pmap_l1_to_l2(pde, va);
3575 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3579 if (lvl == 2 && pmap_load(pde) != 0) {
3581 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3585 * Pass NULL instead of the PV list lock
3586 * pointer, because we don't intend to sleep.
3588 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3593 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3594 l3 = &l3[pmap_l3_index(va)];
3597 pde = pmap_pde(kernel_pmap, va, &lvl);
3598 KASSERT(pde != NULL,
3599 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3602 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3603 l3 = pmap_l2_to_l3(pde, va);
3607 * Abort if a mapping already exists.
3609 if (pmap_load(l3) != 0) {
3618 * Enter on the PV list if part of our managed memory.
3620 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3621 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3624 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
3625 pmap_invalidate_page(pmap, va);
3626 vm_page_free_pages_toq(&free, true);
3634 * Increment counters
3636 pmap_resident_count_inc(pmap, 1);
3638 pa = VM_PAGE_TO_PHYS(m);
3639 l3_val = pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3640 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3641 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3643 else if (va < VM_MAXUSER_ADDRESS)
3647 * Now validate mapping with RO protection
3649 if ((m->oflags & VPO_UNMANAGED) == 0)
3650 l3_val |= ATTR_SW_MANAGED;
3652 /* Sync icache before the mapping is stored to PTE */
3653 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3654 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
3655 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3657 pmap_load_store(l3, l3_val);
3664 * This code maps large physical mmap regions into the
3665 * processor address space. Note that some shortcuts
3666 * are taken, but the code works.
3669 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3670 vm_pindex_t pindex, vm_size_t size)
3673 VM_OBJECT_ASSERT_WLOCKED(object);
3674 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3675 ("pmap_object_init_pt: non-device object"));
3679 * Clear the wired attribute from the mappings for the specified range of
3680 * addresses in the given pmap. Every valid mapping within that range
3681 * must have the wired attribute set. In contrast, invalid mappings
3682 * cannot have the wired attribute set, so they are ignored.
3684 * The wired attribute of the page table entry is not a hardware feature,
3685 * so there is no need to invalidate any TLB entries.
3688 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3690 vm_offset_t va_next;
3691 pd_entry_t *l0, *l1, *l2;
3695 for (; sva < eva; sva = va_next) {
3696 l0 = pmap_l0(pmap, sva);
3697 if (pmap_load(l0) == 0) {
3698 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3704 l1 = pmap_l0_to_l1(l0, sva);
3705 if (pmap_load(l1) == 0) {
3706 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3712 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3716 l2 = pmap_l1_to_l2(l1, sva);
3717 if (pmap_load(l2) == 0)
3720 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3721 l3 = pmap_demote_l2(pmap, l2, sva);
3725 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3726 ("pmap_unwire: Invalid l2 entry after demotion"));
3730 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3732 if (pmap_load(l3) == 0)
3734 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
3735 panic("pmap_unwire: l3 %#jx is missing "
3736 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
3739 * PG_W must be cleared atomically. Although the pmap
3740 * lock synchronizes access to PG_W, another processor
3741 * could be setting PG_M and/or PG_A concurrently.
3743 atomic_clear_long(l3, ATTR_SW_WIRED);
3744 pmap->pm_stats.wired_count--;
3751 * Copy the range specified by src_addr/len
3752 * from the source map to the range dst_addr/len
3753 * in the destination map.
3755 * This routine is only advisory and need not do anything.
3757 * Because the executable mappings created by this routine are copied,
3758 * it should not have to flush the instruction cache.
3761 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3762 vm_offset_t src_addr)
3764 struct rwlock *lock;
3765 struct spglist free;
3766 pd_entry_t *l0, *l1, *l2, srcptepaddr;
3767 pt_entry_t *dst_pte, ptetemp, *src_pte;
3768 vm_offset_t addr, end_addr, va_next;
3769 vm_page_t dst_l2pg, dstmpte, srcmpte;
3771 if (dst_addr != src_addr)
3773 end_addr = src_addr + len;
3775 if (dst_pmap < src_pmap) {
3776 PMAP_LOCK(dst_pmap);
3777 PMAP_LOCK(src_pmap);
3779 PMAP_LOCK(src_pmap);
3780 PMAP_LOCK(dst_pmap);
3782 for (addr = src_addr; addr < end_addr; addr = va_next) {
3783 l0 = pmap_l0(src_pmap, addr);
3784 if (pmap_load(l0) == 0) {
3785 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
3790 l1 = pmap_l0_to_l1(l0, addr);
3791 if (pmap_load(l1) == 0) {
3792 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
3797 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
3800 l2 = pmap_l1_to_l2(l1, addr);
3801 srcptepaddr = pmap_load(l2);
3802 if (srcptepaddr == 0)
3804 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
3805 if ((addr & L2_OFFSET) != 0 ||
3806 addr + L2_SIZE > end_addr)
3808 dst_l2pg = pmap_alloc_l2(dst_pmap, addr, NULL);
3809 if (dst_l2pg == NULL)
3812 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_l2pg));
3813 l2 = &l2[pmap_l2_index(addr)];
3814 if (pmap_load(l2) == 0 &&
3815 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
3816 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
3817 PMAP_ENTER_NORECLAIM, &lock))) {
3818 (void)pmap_load_store(l2, srcptepaddr &
3820 pmap_resident_count_inc(dst_pmap, L2_SIZE /
3822 atomic_add_long(&pmap_l2_mappings, 1);
3824 dst_l2pg->wire_count--;
3827 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
3828 ("pmap_copy: invalid L2 entry"));
3829 srcptepaddr &= ~ATTR_MASK;
3830 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
3831 KASSERT(srcmpte->wire_count > 0,
3832 ("pmap_copy: source page table page is unused"));
3833 if (va_next > end_addr)
3835 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
3836 src_pte = &src_pte[pmap_l3_index(addr)];
3838 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
3839 ptetemp = pmap_load(src_pte);
3842 * We only virtual copy managed pages.
3844 if ((ptetemp & ATTR_SW_MANAGED) == 0)
3847 if (dstmpte != NULL) {
3848 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
3849 ("dstmpte pindex/addr mismatch"));
3850 dstmpte->wire_count++;
3851 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
3854 dst_pte = (pt_entry_t *)
3855 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
3856 dst_pte = &dst_pte[pmap_l3_index(addr)];
3857 if (pmap_load(dst_pte) == 0 &&
3858 pmap_try_insert_pv_entry(dst_pmap, addr,
3859 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
3861 * Clear the wired, modified, and accessed
3862 * (referenced) bits during the copy.
3866 (void)pmap_load_store(dst_pte, ptetemp &
3868 pmap_resident_count_inc(dst_pmap, 1);
3871 if (pmap_unwire_l3(dst_pmap, addr, dstmpte,
3874 * Although "addr" is not mapped,
3875 * paging-structure caches could
3876 * nonetheless have entries that refer
3877 * to the freed page table pages.
3878 * Invalidate those entries.
3880 * XXX redundant invalidation
3882 pmap_invalidate_page(dst_pmap, addr);
3883 vm_page_free_pages_toq(&free, true);
3887 /* Have we copied all of the valid mappings? */
3888 if (dstmpte->wire_count >= srcmpte->wire_count)
3894 * XXX This barrier may not be needed because the destination pmap is
3901 PMAP_UNLOCK(src_pmap);
3902 PMAP_UNLOCK(dst_pmap);
3906 * pmap_zero_page zeros the specified hardware page by mapping
3907 * the page into KVM and using bzero to clear its contents.
3910 pmap_zero_page(vm_page_t m)
3912 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3914 pagezero((void *)va);
3918 * pmap_zero_page_area zeros the specified hardware page by mapping
3919 * the page into KVM and using bzero to clear its contents.
3921 * off and size may not cover an area beyond a single hardware page.
3924 pmap_zero_page_area(vm_page_t m, int off, int size)
3926 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3928 if (off == 0 && size == PAGE_SIZE)
3929 pagezero((void *)va);
3931 bzero((char *)va + off, size);
3935 * pmap_copy_page copies the specified (machine independent)
3936 * page by mapping the page into virtual memory and using
3937 * bcopy to copy the page, one machine dependent page at a
3941 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
3943 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
3944 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
3946 pagecopy((void *)src, (void *)dst);
3949 int unmapped_buf_allowed = 1;
3952 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
3953 vm_offset_t b_offset, int xfersize)
3957 vm_paddr_t p_a, p_b;
3958 vm_offset_t a_pg_offset, b_pg_offset;
3961 while (xfersize > 0) {
3962 a_pg_offset = a_offset & PAGE_MASK;
3963 m_a = ma[a_offset >> PAGE_SHIFT];
3964 p_a = m_a->phys_addr;
3965 b_pg_offset = b_offset & PAGE_MASK;
3966 m_b = mb[b_offset >> PAGE_SHIFT];
3967 p_b = m_b->phys_addr;
3968 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
3969 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
3970 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
3971 panic("!DMAP a %lx", p_a);
3973 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
3975 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
3976 panic("!DMAP b %lx", p_b);
3978 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
3980 bcopy(a_cp, b_cp, cnt);
3988 pmap_quick_enter_page(vm_page_t m)
3991 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
3995 pmap_quick_remove_page(vm_offset_t addr)
4000 * Returns true if the pmap's pv is one of the first
4001 * 16 pvs linked to from this page. This count may
4002 * be changed upwards or downwards in the future; it
4003 * is only necessary that true be returned for a small
4004 * subset of pmaps for proper page aging.
4007 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4009 struct md_page *pvh;
4010 struct rwlock *lock;
4015 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4016 ("pmap_page_exists_quick: page %p is not managed", m));
4018 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4020 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4021 if (PV_PMAP(pv) == pmap) {
4029 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4030 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4031 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4032 if (PV_PMAP(pv) == pmap) {
4046 * pmap_page_wired_mappings:
4048 * Return the number of managed mappings to the given physical page
4052 pmap_page_wired_mappings(vm_page_t m)
4054 struct rwlock *lock;
4055 struct md_page *pvh;
4059 int count, lvl, md_gen, pvh_gen;
4061 if ((m->oflags & VPO_UNMANAGED) != 0)
4063 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4067 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4069 if (!PMAP_TRYLOCK(pmap)) {
4070 md_gen = m->md.pv_gen;
4074 if (md_gen != m->md.pv_gen) {
4079 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4080 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4084 if ((m->flags & PG_FICTITIOUS) == 0) {
4085 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4086 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4088 if (!PMAP_TRYLOCK(pmap)) {
4089 md_gen = m->md.pv_gen;
4090 pvh_gen = pvh->pv_gen;
4094 if (md_gen != m->md.pv_gen ||
4095 pvh_gen != pvh->pv_gen) {
4100 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4102 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4112 * Destroy all managed, non-wired mappings in the given user-space
4113 * pmap. This pmap cannot be active on any processor besides the
4116 * This function cannot be applied to the kernel pmap. Moreover, it
4117 * is not intended for general use. It is only to be used during
4118 * process termination. Consequently, it can be implemented in ways
4119 * that make it faster than pmap_remove(). First, it can more quickly
4120 * destroy mappings by iterating over the pmap's collection of PV
4121 * entries, rather than searching the page table. Second, it doesn't
4122 * have to test and clear the page table entries atomically, because
4123 * no processor is currently accessing the user address space. In
4124 * particular, a page table entry's dirty bit won't change state once
4125 * this function starts.
4128 pmap_remove_pages(pmap_t pmap)
4131 pt_entry_t *pte, tpte;
4132 struct spglist free;
4133 vm_page_t m, ml3, mt;
4135 struct md_page *pvh;
4136 struct pv_chunk *pc, *npc;
4137 struct rwlock *lock;
4139 uint64_t inuse, bitmask;
4140 int allfree, field, freed, idx, lvl;
4147 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4150 for (field = 0; field < _NPCM; field++) {
4151 inuse = ~pc->pc_map[field] & pc_freemask[field];
4152 while (inuse != 0) {
4153 bit = ffsl(inuse) - 1;
4154 bitmask = 1UL << bit;
4155 idx = field * 64 + bit;
4156 pv = &pc->pc_pventry[idx];
4159 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4160 KASSERT(pde != NULL,
4161 ("Attempting to remove an unmapped page"));
4165 pte = pmap_l1_to_l2(pde, pv->pv_va);
4166 tpte = pmap_load(pte);
4167 KASSERT((tpte & ATTR_DESCR_MASK) ==
4169 ("Attempting to remove an invalid "
4170 "block: %lx", tpte));
4171 tpte = pmap_load(pte);
4174 pte = pmap_l2_to_l3(pde, pv->pv_va);
4175 tpte = pmap_load(pte);
4176 KASSERT((tpte & ATTR_DESCR_MASK) ==
4178 ("Attempting to remove an invalid "
4179 "page: %lx", tpte));
4183 "Invalid page directory level: %d",
4188 * We cannot remove wired pages from a process' mapping at this time
4190 if (tpte & ATTR_SW_WIRED) {
4195 pa = tpte & ~ATTR_MASK;
4197 m = PHYS_TO_VM_PAGE(pa);
4198 KASSERT(m->phys_addr == pa,
4199 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4200 m, (uintmax_t)m->phys_addr,
4203 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4204 m < &vm_page_array[vm_page_array_size],
4205 ("pmap_remove_pages: bad pte %#jx",
4209 * Because this pmap is not active on other
4210 * processors, the dirty bit cannot have
4211 * changed state since we last loaded pte.
4216 * Update the vm_page_t clean/reference bits.
4218 if ((tpte & ATTR_AP_RW_BIT) ==
4219 ATTR_AP(ATTR_AP_RW)) {
4222 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4231 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4234 pc->pc_map[field] |= bitmask;
4237 pmap_resident_count_dec(pmap,
4238 L2_SIZE / PAGE_SIZE);
4239 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
4240 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
4242 if (TAILQ_EMPTY(&pvh->pv_list)) {
4243 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4244 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
4245 TAILQ_EMPTY(&mt->md.pv_list))
4246 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4248 ml3 = pmap_remove_pt_page(pmap,
4251 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
4252 ("pmap_remove_pages: l3 page not promoted"));
4253 pmap_resident_count_dec(pmap,1);
4254 KASSERT(ml3->wire_count == NL3PG,
4255 ("pmap_remove_pages: l3 page wire count error"));
4256 ml3->wire_count = 0;
4257 pmap_add_delayed_free_list(ml3,
4262 pmap_resident_count_dec(pmap, 1);
4263 TAILQ_REMOVE(&m->md.pv_list, pv,
4266 if ((m->aflags & PGA_WRITEABLE) != 0 &&
4267 TAILQ_EMPTY(&m->md.pv_list) &&
4268 (m->flags & PG_FICTITIOUS) == 0) {
4270 VM_PAGE_TO_PHYS(m));
4271 if (TAILQ_EMPTY(&pvh->pv_list))
4272 vm_page_aflag_clear(m,
4277 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
4282 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4283 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4284 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4286 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4290 pmap_invalidate_all(pmap);
4294 vm_page_free_pages_toq(&free, true);
4298 * This is used to check if a page has been accessed or modified. As we
4299 * don't have a bit to see if it has been modified we have to assume it
4300 * has been if the page is read/write.
4303 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
4305 struct rwlock *lock;
4307 struct md_page *pvh;
4308 pt_entry_t *pte, mask, value;
4310 int lvl, md_gen, pvh_gen;
4314 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4317 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4319 if (!PMAP_TRYLOCK(pmap)) {
4320 md_gen = m->md.pv_gen;
4324 if (md_gen != m->md.pv_gen) {
4329 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4331 ("pmap_page_test_mappings: Invalid level %d", lvl));
4335 mask |= ATTR_AP_RW_BIT;
4336 value |= ATTR_AP(ATTR_AP_RW);
4339 mask |= ATTR_AF | ATTR_DESCR_MASK;
4340 value |= ATTR_AF | L3_PAGE;
4342 rv = (pmap_load(pte) & mask) == value;
4347 if ((m->flags & PG_FICTITIOUS) == 0) {
4348 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4349 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4351 if (!PMAP_TRYLOCK(pmap)) {
4352 md_gen = m->md.pv_gen;
4353 pvh_gen = pvh->pv_gen;
4357 if (md_gen != m->md.pv_gen ||
4358 pvh_gen != pvh->pv_gen) {
4363 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4365 ("pmap_page_test_mappings: Invalid level %d", lvl));
4369 mask |= ATTR_AP_RW_BIT;
4370 value |= ATTR_AP(ATTR_AP_RW);
4373 mask |= ATTR_AF | ATTR_DESCR_MASK;
4374 value |= ATTR_AF | L2_BLOCK;
4376 rv = (pmap_load(pte) & mask) == value;
4390 * Return whether or not the specified physical page was modified
4391 * in any physical maps.
4394 pmap_is_modified(vm_page_t m)
4397 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4398 ("pmap_is_modified: page %p is not managed", m));
4401 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4402 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4403 * is clear, no PTEs can have PG_M set.
4405 VM_OBJECT_ASSERT_WLOCKED(m->object);
4406 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4408 return (pmap_page_test_mappings(m, FALSE, TRUE));
4412 * pmap_is_prefaultable:
4414 * Return whether or not the specified virtual address is eligible
4418 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4426 pte = pmap_pte(pmap, addr, &lvl);
4427 if (pte != NULL && pmap_load(pte) != 0) {
4435 * pmap_is_referenced:
4437 * Return whether or not the specified physical page was referenced
4438 * in any physical maps.
4441 pmap_is_referenced(vm_page_t m)
4444 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4445 ("pmap_is_referenced: page %p is not managed", m));
4446 return (pmap_page_test_mappings(m, TRUE, FALSE));
4450 * Clear the write and modified bits in each of the given page's mappings.
4453 pmap_remove_write(vm_page_t m)
4455 struct md_page *pvh;
4457 struct rwlock *lock;
4458 pv_entry_t next_pv, pv;
4459 pt_entry_t oldpte, *pte;
4461 int lvl, md_gen, pvh_gen;
4463 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4464 ("pmap_remove_write: page %p is not managed", m));
4467 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4468 * set by another thread while the object is locked. Thus,
4469 * if PGA_WRITEABLE is clear, no page table entries need updating.
4471 VM_OBJECT_ASSERT_WLOCKED(m->object);
4472 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4474 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4475 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4476 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4479 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4481 if (!PMAP_TRYLOCK(pmap)) {
4482 pvh_gen = pvh->pv_gen;
4486 if (pvh_gen != pvh->pv_gen) {
4493 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4494 if ((pmap_load(pte) & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
4495 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
4496 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4497 ("inconsistent pv lock %p %p for page %p",
4498 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4501 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4503 if (!PMAP_TRYLOCK(pmap)) {
4504 pvh_gen = pvh->pv_gen;
4505 md_gen = m->md.pv_gen;
4509 if (pvh_gen != pvh->pv_gen ||
4510 md_gen != m->md.pv_gen) {
4516 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4518 oldpte = pmap_load(pte);
4519 if ((oldpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) {
4520 if (!atomic_cmpset_long(pte, oldpte,
4521 oldpte | ATTR_AP(ATTR_AP_RO)))
4523 if ((oldpte & ATTR_AF) != 0)
4525 pmap_invalidate_page(pmap, pv->pv_va);
4530 vm_page_aflag_clear(m, PGA_WRITEABLE);
4533 static __inline boolean_t
4534 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
4541 * pmap_ts_referenced:
4543 * Return a count of reference bits for a page, clearing those bits.
4544 * It is not necessary for every reference bit to be cleared, but it
4545 * is necessary that 0 only be returned when there are truly no
4546 * reference bits set.
4548 * As an optimization, update the page's dirty field if a modified bit is
4549 * found while counting reference bits. This opportunistic update can be
4550 * performed at low cost and can eliminate the need for some future calls
4551 * to pmap_is_modified(). However, since this function stops after
4552 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4553 * dirty pages. Those dirty pages will only be detected by a future call
4554 * to pmap_is_modified().
4557 pmap_ts_referenced(vm_page_t m)
4559 struct md_page *pvh;
4562 struct rwlock *lock;
4563 pd_entry_t *pde, tpde;
4564 pt_entry_t *pte, tpte;
4568 int cleared, md_gen, not_cleared, lvl, pvh_gen;
4569 struct spglist free;
4572 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4573 ("pmap_ts_referenced: page %p is not managed", m));
4576 pa = VM_PAGE_TO_PHYS(m);
4577 lock = PHYS_TO_PV_LIST_LOCK(pa);
4578 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4582 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4583 goto small_mappings;
4589 if (!PMAP_TRYLOCK(pmap)) {
4590 pvh_gen = pvh->pv_gen;
4594 if (pvh_gen != pvh->pv_gen) {
4600 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4601 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4603 ("pmap_ts_referenced: invalid pde level %d", lvl));
4604 tpde = pmap_load(pde);
4605 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4606 ("pmap_ts_referenced: found an invalid l1 table"));
4607 pte = pmap_l1_to_l2(pde, pv->pv_va);
4608 tpte = pmap_load(pte);
4609 if (pmap_page_dirty(tpte)) {
4611 * Although "tpte" is mapping a 2MB page, because
4612 * this function is called at a 4KB page granularity,
4613 * we only update the 4KB page under test.
4617 if ((tpte & ATTR_AF) != 0) {
4619 * Since this reference bit is shared by 512 4KB
4620 * pages, it should not be cleared every time it is
4621 * tested. Apply a simple "hash" function on the
4622 * physical page number, the virtual superpage number,
4623 * and the pmap address to select one 4KB page out of
4624 * the 512 on which testing the reference bit will
4625 * result in clearing that reference bit. This
4626 * function is designed to avoid the selection of the
4627 * same 4KB page for every 2MB page mapping.
4629 * On demotion, a mapping that hasn't been referenced
4630 * is simply destroyed. To avoid the possibility of a
4631 * subsequent page fault on a demoted wired mapping,
4632 * always leave its reference bit set. Moreover,
4633 * since the superpage is wired, the current state of
4634 * its reference bit won't affect page replacement.
4636 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4637 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4638 (tpte & ATTR_SW_WIRED) == 0) {
4639 if (safe_to_clear_referenced(pmap, tpte)) {
4641 * TODO: We don't handle the access
4642 * flag at all. We need to be able
4643 * to set it in the exception handler.
4646 "safe_to_clear_referenced\n");
4647 } else if (pmap_demote_l2_locked(pmap, pte,
4648 pv->pv_va, &lock) != NULL) {
4650 va += VM_PAGE_TO_PHYS(m) -
4651 (tpte & ~ATTR_MASK);
4652 l3 = pmap_l2_to_l3(pte, va);
4653 pmap_remove_l3(pmap, l3, va,
4654 pmap_load(pte), NULL, &lock);
4660 * The superpage mapping was removed
4661 * entirely and therefore 'pv' is no
4669 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4670 ("inconsistent pv lock %p %p for page %p",
4671 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4676 /* Rotate the PV list if it has more than one entry. */
4677 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4678 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4679 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4682 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4684 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4686 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4693 if (!PMAP_TRYLOCK(pmap)) {
4694 pvh_gen = pvh->pv_gen;
4695 md_gen = m->md.pv_gen;
4699 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4704 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4705 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4707 ("pmap_ts_referenced: invalid pde level %d", lvl));
4708 tpde = pmap_load(pde);
4709 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4710 ("pmap_ts_referenced: found an invalid l2 table"));
4711 pte = pmap_l2_to_l3(pde, pv->pv_va);
4712 tpte = pmap_load(pte);
4713 if (pmap_page_dirty(tpte))
4715 if ((tpte & ATTR_AF) != 0) {
4716 if (safe_to_clear_referenced(pmap, tpte)) {
4718 * TODO: We don't handle the access flag
4719 * at all. We need to be able to set it in
4720 * the exception handler.
4722 panic("ARM64TODO: safe_to_clear_referenced\n");
4723 } else if ((tpte & ATTR_SW_WIRED) == 0) {
4725 * Wired pages cannot be paged out so
4726 * doing accessed bit emulation for
4727 * them is wasted effort. We do the
4728 * hard work for unwired pages only.
4730 pmap_remove_l3(pmap, pte, pv->pv_va, tpde,
4736 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4737 ("inconsistent pv lock %p %p for page %p",
4738 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4743 /* Rotate the PV list if it has more than one entry. */
4744 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4745 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4746 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4749 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4750 not_cleared < PMAP_TS_REFERENCED_MAX);
4753 vm_page_free_pages_toq(&free, true);
4754 return (cleared + not_cleared);
4758 * Apply the given advice to the specified range of addresses within the
4759 * given pmap. Depending on the advice, clear the referenced and/or
4760 * modified flags in each mapping and set the mapped page's dirty field.
4763 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4768 * Clear the modify bits on the specified physical page.
4771 pmap_clear_modify(vm_page_t m)
4774 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4775 ("pmap_clear_modify: page %p is not managed", m));
4776 VM_OBJECT_ASSERT_WLOCKED(m->object);
4777 KASSERT(!vm_page_xbusied(m),
4778 ("pmap_clear_modify: page %p is exclusive busied", m));
4781 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4782 * If the object containing the page is locked and the page is not
4783 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4785 if ((m->aflags & PGA_WRITEABLE) == 0)
4788 /* ARM64TODO: We lack support for tracking if a page is modified */
4792 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4794 struct pmap_preinit_mapping *ppim;
4795 vm_offset_t va, offset;
4798 int i, lvl, l2_blocks, free_l2_count, start_idx;
4800 if (!vm_initialized) {
4802 * No L3 ptables so map entire L2 blocks where start VA is:
4803 * preinit_map_va + start_idx * L2_SIZE
4804 * There may be duplicate mappings (multiple VA -> same PA) but
4805 * ARM64 dcache is always PIPT so that's acceptable.
4810 /* Calculate how many full L2 blocks are needed for the mapping */
4811 l2_blocks = (roundup2(pa + size, L2_SIZE) - rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
4813 offset = pa & L2_OFFSET;
4815 if (preinit_map_va == 0)
4818 /* Map 2MiB L2 blocks from reserved VA space */
4822 /* Find enough free contiguous VA space */
4823 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
4824 ppim = pmap_preinit_mapping + i;
4825 if (free_l2_count > 0 && ppim->pa != 0) {
4826 /* Not enough space here */
4832 if (ppim->pa == 0) {
4834 if (start_idx == -1)
4837 if (free_l2_count == l2_blocks)
4841 if (free_l2_count != l2_blocks)
4842 panic("%s: too many preinit mappings", __func__);
4844 va = preinit_map_va + (start_idx * L2_SIZE);
4845 for (i = start_idx; i < start_idx + l2_blocks; i++) {
4846 /* Mark entries as allocated */
4847 ppim = pmap_preinit_mapping + i;
4849 ppim->va = va + offset;
4854 pa = rounddown2(pa, L2_SIZE);
4855 for (i = 0; i < l2_blocks; i++) {
4856 pde = pmap_pde(kernel_pmap, va, &lvl);
4857 KASSERT(pde != NULL,
4858 ("pmap_mapbios: Invalid page entry, va: 0x%lx", va));
4859 KASSERT(lvl == 1, ("pmap_mapbios: Invalid level %d", lvl));
4861 /* Insert L2_BLOCK */
4862 l2 = pmap_l1_to_l2(pde, va);
4864 pa | ATTR_DEFAULT | ATTR_XN |
4865 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
4866 pmap_invalidate_range(kernel_pmap, va, va + L2_SIZE);
4872 va = preinit_map_va + (start_idx * L2_SIZE);
4875 /* kva_alloc may be used to map the pages */
4876 offset = pa & PAGE_MASK;
4877 size = round_page(offset + size);
4879 va = kva_alloc(size);
4881 panic("%s: Couldn't allocate KVA", __func__);
4883 pde = pmap_pde(kernel_pmap, va, &lvl);
4884 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
4886 /* L3 table is linked */
4887 va = trunc_page(va);
4888 pa = trunc_page(pa);
4889 pmap_kenter(va, size, pa, CACHED_MEMORY);
4892 return ((void *)(va + offset));
4896 pmap_unmapbios(vm_offset_t va, vm_size_t size)
4898 struct pmap_preinit_mapping *ppim;
4899 vm_offset_t offset, tmpsize, va_trunc;
4902 int i, lvl, l2_blocks, block;
4904 l2_blocks = (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
4905 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
4907 /* Remove preinit mapping */
4909 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
4910 ppim = pmap_preinit_mapping + i;
4911 if (ppim->va == va) {
4912 KASSERT(ppim->size == size, ("pmap_unmapbios: size mismatch"));
4916 offset = block * L2_SIZE;
4917 va_trunc = rounddown2(va, L2_SIZE) + offset;
4919 /* Remove L2_BLOCK */
4920 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
4921 KASSERT(pde != NULL,
4922 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va_trunc));
4923 l2 = pmap_l1_to_l2(pde, va_trunc);
4925 pmap_invalidate_range(kernel_pmap, va_trunc, va_trunc + L2_SIZE);
4927 if (block == (l2_blocks - 1))
4933 /* Unmap the pages reserved with kva_alloc. */
4934 if (vm_initialized) {
4935 offset = va & PAGE_MASK;
4936 size = round_page(offset + size);
4937 va = trunc_page(va);
4939 pde = pmap_pde(kernel_pmap, va, &lvl);
4940 KASSERT(pde != NULL,
4941 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
4942 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
4944 /* Unmap and invalidate the pages */
4945 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
4946 pmap_kremove(va + tmpsize);
4953 * Sets the memory attribute for the specified page.
4956 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4959 m->md.pv_memattr = ma;
4962 * If "m" is a normal page, update its direct mapping. This update
4963 * can be relied upon to perform any cache operations that are
4964 * required for data coherence.
4966 if ((m->flags & PG_FICTITIOUS) == 0 &&
4967 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
4968 m->md.pv_memattr) != 0)
4969 panic("memory attribute change on the direct map failed");
4973 * Changes the specified virtual address range's memory type to that given by
4974 * the parameter "mode". The specified virtual address range must be
4975 * completely contained within either the direct map or the kernel map. If
4976 * the virtual address range is contained within the kernel map, then the
4977 * memory type for each of the corresponding ranges of the direct map is also
4978 * changed. (The corresponding ranges of the direct map are those ranges that
4979 * map the same physical pages as the specified virtual address range.) These
4980 * changes to the direct map are necessary because Intel describes the
4981 * behavior of their processors as "undefined" if two or more mappings to the
4982 * same physical page have different memory types.
4984 * Returns zero if the change completed successfully, and either EINVAL or
4985 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
4986 * of the virtual address range was not mapped, and ENOMEM is returned if
4987 * there was insufficient memory available to complete the change. In the
4988 * latter case, the memory type may have been changed on some part of the
4989 * virtual address range or the direct map.
4992 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
4996 PMAP_LOCK(kernel_pmap);
4997 error = pmap_change_attr_locked(va, size, mode);
4998 PMAP_UNLOCK(kernel_pmap);
5003 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
5005 vm_offset_t base, offset, tmpva;
5006 pt_entry_t l3, *pte, *newpte;
5009 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
5010 base = trunc_page(va);
5011 offset = va & PAGE_MASK;
5012 size = round_page(offset + size);
5014 if (!VIRT_IN_DMAP(base))
5017 for (tmpva = base; tmpva < base + size; ) {
5018 pte = pmap_pte(kernel_pmap, tmpva, &lvl);
5022 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
5024 * We already have the correct attribute,
5025 * ignore this entry.
5029 panic("Invalid DMAP table level: %d\n", lvl);
5031 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
5034 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
5042 * Split the entry to an level 3 table, then
5043 * set the new attribute.
5047 panic("Invalid DMAP table level: %d\n", lvl);
5049 newpte = pmap_demote_l1(kernel_pmap, pte,
5050 tmpva & ~L1_OFFSET);
5053 pte = pmap_l1_to_l2(pte, tmpva);
5055 newpte = pmap_demote_l2(kernel_pmap, pte,
5059 pte = pmap_l2_to_l3(pte, tmpva);
5061 /* Update the entry */
5062 l3 = pmap_load(pte);
5063 l3 &= ~ATTR_IDX_MASK;
5064 l3 |= ATTR_IDX(mode);
5065 if (mode == DEVICE_MEMORY)
5068 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
5072 * If moving to a non-cacheable entry flush
5075 if (mode == VM_MEMATTR_UNCACHEABLE)
5076 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
5088 * Create an L2 table to map all addresses within an L1 mapping.
5091 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
5093 pt_entry_t *l2, newl2, oldl1;
5095 vm_paddr_t l2phys, phys;
5099 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5100 oldl1 = pmap_load(l1);
5101 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
5102 ("pmap_demote_l1: Demoting a non-block entry"));
5103 KASSERT((va & L1_OFFSET) == 0,
5104 ("pmap_demote_l1: Invalid virtual address %#lx", va));
5105 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
5106 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
5109 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
5110 tmpl1 = kva_alloc(PAGE_SIZE);
5115 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
5116 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
5117 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
5118 " in pmap %p", va, pmap);
5122 l2phys = VM_PAGE_TO_PHYS(ml2);
5123 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
5125 /* Address the range points at */
5126 phys = oldl1 & ~ATTR_MASK;
5127 /* The attributed from the old l1 table to be copied */
5128 newl2 = oldl1 & ATTR_MASK;
5130 /* Create the new entries */
5131 for (i = 0; i < Ln_ENTRIES; i++) {
5132 l2[i] = newl2 | phys;
5135 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
5136 ("Invalid l2 page (%lx != %lx)", l2[0],
5137 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
5140 pmap_kenter(tmpl1, PAGE_SIZE,
5141 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY);
5142 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
5145 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
5148 pmap_kremove(tmpl1);
5149 kva_free(tmpl1, PAGE_SIZE);
5156 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
5157 struct rwlock **lockp)
5159 struct spglist free;
5162 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
5164 vm_page_free_pages_toq(&free, true);
5168 * Create an L3 table to map all addresses within an L2 mapping.
5171 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
5172 struct rwlock **lockp)
5174 pt_entry_t *l3, newl3, oldl2;
5176 vm_paddr_t l3phys, phys;
5180 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5182 oldl2 = pmap_load(l2);
5183 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
5184 ("pmap_demote_l2: Demoting a non-block entry"));
5188 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
5189 tmpl2 = kva_alloc(PAGE_SIZE);
5195 * Invalidate the 2MB page mapping and return "failure" if the
5196 * mapping was never accessed.
5198 if ((oldl2 & ATTR_AF) == 0) {
5199 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5200 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
5201 pmap_demote_l2_abort(pmap, va, l2, lockp);
5202 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
5207 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
5208 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5209 ("pmap_demote_l2: page table page for a wired mapping"
5213 * If the page table page is missing and the mapping
5214 * is for a kernel address, the mapping must belong to
5215 * the direct map. Page table pages are preallocated
5216 * for every other part of the kernel address space,
5217 * so the direct map region is the only part of the
5218 * kernel address space that must be handled here.
5220 KASSERT(va < VM_MAXUSER_ADDRESS || VIRT_IN_DMAP(va),
5221 ("pmap_demote_l2: No saved mpte for va %#lx", va));
5224 * If the 2MB page mapping belongs to the direct map
5225 * region of the kernel's address space, then the page
5226 * allocation request specifies the highest possible
5227 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5228 * priority is normal.
5230 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
5231 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5232 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5235 * If the allocation of the new page table page fails,
5236 * invalidate the 2MB page mapping and return "failure".
5239 pmap_demote_l2_abort(pmap, va, l2, lockp);
5240 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
5241 " in pmap %p", va, pmap);
5245 if (va < VM_MAXUSER_ADDRESS) {
5246 ml3->wire_count = NL3PG;
5247 pmap_resident_count_inc(pmap, 1);
5251 l3phys = VM_PAGE_TO_PHYS(ml3);
5252 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
5254 /* Address the range points at */
5255 phys = oldl2 & ~ATTR_MASK;
5256 /* The attributed from the old l2 table to be copied */
5257 newl3 = (oldl2 & (ATTR_MASK & ~ATTR_DESCR_MASK)) | L3_PAGE;
5260 * If the page table page is not leftover from an earlier promotion,
5263 if (ml3->valid == 0) {
5264 for (i = 0; i < Ln_ENTRIES; i++) {
5265 l3[i] = newl3 | phys;
5269 KASSERT(l3[0] == ((oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE),
5270 ("Invalid l3 page (%lx != %lx)", l3[0],
5271 (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE));
5274 * Map the temporary page so we don't lose access to the l2 table.
5277 pmap_kenter(tmpl2, PAGE_SIZE,
5278 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY);
5279 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
5283 * The spare PV entries must be reserved prior to demoting the
5284 * mapping, that is, prior to changing the PDE. Otherwise, the state
5285 * of the L2 and the PV lists will be inconsistent, which can result
5286 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5287 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
5288 * PV entry for the 2MB page mapping that is being demoted.
5290 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5291 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
5294 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
5295 * the 2MB page mapping.
5297 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
5300 * Demote the PV entry.
5302 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5303 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
5305 atomic_add_long(&pmap_l2_demotions, 1);
5306 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
5307 " in pmap %p %lx", va, pmap, l3[0]);
5311 pmap_kremove(tmpl2);
5312 kva_free(tmpl2, PAGE_SIZE);
5320 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
5322 struct rwlock *lock;
5326 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
5333 * perform the pmap work for mincore
5336 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5338 pt_entry_t *pte, tpte;
5339 vm_paddr_t mask, pa;
5346 pte = pmap_pte(pmap, addr, &lvl);
5348 tpte = pmap_load(pte);
5361 panic("pmap_mincore: invalid level %d", lvl);
5364 val = MINCORE_INCORE;
5366 val |= MINCORE_SUPER;
5367 if (pmap_page_dirty(tpte))
5368 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5369 if ((tpte & ATTR_AF) == ATTR_AF)
5370 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5372 managed = (tpte & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
5373 pa = (tpte & ~ATTR_MASK) | (addr & mask);
5377 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5378 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
5379 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5380 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5383 PA_UNLOCK_COND(*locked_pa);
5390 pmap_activate(struct thread *td)
5395 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5396 td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0);
5398 "msr ttbr0_el1, %0 \n"
5400 : : "r"(td->td_proc->p_md.md_l0addr));
5401 pmap_invalidate_all(pmap);
5406 pmap_switch(struct thread *old, struct thread *new)
5408 pcpu_bp_harden bp_harden;
5411 /* Store the new curthread */
5412 PCPU_SET(curthread, new);
5414 /* And the new pcb */
5416 PCPU_SET(curpcb, pcb);
5419 * TODO: We may need to flush the cache here if switching
5420 * to a user process.
5424 old->td_proc->p_md.md_l0addr != new->td_proc->p_md.md_l0addr) {
5426 /* Switch to the new pmap */
5427 "msr ttbr0_el1, %0 \n"
5430 /* Invalidate the TLB */
5435 : : "r"(new->td_proc->p_md.md_l0addr));
5438 * Stop userspace from training the branch predictor against
5439 * other processes. This will call into a CPU specific
5440 * function that clears the branch predictor state.
5442 bp_harden = PCPU_GET(bp_harden);
5443 if (bp_harden != NULL)
5451 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
5454 if (va >= VM_MIN_KERNEL_ADDRESS) {
5455 cpu_icache_sync_range(va, sz);
5460 /* Find the length of data in this page to flush */
5461 offset = va & PAGE_MASK;
5462 len = imin(PAGE_SIZE - offset, sz);
5465 /* Extract the physical address & find it in the DMAP */
5466 pa = pmap_extract(pmap, va);
5468 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
5470 /* Move to the next page */
5473 /* Set the length for the next iteration */
5474 len = imin(PAGE_SIZE, sz);
5480 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
5486 switch (ESR_ELx_EXCEPTION(esr)) {
5487 case EXCP_INSN_ABORT_L:
5488 case EXCP_INSN_ABORT:
5489 case EXCP_DATA_ABORT_L:
5490 case EXCP_DATA_ABORT:
5493 return (KERN_FAILURE);
5496 /* Data and insn aborts use same encoding for FCS field. */
5497 switch (esr & ISS_DATA_DFSC_MASK) {
5498 case ISS_DATA_DFSC_TF_L0:
5499 case ISS_DATA_DFSC_TF_L1:
5500 case ISS_DATA_DFSC_TF_L2:
5501 case ISS_DATA_DFSC_TF_L3:
5503 /* Ask the MMU to check the address */
5504 intr = intr_disable();
5505 if (pmap == kernel_pmap)
5506 par = arm64_address_translate_s1e1r(far);
5508 par = arm64_address_translate_s1e0r(far);
5513 * If the translation was successful the address was invalid
5514 * due to a break-before-make sequence. We can unlock and
5515 * return success to the trap handler.
5517 if (PAR_SUCCESS(par))
5518 return (KERN_SUCCESS);
5525 return (KERN_FAILURE);
5529 * Increase the starting virtual address of the given mapping if a
5530 * different alignment might result in more superpage mappings.
5533 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5534 vm_offset_t *addr, vm_size_t size)
5536 vm_offset_t superpage_offset;
5540 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5541 offset += ptoa(object->pg_color);
5542 superpage_offset = offset & L2_OFFSET;
5543 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
5544 (*addr & L2_OFFSET) == superpage_offset)
5546 if ((*addr & L2_OFFSET) < superpage_offset)
5547 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
5549 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
5553 * Get the kernel virtual address of a set of physical pages. If there are
5554 * physical addresses not covered by the DMAP perform a transient mapping
5555 * that will be removed when calling pmap_unmap_io_transient.
5557 * \param page The pages the caller wishes to obtain the virtual
5558 * address on the kernel memory map.
5559 * \param vaddr On return contains the kernel virtual memory address
5560 * of the pages passed in the page parameter.
5561 * \param count Number of pages passed in.
5562 * \param can_fault TRUE if the thread using the mapped pages can take
5563 * page faults, FALSE otherwise.
5565 * \returns TRUE if the caller must call pmap_unmap_io_transient when
5566 * finished or FALSE otherwise.
5570 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
5571 boolean_t can_fault)
5574 boolean_t needs_mapping;
5578 * Allocate any KVA space that we need, this is done in a separate
5579 * loop to prevent calling vmem_alloc while pinned.
5581 needs_mapping = FALSE;
5582 for (i = 0; i < count; i++) {
5583 paddr = VM_PAGE_TO_PHYS(page[i]);
5584 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
5585 error = vmem_alloc(kernel_arena, PAGE_SIZE,
5586 M_BESTFIT | M_WAITOK, &vaddr[i]);
5587 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
5588 needs_mapping = TRUE;
5590 vaddr[i] = PHYS_TO_DMAP(paddr);
5594 /* Exit early if everything is covered by the DMAP */
5600 for (i = 0; i < count; i++) {
5601 paddr = VM_PAGE_TO_PHYS(page[i]);
5602 if (!PHYS_IN_DMAP(paddr)) {
5604 "pmap_map_io_transient: TODO: Map out of DMAP data");
5608 return (needs_mapping);
5612 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
5613 boolean_t can_fault)
5620 for (i = 0; i < count; i++) {
5621 paddr = VM_PAGE_TO_PHYS(page[i]);
5622 if (!PHYS_IN_DMAP(paddr)) {
5623 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
5629 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
5632 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);