2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/limits.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sbuf.h>
126 #include <sys/vmem.h>
127 #include <sys/vmmeter.h>
128 #include <sys/sched.h>
129 #include <sys/sysctl.h>
130 #include <sys/_unrhdr.h>
134 #include <vm/vm_param.h>
135 #include <vm/vm_kern.h>
136 #include <vm/vm_page.h>
137 #include <vm/vm_map.h>
138 #include <vm/vm_object.h>
139 #include <vm/vm_extern.h>
140 #include <vm/vm_pageout.h>
141 #include <vm/vm_pager.h>
142 #include <vm/vm_phys.h>
143 #include <vm/vm_radix.h>
144 #include <vm/vm_reserv.h>
147 #include <machine/machdep.h>
148 #include <machine/md_var.h>
149 #include <machine/pcb.h>
151 #include <arm/include/physmem.h>
153 #define PMAP_ASSERT_STAGE1(pmap) MPASS((pmap)->pm_stage == PM_STAGE1)
155 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
156 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
157 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
158 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
160 #define NUL0E L0_ENTRIES
161 #define NUL1E (NUL0E * NL1PG)
162 #define NUL2E (NUL1E * NL2PG)
164 #if !defined(DIAGNOSTIC)
165 #ifdef __GNUC_GNU_INLINE__
166 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
168 #define PMAP_INLINE extern inline
175 #define PV_STAT(x) do { x ; } while (0)
177 #define PV_STAT(x) do { } while (0)
180 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
181 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
183 #define NPV_LIST_LOCKS MAXCPU
185 #define PHYS_TO_PV_LIST_LOCK(pa) \
186 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
188 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
189 struct rwlock **_lockp = (lockp); \
190 struct rwlock *_new_lock; \
192 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
193 if (_new_lock != *_lockp) { \
194 if (*_lockp != NULL) \
195 rw_wunlock(*_lockp); \
196 *_lockp = _new_lock; \
201 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
202 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
204 #define RELEASE_PV_LIST_LOCK(lockp) do { \
205 struct rwlock **_lockp = (lockp); \
207 if (*_lockp != NULL) { \
208 rw_wunlock(*_lockp); \
213 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
214 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
217 * The presence of this flag indicates that the mapping is writeable.
218 * If the ATTR_S1_AP_RO bit is also set, then the mapping is clean, otherwise
219 * it is dirty. This flag may only be set on managed mappings.
221 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
222 * as a software managed bit.
224 #define ATTR_SW_DBM ATTR_DBM
226 struct pmap kernel_pmap_store;
228 /* Used for mapping ACPI memory before VM is initialized */
229 #define PMAP_PREINIT_MAPPING_COUNT 32
230 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
231 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
232 static int vm_initialized = 0; /* No need to use pre-init maps when set */
235 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
236 * Always map entire L2 block for simplicity.
237 * VA of L2 block = preinit_map_va + i * L2_SIZE
239 static struct pmap_preinit_mapping {
243 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
245 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
246 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
247 vm_offset_t kernel_vm_end = 0;
250 * Data for the pv entry allocation mechanism.
252 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
253 static struct mtx pv_chunks_mutex;
254 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
255 static struct md_page *pv_table;
256 static struct md_page pv_dummy;
258 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
259 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
260 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
262 /* This code assumes all L1 DMAP entries will be used */
263 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
264 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
266 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
267 extern pt_entry_t pagetable_dmap[];
269 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
270 static vm_paddr_t physmap[PHYSMAP_SIZE];
271 static u_int physmap_idx;
273 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
276 * This ASID allocator uses a bit vector ("asid_set") to remember which ASIDs
277 * that it has currently allocated to a pmap, a cursor ("asid_next") to
278 * optimize its search for a free ASID in the bit vector, and an epoch number
279 * ("asid_epoch") to indicate when it has reclaimed all previously allocated
280 * ASIDs that are not currently active on a processor.
282 * The current epoch number is always in the range [0, INT_MAX). Negative
283 * numbers and INT_MAX are reserved for special cases that are described
286 static SYSCTL_NODE(_vm_pmap, OID_AUTO, asid, CTLFLAG_RD, 0, "ASID allocator");
287 static int asid_bits;
288 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, bits, CTLFLAG_RD, &asid_bits, 0,
289 "The number of bits in an ASID");
290 static bitstr_t *asid_set;
291 static int asid_set_size;
292 static int asid_next;
293 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, next, CTLFLAG_RD, &asid_next, 0,
294 "The last allocated ASID plus one");
295 static int asid_epoch;
296 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, epoch, CTLFLAG_RD, &asid_epoch, 0,
297 "The current epoch number");
298 static struct mtx asid_set_mutex;
301 * A pmap's cookie encodes an ASID and epoch number. Cookies for reserved
302 * ASIDs have a negative epoch number, specifically, INT_MIN. Cookies for
303 * dynamically allocated ASIDs have a non-negative epoch number.
305 * An invalid ASID is represented by -1.
307 * There are two special-case cookie values: (1) COOKIE_FROM(-1, INT_MIN),
308 * which indicates that an ASID should never be allocated to the pmap, and
309 * (2) COOKIE_FROM(-1, INT_MAX), which indicates that an ASID should be
310 * allocated when the pmap is next activated.
312 #define COOKIE_FROM(asid, epoch) ((long)((u_int)(asid) | \
313 ((u_long)(epoch) << 32)))
314 #define COOKIE_TO_ASID(cookie) ((int)(cookie))
315 #define COOKIE_TO_EPOCH(cookie) ((int)((u_long)(cookie) >> 32))
317 static int superpages_enabled = 1;
318 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
319 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
320 "Are large page mappings enabled?");
323 * Internal flags for pmap_enter()'s helper functions.
325 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
326 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
328 static void free_pv_chunk(struct pv_chunk *pc);
329 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
330 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
331 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
332 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
333 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
336 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
337 static bool pmap_activate_int(pmap_t pmap);
338 static void pmap_alloc_asid(pmap_t pmap);
339 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
340 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
341 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
342 vm_offset_t va, struct rwlock **lockp);
343 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
344 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
345 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
346 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
347 u_int flags, vm_page_t m, struct rwlock **lockp);
348 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
349 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
350 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
351 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
352 static void pmap_reset_asid_set(void);
353 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
354 vm_page_t m, struct rwlock **lockp);
356 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
357 struct rwlock **lockp);
359 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
360 struct spglist *free);
361 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
362 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
365 * These load the old table data and store the new value.
366 * They need to be atomic as the System MMU may write to the table at
367 * the same time as the CPU.
369 #define pmap_clear(table) atomic_store_64(table, 0)
370 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
371 #define pmap_load(table) (*table)
372 #define pmap_load_clear(table) atomic_swap_64(table, 0)
373 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
374 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
375 #define pmap_store(table, entry) atomic_store_64(table, entry)
377 /********************/
378 /* Inline functions */
379 /********************/
382 pagecopy(void *s, void *d)
385 memcpy(d, s, PAGE_SIZE);
388 static __inline pd_entry_t *
389 pmap_l0(pmap_t pmap, vm_offset_t va)
392 return (&pmap->pm_l0[pmap_l0_index(va)]);
395 static __inline pd_entry_t *
396 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
400 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
401 return (&l1[pmap_l1_index(va)]);
404 static __inline pd_entry_t *
405 pmap_l1(pmap_t pmap, vm_offset_t va)
409 l0 = pmap_l0(pmap, va);
410 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
413 return (pmap_l0_to_l1(l0, va));
416 static __inline pd_entry_t *
417 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
421 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
422 return (&l2[pmap_l2_index(va)]);
425 static __inline pd_entry_t *
426 pmap_l2(pmap_t pmap, vm_offset_t va)
430 l1 = pmap_l1(pmap, va);
431 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
434 return (pmap_l1_to_l2(l1, va));
437 static __inline pt_entry_t *
438 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
442 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
443 return (&l3[pmap_l3_index(va)]);
447 * Returns the lowest valid pde for a given virtual address.
448 * The next level may or may not point to a valid page or block.
450 static __inline pd_entry_t *
451 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
453 pd_entry_t *l0, *l1, *l2, desc;
455 l0 = pmap_l0(pmap, va);
456 desc = pmap_load(l0) & ATTR_DESCR_MASK;
457 if (desc != L0_TABLE) {
462 l1 = pmap_l0_to_l1(l0, va);
463 desc = pmap_load(l1) & ATTR_DESCR_MASK;
464 if (desc != L1_TABLE) {
469 l2 = pmap_l1_to_l2(l1, va);
470 desc = pmap_load(l2) & ATTR_DESCR_MASK;
471 if (desc != L2_TABLE) {
481 * Returns the lowest valid pte block or table entry for a given virtual
482 * address. If there are no valid entries return NULL and set the level to
483 * the first invalid level.
485 static __inline pt_entry_t *
486 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
488 pd_entry_t *l1, *l2, desc;
491 l1 = pmap_l1(pmap, va);
496 desc = pmap_load(l1) & ATTR_DESCR_MASK;
497 if (desc == L1_BLOCK) {
502 if (desc != L1_TABLE) {
507 l2 = pmap_l1_to_l2(l1, va);
508 desc = pmap_load(l2) & ATTR_DESCR_MASK;
509 if (desc == L2_BLOCK) {
514 if (desc != L2_TABLE) {
520 l3 = pmap_l2_to_l3(l2, va);
521 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
528 pmap_ps_enabled(pmap_t pmap __unused)
531 return (superpages_enabled != 0);
535 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
536 pd_entry_t **l2, pt_entry_t **l3)
538 pd_entry_t *l0p, *l1p, *l2p;
540 if (pmap->pm_l0 == NULL)
543 l0p = pmap_l0(pmap, va);
546 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
549 l1p = pmap_l0_to_l1(l0p, va);
552 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
558 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
561 l2p = pmap_l1_to_l2(l1p, va);
564 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
569 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
572 *l3 = pmap_l2_to_l3(l2p, va);
578 pmap_l3_valid(pt_entry_t l3)
581 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
585 CTASSERT(L1_BLOCK == L2_BLOCK);
588 * Checks if the PTE is dirty.
591 pmap_pte_dirty(pmap_t pmap, pt_entry_t pte)
594 PMAP_ASSERT_STAGE1(pmap);
595 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
596 KASSERT((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) != 0,
597 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
599 return ((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
600 (ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_SW_DBM));
604 pmap_resident_count_inc(pmap_t pmap, int count)
607 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
608 pmap->pm_stats.resident_count += count;
612 pmap_resident_count_dec(pmap_t pmap, int count)
615 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
616 KASSERT(pmap->pm_stats.resident_count >= count,
617 ("pmap %p resident count underflow %ld %d", pmap,
618 pmap->pm_stats.resident_count, count));
619 pmap->pm_stats.resident_count -= count;
623 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
629 l1 = (pd_entry_t *)l1pt;
630 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
632 /* Check locore has used a table L1 map */
633 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
634 ("Invalid bootstrap L1 table"));
635 /* Find the address of the L2 table */
636 l2 = (pt_entry_t *)init_pt_va;
637 *l2_slot = pmap_l2_index(va);
643 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
645 u_int l1_slot, l2_slot;
648 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
650 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
654 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
655 vm_offset_t freemempos)
659 vm_paddr_t l2_pa, pa;
660 u_int l1_slot, l2_slot, prev_l1_slot;
663 dmap_phys_base = min_pa & ~L1_OFFSET;
669 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
670 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
672 for (i = 0; i < (physmap_idx * 2); i += 2) {
673 pa = physmap[i] & ~L2_OFFSET;
674 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
676 /* Create L2 mappings at the start of the region */
677 if ((pa & L1_OFFSET) != 0) {
678 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
679 if (l1_slot != prev_l1_slot) {
680 prev_l1_slot = l1_slot;
681 l2 = (pt_entry_t *)freemempos;
682 l2_pa = pmap_early_vtophys(kern_l1,
684 freemempos += PAGE_SIZE;
686 pmap_store(&pagetable_dmap[l1_slot],
687 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
689 memset(l2, 0, PAGE_SIZE);
692 ("pmap_bootstrap_dmap: NULL l2 map"));
693 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
694 pa += L2_SIZE, va += L2_SIZE) {
696 * We are on a boundary, stop to
697 * create a level 1 block
699 if ((pa & L1_OFFSET) == 0)
702 l2_slot = pmap_l2_index(va);
703 KASSERT(l2_slot != 0, ("..."));
704 pmap_store(&l2[l2_slot],
705 (pa & ~L2_OFFSET) | ATTR_DEFAULT |
707 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
710 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
714 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
715 (physmap[i + 1] - pa) >= L1_SIZE;
716 pa += L1_SIZE, va += L1_SIZE) {
717 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
718 pmap_store(&pagetable_dmap[l1_slot],
719 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_S1_XN |
720 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L1_BLOCK);
723 /* Create L2 mappings at the end of the region */
724 if (pa < physmap[i + 1]) {
725 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
726 if (l1_slot != prev_l1_slot) {
727 prev_l1_slot = l1_slot;
728 l2 = (pt_entry_t *)freemempos;
729 l2_pa = pmap_early_vtophys(kern_l1,
731 freemempos += PAGE_SIZE;
733 pmap_store(&pagetable_dmap[l1_slot],
734 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
736 memset(l2, 0, PAGE_SIZE);
739 ("pmap_bootstrap_dmap: NULL l2 map"));
740 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
741 pa += L2_SIZE, va += L2_SIZE) {
742 l2_slot = pmap_l2_index(va);
743 pmap_store(&l2[l2_slot],
744 (pa & ~L2_OFFSET) | ATTR_DEFAULT |
746 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
751 if (pa > dmap_phys_max) {
763 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
770 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
772 l1 = (pd_entry_t *)l1pt;
773 l1_slot = pmap_l1_index(va);
776 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
777 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
779 pa = pmap_early_vtophys(l1pt, l2pt);
780 pmap_store(&l1[l1_slot],
781 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
785 /* Clean the L2 page table */
786 memset((void *)l2_start, 0, l2pt - l2_start);
792 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
799 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
801 l2 = pmap_l2(kernel_pmap, va);
802 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
803 l2_slot = pmap_l2_index(va);
806 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
807 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
809 pa = pmap_early_vtophys(l1pt, l3pt);
810 pmap_store(&l2[l2_slot],
811 (pa & ~Ln_TABLE_MASK) | ATTR_S1_UXN | L2_TABLE);
815 /* Clean the L2 page table */
816 memset((void *)l3_start, 0, l3pt - l3_start);
822 * Bootstrap the system enough to run with virtual memory.
825 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
828 u_int l1_slot, l2_slot;
830 vm_offset_t va, freemempos;
831 vm_offset_t dpcpu, msgbufpv;
832 vm_paddr_t start_pa, pa, min_pa;
836 /* Verify that the ASID is set through TTBR0. */
837 KASSERT((READ_SPECIALREG(tcr_el1) & TCR_A1) == 0,
838 ("pmap_bootstrap: TCR_EL1.A1 != 0"));
840 kern_delta = KERNBASE - kernstart;
842 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
843 printf("%lx\n", l1pt);
844 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
846 /* Set this early so we can use the pagetable walking functions */
847 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
848 PMAP_LOCK_INIT(kernel_pmap);
849 kernel_pmap->pm_l0_paddr = l0pt - kern_delta;
850 kernel_pmap->pm_cookie = COOKIE_FROM(-1, INT_MIN);
851 kernel_pmap->pm_stage = PM_STAGE1;
853 /* Assume the address we were loaded to is a valid physical address */
854 min_pa = KERNBASE - kern_delta;
856 physmap_idx = arm_physmem_avail(physmap, nitems(physmap));
860 * Find the minimum physical address. physmap is sorted,
861 * but may contain empty ranges.
863 for (i = 0; i < (physmap_idx * 2); i += 2) {
864 if (physmap[i] == physmap[i + 1])
866 if (physmap[i] <= min_pa)
870 freemempos = KERNBASE + kernlen;
871 freemempos = roundup2(freemempos, PAGE_SIZE);
873 /* Create a direct map region early so we can use it for pa -> va */
874 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
877 start_pa = pa = KERNBASE - kern_delta;
880 * Read the page table to find out what is already mapped.
881 * This assumes we have mapped a block of memory from KERNBASE
882 * using a single L1 entry.
884 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
886 /* Sanity check the index, KERNBASE should be the first VA */
887 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
889 /* Find how many pages we have mapped */
890 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
891 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
894 /* Check locore used L2 blocks */
895 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
896 ("Invalid bootstrap L2 table"));
897 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
898 ("Incorrect PA in L2 table"));
904 va = roundup2(va, L1_SIZE);
906 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
907 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
908 /* And the l3 tables for the early devmap */
909 freemempos = pmap_bootstrap_l3(l1pt,
910 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
914 #define alloc_pages(var, np) \
915 (var) = freemempos; \
916 freemempos += (np * PAGE_SIZE); \
917 memset((char *)(var), 0, ((np) * PAGE_SIZE));
919 /* Allocate dynamic per-cpu area. */
920 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
921 dpcpu_init((void *)dpcpu, 0);
923 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
924 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
925 msgbufp = (void *)msgbufpv;
927 /* Reserve some VA space for early BIOS/ACPI mapping */
928 preinit_map_va = roundup2(freemempos, L2_SIZE);
930 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
931 virtual_avail = roundup2(virtual_avail, L1_SIZE);
932 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
933 kernel_vm_end = virtual_avail;
935 pa = pmap_early_vtophys(l1pt, freemempos);
937 arm_physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
943 * Initialize a vm_page's machine-dependent fields.
946 pmap_page_init(vm_page_t m)
949 TAILQ_INIT(&m->md.pv_list);
950 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
954 * Initialize the pmap module.
955 * Called by vm_init, to initialize any structures that the pmap
956 * system needs to map virtual memory.
965 * Determine whether an ASID is 8 or 16 bits in size.
967 asid_bits = (READ_SPECIALREG(tcr_el1) & TCR_ASID_16) != 0 ? 16 : 8;
970 * Are large page mappings enabled?
972 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
973 if (superpages_enabled) {
974 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
975 ("pmap_init: can't assign to pagesizes[1]"));
976 pagesizes[1] = L2_SIZE;
980 * Initialize the ASID allocator. At this point, we are still too
981 * early in the overall initialization process to use bit_alloc().
983 asid_set_size = 1 << asid_bits;
984 asid_set = (bitstr_t *)kmem_malloc(bitstr_size(asid_set_size),
986 for (i = 0; i < ASID_FIRST_AVAILABLE; i++)
987 bit_set(asid_set, i);
988 asid_next = ASID_FIRST_AVAILABLE;
989 mtx_init(&asid_set_mutex, "asid set", NULL, MTX_SPIN);
992 * Initialize the pv chunk list mutex.
994 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
997 * Initialize the pool of pv list locks.
999 for (i = 0; i < NPV_LIST_LOCKS; i++)
1000 rw_init(&pv_list_locks[i], "pmap pv list");
1003 * Calculate the size of the pv head table for superpages.
1005 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
1008 * Allocate memory for the pv head table for superpages.
1010 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1012 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1013 for (i = 0; i < pv_npg; i++)
1014 TAILQ_INIT(&pv_table[i].pv_list);
1015 TAILQ_INIT(&pv_dummy.pv_list);
1020 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
1021 "2MB page mapping counters");
1023 static u_long pmap_l2_demotions;
1024 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
1025 &pmap_l2_demotions, 0, "2MB page demotions");
1027 static u_long pmap_l2_mappings;
1028 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
1029 &pmap_l2_mappings, 0, "2MB page mappings");
1031 static u_long pmap_l2_p_failures;
1032 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
1033 &pmap_l2_p_failures, 0, "2MB page promotion failures");
1035 static u_long pmap_l2_promotions;
1036 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
1037 &pmap_l2_promotions, 0, "2MB page promotions");
1040 * Invalidate a single TLB entry.
1042 static __inline void
1043 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1047 PMAP_ASSERT_STAGE1(pmap);
1050 if (pmap == kernel_pmap) {
1052 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1054 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) | atop(va);
1055 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1061 static __inline void
1062 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1064 uint64_t end, r, start;
1066 PMAP_ASSERT_STAGE1(pmap);
1069 if (pmap == kernel_pmap) {
1072 for (r = start; r < end; r++)
1073 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1075 start = end = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1078 for (r = start; r < end; r++)
1079 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1085 static __inline void
1086 pmap_invalidate_all(pmap_t pmap)
1090 PMAP_ASSERT_STAGE1(pmap);
1093 if (pmap == kernel_pmap) {
1094 __asm __volatile("tlbi vmalle1is");
1096 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1097 __asm __volatile("tlbi aside1is, %0" : : "r" (r));
1104 * Routine: pmap_extract
1106 * Extract the physical page address associated
1107 * with the given map/virtual_address pair.
1110 pmap_extract(pmap_t pmap, vm_offset_t va)
1112 pt_entry_t *pte, tpte;
1119 * Find the block or page map for this virtual address. pmap_pte
1120 * will return either a valid block/page entry, or NULL.
1122 pte = pmap_pte(pmap, va, &lvl);
1124 tpte = pmap_load(pte);
1125 pa = tpte & ~ATTR_MASK;
1128 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1129 ("pmap_extract: Invalid L1 pte found: %lx",
1130 tpte & ATTR_DESCR_MASK));
1131 pa |= (va & L1_OFFSET);
1134 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1135 ("pmap_extract: Invalid L2 pte found: %lx",
1136 tpte & ATTR_DESCR_MASK));
1137 pa |= (va & L2_OFFSET);
1140 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1141 ("pmap_extract: Invalid L3 pte found: %lx",
1142 tpte & ATTR_DESCR_MASK));
1143 pa |= (va & L3_OFFSET);
1152 * Routine: pmap_extract_and_hold
1154 * Atomically extract and hold the physical page
1155 * with the given pmap and virtual address pair
1156 * if that mapping permits the given protection.
1159 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1161 pt_entry_t *pte, tpte;
1166 PMAP_ASSERT_STAGE1(pmap);
1170 pte = pmap_pte(pmap, va, &lvl);
1172 tpte = pmap_load(pte);
1174 KASSERT(lvl > 0 && lvl <= 3,
1175 ("pmap_extract_and_hold: Invalid level %d", lvl));
1176 CTASSERT(L1_BLOCK == L2_BLOCK);
1177 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1178 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1179 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1180 tpte & ATTR_DESCR_MASK));
1181 if (((tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW)) ||
1182 ((prot & VM_PROT_WRITE) == 0)) {
1185 off = va & L1_OFFSET;
1188 off = va & L2_OFFSET;
1194 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1195 if (!vm_page_wire_mapped(m))
1204 pmap_kextract(vm_offset_t va)
1206 pt_entry_t *pte, tpte;
1208 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
1209 return (DMAP_TO_PHYS(va));
1210 pte = pmap_l1(kernel_pmap, va);
1215 * A concurrent pmap_update_entry() will clear the entry's valid bit
1216 * but leave the rest of the entry unchanged. Therefore, we treat a
1217 * non-zero entry as being valid, and we ignore the valid bit when
1218 * determining whether the entry maps a block, page, or table.
1220 tpte = pmap_load(pte);
1223 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1224 return ((tpte & ~ATTR_MASK) | (va & L1_OFFSET));
1225 pte = pmap_l1_to_l2(&tpte, va);
1226 tpte = pmap_load(pte);
1229 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1230 return ((tpte & ~ATTR_MASK) | (va & L2_OFFSET));
1231 pte = pmap_l2_to_l3(&tpte, va);
1232 tpte = pmap_load(pte);
1235 return ((tpte & ~ATTR_MASK) | (va & L3_OFFSET));
1238 /***************************************************
1239 * Low level mapping routines.....
1240 ***************************************************/
1243 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1246 pt_entry_t *pte, attr;
1250 KASSERT((pa & L3_OFFSET) == 0,
1251 ("pmap_kenter: Invalid physical address"));
1252 KASSERT((sva & L3_OFFSET) == 0,
1253 ("pmap_kenter: Invalid virtual address"));
1254 KASSERT((size & PAGE_MASK) == 0,
1255 ("pmap_kenter: Mapping is not page-sized"));
1257 attr = ATTR_DEFAULT | ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1258 ATTR_S1_IDX(mode) | L3_PAGE;
1261 pde = pmap_pde(kernel_pmap, va, &lvl);
1262 KASSERT(pde != NULL,
1263 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1264 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1266 pte = pmap_l2_to_l3(pde, va);
1267 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1273 pmap_invalidate_range(kernel_pmap, sva, va);
1277 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1280 pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
1284 * Remove a page from the kernel pagetables.
1287 pmap_kremove(vm_offset_t va)
1292 pte = pmap_pte(kernel_pmap, va, &lvl);
1293 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1294 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1297 pmap_invalidate_page(kernel_pmap, va);
1301 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1307 KASSERT((sva & L3_OFFSET) == 0,
1308 ("pmap_kremove_device: Invalid virtual address"));
1309 KASSERT((size & PAGE_MASK) == 0,
1310 ("pmap_kremove_device: Mapping is not page-sized"));
1314 pte = pmap_pte(kernel_pmap, va, &lvl);
1315 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1317 ("Invalid device pagetable level: %d != 3", lvl));
1323 pmap_invalidate_range(kernel_pmap, sva, va);
1327 * Used to map a range of physical addresses into kernel
1328 * virtual address space.
1330 * The value passed in '*virt' is a suggested virtual address for
1331 * the mapping. Architectures which can support a direct-mapped
1332 * physical to virtual region can return the appropriate address
1333 * within that region, leaving '*virt' unchanged. Other
1334 * architectures should map the pages starting at '*virt' and
1335 * update '*virt' with the first usable address after the mapped
1339 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1341 return PHYS_TO_DMAP(start);
1346 * Add a list of wired pages to the kva
1347 * this routine is only used for temporary
1348 * kernel mappings that do not need to have
1349 * page modification or references recorded.
1350 * Note that old mappings are simply written
1351 * over. The page *must* be wired.
1352 * Note: SMP coherent. Uses a ranged shootdown IPI.
1355 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1358 pt_entry_t *pte, pa;
1364 for (i = 0; i < count; i++) {
1365 pde = pmap_pde(kernel_pmap, va, &lvl);
1366 KASSERT(pde != NULL,
1367 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1369 ("pmap_qenter: Invalid level %d", lvl));
1372 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
1373 ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1374 ATTR_S1_IDX(m->md.pv_memattr) | L3_PAGE;
1375 pte = pmap_l2_to_l3(pde, va);
1376 pmap_load_store(pte, pa);
1380 pmap_invalidate_range(kernel_pmap, sva, va);
1384 * This routine tears out page mappings from the
1385 * kernel -- it is meant only for temporary mappings.
1388 pmap_qremove(vm_offset_t sva, int count)
1394 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1397 while (count-- > 0) {
1398 pte = pmap_pte(kernel_pmap, va, &lvl);
1400 ("Invalid device pagetable level: %d != 3", lvl));
1407 pmap_invalidate_range(kernel_pmap, sva, va);
1410 /***************************************************
1411 * Page table page management routines.....
1412 ***************************************************/
1414 * Schedule the specified unused page table page to be freed. Specifically,
1415 * add the page to the specified list of pages that will be released to the
1416 * physical memory manager after the TLB has been updated.
1418 static __inline void
1419 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1420 boolean_t set_PG_ZERO)
1424 m->flags |= PG_ZERO;
1426 m->flags &= ~PG_ZERO;
1427 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1431 * Decrements a page table page's reference count, which is used to record the
1432 * number of valid page table entries within the page. If the reference count
1433 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1434 * page table page was unmapped and FALSE otherwise.
1436 static inline boolean_t
1437 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1441 if (m->ref_count == 0) {
1442 _pmap_unwire_l3(pmap, va, m, free);
1449 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1452 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1454 * unmap the page table page
1456 if (m->pindex >= (NUL2E + NUL1E)) {
1460 l0 = pmap_l0(pmap, va);
1462 } else if (m->pindex >= NUL2E) {
1466 l1 = pmap_l1(pmap, va);
1472 l2 = pmap_l2(pmap, va);
1475 pmap_resident_count_dec(pmap, 1);
1476 if (m->pindex < NUL2E) {
1477 /* We just released an l3, unhold the matching l2 */
1478 pd_entry_t *l1, tl1;
1481 l1 = pmap_l1(pmap, va);
1482 tl1 = pmap_load(l1);
1483 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1484 pmap_unwire_l3(pmap, va, l2pg, free);
1485 } else if (m->pindex < (NUL2E + NUL1E)) {
1486 /* We just released an l2, unhold the matching l1 */
1487 pd_entry_t *l0, tl0;
1490 l0 = pmap_l0(pmap, va);
1491 tl0 = pmap_load(l0);
1492 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1493 pmap_unwire_l3(pmap, va, l1pg, free);
1495 pmap_invalidate_page(pmap, va);
1498 * Put page on a list so that it is released after
1499 * *ALL* TLB shootdown is done
1501 pmap_add_delayed_free_list(m, free, TRUE);
1505 * After removing a page table entry, this routine is used to
1506 * conditionally free the page, and manage the reference count.
1509 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1510 struct spglist *free)
1514 if (va >= VM_MAXUSER_ADDRESS)
1516 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1517 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1518 return (pmap_unwire_l3(pmap, va, mpte, free));
1522 * Release a page table page reference after a failed attempt to create a
1526 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
1528 struct spglist free;
1531 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
1533 * Although "va" was never mapped, the TLB could nonetheless
1534 * have intermediate entries that refer to the freed page
1535 * table pages. Invalidate those entries.
1537 * XXX redundant invalidation (See _pmap_unwire_l3().)
1539 pmap_invalidate_page(pmap, va);
1540 vm_page_free_pages_toq(&free, true);
1545 pmap_pinit0(pmap_t pmap)
1548 PMAP_LOCK_INIT(pmap);
1549 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1550 pmap->pm_l0_paddr = READ_SPECIALREG(ttbr0_el1);
1551 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1552 pmap->pm_root.rt_root = 0;
1553 pmap->pm_cookie = COOKIE_FROM(ASID_RESERVED_FOR_PID_0, INT_MIN);
1554 pmap->pm_stage = PM_STAGE1;
1556 PCPU_SET(curpmap, pmap);
1560 pmap_pinit(pmap_t pmap)
1565 * allocate the l0 page
1567 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1568 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1571 pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(l0pt);
1572 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1574 if ((l0pt->flags & PG_ZERO) == 0)
1575 pagezero(pmap->pm_l0);
1577 pmap->pm_root.rt_root = 0;
1578 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1579 pmap->pm_cookie = COOKIE_FROM(-1, INT_MAX);
1580 pmap->pm_stage = PM_STAGE1;
1581 /* XXX Temporarily disable deferred ASID allocation. */
1582 pmap_alloc_asid(pmap);
1588 * This routine is called if the desired page table page does not exist.
1590 * If page table page allocation fails, this routine may sleep before
1591 * returning NULL. It sleeps only if a lock pointer was given.
1593 * Note: If a page allocation fails at page table level two or three,
1594 * one or two pages may be held during the wait, only to be released
1595 * afterwards. This conservative approach is easily argued to avoid
1599 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1601 vm_page_t m, l1pg, l2pg;
1603 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1606 * Allocate a page table page.
1608 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1609 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1610 if (lockp != NULL) {
1611 RELEASE_PV_LIST_LOCK(lockp);
1618 * Indicate the need to retry. While waiting, the page table
1619 * page may have been allocated.
1623 if ((m->flags & PG_ZERO) == 0)
1627 * Because of AArch64's weak memory consistency model, we must have a
1628 * barrier here to ensure that the stores for zeroing "m", whether by
1629 * pmap_zero_page() or an earlier function, are visible before adding
1630 * "m" to the page table. Otherwise, a page table walk by another
1631 * processor's MMU could see the mapping to "m" and a stale, non-zero
1637 * Map the pagetable page into the process address space, if
1638 * it isn't already there.
1641 if (ptepindex >= (NUL2E + NUL1E)) {
1643 vm_pindex_t l0index;
1645 l0index = ptepindex - (NUL2E + NUL1E);
1646 l0 = &pmap->pm_l0[l0index];
1647 pmap_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1648 } else if (ptepindex >= NUL2E) {
1649 vm_pindex_t l0index, l1index;
1650 pd_entry_t *l0, *l1;
1653 l1index = ptepindex - NUL2E;
1654 l0index = l1index >> L0_ENTRIES_SHIFT;
1656 l0 = &pmap->pm_l0[l0index];
1657 tl0 = pmap_load(l0);
1659 /* recurse for allocating page dir */
1660 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1662 vm_page_unwire_noq(m);
1663 vm_page_free_zero(m);
1667 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1671 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1672 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1673 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1675 vm_pindex_t l0index, l1index;
1676 pd_entry_t *l0, *l1, *l2;
1677 pd_entry_t tl0, tl1;
1679 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1680 l0index = l1index >> L0_ENTRIES_SHIFT;
1682 l0 = &pmap->pm_l0[l0index];
1683 tl0 = pmap_load(l0);
1685 /* recurse for allocating page dir */
1686 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1688 vm_page_unwire_noq(m);
1689 vm_page_free_zero(m);
1692 tl0 = pmap_load(l0);
1693 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1694 l1 = &l1[l1index & Ln_ADDR_MASK];
1696 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1697 l1 = &l1[l1index & Ln_ADDR_MASK];
1698 tl1 = pmap_load(l1);
1700 /* recurse for allocating page dir */
1701 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1703 vm_page_unwire_noq(m);
1704 vm_page_free_zero(m);
1708 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1713 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1714 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1715 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1718 pmap_resident_count_inc(pmap, 1);
1724 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, vm_page_t *l2pgp,
1725 struct rwlock **lockp)
1727 pd_entry_t *l1, *l2;
1729 vm_pindex_t l2pindex;
1732 l1 = pmap_l1(pmap, va);
1733 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1734 l2 = pmap_l1_to_l2(l1, va);
1735 if (va < VM_MAXUSER_ADDRESS) {
1736 /* Add a reference to the L2 page. */
1737 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1741 } else if (va < VM_MAXUSER_ADDRESS) {
1742 /* Allocate a L2 page. */
1743 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1744 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1751 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
1752 l2 = &l2[pmap_l2_index(va)];
1754 panic("pmap_alloc_l2: missing page table page for va %#lx",
1761 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1763 vm_pindex_t ptepindex;
1764 pd_entry_t *pde, tpde;
1772 * Calculate pagetable page index
1774 ptepindex = pmap_l2_pindex(va);
1777 * Get the page directory entry
1779 pde = pmap_pde(pmap, va, &lvl);
1782 * If the page table page is mapped, we just increment the hold count,
1783 * and activate it. If we get a level 2 pde it will point to a level 3
1791 pte = pmap_l0_to_l1(pde, va);
1792 KASSERT(pmap_load(pte) == 0,
1793 ("pmap_alloc_l3: TODO: l0 superpages"));
1798 pte = pmap_l1_to_l2(pde, va);
1799 KASSERT(pmap_load(pte) == 0,
1800 ("pmap_alloc_l3: TODO: l1 superpages"));
1804 tpde = pmap_load(pde);
1806 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1812 panic("pmap_alloc_l3: Invalid level %d", lvl);
1816 * Here if the pte page isn't mapped, or if it has been deallocated.
1818 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1819 if (m == NULL && lockp != NULL)
1825 /***************************************************
1826 * Pmap allocation/deallocation routines.
1827 ***************************************************/
1830 * Release any resources held by the given physical map.
1831 * Called when a pmap initialized by pmap_pinit is being released.
1832 * Should only be called if the map contains no valid mappings.
1835 pmap_release(pmap_t pmap)
1840 KASSERT(pmap->pm_stats.resident_count == 0,
1841 ("pmap_release: pmap resident count %ld != 0",
1842 pmap->pm_stats.resident_count));
1843 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1844 ("pmap_release: pmap has reserved page table page(s)"));
1845 PMAP_ASSERT_STAGE1(pmap);
1847 mtx_lock_spin(&asid_set_mutex);
1848 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == asid_epoch) {
1849 asid = COOKIE_TO_ASID(pmap->pm_cookie);
1850 KASSERT(asid >= ASID_FIRST_AVAILABLE && asid < asid_set_size,
1851 ("pmap_release: pmap cookie has out-of-range asid"));
1852 bit_clear(asid_set, asid);
1854 mtx_unlock_spin(&asid_set_mutex);
1856 m = PHYS_TO_VM_PAGE(pmap->pm_l0_paddr);
1857 vm_page_unwire_noq(m);
1858 vm_page_free_zero(m);
1862 kvm_size(SYSCTL_HANDLER_ARGS)
1864 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1866 return sysctl_handle_long(oidp, &ksize, 0, req);
1868 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
1869 0, 0, kvm_size, "LU",
1873 kvm_free(SYSCTL_HANDLER_ARGS)
1875 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1877 return sysctl_handle_long(oidp, &kfree, 0, req);
1879 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
1880 0, 0, kvm_free, "LU",
1881 "Amount of KVM free");
1884 * grow the number of kernel page table entries, if needed
1887 pmap_growkernel(vm_offset_t addr)
1891 pd_entry_t *l0, *l1, *l2;
1893 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1895 addr = roundup2(addr, L2_SIZE);
1896 if (addr - 1 >= vm_map_max(kernel_map))
1897 addr = vm_map_max(kernel_map);
1898 while (kernel_vm_end < addr) {
1899 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1900 KASSERT(pmap_load(l0) != 0,
1901 ("pmap_growkernel: No level 0 kernel entry"));
1903 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1904 if (pmap_load(l1) == 0) {
1905 /* We need a new PDP entry */
1906 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1907 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1908 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1910 panic("pmap_growkernel: no memory to grow kernel");
1911 if ((nkpg->flags & PG_ZERO) == 0)
1912 pmap_zero_page(nkpg);
1913 /* See the dmb() in _pmap_alloc_l3(). */
1915 paddr = VM_PAGE_TO_PHYS(nkpg);
1916 pmap_store(l1, paddr | L1_TABLE);
1917 continue; /* try again */
1919 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1920 if (pmap_load(l2) != 0) {
1921 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1922 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1923 kernel_vm_end = vm_map_max(kernel_map);
1929 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1930 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1933 panic("pmap_growkernel: no memory to grow kernel");
1934 if ((nkpg->flags & PG_ZERO) == 0)
1935 pmap_zero_page(nkpg);
1936 /* See the dmb() in _pmap_alloc_l3(). */
1938 paddr = VM_PAGE_TO_PHYS(nkpg);
1939 pmap_store(l2, paddr | L2_TABLE);
1941 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1942 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1943 kernel_vm_end = vm_map_max(kernel_map);
1950 /***************************************************
1951 * page management routines.
1952 ***************************************************/
1954 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1955 CTASSERT(_NPCM == 3);
1956 CTASSERT(_NPCPV == 168);
1958 static __inline struct pv_chunk *
1959 pv_to_chunk(pv_entry_t pv)
1962 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1965 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1967 #define PC_FREE0 0xfffffffffffffffful
1968 #define PC_FREE1 0xfffffffffffffffful
1969 #define PC_FREE2 0x000000fffffffffful
1971 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1975 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1977 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1978 "Current number of pv entry chunks");
1979 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1980 "Current number of pv entry chunks allocated");
1981 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1982 "Current number of pv entry chunks frees");
1983 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1984 "Number of times tried to get a chunk page but failed.");
1986 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1987 static int pv_entry_spare;
1989 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1990 "Current number of pv entry frees");
1991 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1992 "Current number of pv entry allocs");
1993 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1994 "Current number of pv entries");
1995 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1996 "Current number of spare pv entries");
2001 * We are in a serious low memory condition. Resort to
2002 * drastic measures to free some pages so we can allocate
2003 * another pv entry chunk.
2005 * Returns NULL if PV entries were reclaimed from the specified pmap.
2007 * We do not, however, unmap 2mpages because subsequent accesses will
2008 * allocate per-page pv entries until repromotion occurs, thereby
2009 * exacerbating the shortage of free pv entries.
2012 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2014 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
2015 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
2016 struct md_page *pvh;
2018 pmap_t next_pmap, pmap;
2019 pt_entry_t *pte, tpte;
2023 struct spglist free;
2025 int bit, field, freed, lvl;
2026 static int active_reclaims = 0;
2028 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2029 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2034 bzero(&pc_marker_b, sizeof(pc_marker_b));
2035 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
2036 pc_marker = (struct pv_chunk *)&pc_marker_b;
2037 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
2039 mtx_lock(&pv_chunks_mutex);
2041 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
2042 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
2043 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
2044 SLIST_EMPTY(&free)) {
2045 next_pmap = pc->pc_pmap;
2046 if (next_pmap == NULL) {
2048 * The next chunk is a marker. However, it is
2049 * not our marker, so active_reclaims must be
2050 * > 1. Consequently, the next_chunk code
2051 * will not rotate the pv_chunks list.
2055 mtx_unlock(&pv_chunks_mutex);
2058 * A pv_chunk can only be removed from the pc_lru list
2059 * when both pv_chunks_mutex is owned and the
2060 * corresponding pmap is locked.
2062 if (pmap != next_pmap) {
2063 if (pmap != NULL && pmap != locked_pmap)
2066 /* Avoid deadlock and lock recursion. */
2067 if (pmap > locked_pmap) {
2068 RELEASE_PV_LIST_LOCK(lockp);
2070 mtx_lock(&pv_chunks_mutex);
2072 } else if (pmap != locked_pmap) {
2073 if (PMAP_TRYLOCK(pmap)) {
2074 mtx_lock(&pv_chunks_mutex);
2077 pmap = NULL; /* pmap is not locked */
2078 mtx_lock(&pv_chunks_mutex);
2079 pc = TAILQ_NEXT(pc_marker, pc_lru);
2081 pc->pc_pmap != next_pmap)
2089 * Destroy every non-wired, 4 KB page mapping in the chunk.
2092 for (field = 0; field < _NPCM; field++) {
2093 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2094 inuse != 0; inuse &= ~(1UL << bit)) {
2095 bit = ffsl(inuse) - 1;
2096 pv = &pc->pc_pventry[field * 64 + bit];
2098 pde = pmap_pde(pmap, va, &lvl);
2101 pte = pmap_l2_to_l3(pde, va);
2102 tpte = pmap_load(pte);
2103 if ((tpte & ATTR_SW_WIRED) != 0)
2105 tpte = pmap_load_clear(pte);
2106 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
2107 if (pmap_pte_dirty(pmap, tpte))
2109 if ((tpte & ATTR_AF) != 0) {
2110 pmap_invalidate_page(pmap, va);
2111 vm_page_aflag_set(m, PGA_REFERENCED);
2113 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2114 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2116 if (TAILQ_EMPTY(&m->md.pv_list) &&
2117 (m->flags & PG_FICTITIOUS) == 0) {
2118 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2119 if (TAILQ_EMPTY(&pvh->pv_list)) {
2120 vm_page_aflag_clear(m,
2124 pc->pc_map[field] |= 1UL << bit;
2125 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
2130 mtx_lock(&pv_chunks_mutex);
2133 /* Every freed mapping is for a 4 KB page. */
2134 pmap_resident_count_dec(pmap, freed);
2135 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2136 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2137 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2138 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2139 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2140 pc->pc_map[2] == PC_FREE2) {
2141 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2142 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2143 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2144 /* Entire chunk is free; return it. */
2145 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2146 dump_drop_page(m_pc->phys_addr);
2147 mtx_lock(&pv_chunks_mutex);
2148 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2151 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2152 mtx_lock(&pv_chunks_mutex);
2153 /* One freed pv entry in locked_pmap is sufficient. */
2154 if (pmap == locked_pmap)
2158 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2159 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2160 if (active_reclaims == 1 && pmap != NULL) {
2162 * Rotate the pv chunks list so that we do not
2163 * scan the same pv chunks that could not be
2164 * freed (because they contained a wired
2165 * and/or superpage mapping) on every
2166 * invocation of reclaim_pv_chunk().
2168 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2169 MPASS(pc->pc_pmap != NULL);
2170 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2171 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2175 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2176 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2178 mtx_unlock(&pv_chunks_mutex);
2179 if (pmap != NULL && pmap != locked_pmap)
2181 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2182 m_pc = SLIST_FIRST(&free);
2183 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2184 /* Recycle a freed page table page. */
2185 m_pc->ref_count = 1;
2187 vm_page_free_pages_toq(&free, true);
2192 * free the pv_entry back to the free list
2195 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2197 struct pv_chunk *pc;
2198 int idx, field, bit;
2200 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2201 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2202 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2203 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2204 pc = pv_to_chunk(pv);
2205 idx = pv - &pc->pc_pventry[0];
2208 pc->pc_map[field] |= 1ul << bit;
2209 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2210 pc->pc_map[2] != PC_FREE2) {
2211 /* 98% of the time, pc is already at the head of the list. */
2212 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2213 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2214 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2218 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2223 free_pv_chunk(struct pv_chunk *pc)
2227 mtx_lock(&pv_chunks_mutex);
2228 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2229 mtx_unlock(&pv_chunks_mutex);
2230 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2231 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2232 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2233 /* entire chunk is free, return it */
2234 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2235 dump_drop_page(m->phys_addr);
2236 vm_page_unwire_noq(m);
2241 * Returns a new PV entry, allocating a new PV chunk from the system when
2242 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2243 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2246 * The given PV list lock may be released.
2249 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2253 struct pv_chunk *pc;
2256 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2257 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2259 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2261 for (field = 0; field < _NPCM; field++) {
2262 if (pc->pc_map[field]) {
2263 bit = ffsl(pc->pc_map[field]) - 1;
2267 if (field < _NPCM) {
2268 pv = &pc->pc_pventry[field * 64 + bit];
2269 pc->pc_map[field] &= ~(1ul << bit);
2270 /* If this was the last item, move it to tail */
2271 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2272 pc->pc_map[2] == 0) {
2273 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2274 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2277 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2278 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2282 /* No free items, allocate another chunk */
2283 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2286 if (lockp == NULL) {
2287 PV_STAT(pc_chunk_tryfail++);
2290 m = reclaim_pv_chunk(pmap, lockp);
2294 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2295 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2296 dump_add_page(m->phys_addr);
2297 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2299 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2300 pc->pc_map[1] = PC_FREE1;
2301 pc->pc_map[2] = PC_FREE2;
2302 mtx_lock(&pv_chunks_mutex);
2303 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2304 mtx_unlock(&pv_chunks_mutex);
2305 pv = &pc->pc_pventry[0];
2306 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2307 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2308 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2313 * Ensure that the number of spare PV entries in the specified pmap meets or
2314 * exceeds the given count, "needed".
2316 * The given PV list lock may be released.
2319 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2321 struct pch new_tail;
2322 struct pv_chunk *pc;
2327 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2328 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2331 * Newly allocated PV chunks must be stored in a private list until
2332 * the required number of PV chunks have been allocated. Otherwise,
2333 * reclaim_pv_chunk() could recycle one of these chunks. In
2334 * contrast, these chunks must be added to the pmap upon allocation.
2336 TAILQ_INIT(&new_tail);
2339 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2340 bit_count((bitstr_t *)pc->pc_map, 0,
2341 sizeof(pc->pc_map) * NBBY, &free);
2345 if (avail >= needed)
2348 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2349 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2352 m = reclaim_pv_chunk(pmap, lockp);
2357 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2358 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2359 dump_add_page(m->phys_addr);
2360 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2362 pc->pc_map[0] = PC_FREE0;
2363 pc->pc_map[1] = PC_FREE1;
2364 pc->pc_map[2] = PC_FREE2;
2365 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2366 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2367 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2370 * The reclaim might have freed a chunk from the current pmap.
2371 * If that chunk contained available entries, we need to
2372 * re-count the number of available entries.
2377 if (!TAILQ_EMPTY(&new_tail)) {
2378 mtx_lock(&pv_chunks_mutex);
2379 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2380 mtx_unlock(&pv_chunks_mutex);
2385 * First find and then remove the pv entry for the specified pmap and virtual
2386 * address from the specified pv list. Returns the pv entry if found and NULL
2387 * otherwise. This operation can be performed on pv lists for either 4KB or
2388 * 2MB page mappings.
2390 static __inline pv_entry_t
2391 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2395 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2396 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2397 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2406 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2407 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2408 * entries for each of the 4KB page mappings.
2411 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2412 struct rwlock **lockp)
2414 struct md_page *pvh;
2415 struct pv_chunk *pc;
2417 vm_offset_t va_last;
2421 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2422 KASSERT((va & L2_OFFSET) == 0,
2423 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
2424 KASSERT((pa & L2_OFFSET) == 0,
2425 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2426 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2429 * Transfer the 2mpage's pv entry for this mapping to the first
2430 * page's pv list. Once this transfer begins, the pv list lock
2431 * must not be released until the last pv entry is reinstantiated.
2433 pvh = pa_to_pvh(pa);
2434 pv = pmap_pvh_remove(pvh, pmap, va);
2435 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2436 m = PHYS_TO_VM_PAGE(pa);
2437 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2439 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2440 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2441 va_last = va + L2_SIZE - PAGE_SIZE;
2443 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2444 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2445 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2446 for (field = 0; field < _NPCM; field++) {
2447 while (pc->pc_map[field]) {
2448 bit = ffsl(pc->pc_map[field]) - 1;
2449 pc->pc_map[field] &= ~(1ul << bit);
2450 pv = &pc->pc_pventry[field * 64 + bit];
2454 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2455 ("pmap_pv_demote_l2: page %p is not managed", m));
2456 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2462 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2463 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2466 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2467 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2468 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2470 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2471 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2475 * First find and then destroy the pv entry for the specified pmap and virtual
2476 * address. This operation can be performed on pv lists for either 4KB or 2MB
2480 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2484 pv = pmap_pvh_remove(pvh, pmap, va);
2485 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2486 free_pv_entry(pmap, pv);
2490 * Conditionally create the PV entry for a 4KB page mapping if the required
2491 * memory can be allocated without resorting to reclamation.
2494 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2495 struct rwlock **lockp)
2499 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2500 /* Pass NULL instead of the lock pointer to disable reclamation. */
2501 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2503 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2504 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2512 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2513 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2514 * false if the PV entry cannot be allocated without resorting to reclamation.
2517 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2518 struct rwlock **lockp)
2520 struct md_page *pvh;
2524 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2525 /* Pass NULL instead of the lock pointer to disable reclamation. */
2526 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2527 NULL : lockp)) == NULL)
2530 pa = l2e & ~ATTR_MASK;
2531 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2532 pvh = pa_to_pvh(pa);
2533 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2539 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2541 pt_entry_t newl2, oldl2;
2545 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2546 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2547 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2549 ml3 = pmap_remove_pt_page(pmap, va);
2551 panic("pmap_remove_kernel_l2: Missing pt page");
2553 ml3pa = VM_PAGE_TO_PHYS(ml3);
2554 newl2 = ml3pa | L2_TABLE;
2557 * If this page table page was unmapped by a promotion, then it
2558 * contains valid mappings. Zero it to invalidate those mappings.
2560 if (ml3->valid != 0)
2561 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2564 * Demote the mapping. The caller must have already invalidated the
2565 * mapping (i.e., the "break" in break-before-make).
2567 oldl2 = pmap_load_store(l2, newl2);
2568 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
2569 __func__, l2, oldl2));
2573 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
2576 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2577 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2579 struct md_page *pvh;
2581 vm_offset_t eva, va;
2584 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2585 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2586 old_l2 = pmap_load_clear(l2);
2587 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2588 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2591 * Since a promotion must break the 4KB page mappings before making
2592 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2594 pmap_invalidate_page(pmap, sva);
2596 if (old_l2 & ATTR_SW_WIRED)
2597 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2598 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2599 if (old_l2 & ATTR_SW_MANAGED) {
2600 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2601 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2602 pmap_pvh_free(pvh, pmap, sva);
2603 eva = sva + L2_SIZE;
2604 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2605 va < eva; va += PAGE_SIZE, m++) {
2606 if (pmap_pte_dirty(pmap, old_l2))
2608 if (old_l2 & ATTR_AF)
2609 vm_page_aflag_set(m, PGA_REFERENCED);
2610 if (TAILQ_EMPTY(&m->md.pv_list) &&
2611 TAILQ_EMPTY(&pvh->pv_list))
2612 vm_page_aflag_clear(m, PGA_WRITEABLE);
2615 if (pmap == kernel_pmap) {
2616 pmap_remove_kernel_l2(pmap, l2, sva);
2618 ml3 = pmap_remove_pt_page(pmap, sva);
2620 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
2621 ("pmap_remove_l2: l3 page not promoted"));
2622 pmap_resident_count_dec(pmap, 1);
2623 KASSERT(ml3->ref_count == NL3PG,
2624 ("pmap_remove_l2: l3 page ref count error"));
2626 pmap_add_delayed_free_list(ml3, free, FALSE);
2629 return (pmap_unuse_pt(pmap, sva, l1e, free));
2633 * pmap_remove_l3: do the things to unmap a page in a process
2636 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2637 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2639 struct md_page *pvh;
2643 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2644 old_l3 = pmap_load_clear(l3);
2645 pmap_invalidate_page(pmap, va);
2646 if (old_l3 & ATTR_SW_WIRED)
2647 pmap->pm_stats.wired_count -= 1;
2648 pmap_resident_count_dec(pmap, 1);
2649 if (old_l3 & ATTR_SW_MANAGED) {
2650 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2651 if (pmap_pte_dirty(pmap, old_l3))
2653 if (old_l3 & ATTR_AF)
2654 vm_page_aflag_set(m, PGA_REFERENCED);
2655 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2656 pmap_pvh_free(&m->md, pmap, va);
2657 if (TAILQ_EMPTY(&m->md.pv_list) &&
2658 (m->flags & PG_FICTITIOUS) == 0) {
2659 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2660 if (TAILQ_EMPTY(&pvh->pv_list))
2661 vm_page_aflag_clear(m, PGA_WRITEABLE);
2664 return (pmap_unuse_pt(pmap, va, l2e, free));
2668 * Remove the specified range of addresses from the L3 page table that is
2669 * identified by the given L2 entry.
2672 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
2673 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
2675 struct md_page *pvh;
2676 struct rwlock *new_lock;
2677 pt_entry_t *l3, old_l3;
2681 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2682 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
2683 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
2684 l3pg = sva < VM_MAXUSER_ADDRESS ? PHYS_TO_VM_PAGE(l2e & ~ATTR_MASK) :
2687 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
2688 if (!pmap_l3_valid(pmap_load(l3))) {
2690 pmap_invalidate_range(pmap, va, sva);
2695 old_l3 = pmap_load_clear(l3);
2696 if ((old_l3 & ATTR_SW_WIRED) != 0)
2697 pmap->pm_stats.wired_count--;
2698 pmap_resident_count_dec(pmap, 1);
2699 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
2700 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2701 if (pmap_pte_dirty(pmap, old_l3))
2703 if ((old_l3 & ATTR_AF) != 0)
2704 vm_page_aflag_set(m, PGA_REFERENCED);
2705 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
2706 if (new_lock != *lockp) {
2707 if (*lockp != NULL) {
2709 * Pending TLB invalidations must be
2710 * performed before the PV list lock is
2711 * released. Otherwise, a concurrent
2712 * pmap_remove_all() on a physical page
2713 * could return while a stale TLB entry
2714 * still provides access to that page.
2717 pmap_invalidate_range(pmap, va,
2726 pmap_pvh_free(&m->md, pmap, sva);
2727 if (TAILQ_EMPTY(&m->md.pv_list) &&
2728 (m->flags & PG_FICTITIOUS) == 0) {
2729 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2730 if (TAILQ_EMPTY(&pvh->pv_list))
2731 vm_page_aflag_clear(m, PGA_WRITEABLE);
2736 if (l3pg != NULL && pmap_unwire_l3(pmap, sva, l3pg, free)) {
2742 pmap_invalidate_range(pmap, va, sva);
2746 * Remove the given range of addresses from the specified map.
2748 * It is assumed that the start and end are properly
2749 * rounded to the page size.
2752 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2754 struct rwlock *lock;
2755 vm_offset_t va_next;
2756 pd_entry_t *l0, *l1, *l2;
2757 pt_entry_t l3_paddr;
2758 struct spglist free;
2761 * Perform an unsynchronized read. This is, however, safe.
2763 if (pmap->pm_stats.resident_count == 0)
2771 for (; sva < eva; sva = va_next) {
2773 if (pmap->pm_stats.resident_count == 0)
2776 l0 = pmap_l0(pmap, sva);
2777 if (pmap_load(l0) == 0) {
2778 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2784 l1 = pmap_l0_to_l1(l0, sva);
2785 if (pmap_load(l1) == 0) {
2786 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2793 * Calculate index for next page table.
2795 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2799 l2 = pmap_l1_to_l2(l1, sva);
2803 l3_paddr = pmap_load(l2);
2805 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2806 if (sva + L2_SIZE == va_next && eva >= va_next) {
2807 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2810 } else if (pmap_demote_l2_locked(pmap, l2, sva,
2813 l3_paddr = pmap_load(l2);
2817 * Weed out invalid mappings.
2819 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2823 * Limit our scan to either the end of the va represented
2824 * by the current page table page, or to the end of the
2825 * range being removed.
2830 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
2836 vm_page_free_pages_toq(&free, true);
2840 * Routine: pmap_remove_all
2842 * Removes this physical page from
2843 * all physical maps in which it resides.
2844 * Reflects back modify bits to the pager.
2847 * Original versions of this routine were very
2848 * inefficient because they iteratively called
2849 * pmap_remove (slow...)
2853 pmap_remove_all(vm_page_t m)
2855 struct md_page *pvh;
2858 struct rwlock *lock;
2859 pd_entry_t *pde, tpde;
2860 pt_entry_t *pte, tpte;
2862 struct spglist free;
2863 int lvl, pvh_gen, md_gen;
2865 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2866 ("pmap_remove_all: page %p is not managed", m));
2868 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2869 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2870 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2873 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2875 if (!PMAP_TRYLOCK(pmap)) {
2876 pvh_gen = pvh->pv_gen;
2880 if (pvh_gen != pvh->pv_gen) {
2887 pte = pmap_pte(pmap, va, &lvl);
2888 KASSERT(pte != NULL,
2889 ("pmap_remove_all: no page table entry found"));
2891 ("pmap_remove_all: invalid pte level %d", lvl));
2893 pmap_demote_l2_locked(pmap, pte, va, &lock);
2896 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2898 PMAP_ASSERT_STAGE1(pmap);
2899 if (!PMAP_TRYLOCK(pmap)) {
2900 pvh_gen = pvh->pv_gen;
2901 md_gen = m->md.pv_gen;
2905 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2911 pmap_resident_count_dec(pmap, 1);
2913 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2914 KASSERT(pde != NULL,
2915 ("pmap_remove_all: no page directory entry found"));
2917 ("pmap_remove_all: invalid pde level %d", lvl));
2918 tpde = pmap_load(pde);
2920 pte = pmap_l2_to_l3(pde, pv->pv_va);
2921 tpte = pmap_load_clear(pte);
2922 if (tpte & ATTR_SW_WIRED)
2923 pmap->pm_stats.wired_count--;
2924 if ((tpte & ATTR_AF) != 0) {
2925 pmap_invalidate_page(pmap, pv->pv_va);
2926 vm_page_aflag_set(m, PGA_REFERENCED);
2930 * Update the vm_page_t clean and reference bits.
2932 if (pmap_pte_dirty(pmap, tpte))
2934 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2935 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2937 free_pv_entry(pmap, pv);
2940 vm_page_aflag_clear(m, PGA_WRITEABLE);
2942 vm_page_free_pages_toq(&free, true);
2946 * pmap_protect_l2: do the things to protect a 2MB page in a pmap
2949 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
2955 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2956 PMAP_ASSERT_STAGE1(pmap);
2957 KASSERT((sva & L2_OFFSET) == 0,
2958 ("pmap_protect_l2: sva is not 2mpage aligned"));
2959 old_l2 = pmap_load(l2);
2960 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2961 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
2964 * Return if the L2 entry already has the desired access restrictions
2968 if ((old_l2 & mask) == nbits)
2972 * When a dirty read/write superpage mapping is write protected,
2973 * update the dirty field of each of the superpage's constituent 4KB
2976 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
2977 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
2978 pmap_pte_dirty(pmap, old_l2)) {
2979 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2980 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
2984 if (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
2988 * Since a promotion must break the 4KB page mappings before making
2989 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2991 pmap_invalidate_page(pmap, sva);
2995 * Set the physical protection on the
2996 * specified range of this map as requested.
2999 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3001 vm_offset_t va, va_next;
3002 pd_entry_t *l0, *l1, *l2;
3003 pt_entry_t *l3p, l3, mask, nbits;
3005 PMAP_ASSERT_STAGE1(pmap);
3006 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3007 if (prot == VM_PROT_NONE) {
3008 pmap_remove(pmap, sva, eva);
3013 if ((prot & VM_PROT_WRITE) == 0) {
3014 mask |= ATTR_S1_AP_RW_BIT | ATTR_SW_DBM;
3015 nbits |= ATTR_S1_AP(ATTR_S1_AP_RO);
3017 if ((prot & VM_PROT_EXECUTE) == 0) {
3019 nbits |= ATTR_S1_XN;
3025 for (; sva < eva; sva = va_next) {
3027 l0 = pmap_l0(pmap, sva);
3028 if (pmap_load(l0) == 0) {
3029 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3035 l1 = pmap_l0_to_l1(l0, sva);
3036 if (pmap_load(l1) == 0) {
3037 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3043 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3047 l2 = pmap_l1_to_l2(l1, sva);
3048 if (pmap_load(l2) == 0)
3051 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3052 if (sva + L2_SIZE == va_next && eva >= va_next) {
3053 pmap_protect_l2(pmap, l2, sva, mask, nbits);
3055 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3058 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3059 ("pmap_protect: Invalid L2 entry after demotion"));
3065 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
3067 l3 = pmap_load(l3p);
3070 * Go to the next L3 entry if the current one is
3071 * invalid or already has the desired access
3072 * restrictions in place. (The latter case occurs
3073 * frequently. For example, in a "buildworld"
3074 * workload, almost 1 out of 4 L3 entries already
3075 * have the desired restrictions.)
3077 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
3078 if (va != va_next) {
3079 pmap_invalidate_range(pmap, va, sva);
3086 * When a dirty read/write mapping is write protected,
3087 * update the page's dirty field.
3089 if ((l3 & ATTR_SW_MANAGED) != 0 &&
3090 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3091 pmap_pte_dirty(pmap, l3))
3092 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK));
3094 if (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) | nbits))
3100 pmap_invalidate_range(pmap, va, sva);
3106 * Inserts the specified page table page into the specified pmap's collection
3107 * of idle page table pages. Each of a pmap's page table pages is responsible
3108 * for mapping a distinct range of virtual addresses. The pmap's collection is
3109 * ordered by this virtual address range.
3111 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3114 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3117 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3118 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3119 return (vm_radix_insert(&pmap->pm_root, mpte));
3123 * Removes the page table page mapping the specified virtual address from the
3124 * specified pmap's collection of idle page table pages, and returns it.
3125 * Otherwise, returns NULL if there is no page table page corresponding to the
3126 * specified virtual address.
3128 static __inline vm_page_t
3129 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3132 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3133 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
3137 * Performs a break-before-make update of a pmap entry. This is needed when
3138 * either promoting or demoting pages to ensure the TLB doesn't get into an
3139 * inconsistent state.
3142 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
3143 vm_offset_t va, vm_size_t size)
3147 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3150 * Ensure we don't get switched out with the page table in an
3151 * inconsistent state. We also need to ensure no interrupts fire
3152 * as they may make use of an address we are about to invalidate.
3154 intr = intr_disable();
3157 * Clear the old mapping's valid bit, but leave the rest of the entry
3158 * unchanged, so that a lockless, concurrent pmap_kextract() can still
3159 * lookup the physical address.
3161 pmap_clear_bits(pte, ATTR_DESCR_VALID);
3162 pmap_invalidate_range(pmap, va, va + size);
3164 /* Create the new mapping */
3165 pmap_store(pte, newpte);
3171 #if VM_NRESERVLEVEL > 0
3173 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3174 * replace the many pv entries for the 4KB page mappings by a single pv entry
3175 * for the 2MB page mapping.
3178 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3179 struct rwlock **lockp)
3181 struct md_page *pvh;
3183 vm_offset_t va_last;
3186 KASSERT((pa & L2_OFFSET) == 0,
3187 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
3188 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3191 * Transfer the first page's pv entry for this mapping to the 2mpage's
3192 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3193 * a transfer avoids the possibility that get_pv_entry() calls
3194 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3195 * mappings that is being promoted.
3197 m = PHYS_TO_VM_PAGE(pa);
3198 va = va & ~L2_OFFSET;
3199 pv = pmap_pvh_remove(&m->md, pmap, va);
3200 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
3201 pvh = pa_to_pvh(pa);
3202 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3204 /* Free the remaining NPTEPG - 1 pv entries. */
3205 va_last = va + L2_SIZE - PAGE_SIZE;
3209 pmap_pvh_free(&m->md, pmap, va);
3210 } while (va < va_last);
3214 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3215 * single level 2 table entry to a single 2MB page mapping. For promotion
3216 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3217 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3218 * identical characteristics.
3221 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
3222 struct rwlock **lockp)
3224 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
3228 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3229 PMAP_ASSERT_STAGE1(pmap);
3231 sva = va & ~L2_OFFSET;
3232 firstl3 = pmap_l2_to_l3(l2, sva);
3233 newl2 = pmap_load(firstl3);
3236 if (((newl2 & (~ATTR_MASK | ATTR_AF)) & L2_OFFSET) != ATTR_AF) {
3237 atomic_add_long(&pmap_l2_p_failures, 1);
3238 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3239 " in pmap %p", va, pmap);
3243 if ((newl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3244 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3245 if (!atomic_fcmpset_64(l2, &newl2, newl2 & ~ATTR_SW_DBM))
3247 newl2 &= ~ATTR_SW_DBM;
3250 pa = newl2 + L2_SIZE - PAGE_SIZE;
3251 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
3252 oldl3 = pmap_load(l3);
3254 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3255 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3256 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
3259 oldl3 &= ~ATTR_SW_DBM;
3262 atomic_add_long(&pmap_l2_p_failures, 1);
3263 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3264 " in pmap %p", va, pmap);
3271 * Save the page table page in its current state until the L2
3272 * mapping the superpage is demoted by pmap_demote_l2() or
3273 * destroyed by pmap_remove_l3().
3275 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3276 KASSERT(mpte >= vm_page_array &&
3277 mpte < &vm_page_array[vm_page_array_size],
3278 ("pmap_promote_l2: page table page is out of range"));
3279 KASSERT(mpte->pindex == pmap_l2_pindex(va),
3280 ("pmap_promote_l2: page table page's pindex is wrong"));
3281 if (pmap_insert_pt_page(pmap, mpte, true)) {
3282 atomic_add_long(&pmap_l2_p_failures, 1);
3284 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
3289 if ((newl2 & ATTR_SW_MANAGED) != 0)
3290 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
3292 newl2 &= ~ATTR_DESCR_MASK;
3295 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
3297 atomic_add_long(&pmap_l2_promotions, 1);
3298 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
3301 #endif /* VM_NRESERVLEVEL > 0 */
3304 * Insert the given physical page (p) at
3305 * the specified virtual address (v) in the
3306 * target physical map with the protection requested.
3308 * If specified, the page will be wired down, meaning
3309 * that the related pte can not be reclaimed.
3311 * NB: This is the only routine which MAY NOT lazy-evaluate
3312 * or lose information. That is, this routine must actually
3313 * insert this page into the given map NOW.
3316 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3317 u_int flags, int8_t psind)
3319 struct rwlock *lock;
3321 pt_entry_t new_l3, orig_l3;
3322 pt_entry_t *l2, *l3;
3329 PMAP_ASSERT_STAGE1(pmap);
3331 va = trunc_page(va);
3332 if ((m->oflags & VPO_UNMANAGED) == 0)
3333 VM_PAGE_OBJECT_BUSY_ASSERT(m);
3334 pa = VM_PAGE_TO_PHYS(m);
3335 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_S1_IDX(m->md.pv_memattr) |
3337 if ((prot & VM_PROT_WRITE) == 0)
3338 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
3339 if ((prot & VM_PROT_EXECUTE) == 0 ||
3340 m->md.pv_memattr == VM_MEMATTR_DEVICE)
3341 new_l3 |= ATTR_S1_XN;
3342 if ((flags & PMAP_ENTER_WIRED) != 0)
3343 new_l3 |= ATTR_SW_WIRED;
3344 if (va < VM_MAXUSER_ADDRESS)
3345 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
3347 new_l3 |= ATTR_S1_UXN;
3348 if (pmap != kernel_pmap)
3349 new_l3 |= ATTR_S1_nG;
3350 if ((m->oflags & VPO_UNMANAGED) == 0) {
3351 new_l3 |= ATTR_SW_MANAGED;
3352 if ((prot & VM_PROT_WRITE) != 0) {
3353 new_l3 |= ATTR_SW_DBM;
3354 if ((flags & VM_PROT_WRITE) == 0)
3355 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
3359 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3364 /* Assert the required virtual and physical alignment. */
3365 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3366 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3367 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3374 * In the case that a page table page is not
3375 * resident, we are creating it here.
3378 pde = pmap_pde(pmap, va, &lvl);
3379 if (pde != NULL && lvl == 2) {
3380 l3 = pmap_l2_to_l3(pde, va);
3381 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3382 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3386 } else if (pde != NULL && lvl == 1) {
3387 l2 = pmap_l1_to_l2(pde, va);
3388 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3389 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
3390 l3 = &l3[pmap_l3_index(va)];
3391 if (va < VM_MAXUSER_ADDRESS) {
3392 mpte = PHYS_TO_VM_PAGE(
3393 pmap_load(l2) & ~ATTR_MASK);
3398 /* We need to allocate an L3 table. */
3400 if (va < VM_MAXUSER_ADDRESS) {
3401 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
3404 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
3405 * to handle the possibility that a superpage mapping for "va"
3406 * was created while we slept.
3408 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
3409 nosleep ? NULL : &lock);
3410 if (mpte == NULL && nosleep) {
3411 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3412 rv = KERN_RESOURCE_SHORTAGE;
3417 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
3420 orig_l3 = pmap_load(l3);
3421 opa = orig_l3 & ~ATTR_MASK;
3425 * Is the specified virtual address already mapped?
3427 if (pmap_l3_valid(orig_l3)) {
3429 * Wiring change, just update stats. We don't worry about
3430 * wiring PT pages as they remain resident as long as there
3431 * are valid mappings in them. Hence, if a user page is wired,
3432 * the PT page will be also.
3434 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3435 (orig_l3 & ATTR_SW_WIRED) == 0)
3436 pmap->pm_stats.wired_count++;
3437 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3438 (orig_l3 & ATTR_SW_WIRED) != 0)
3439 pmap->pm_stats.wired_count--;
3442 * Remove the extra PT page reference.
3446 KASSERT(mpte->ref_count > 0,
3447 ("pmap_enter: missing reference to page table page,"
3452 * Has the physical page changed?
3456 * No, might be a protection or wiring change.
3458 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3459 (new_l3 & ATTR_SW_DBM) != 0)
3460 vm_page_aflag_set(m, PGA_WRITEABLE);
3465 * The physical page has changed. Temporarily invalidate
3468 orig_l3 = pmap_load_clear(l3);
3469 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
3470 ("pmap_enter: unexpected pa update for %#lx", va));
3471 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3472 om = PHYS_TO_VM_PAGE(opa);
3475 * The pmap lock is sufficient to synchronize with
3476 * concurrent calls to pmap_page_test_mappings() and
3477 * pmap_ts_referenced().
3479 if (pmap_pte_dirty(pmap, orig_l3))
3481 if ((orig_l3 & ATTR_AF) != 0) {
3482 pmap_invalidate_page(pmap, va);
3483 vm_page_aflag_set(om, PGA_REFERENCED);
3485 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3486 pv = pmap_pvh_remove(&om->md, pmap, va);
3487 if ((m->oflags & VPO_UNMANAGED) != 0)
3488 free_pv_entry(pmap, pv);
3489 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
3490 TAILQ_EMPTY(&om->md.pv_list) &&
3491 ((om->flags & PG_FICTITIOUS) != 0 ||
3492 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3493 vm_page_aflag_clear(om, PGA_WRITEABLE);
3495 KASSERT((orig_l3 & ATTR_AF) != 0,
3496 ("pmap_enter: unmanaged mapping lacks ATTR_AF"));
3497 pmap_invalidate_page(pmap, va);
3502 * Increment the counters.
3504 if ((new_l3 & ATTR_SW_WIRED) != 0)
3505 pmap->pm_stats.wired_count++;
3506 pmap_resident_count_inc(pmap, 1);
3509 * Enter on the PV list if part of our managed memory.
3511 if ((m->oflags & VPO_UNMANAGED) == 0) {
3513 pv = get_pv_entry(pmap, &lock);
3516 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3517 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3519 if ((new_l3 & ATTR_SW_DBM) != 0)
3520 vm_page_aflag_set(m, PGA_WRITEABLE);
3525 * Sync icache if exec permission and attribute VM_MEMATTR_WRITE_BACK
3526 * is set. Do it now, before the mapping is stored and made
3527 * valid for hardware table walk. If done later, then other can
3528 * access this page before caches are properly synced.
3529 * Don't do it for kernel memory which is mapped with exec
3530 * permission even if the memory isn't going to hold executable
3531 * code. The only time when icache sync is needed is after
3532 * kernel module is loaded and the relocation info is processed.
3533 * And it's done in elf_cpu_load_file().
3535 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3536 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3537 (opa != pa || (orig_l3 & ATTR_S1_XN)))
3538 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3541 * Update the L3 entry
3543 if (pmap_l3_valid(orig_l3)) {
3544 KASSERT(opa == pa, ("pmap_enter: invalid update"));
3545 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3546 /* same PA, different attributes */
3547 orig_l3 = pmap_load_store(l3, new_l3);
3548 pmap_invalidate_page(pmap, va);
3549 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3550 pmap_pte_dirty(pmap, orig_l3))
3555 * This can happens if multiple threads simultaneously
3556 * access not yet mapped page. This bad for performance
3557 * since this can cause full demotion-NOP-promotion
3559 * Another possible reasons are:
3560 * - VM and pmap memory layout are diverged
3561 * - tlb flush is missing somewhere and CPU doesn't see
3564 CTR4(KTR_PMAP, "%s: already mapped page - "
3565 "pmap %p va 0x%#lx pte 0x%lx",
3566 __func__, pmap, va, new_l3);
3570 pmap_store(l3, new_l3);
3574 #if VM_NRESERVLEVEL > 0
3575 if ((mpte == NULL || mpte->ref_count == NL3PG) &&
3576 pmap_ps_enabled(pmap) &&
3577 (m->flags & PG_FICTITIOUS) == 0 &&
3578 vm_reserv_level_iffullpop(m) == 0) {
3579 pmap_promote_l2(pmap, pde, va, &lock);
3592 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
3593 * if successful. Returns false if (1) a page table page cannot be allocated
3594 * without sleeping, (2) a mapping already exists at the specified virtual
3595 * address, or (3) a PV entry cannot be allocated without reclaiming another
3599 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3600 struct rwlock **lockp)
3604 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3605 PMAP_ASSERT_STAGE1(pmap);
3607 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
3608 ATTR_S1_IDX(m->md.pv_memattr) | ATTR_S1_AP(ATTR_S1_AP_RO) |
3610 if ((m->oflags & VPO_UNMANAGED) == 0) {
3611 new_l2 |= ATTR_SW_MANAGED;
3614 if ((prot & VM_PROT_EXECUTE) == 0 ||
3615 m->md.pv_memattr == VM_MEMATTR_DEVICE)
3616 new_l2 |= ATTR_S1_XN;
3617 if (va < VM_MAXUSER_ADDRESS)
3618 new_l2 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
3620 new_l2 |= ATTR_S1_UXN;
3621 if (pmap != kernel_pmap)
3622 new_l2 |= ATTR_S1_nG;
3623 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
3624 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
3629 * Returns true if every page table entry in the specified page table is
3633 pmap_every_pte_zero(vm_paddr_t pa)
3635 pt_entry_t *pt_end, *pte;
3637 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
3638 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
3639 for (pt_end = pte + Ln_ENTRIES; pte < pt_end; pte++) {
3647 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
3648 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
3649 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
3650 * a mapping already exists at the specified virtual address. Returns
3651 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
3652 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
3653 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3655 * The parameter "m" is only used when creating a managed, writeable mapping.
3658 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
3659 vm_page_t m, struct rwlock **lockp)
3661 struct spglist free;
3662 pd_entry_t *l2, old_l2;
3665 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3667 if ((l2 = pmap_alloc_l2(pmap, va, &l2pg, (flags &
3668 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
3669 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
3671 return (KERN_RESOURCE_SHORTAGE);
3675 * If there are existing mappings, either abort or remove them.
3677 if ((old_l2 = pmap_load(l2)) != 0) {
3678 KASSERT(l2pg == NULL || l2pg->ref_count > 1,
3679 ("pmap_enter_l2: l2pg's ref count is too low"));
3680 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
3681 VM_MAXUSER_ADDRESS || (old_l2 & ATTR_DESCR_MASK) ==
3682 L2_BLOCK || !pmap_every_pte_zero(old_l2 & ~ATTR_MASK))) {
3685 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx"
3686 " in pmap %p", va, pmap);
3687 return (KERN_FAILURE);
3690 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
3691 (void)pmap_remove_l2(pmap, l2, va,
3692 pmap_load(pmap_l1(pmap, va)), &free, lockp);
3694 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
3696 if (va < VM_MAXUSER_ADDRESS) {
3697 vm_page_free_pages_toq(&free, true);
3698 KASSERT(pmap_load(l2) == 0,
3699 ("pmap_enter_l2: non-zero L2 entry %p", l2));
3701 KASSERT(SLIST_EMPTY(&free),
3702 ("pmap_enter_l2: freed kernel page table page"));
3705 * Both pmap_remove_l2() and pmap_remove_l3_range()
3706 * will leave the kernel page table page zero filled.
3707 * Nonetheless, the TLB could have an intermediate
3708 * entry for the kernel page table page.
3710 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3711 if (pmap_insert_pt_page(pmap, mt, false))
3712 panic("pmap_enter_l2: trie insert failed");
3714 pmap_invalidate_page(pmap, va);
3718 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
3720 * Abort this mapping if its PV entry could not be created.
3722 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
3724 pmap_abort_ptp(pmap, va, l2pg);
3726 "pmap_enter_l2: failure for va %#lx in pmap %p",
3728 return (KERN_RESOURCE_SHORTAGE);
3730 if ((new_l2 & ATTR_SW_DBM) != 0)
3731 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3732 vm_page_aflag_set(mt, PGA_WRITEABLE);
3736 * Increment counters.
3738 if ((new_l2 & ATTR_SW_WIRED) != 0)
3739 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
3740 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
3743 * Map the superpage.
3745 pmap_store(l2, new_l2);
3748 atomic_add_long(&pmap_l2_mappings, 1);
3749 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
3752 return (KERN_SUCCESS);
3756 * Maps a sequence of resident pages belonging to the same object.
3757 * The sequence begins with the given page m_start. This page is
3758 * mapped at the given virtual address start. Each subsequent page is
3759 * mapped at a virtual address that is offset from start by the same
3760 * amount as the page is offset from m_start within the object. The
3761 * last page in the sequence is the page with the largest offset from
3762 * m_start that can be mapped at a virtual address less than the given
3763 * virtual address end. Not every virtual page between start and end
3764 * is mapped; only those for which a resident page exists with the
3765 * corresponding offset from m_start are mapped.
3768 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3769 vm_page_t m_start, vm_prot_t prot)
3771 struct rwlock *lock;
3774 vm_pindex_t diff, psize;
3776 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3778 psize = atop(end - start);
3783 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3784 va = start + ptoa(diff);
3785 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
3786 m->psind == 1 && pmap_ps_enabled(pmap) &&
3787 pmap_enter_2mpage(pmap, va, m, prot, &lock))
3788 m = &m[L2_SIZE / PAGE_SIZE - 1];
3790 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
3792 m = TAILQ_NEXT(m, listq);
3800 * this code makes some *MAJOR* assumptions:
3801 * 1. Current pmap & pmap exists.
3804 * 4. No page table pages.
3805 * but is *MUCH* faster than pmap_enter...
3809 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3811 struct rwlock *lock;
3815 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3822 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3823 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3826 pt_entry_t *l2, *l3, l3_val;
3830 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3831 (m->oflags & VPO_UNMANAGED) != 0,
3832 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3833 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3834 PMAP_ASSERT_STAGE1(pmap);
3836 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3838 * In the case that a page table page is not
3839 * resident, we are creating it here.
3841 if (va < VM_MAXUSER_ADDRESS) {
3842 vm_pindex_t l2pindex;
3845 * Calculate pagetable page index
3847 l2pindex = pmap_l2_pindex(va);
3848 if (mpte && (mpte->pindex == l2pindex)) {
3854 pde = pmap_pde(pmap, va, &lvl);
3857 * If the page table page is mapped, we just increment
3858 * the hold count, and activate it. Otherwise, we
3859 * attempt to allocate a page table page. If this
3860 * attempt fails, we don't retry. Instead, we give up.
3863 l2 = pmap_l1_to_l2(pde, va);
3864 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3868 if (lvl == 2 && pmap_load(pde) != 0) {
3870 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3874 * Pass NULL instead of the PV list lock
3875 * pointer, because we don't intend to sleep.
3877 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3882 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3883 l3 = &l3[pmap_l3_index(va)];
3886 pde = pmap_pde(kernel_pmap, va, &lvl);
3887 KASSERT(pde != NULL,
3888 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3891 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3892 l3 = pmap_l2_to_l3(pde, va);
3896 * Abort if a mapping already exists.
3898 if (pmap_load(l3) != 0) {
3905 * Enter on the PV list if part of our managed memory.
3907 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3908 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3910 pmap_abort_ptp(pmap, va, mpte);
3915 * Increment counters
3917 pmap_resident_count_inc(pmap, 1);
3919 pa = VM_PAGE_TO_PHYS(m);
3920 l3_val = pa | ATTR_DEFAULT | ATTR_S1_IDX(m->md.pv_memattr) |
3921 ATTR_S1_AP(ATTR_S1_AP_RO) | L3_PAGE;
3922 if ((prot & VM_PROT_EXECUTE) == 0 ||
3923 m->md.pv_memattr == VM_MEMATTR_DEVICE)
3924 l3_val |= ATTR_S1_XN;
3925 if (va < VM_MAXUSER_ADDRESS)
3926 l3_val |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
3928 l3_val |= ATTR_S1_UXN;
3929 if (pmap != kernel_pmap)
3930 l3_val |= ATTR_S1_nG;
3933 * Now validate mapping with RO protection
3935 if ((m->oflags & VPO_UNMANAGED) == 0) {
3936 l3_val |= ATTR_SW_MANAGED;
3940 /* Sync icache before the mapping is stored to PTE */
3941 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3942 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
3943 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3945 pmap_store(l3, l3_val);
3952 * This code maps large physical mmap regions into the
3953 * processor address space. Note that some shortcuts
3954 * are taken, but the code works.
3957 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3958 vm_pindex_t pindex, vm_size_t size)
3961 VM_OBJECT_ASSERT_WLOCKED(object);
3962 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3963 ("pmap_object_init_pt: non-device object"));
3967 * Clear the wired attribute from the mappings for the specified range of
3968 * addresses in the given pmap. Every valid mapping within that range
3969 * must have the wired attribute set. In contrast, invalid mappings
3970 * cannot have the wired attribute set, so they are ignored.
3972 * The wired attribute of the page table entry is not a hardware feature,
3973 * so there is no need to invalidate any TLB entries.
3976 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3978 vm_offset_t va_next;
3979 pd_entry_t *l0, *l1, *l2;
3983 for (; sva < eva; sva = va_next) {
3984 l0 = pmap_l0(pmap, sva);
3985 if (pmap_load(l0) == 0) {
3986 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3992 l1 = pmap_l0_to_l1(l0, sva);
3993 if (pmap_load(l1) == 0) {
3994 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
4000 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
4004 l2 = pmap_l1_to_l2(l1, sva);
4005 if (pmap_load(l2) == 0)
4008 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
4009 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
4010 panic("pmap_unwire: l2 %#jx is missing "
4011 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
4014 * Are we unwiring the entire large page? If not,
4015 * demote the mapping and fall through.
4017 if (sva + L2_SIZE == va_next && eva >= va_next) {
4018 pmap_clear_bits(l2, ATTR_SW_WIRED);
4019 pmap->pm_stats.wired_count -= L2_SIZE /
4022 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
4023 panic("pmap_unwire: demotion failed");
4025 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
4026 ("pmap_unwire: Invalid l2 entry after demotion"));
4030 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
4032 if (pmap_load(l3) == 0)
4034 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
4035 panic("pmap_unwire: l3 %#jx is missing "
4036 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
4039 * ATTR_SW_WIRED must be cleared atomically. Although
4040 * the pmap lock synchronizes access to ATTR_SW_WIRED,
4041 * the System MMU may write to the entry concurrently.
4043 pmap_clear_bits(l3, ATTR_SW_WIRED);
4044 pmap->pm_stats.wired_count--;
4051 * Copy the range specified by src_addr/len
4052 * from the source map to the range dst_addr/len
4053 * in the destination map.
4055 * This routine is only advisory and need not do anything.
4057 * Because the executable mappings created by this routine are copied,
4058 * it should not have to flush the instruction cache.
4061 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4062 vm_offset_t src_addr)
4064 struct rwlock *lock;
4065 pd_entry_t *l0, *l1, *l2, srcptepaddr;
4066 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
4067 vm_offset_t addr, end_addr, va_next;
4068 vm_page_t dst_l2pg, dstmpte, srcmpte;
4070 PMAP_ASSERT_STAGE1(dst_pmap);
4071 PMAP_ASSERT_STAGE1(src_pmap);
4073 if (dst_addr != src_addr)
4075 end_addr = src_addr + len;
4077 if (dst_pmap < src_pmap) {
4078 PMAP_LOCK(dst_pmap);
4079 PMAP_LOCK(src_pmap);
4081 PMAP_LOCK(src_pmap);
4082 PMAP_LOCK(dst_pmap);
4084 for (addr = src_addr; addr < end_addr; addr = va_next) {
4085 l0 = pmap_l0(src_pmap, addr);
4086 if (pmap_load(l0) == 0) {
4087 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
4092 l1 = pmap_l0_to_l1(l0, addr);
4093 if (pmap_load(l1) == 0) {
4094 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
4099 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
4102 l2 = pmap_l1_to_l2(l1, addr);
4103 srcptepaddr = pmap_load(l2);
4104 if (srcptepaddr == 0)
4106 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
4107 if ((addr & L2_OFFSET) != 0 ||
4108 addr + L2_SIZE > end_addr)
4110 l2 = pmap_alloc_l2(dst_pmap, addr, &dst_l2pg, NULL);
4113 if (pmap_load(l2) == 0 &&
4114 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
4115 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
4116 PMAP_ENTER_NORECLAIM, &lock))) {
4117 mask = ATTR_AF | ATTR_SW_WIRED;
4119 if ((srcptepaddr & ATTR_SW_DBM) != 0)
4120 nbits |= ATTR_S1_AP_RW_BIT;
4121 pmap_store(l2, (srcptepaddr & ~mask) | nbits);
4122 pmap_resident_count_inc(dst_pmap, L2_SIZE /
4124 atomic_add_long(&pmap_l2_mappings, 1);
4126 pmap_abort_ptp(dst_pmap, addr, dst_l2pg);
4129 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
4130 ("pmap_copy: invalid L2 entry"));
4131 srcptepaddr &= ~ATTR_MASK;
4132 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4133 KASSERT(srcmpte->ref_count > 0,
4134 ("pmap_copy: source page table page is unused"));
4135 if (va_next > end_addr)
4137 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4138 src_pte = &src_pte[pmap_l3_index(addr)];
4140 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
4141 ptetemp = pmap_load(src_pte);
4144 * We only virtual copy managed pages.
4146 if ((ptetemp & ATTR_SW_MANAGED) == 0)
4149 if (dstmpte != NULL) {
4150 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
4151 ("dstmpte pindex/addr mismatch"));
4152 dstmpte->ref_count++;
4153 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
4156 dst_pte = (pt_entry_t *)
4157 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4158 dst_pte = &dst_pte[pmap_l3_index(addr)];
4159 if (pmap_load(dst_pte) == 0 &&
4160 pmap_try_insert_pv_entry(dst_pmap, addr,
4161 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
4163 * Clear the wired, modified, and accessed
4164 * (referenced) bits during the copy.
4166 mask = ATTR_AF | ATTR_SW_WIRED;
4168 if ((ptetemp & ATTR_SW_DBM) != 0)
4169 nbits |= ATTR_S1_AP_RW_BIT;
4170 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
4171 pmap_resident_count_inc(dst_pmap, 1);
4173 pmap_abort_ptp(dst_pmap, addr, dstmpte);
4176 /* Have we copied all of the valid mappings? */
4177 if (dstmpte->ref_count >= srcmpte->ref_count)
4183 * XXX This barrier may not be needed because the destination pmap is
4190 PMAP_UNLOCK(src_pmap);
4191 PMAP_UNLOCK(dst_pmap);
4195 * pmap_zero_page zeros the specified hardware page by mapping
4196 * the page into KVM and using bzero to clear its contents.
4199 pmap_zero_page(vm_page_t m)
4201 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4203 pagezero((void *)va);
4207 * pmap_zero_page_area zeros the specified hardware page by mapping
4208 * the page into KVM and using bzero to clear its contents.
4210 * off and size may not cover an area beyond a single hardware page.
4213 pmap_zero_page_area(vm_page_t m, int off, int size)
4215 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4217 if (off == 0 && size == PAGE_SIZE)
4218 pagezero((void *)va);
4220 bzero((char *)va + off, size);
4224 * pmap_copy_page copies the specified (machine independent)
4225 * page by mapping the page into virtual memory and using
4226 * bcopy to copy the page, one machine dependent page at a
4230 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4232 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4233 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4235 pagecopy((void *)src, (void *)dst);
4238 int unmapped_buf_allowed = 1;
4241 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4242 vm_offset_t b_offset, int xfersize)
4246 vm_paddr_t p_a, p_b;
4247 vm_offset_t a_pg_offset, b_pg_offset;
4250 while (xfersize > 0) {
4251 a_pg_offset = a_offset & PAGE_MASK;
4252 m_a = ma[a_offset >> PAGE_SHIFT];
4253 p_a = m_a->phys_addr;
4254 b_pg_offset = b_offset & PAGE_MASK;
4255 m_b = mb[b_offset >> PAGE_SHIFT];
4256 p_b = m_b->phys_addr;
4257 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4258 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4259 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
4260 panic("!DMAP a %lx", p_a);
4262 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
4264 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
4265 panic("!DMAP b %lx", p_b);
4267 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
4269 bcopy(a_cp, b_cp, cnt);
4277 pmap_quick_enter_page(vm_page_t m)
4280 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
4284 pmap_quick_remove_page(vm_offset_t addr)
4289 * Returns true if the pmap's pv is one of the first
4290 * 16 pvs linked to from this page. This count may
4291 * be changed upwards or downwards in the future; it
4292 * is only necessary that true be returned for a small
4293 * subset of pmaps for proper page aging.
4296 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4298 struct md_page *pvh;
4299 struct rwlock *lock;
4304 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4305 ("pmap_page_exists_quick: page %p is not managed", m));
4307 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4309 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4310 if (PV_PMAP(pv) == pmap) {
4318 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4319 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4320 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4321 if (PV_PMAP(pv) == pmap) {
4335 * pmap_page_wired_mappings:
4337 * Return the number of managed mappings to the given physical page
4341 pmap_page_wired_mappings(vm_page_t m)
4343 struct rwlock *lock;
4344 struct md_page *pvh;
4348 int count, lvl, md_gen, pvh_gen;
4350 if ((m->oflags & VPO_UNMANAGED) != 0)
4352 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4356 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4358 if (!PMAP_TRYLOCK(pmap)) {
4359 md_gen = m->md.pv_gen;
4363 if (md_gen != m->md.pv_gen) {
4368 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4369 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4373 if ((m->flags & PG_FICTITIOUS) == 0) {
4374 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4375 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4377 if (!PMAP_TRYLOCK(pmap)) {
4378 md_gen = m->md.pv_gen;
4379 pvh_gen = pvh->pv_gen;
4383 if (md_gen != m->md.pv_gen ||
4384 pvh_gen != pvh->pv_gen) {
4389 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4391 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4401 * Returns true if the given page is mapped individually or as part of
4402 * a 2mpage. Otherwise, returns false.
4405 pmap_page_is_mapped(vm_page_t m)
4407 struct rwlock *lock;
4410 if ((m->oflags & VPO_UNMANAGED) != 0)
4412 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4414 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4415 ((m->flags & PG_FICTITIOUS) == 0 &&
4416 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4422 * Destroy all managed, non-wired mappings in the given user-space
4423 * pmap. This pmap cannot be active on any processor besides the
4426 * This function cannot be applied to the kernel pmap. Moreover, it
4427 * is not intended for general use. It is only to be used during
4428 * process termination. Consequently, it can be implemented in ways
4429 * that make it faster than pmap_remove(). First, it can more quickly
4430 * destroy mappings by iterating over the pmap's collection of PV
4431 * entries, rather than searching the page table. Second, it doesn't
4432 * have to test and clear the page table entries atomically, because
4433 * no processor is currently accessing the user address space. In
4434 * particular, a page table entry's dirty bit won't change state once
4435 * this function starts.
4438 pmap_remove_pages(pmap_t pmap)
4441 pt_entry_t *pte, tpte;
4442 struct spglist free;
4443 vm_page_t m, ml3, mt;
4445 struct md_page *pvh;
4446 struct pv_chunk *pc, *npc;
4447 struct rwlock *lock;
4449 uint64_t inuse, bitmask;
4450 int allfree, field, freed, idx, lvl;
4453 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
4459 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4462 for (field = 0; field < _NPCM; field++) {
4463 inuse = ~pc->pc_map[field] & pc_freemask[field];
4464 while (inuse != 0) {
4465 bit = ffsl(inuse) - 1;
4466 bitmask = 1UL << bit;
4467 idx = field * 64 + bit;
4468 pv = &pc->pc_pventry[idx];
4471 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4472 KASSERT(pde != NULL,
4473 ("Attempting to remove an unmapped page"));
4477 pte = pmap_l1_to_l2(pde, pv->pv_va);
4478 tpte = pmap_load(pte);
4479 KASSERT((tpte & ATTR_DESCR_MASK) ==
4481 ("Attempting to remove an invalid "
4482 "block: %lx", tpte));
4485 pte = pmap_l2_to_l3(pde, pv->pv_va);
4486 tpte = pmap_load(pte);
4487 KASSERT((tpte & ATTR_DESCR_MASK) ==
4489 ("Attempting to remove an invalid "
4490 "page: %lx", tpte));
4494 "Invalid page directory level: %d",
4499 * We cannot remove wired pages from a process' mapping at this time
4501 if (tpte & ATTR_SW_WIRED) {
4506 pa = tpte & ~ATTR_MASK;
4508 m = PHYS_TO_VM_PAGE(pa);
4509 KASSERT(m->phys_addr == pa,
4510 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4511 m, (uintmax_t)m->phys_addr,
4514 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4515 m < &vm_page_array[vm_page_array_size],
4516 ("pmap_remove_pages: bad pte %#jx",
4520 * Because this pmap is not active on other
4521 * processors, the dirty bit cannot have
4522 * changed state since we last loaded pte.
4527 * Update the vm_page_t clean/reference bits.
4529 if (pmap_pte_dirty(pmap, tpte)) {
4532 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4541 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4544 pc->pc_map[field] |= bitmask;
4547 pmap_resident_count_dec(pmap,
4548 L2_SIZE / PAGE_SIZE);
4549 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
4550 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
4552 if (TAILQ_EMPTY(&pvh->pv_list)) {
4553 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4554 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
4555 TAILQ_EMPTY(&mt->md.pv_list))
4556 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4558 ml3 = pmap_remove_pt_page(pmap,
4561 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
4562 ("pmap_remove_pages: l3 page not promoted"));
4563 pmap_resident_count_dec(pmap,1);
4564 KASSERT(ml3->ref_count == NL3PG,
4565 ("pmap_remove_pages: l3 page ref count error"));
4567 pmap_add_delayed_free_list(ml3,
4572 pmap_resident_count_dec(pmap, 1);
4573 TAILQ_REMOVE(&m->md.pv_list, pv,
4576 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
4577 TAILQ_EMPTY(&m->md.pv_list) &&
4578 (m->flags & PG_FICTITIOUS) == 0) {
4580 VM_PAGE_TO_PHYS(m));
4581 if (TAILQ_EMPTY(&pvh->pv_list))
4582 vm_page_aflag_clear(m,
4587 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
4592 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4593 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4594 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4596 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4602 pmap_invalidate_all(pmap);
4604 vm_page_free_pages_toq(&free, true);
4608 * This is used to check if a page has been accessed or modified.
4611 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
4613 struct rwlock *lock;
4615 struct md_page *pvh;
4616 pt_entry_t *pte, mask, value;
4618 int lvl, md_gen, pvh_gen;
4622 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4625 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4627 PMAP_ASSERT_STAGE1(pmap);
4628 if (!PMAP_TRYLOCK(pmap)) {
4629 md_gen = m->md.pv_gen;
4633 if (md_gen != m->md.pv_gen) {
4638 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4640 ("pmap_page_test_mappings: Invalid level %d", lvl));
4644 mask |= ATTR_S1_AP_RW_BIT;
4645 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
4648 mask |= ATTR_AF | ATTR_DESCR_MASK;
4649 value |= ATTR_AF | L3_PAGE;
4651 rv = (pmap_load(pte) & mask) == value;
4656 if ((m->flags & PG_FICTITIOUS) == 0) {
4657 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4658 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4660 PMAP_ASSERT_STAGE1(pmap);
4661 if (!PMAP_TRYLOCK(pmap)) {
4662 md_gen = m->md.pv_gen;
4663 pvh_gen = pvh->pv_gen;
4667 if (md_gen != m->md.pv_gen ||
4668 pvh_gen != pvh->pv_gen) {
4673 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4675 ("pmap_page_test_mappings: Invalid level %d", lvl));
4679 mask |= ATTR_S1_AP_RW_BIT;
4680 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
4683 mask |= ATTR_AF | ATTR_DESCR_MASK;
4684 value |= ATTR_AF | L2_BLOCK;
4686 rv = (pmap_load(pte) & mask) == value;
4700 * Return whether or not the specified physical page was modified
4701 * in any physical maps.
4704 pmap_is_modified(vm_page_t m)
4707 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4708 ("pmap_is_modified: page %p is not managed", m));
4711 * If the page is not busied then this check is racy.
4713 if (!pmap_page_is_write_mapped(m))
4715 return (pmap_page_test_mappings(m, FALSE, TRUE));
4719 * pmap_is_prefaultable:
4721 * Return whether or not the specified virtual address is eligible
4725 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4733 pte = pmap_pte(pmap, addr, &lvl);
4734 if (pte != NULL && pmap_load(pte) != 0) {
4742 * pmap_is_referenced:
4744 * Return whether or not the specified physical page was referenced
4745 * in any physical maps.
4748 pmap_is_referenced(vm_page_t m)
4751 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4752 ("pmap_is_referenced: page %p is not managed", m));
4753 return (pmap_page_test_mappings(m, TRUE, FALSE));
4757 * Clear the write and modified bits in each of the given page's mappings.
4760 pmap_remove_write(vm_page_t m)
4762 struct md_page *pvh;
4764 struct rwlock *lock;
4765 pv_entry_t next_pv, pv;
4766 pt_entry_t oldpte, *pte;
4768 int lvl, md_gen, pvh_gen;
4770 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4771 ("pmap_remove_write: page %p is not managed", m));
4772 vm_page_assert_busied(m);
4774 if (!pmap_page_is_write_mapped(m))
4776 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4777 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4778 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4781 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4783 PMAP_ASSERT_STAGE1(pmap);
4784 if (!PMAP_TRYLOCK(pmap)) {
4785 pvh_gen = pvh->pv_gen;
4789 if (pvh_gen != pvh->pv_gen) {
4796 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4797 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
4798 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
4799 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4800 ("inconsistent pv lock %p %p for page %p",
4801 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4804 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4806 PMAP_ASSERT_STAGE1(pmap);
4807 if (!PMAP_TRYLOCK(pmap)) {
4808 pvh_gen = pvh->pv_gen;
4809 md_gen = m->md.pv_gen;
4813 if (pvh_gen != pvh->pv_gen ||
4814 md_gen != m->md.pv_gen) {
4820 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4821 oldpte = pmap_load(pte);
4823 if ((oldpte & ATTR_SW_DBM) != 0) {
4824 if (!atomic_fcmpset_long(pte, &oldpte,
4825 (oldpte | ATTR_S1_AP_RW_BIT) & ~ATTR_SW_DBM))
4827 if ((oldpte & ATTR_S1_AP_RW_BIT) ==
4828 ATTR_S1_AP(ATTR_S1_AP_RW))
4830 pmap_invalidate_page(pmap, pv->pv_va);
4835 vm_page_aflag_clear(m, PGA_WRITEABLE);
4839 * pmap_ts_referenced:
4841 * Return a count of reference bits for a page, clearing those bits.
4842 * It is not necessary for every reference bit to be cleared, but it
4843 * is necessary that 0 only be returned when there are truly no
4844 * reference bits set.
4846 * As an optimization, update the page's dirty field if a modified bit is
4847 * found while counting reference bits. This opportunistic update can be
4848 * performed at low cost and can eliminate the need for some future calls
4849 * to pmap_is_modified(). However, since this function stops after
4850 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4851 * dirty pages. Those dirty pages will only be detected by a future call
4852 * to pmap_is_modified().
4855 pmap_ts_referenced(vm_page_t m)
4857 struct md_page *pvh;
4860 struct rwlock *lock;
4861 pd_entry_t *pde, tpde;
4862 pt_entry_t *pte, tpte;
4865 int cleared, lvl, md_gen, not_cleared, pvh_gen;
4866 struct spglist free;
4868 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4869 ("pmap_ts_referenced: page %p is not managed", m));
4872 pa = VM_PAGE_TO_PHYS(m);
4873 lock = PHYS_TO_PV_LIST_LOCK(pa);
4874 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4878 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4879 goto small_mappings;
4885 if (!PMAP_TRYLOCK(pmap)) {
4886 pvh_gen = pvh->pv_gen;
4890 if (pvh_gen != pvh->pv_gen) {
4896 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4897 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4899 ("pmap_ts_referenced: invalid pde level %d", lvl));
4900 tpde = pmap_load(pde);
4901 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4902 ("pmap_ts_referenced: found an invalid l1 table"));
4903 pte = pmap_l1_to_l2(pde, pv->pv_va);
4904 tpte = pmap_load(pte);
4905 if (pmap_pte_dirty(pmap, tpte)) {
4907 * Although "tpte" is mapping a 2MB page, because
4908 * this function is called at a 4KB page granularity,
4909 * we only update the 4KB page under test.
4914 if ((tpte & ATTR_AF) != 0) {
4916 * Since this reference bit is shared by 512 4KB pages,
4917 * it should not be cleared every time it is tested.
4918 * Apply a simple "hash" function on the physical page
4919 * number, the virtual superpage number, and the pmap
4920 * address to select one 4KB page out of the 512 on
4921 * which testing the reference bit will result in
4922 * clearing that reference bit. This function is
4923 * designed to avoid the selection of the same 4KB page
4924 * for every 2MB page mapping.
4926 * On demotion, a mapping that hasn't been referenced
4927 * is simply destroyed. To avoid the possibility of a
4928 * subsequent page fault on a demoted wired mapping,
4929 * always leave its reference bit set. Moreover,
4930 * since the superpage is wired, the current state of
4931 * its reference bit won't affect page replacement.
4933 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4934 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4935 (tpte & ATTR_SW_WIRED) == 0) {
4936 pmap_clear_bits(pte, ATTR_AF);
4937 pmap_invalidate_page(pmap, pv->pv_va);
4943 /* Rotate the PV list if it has more than one entry. */
4944 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4945 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4946 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4949 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4951 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4953 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4960 if (!PMAP_TRYLOCK(pmap)) {
4961 pvh_gen = pvh->pv_gen;
4962 md_gen = m->md.pv_gen;
4966 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4971 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4972 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4974 ("pmap_ts_referenced: invalid pde level %d", lvl));
4975 tpde = pmap_load(pde);
4976 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4977 ("pmap_ts_referenced: found an invalid l2 table"));
4978 pte = pmap_l2_to_l3(pde, pv->pv_va);
4979 tpte = pmap_load(pte);
4980 if (pmap_pte_dirty(pmap, tpte))
4982 if ((tpte & ATTR_AF) != 0) {
4983 if ((tpte & ATTR_SW_WIRED) == 0) {
4984 pmap_clear_bits(pte, ATTR_AF);
4985 pmap_invalidate_page(pmap, pv->pv_va);
4991 /* Rotate the PV list if it has more than one entry. */
4992 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4993 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4994 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4997 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4998 not_cleared < PMAP_TS_REFERENCED_MAX);
5001 vm_page_free_pages_toq(&free, true);
5002 return (cleared + not_cleared);
5006 * Apply the given advice to the specified range of addresses within the
5007 * given pmap. Depending on the advice, clear the referenced and/or
5008 * modified flags in each mapping and set the mapped page's dirty field.
5011 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5013 struct rwlock *lock;
5014 vm_offset_t va, va_next;
5016 pd_entry_t *l0, *l1, *l2, oldl2;
5017 pt_entry_t *l3, oldl3;
5019 PMAP_ASSERT_STAGE1(pmap);
5021 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5025 for (; sva < eva; sva = va_next) {
5026 l0 = pmap_l0(pmap, sva);
5027 if (pmap_load(l0) == 0) {
5028 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
5033 l1 = pmap_l0_to_l1(l0, sva);
5034 if (pmap_load(l1) == 0) {
5035 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
5040 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
5043 l2 = pmap_l1_to_l2(l1, sva);
5044 oldl2 = pmap_load(l2);
5047 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
5048 if ((oldl2 & ATTR_SW_MANAGED) == 0)
5051 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
5056 * The 2MB page mapping was destroyed.
5062 * Unless the page mappings are wired, remove the
5063 * mapping to a single page so that a subsequent
5064 * access may repromote. Choosing the last page
5065 * within the address range [sva, min(va_next, eva))
5066 * generally results in more repromotions. Since the
5067 * underlying page table page is fully populated, this
5068 * removal never frees a page table page.
5070 if ((oldl2 & ATTR_SW_WIRED) == 0) {
5076 ("pmap_advise: no address gap"));
5077 l3 = pmap_l2_to_l3(l2, va);
5078 KASSERT(pmap_load(l3) != 0,
5079 ("pmap_advise: invalid PTE"));
5080 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
5086 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
5087 ("pmap_advise: invalid L2 entry after demotion"));
5091 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
5093 oldl3 = pmap_load(l3);
5094 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
5095 (ATTR_SW_MANAGED | L3_PAGE))
5097 else if (pmap_pte_dirty(pmap, oldl3)) {
5098 if (advice == MADV_DONTNEED) {
5100 * Future calls to pmap_is_modified()
5101 * can be avoided by making the page
5104 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK);
5107 while (!atomic_fcmpset_long(l3, &oldl3,
5108 (oldl3 & ~ATTR_AF) |
5109 ATTR_S1_AP(ATTR_S1_AP_RO)))
5111 } else if ((oldl3 & ATTR_AF) != 0)
5112 pmap_clear_bits(l3, ATTR_AF);
5119 if (va != va_next) {
5120 pmap_invalidate_range(pmap, va, sva);
5125 pmap_invalidate_range(pmap, va, sva);
5131 * Clear the modify bits on the specified physical page.
5134 pmap_clear_modify(vm_page_t m)
5136 struct md_page *pvh;
5137 struct rwlock *lock;
5139 pv_entry_t next_pv, pv;
5140 pd_entry_t *l2, oldl2;
5141 pt_entry_t *l3, oldl3;
5143 int md_gen, pvh_gen;
5145 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5146 ("pmap_clear_modify: page %p is not managed", m));
5147 vm_page_assert_busied(m);
5149 if (!pmap_page_is_write_mapped(m))
5151 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5152 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5153 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5156 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5158 PMAP_ASSERT_STAGE1(pmap);
5159 if (!PMAP_TRYLOCK(pmap)) {
5160 pvh_gen = pvh->pv_gen;
5164 if (pvh_gen != pvh->pv_gen) {
5170 l2 = pmap_l2(pmap, va);
5171 oldl2 = pmap_load(l2);
5172 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */
5173 if ((oldl2 & ATTR_SW_DBM) != 0 &&
5174 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
5175 (oldl2 & ATTR_SW_WIRED) == 0) {
5177 * Write protect the mapping to a single page so that
5178 * a subsequent write access may repromote.
5180 va += VM_PAGE_TO_PHYS(m) - (oldl2 & ~ATTR_MASK);
5181 l3 = pmap_l2_to_l3(l2, va);
5182 oldl3 = pmap_load(l3);
5183 while (!atomic_fcmpset_long(l3, &oldl3,
5184 (oldl3 & ~ATTR_SW_DBM) | ATTR_S1_AP(ATTR_S1_AP_RO)))
5187 pmap_invalidate_page(pmap, va);
5191 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5193 PMAP_ASSERT_STAGE1(pmap);
5194 if (!PMAP_TRYLOCK(pmap)) {
5195 md_gen = m->md.pv_gen;
5196 pvh_gen = pvh->pv_gen;
5200 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5205 l2 = pmap_l2(pmap, pv->pv_va);
5206 l3 = pmap_l2_to_l3(l2, pv->pv_va);
5207 oldl3 = pmap_load(l3);
5208 if (pmap_l3_valid(oldl3) &&
5209 (oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM){
5210 pmap_set_bits(l3, ATTR_S1_AP(ATTR_S1_AP_RO));
5211 pmap_invalidate_page(pmap, pv->pv_va);
5219 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5221 struct pmap_preinit_mapping *ppim;
5222 vm_offset_t va, offset;
5225 int i, lvl, l2_blocks, free_l2_count, start_idx;
5227 if (!vm_initialized) {
5229 * No L3 ptables so map entire L2 blocks where start VA is:
5230 * preinit_map_va + start_idx * L2_SIZE
5231 * There may be duplicate mappings (multiple VA -> same PA) but
5232 * ARM64 dcache is always PIPT so that's acceptable.
5237 /* Calculate how many L2 blocks are needed for the mapping */
5238 l2_blocks = (roundup2(pa + size, L2_SIZE) -
5239 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
5241 offset = pa & L2_OFFSET;
5243 if (preinit_map_va == 0)
5246 /* Map 2MiB L2 blocks from reserved VA space */
5250 /* Find enough free contiguous VA space */
5251 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5252 ppim = pmap_preinit_mapping + i;
5253 if (free_l2_count > 0 && ppim->pa != 0) {
5254 /* Not enough space here */
5260 if (ppim->pa == 0) {
5262 if (start_idx == -1)
5265 if (free_l2_count == l2_blocks)
5269 if (free_l2_count != l2_blocks)
5270 panic("%s: too many preinit mappings", __func__);
5272 va = preinit_map_va + (start_idx * L2_SIZE);
5273 for (i = start_idx; i < start_idx + l2_blocks; i++) {
5274 /* Mark entries as allocated */
5275 ppim = pmap_preinit_mapping + i;
5277 ppim->va = va + offset;
5282 pa = rounddown2(pa, L2_SIZE);
5283 for (i = 0; i < l2_blocks; i++) {
5284 pde = pmap_pde(kernel_pmap, va, &lvl);
5285 KASSERT(pde != NULL,
5286 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
5289 ("pmap_mapbios: Invalid level %d", lvl));
5291 /* Insert L2_BLOCK */
5292 l2 = pmap_l1_to_l2(pde, va);
5294 pa | ATTR_DEFAULT | ATTR_S1_XN |
5295 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
5300 pmap_invalidate_all(kernel_pmap);
5302 va = preinit_map_va + (start_idx * L2_SIZE);
5305 /* kva_alloc may be used to map the pages */
5306 offset = pa & PAGE_MASK;
5307 size = round_page(offset + size);
5309 va = kva_alloc(size);
5311 panic("%s: Couldn't allocate KVA", __func__);
5313 pde = pmap_pde(kernel_pmap, va, &lvl);
5314 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
5316 /* L3 table is linked */
5317 va = trunc_page(va);
5318 pa = trunc_page(pa);
5319 pmap_kenter(va, size, pa, VM_MEMATTR_WRITE_BACK);
5322 return ((void *)(va + offset));
5326 pmap_unmapbios(vm_offset_t va, vm_size_t size)
5328 struct pmap_preinit_mapping *ppim;
5329 vm_offset_t offset, tmpsize, va_trunc;
5332 int i, lvl, l2_blocks, block;
5336 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
5337 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
5339 /* Remove preinit mapping */
5340 preinit_map = false;
5342 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5343 ppim = pmap_preinit_mapping + i;
5344 if (ppim->va == va) {
5345 KASSERT(ppim->size == size,
5346 ("pmap_unmapbios: size mismatch"));
5351 offset = block * L2_SIZE;
5352 va_trunc = rounddown2(va, L2_SIZE) + offset;
5354 /* Remove L2_BLOCK */
5355 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
5356 KASSERT(pde != NULL,
5357 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
5359 l2 = pmap_l1_to_l2(pde, va_trunc);
5362 if (block == (l2_blocks - 1))
5368 pmap_invalidate_all(kernel_pmap);
5372 /* Unmap the pages reserved with kva_alloc. */
5373 if (vm_initialized) {
5374 offset = va & PAGE_MASK;
5375 size = round_page(offset + size);
5376 va = trunc_page(va);
5378 pde = pmap_pde(kernel_pmap, va, &lvl);
5379 KASSERT(pde != NULL,
5380 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
5381 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
5383 /* Unmap and invalidate the pages */
5384 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5385 pmap_kremove(va + tmpsize);
5392 * Sets the memory attribute for the specified page.
5395 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5398 m->md.pv_memattr = ma;
5401 * If "m" is a normal page, update its direct mapping. This update
5402 * can be relied upon to perform any cache operations that are
5403 * required for data coherence.
5405 if ((m->flags & PG_FICTITIOUS) == 0 &&
5406 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
5407 m->md.pv_memattr) != 0)
5408 panic("memory attribute change on the direct map failed");
5412 * Changes the specified virtual address range's memory type to that given by
5413 * the parameter "mode". The specified virtual address range must be
5414 * completely contained within either the direct map or the kernel map. If
5415 * the virtual address range is contained within the kernel map, then the
5416 * memory type for each of the corresponding ranges of the direct map is also
5417 * changed. (The corresponding ranges of the direct map are those ranges that
5418 * map the same physical pages as the specified virtual address range.) These
5419 * changes to the direct map are necessary because Intel describes the
5420 * behavior of their processors as "undefined" if two or more mappings to the
5421 * same physical page have different memory types.
5423 * Returns zero if the change completed successfully, and either EINVAL or
5424 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5425 * of the virtual address range was not mapped, and ENOMEM is returned if
5426 * there was insufficient memory available to complete the change. In the
5427 * latter case, the memory type may have been changed on some part of the
5428 * virtual address range or the direct map.
5431 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5435 PMAP_LOCK(kernel_pmap);
5436 error = pmap_change_attr_locked(va, size, mode);
5437 PMAP_UNLOCK(kernel_pmap);
5442 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
5444 vm_offset_t base, offset, tmpva;
5445 pt_entry_t l3, *pte, *newpte;
5448 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
5449 base = trunc_page(va);
5450 offset = va & PAGE_MASK;
5451 size = round_page(offset + size);
5453 if (!VIRT_IN_DMAP(base) &&
5454 !(base >= VM_MIN_KERNEL_ADDRESS && base < VM_MAX_KERNEL_ADDRESS))
5457 for (tmpva = base; tmpva < base + size; ) {
5458 pte = pmap_pte(kernel_pmap, tmpva, &lvl);
5462 if ((pmap_load(pte) & ATTR_S1_IDX_MASK) == ATTR_S1_IDX(mode)) {
5464 * We already have the correct attribute,
5465 * ignore this entry.
5469 panic("Invalid DMAP table level: %d\n", lvl);
5471 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
5474 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
5482 * Split the entry to an level 3 table, then
5483 * set the new attribute.
5487 panic("Invalid DMAP table level: %d\n", lvl);
5489 newpte = pmap_demote_l1(kernel_pmap, pte,
5490 tmpva & ~L1_OFFSET);
5493 pte = pmap_l1_to_l2(pte, tmpva);
5495 newpte = pmap_demote_l2(kernel_pmap, pte,
5499 pte = pmap_l2_to_l3(pte, tmpva);
5501 /* Update the entry */
5502 l3 = pmap_load(pte);
5503 l3 &= ~ATTR_S1_IDX_MASK;
5504 l3 |= ATTR_S1_IDX(mode);
5505 if (mode == VM_MEMATTR_DEVICE)
5508 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
5512 * If moving to a non-cacheable entry flush
5515 if (mode == VM_MEMATTR_UNCACHEABLE)
5516 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
5528 * Create an L2 table to map all addresses within an L1 mapping.
5531 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
5533 pt_entry_t *l2, newl2, oldl1;
5535 vm_paddr_t l2phys, phys;
5539 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5540 oldl1 = pmap_load(l1);
5541 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
5542 ("pmap_demote_l1: Demoting a non-block entry"));
5543 KASSERT((va & L1_OFFSET) == 0,
5544 ("pmap_demote_l1: Invalid virtual address %#lx", va));
5545 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
5546 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
5549 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
5550 tmpl1 = kva_alloc(PAGE_SIZE);
5555 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
5556 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
5557 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
5558 " in pmap %p", va, pmap);
5562 l2phys = VM_PAGE_TO_PHYS(ml2);
5563 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
5565 /* Address the range points at */
5566 phys = oldl1 & ~ATTR_MASK;
5567 /* The attributed from the old l1 table to be copied */
5568 newl2 = oldl1 & ATTR_MASK;
5570 /* Create the new entries */
5571 for (i = 0; i < Ln_ENTRIES; i++) {
5572 l2[i] = newl2 | phys;
5575 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
5576 ("Invalid l2 page (%lx != %lx)", l2[0],
5577 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
5580 pmap_kenter(tmpl1, PAGE_SIZE,
5581 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET,
5582 VM_MEMATTR_WRITE_BACK);
5583 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
5586 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
5589 pmap_kremove(tmpl1);
5590 kva_free(tmpl1, PAGE_SIZE);
5597 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
5601 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
5608 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
5609 struct rwlock **lockp)
5611 struct spglist free;
5614 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
5616 vm_page_free_pages_toq(&free, true);
5620 * Create an L3 table to map all addresses within an L2 mapping.
5623 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
5624 struct rwlock **lockp)
5626 pt_entry_t *l3, newl3, oldl2;
5631 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5632 PMAP_ASSERT_STAGE1(pmap);
5634 oldl2 = pmap_load(l2);
5635 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
5636 ("pmap_demote_l2: Demoting a non-block entry"));
5640 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
5641 tmpl2 = kva_alloc(PAGE_SIZE);
5647 * Invalidate the 2MB page mapping and return "failure" if the
5648 * mapping was never accessed.
5650 if ((oldl2 & ATTR_AF) == 0) {
5651 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5652 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
5653 pmap_demote_l2_abort(pmap, va, l2, lockp);
5654 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
5659 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
5660 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5661 ("pmap_demote_l2: page table page for a wired mapping"
5665 * If the page table page is missing and the mapping
5666 * is for a kernel address, the mapping must belong to
5667 * the direct map. Page table pages are preallocated
5668 * for every other part of the kernel address space,
5669 * so the direct map region is the only part of the
5670 * kernel address space that must be handled here.
5672 KASSERT(va < VM_MAXUSER_ADDRESS || VIRT_IN_DMAP(va),
5673 ("pmap_demote_l2: No saved mpte for va %#lx", va));
5676 * If the 2MB page mapping belongs to the direct map
5677 * region of the kernel's address space, then the page
5678 * allocation request specifies the highest possible
5679 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5680 * priority is normal.
5682 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
5683 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5684 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5687 * If the allocation of the new page table page fails,
5688 * invalidate the 2MB page mapping and return "failure".
5691 pmap_demote_l2_abort(pmap, va, l2, lockp);
5692 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
5693 " in pmap %p", va, pmap);
5697 if (va < VM_MAXUSER_ADDRESS) {
5698 ml3->ref_count = NL3PG;
5699 pmap_resident_count_inc(pmap, 1);
5702 l3phys = VM_PAGE_TO_PHYS(ml3);
5703 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
5704 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
5705 KASSERT((oldl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) !=
5706 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM),
5707 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
5710 * If the page table page is not leftover from an earlier promotion,
5711 * or the mapping attributes have changed, (re)initialize the L3 table.
5713 * When pmap_update_entry() clears the old L2 mapping, it (indirectly)
5714 * performs a dsb(). That dsb() ensures that the stores for filling
5715 * "l3" are visible before "l3" is added to the page table.
5717 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK))
5718 pmap_fill_l3(l3, newl3);
5721 * Map the temporary page so we don't lose access to the l2 table.
5724 pmap_kenter(tmpl2, PAGE_SIZE,
5725 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET,
5726 VM_MEMATTR_WRITE_BACK);
5727 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
5731 * The spare PV entries must be reserved prior to demoting the
5732 * mapping, that is, prior to changing the PDE. Otherwise, the state
5733 * of the L2 and the PV lists will be inconsistent, which can result
5734 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5735 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
5736 * PV entry for the 2MB page mapping that is being demoted.
5738 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5739 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
5742 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
5743 * the 2MB page mapping.
5745 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
5748 * Demote the PV entry.
5750 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5751 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
5753 atomic_add_long(&pmap_l2_demotions, 1);
5754 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
5755 " in pmap %p %lx", va, pmap, l3[0]);
5759 pmap_kremove(tmpl2);
5760 kva_free(tmpl2, PAGE_SIZE);
5768 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
5770 struct rwlock *lock;
5774 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
5781 * Perform the pmap work for mincore(2). If the page is not both referenced and
5782 * modified by this pmap, returns its physical address so that the caller can
5783 * find other mappings.
5786 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
5788 pt_entry_t *pte, tpte;
5789 vm_paddr_t mask, pa;
5793 PMAP_ASSERT_STAGE1(pmap);
5795 pte = pmap_pte(pmap, addr, &lvl);
5797 tpte = pmap_load(pte);
5810 panic("pmap_mincore: invalid level %d", lvl);
5813 managed = (tpte & ATTR_SW_MANAGED) != 0;
5814 val = MINCORE_INCORE;
5816 val |= MINCORE_SUPER;
5817 if ((managed && pmap_pte_dirty(pmap, tpte)) || (!managed &&
5818 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW)))
5819 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5820 if ((tpte & ATTR_AF) == ATTR_AF)
5821 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5823 pa = (tpte & ~ATTR_MASK) | (addr & mask);
5829 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5830 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
5838 * Garbage collect every ASID that is neither active on a processor nor
5842 pmap_reset_asid_set(void)
5845 int asid, cpuid, epoch;
5847 mtx_assert(&asid_set_mutex, MA_OWNED);
5850 * Ensure that the store to asid_epoch is globally visible before the
5851 * loads from pc_curpmap are performed.
5853 epoch = asid_epoch + 1;
5854 if (epoch == INT_MAX)
5858 __asm __volatile("tlbi vmalle1is");
5860 bit_nclear(asid_set, ASID_FIRST_AVAILABLE, asid_set_size - 1);
5861 CPU_FOREACH(cpuid) {
5862 if (cpuid == curcpu)
5864 pmap = pcpu_find(cpuid)->pc_curpmap;
5865 PMAP_ASSERT_STAGE1(pmap);
5866 asid = COOKIE_TO_ASID(pmap->pm_cookie);
5869 bit_set(asid_set, asid);
5870 pmap->pm_cookie = COOKIE_FROM(asid, epoch);
5875 * Allocate a new ASID for the specified pmap.
5878 pmap_alloc_asid(pmap_t pmap)
5882 PMAP_ASSERT_STAGE1(pmap);
5883 mtx_lock_spin(&asid_set_mutex);
5886 * While this processor was waiting to acquire the asid set mutex,
5887 * pmap_reset_asid_set() running on another processor might have
5888 * updated this pmap's cookie to the current epoch. In which case, we
5889 * don't need to allocate a new ASID.
5891 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == asid_epoch)
5894 bit_ffc_at(asid_set, asid_next, asid_set_size, &new_asid);
5895 if (new_asid == -1) {
5896 bit_ffc_at(asid_set, ASID_FIRST_AVAILABLE, asid_next,
5898 if (new_asid == -1) {
5899 pmap_reset_asid_set();
5900 bit_ffc_at(asid_set, ASID_FIRST_AVAILABLE,
5901 asid_set_size, &new_asid);
5902 KASSERT(new_asid != -1, ("ASID allocation failure"));
5905 bit_set(asid_set, new_asid);
5906 asid_next = new_asid + 1;
5907 pmap->pm_cookie = COOKIE_FROM(new_asid, asid_epoch);
5909 mtx_unlock_spin(&asid_set_mutex);
5913 * Compute the value that should be stored in ttbr0 to activate the specified
5914 * pmap. This value may change from time to time.
5917 pmap_to_ttbr0(pmap_t pmap)
5920 PMAP_ASSERT_STAGE1(pmap);
5921 return (ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) |
5926 pmap_activate_int(pmap_t pmap)
5930 PMAP_ASSERT_STAGE1(pmap);
5931 KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap"));
5932 KASSERT(pmap != kernel_pmap, ("kernel pmap activation"));
5933 if (pmap == PCPU_GET(curpmap)) {
5935 * Handle the possibility that the old thread was preempted
5936 * after an "ic" or "tlbi" instruction but before it performed
5937 * a "dsb" instruction. If the old thread migrates to a new
5938 * processor, its completion of a "dsb" instruction on that
5939 * new processor does not guarantee that the "ic" or "tlbi"
5940 * instructions performed on the old processor have completed.
5947 * Ensure that the store to curpmap is globally visible before the
5948 * load from asid_epoch is performed.
5950 PCPU_SET(curpmap, pmap);
5952 epoch = COOKIE_TO_EPOCH(pmap->pm_cookie);
5953 if (epoch >= 0 && epoch != asid_epoch)
5954 pmap_alloc_asid(pmap);
5956 set_ttbr0(pmap_to_ttbr0(pmap));
5957 if (PCPU_GET(bcast_tlbi_workaround) != 0)
5958 invalidate_local_icache();
5963 pmap_activate(struct thread *td)
5967 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5968 PMAP_ASSERT_STAGE1(pmap);
5970 (void)pmap_activate_int(pmap);
5975 * To eliminate the unused parameter "old", we would have to add an instruction
5979 pmap_switch(struct thread *old __unused, struct thread *new)
5981 pcpu_bp_harden bp_harden;
5984 /* Store the new curthread */
5985 PCPU_SET(curthread, new);
5987 /* And the new pcb */
5989 PCPU_SET(curpcb, pcb);
5992 * TODO: We may need to flush the cache here if switching
5993 * to a user process.
5996 if (pmap_activate_int(vmspace_pmap(new->td_proc->p_vmspace))) {
5998 * Stop userspace from training the branch predictor against
5999 * other processes. This will call into a CPU specific
6000 * function that clears the branch predictor state.
6002 bp_harden = PCPU_GET(bp_harden);
6003 if (bp_harden != NULL)
6011 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
6014 PMAP_ASSERT_STAGE1(pmap);
6015 if (va >= VM_MIN_KERNEL_ADDRESS) {
6016 cpu_icache_sync_range(va, sz);
6021 /* Find the length of data in this page to flush */
6022 offset = va & PAGE_MASK;
6023 len = imin(PAGE_SIZE - offset, sz);
6026 /* Extract the physical address & find it in the DMAP */
6027 pa = pmap_extract(pmap, va);
6029 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
6031 /* Move to the next page */
6034 /* Set the length for the next iteration */
6035 len = imin(PAGE_SIZE, sz);
6041 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
6043 pt_entry_t pte, *ptep;
6048 PMAP_ASSERT_STAGE1(pmap);
6051 ec = ESR_ELx_EXCEPTION(esr);
6053 case EXCP_INSN_ABORT_L:
6054 case EXCP_INSN_ABORT:
6055 case EXCP_DATA_ABORT_L:
6056 case EXCP_DATA_ABORT:
6062 /* Data and insn aborts use same encoding for FSC field. */
6063 switch (esr & ISS_DATA_DFSC_MASK) {
6064 case ISS_DATA_DFSC_AFF_L1:
6065 case ISS_DATA_DFSC_AFF_L2:
6066 case ISS_DATA_DFSC_AFF_L3:
6068 ptep = pmap_pte(pmap, far, &lvl);
6070 pmap_set_bits(ptep, ATTR_AF);
6073 * XXXMJ as an optimization we could mark the entry
6074 * dirty if this is a write fault.
6079 case ISS_DATA_DFSC_PF_L1:
6080 case ISS_DATA_DFSC_PF_L2:
6081 case ISS_DATA_DFSC_PF_L3:
6082 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
6083 (esr & ISS_DATA_WnR) == 0)
6086 ptep = pmap_pte(pmap, far, &lvl);
6088 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
6089 if ((pte & ATTR_S1_AP_RW_BIT) ==
6090 ATTR_S1_AP(ATTR_S1_AP_RO)) {
6091 pmap_clear_bits(ptep, ATTR_S1_AP_RW_BIT);
6092 pmap_invalidate_page(pmap, far);
6098 case ISS_DATA_DFSC_TF_L0:
6099 case ISS_DATA_DFSC_TF_L1:
6100 case ISS_DATA_DFSC_TF_L2:
6101 case ISS_DATA_DFSC_TF_L3:
6103 * Retry the translation. A break-before-make sequence can
6104 * produce a transient fault.
6106 if (pmap == kernel_pmap) {
6108 * The translation fault may have occurred within a
6109 * critical section. Therefore, we must check the
6110 * address without acquiring the kernel pmap's lock.
6112 if (pmap_kextract(far) != 0)
6116 /* Ask the MMU to check the address. */
6117 intr = intr_disable();
6118 par = arm64_address_translate_s1e0r(far);
6123 * If the translation was successful, then we can
6124 * return success to the trap handler.
6126 if (PAR_SUCCESS(par))
6136 * Increase the starting virtual address of the given mapping if a
6137 * different alignment might result in more superpage mappings.
6140 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6141 vm_offset_t *addr, vm_size_t size)
6143 vm_offset_t superpage_offset;
6147 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6148 offset += ptoa(object->pg_color);
6149 superpage_offset = offset & L2_OFFSET;
6150 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
6151 (*addr & L2_OFFSET) == superpage_offset)
6153 if ((*addr & L2_OFFSET) < superpage_offset)
6154 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
6156 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
6160 * Get the kernel virtual address of a set of physical pages. If there are
6161 * physical addresses not covered by the DMAP perform a transient mapping
6162 * that will be removed when calling pmap_unmap_io_transient.
6164 * \param page The pages the caller wishes to obtain the virtual
6165 * address on the kernel memory map.
6166 * \param vaddr On return contains the kernel virtual memory address
6167 * of the pages passed in the page parameter.
6168 * \param count Number of pages passed in.
6169 * \param can_fault TRUE if the thread using the mapped pages can take
6170 * page faults, FALSE otherwise.
6172 * \returns TRUE if the caller must call pmap_unmap_io_transient when
6173 * finished or FALSE otherwise.
6177 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6178 boolean_t can_fault)
6181 boolean_t needs_mapping;
6185 * Allocate any KVA space that we need, this is done in a separate
6186 * loop to prevent calling vmem_alloc while pinned.
6188 needs_mapping = FALSE;
6189 for (i = 0; i < count; i++) {
6190 paddr = VM_PAGE_TO_PHYS(page[i]);
6191 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
6192 error = vmem_alloc(kernel_arena, PAGE_SIZE,
6193 M_BESTFIT | M_WAITOK, &vaddr[i]);
6194 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
6195 needs_mapping = TRUE;
6197 vaddr[i] = PHYS_TO_DMAP(paddr);
6201 /* Exit early if everything is covered by the DMAP */
6207 for (i = 0; i < count; i++) {
6208 paddr = VM_PAGE_TO_PHYS(page[i]);
6209 if (!PHYS_IN_DMAP(paddr)) {
6211 "pmap_map_io_transient: TODO: Map out of DMAP data");
6215 return (needs_mapping);
6219 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6220 boolean_t can_fault)
6227 for (i = 0; i < count; i++) {
6228 paddr = VM_PAGE_TO_PHYS(page[i]);
6229 if (!PHYS_IN_DMAP(paddr)) {
6230 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
6236 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
6239 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);
6243 * Track a range of the kernel's virtual address space that is contiguous
6244 * in various mapping attributes.
6246 struct pmap_kernel_map_range {
6256 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
6262 if (eva <= range->sva)
6265 index = range->attrs & ATTR_S1_IDX_MASK;
6267 case ATTR_S1_IDX(VM_MEMATTR_DEVICE):
6270 case ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE):
6273 case ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK):
6276 case ATTR_S1_IDX(VM_MEMATTR_WRITE_THROUGH):
6281 "%s: unknown memory type %x for range 0x%016lx-0x%016lx\n",
6282 __func__, index, range->sva, eva);
6287 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c %3s %d %d %d %d\n",
6289 (range->attrs & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP_RW ? 'w' : '-',
6290 (range->attrs & ATTR_S1_PXN) != 0 ? '-' : 'x',
6291 (range->attrs & ATTR_S1_AP_USER) != 0 ? 'u' : 's',
6292 mode, range->l1blocks, range->l2blocks, range->l3contig,
6295 /* Reset to sentinel value. */
6296 range->sva = 0xfffffffffffffffful;
6300 * Determine whether the attributes specified by a page table entry match those
6301 * being tracked by the current range.
6304 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
6307 return (range->attrs == attrs);
6311 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
6315 memset(range, 0, sizeof(*range));
6317 range->attrs = attrs;
6321 * Given a leaf PTE, derive the mapping's attributes. If they do not match
6322 * those of the current run, dump the address range and its attributes, and
6326 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
6327 vm_offset_t va, pd_entry_t l0e, pd_entry_t l1e, pd_entry_t l2e,
6332 attrs = l0e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6333 attrs |= l1e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6334 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK)
6335 attrs |= l1e & ATTR_S1_IDX_MASK;
6336 attrs |= l2e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6337 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK)
6338 attrs |= l2e & ATTR_S1_IDX_MASK;
6339 attrs |= l3e & (ATTR_S1_AP_MASK | ATTR_S1_XN | ATTR_S1_IDX_MASK);
6341 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
6342 sysctl_kmaps_dump(sb, range, va);
6343 sysctl_kmaps_reinit(range, va, attrs);
6348 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
6350 struct pmap_kernel_map_range range;
6351 struct sbuf sbuf, *sb;
6352 pd_entry_t l0e, *l1, l1e, *l2, l2e;
6353 pt_entry_t *l3, l3e;
6356 int error, i, j, k, l;
6358 error = sysctl_wire_old_buffer(req, 0);
6362 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
6364 /* Sentinel value. */
6365 range.sva = 0xfffffffffffffffful;
6368 * Iterate over the kernel page tables without holding the kernel pmap
6369 * lock. Kernel page table pages are never freed, so at worst we will
6370 * observe inconsistencies in the output.
6372 for (sva = 0xffff000000000000ul, i = pmap_l0_index(sva); i < Ln_ENTRIES;
6374 if (i == pmap_l0_index(DMAP_MIN_ADDRESS))
6375 sbuf_printf(sb, "\nDirect map:\n");
6376 else if (i == pmap_l0_index(VM_MIN_KERNEL_ADDRESS))
6377 sbuf_printf(sb, "\nKernel map:\n");
6379 l0e = kernel_pmap->pm_l0[i];
6380 if ((l0e & ATTR_DESCR_VALID) == 0) {
6381 sysctl_kmaps_dump(sb, &range, sva);
6385 pa = l0e & ~ATTR_MASK;
6386 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa);
6388 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
6390 if ((l1e & ATTR_DESCR_VALID) == 0) {
6391 sysctl_kmaps_dump(sb, &range, sva);
6395 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
6396 sysctl_kmaps_check(sb, &range, sva, l0e, l1e,
6402 pa = l1e & ~ATTR_MASK;
6403 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa);
6405 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
6407 if ((l2e & ATTR_DESCR_VALID) == 0) {
6408 sysctl_kmaps_dump(sb, &range, sva);
6412 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK) {
6413 sysctl_kmaps_check(sb, &range, sva,
6419 pa = l2e & ~ATTR_MASK;
6420 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
6422 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
6423 l++, sva += L3_SIZE) {
6425 if ((l3e & ATTR_DESCR_VALID) == 0) {
6426 sysctl_kmaps_dump(sb, &range,
6430 sysctl_kmaps_check(sb, &range, sva,
6431 l0e, l1e, l2e, l3e);
6432 if ((l3e & ATTR_CONTIGUOUS) != 0)
6433 range.l3contig += l % 16 == 0 ?
6442 error = sbuf_finish(sb);
6446 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
6447 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
6448 NULL, 0, sysctl_kmaps, "A",
6449 "Dump kernel address layout");