2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/limits.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/physmem.h>
123 #include <sys/proc.h>
124 #include <sys/rwlock.h>
125 #include <sys/sbuf.h>
127 #include <sys/vmem.h>
128 #include <sys/vmmeter.h>
129 #include <sys/sched.h>
130 #include <sys/sysctl.h>
131 #include <sys/_unrhdr.h>
135 #include <vm/vm_param.h>
136 #include <vm/vm_kern.h>
137 #include <vm/vm_page.h>
138 #include <vm/vm_map.h>
139 #include <vm/vm_object.h>
140 #include <vm/vm_extern.h>
141 #include <vm/vm_pageout.h>
142 #include <vm/vm_pager.h>
143 #include <vm/vm_phys.h>
144 #include <vm/vm_radix.h>
145 #include <vm/vm_reserv.h>
146 #include <vm/vm_dumpset.h>
149 #include <machine/machdep.h>
150 #include <machine/md_var.h>
151 #include <machine/pcb.h>
153 #define PMAP_ASSERT_STAGE1(pmap) MPASS((pmap)->pm_stage == PM_STAGE1)
154 #define PMAP_ASSERT_STAGE2(pmap) MPASS((pmap)->pm_stage == PM_STAGE2)
156 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
157 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
158 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
159 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
161 #define NUL0E L0_ENTRIES
162 #define NUL1E (NUL0E * NL1PG)
163 #define NUL2E (NUL1E * NL2PG)
165 #if !defined(DIAGNOSTIC)
166 #ifdef __GNUC_GNU_INLINE__
167 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
169 #define PMAP_INLINE extern inline
176 #define PV_STAT(x) do { x ; } while (0)
178 #define PV_STAT(x) do { } while (0)
181 #define pmap_l0_pindex(v) (NUL2E + NUL1E + ((v) >> L0_SHIFT))
182 #define pmap_l1_pindex(v) (NUL2E + ((v) >> L1_SHIFT))
183 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
185 static struct md_page *
186 pa_to_pvh(vm_paddr_t pa)
188 struct vm_phys_seg *seg;
191 for (segind = 0; segind < vm_phys_nsegs; segind++) {
192 seg = &vm_phys_segs[segind];
193 if (pa >= seg->start && pa < seg->end)
194 return ((struct md_page *)seg->md_first +
195 pmap_l2_pindex(pa) - pmap_l2_pindex(seg->start));
197 panic("pa 0x%jx not within vm_phys_segs", (uintmax_t)pa);
200 static struct md_page *
201 page_to_pvh(vm_page_t m)
203 struct vm_phys_seg *seg;
205 seg = &vm_phys_segs[m->segind];
206 return ((struct md_page *)seg->md_first +
207 pmap_l2_pindex(VM_PAGE_TO_PHYS(m)) - pmap_l2_pindex(seg->start));
210 #define NPV_LIST_LOCKS MAXCPU
212 #define PHYS_TO_PV_LIST_LOCK(pa) \
213 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
215 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
216 struct rwlock **_lockp = (lockp); \
217 struct rwlock *_new_lock; \
219 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
220 if (_new_lock != *_lockp) { \
221 if (*_lockp != NULL) \
222 rw_wunlock(*_lockp); \
223 *_lockp = _new_lock; \
228 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
229 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
231 #define RELEASE_PV_LIST_LOCK(lockp) do { \
232 struct rwlock **_lockp = (lockp); \
234 if (*_lockp != NULL) { \
235 rw_wunlock(*_lockp); \
240 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
241 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
244 * The presence of this flag indicates that the mapping is writeable.
245 * If the ATTR_S1_AP_RO bit is also set, then the mapping is clean, otherwise
246 * it is dirty. This flag may only be set on managed mappings.
248 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
249 * as a software managed bit.
251 #define ATTR_SW_DBM ATTR_DBM
253 struct pmap kernel_pmap_store;
255 /* Used for mapping ACPI memory before VM is initialized */
256 #define PMAP_PREINIT_MAPPING_COUNT 32
257 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
258 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
259 static int vm_initialized = 0; /* No need to use pre-init maps when set */
262 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
263 * Always map entire L2 block for simplicity.
264 * VA of L2 block = preinit_map_va + i * L2_SIZE
266 static struct pmap_preinit_mapping {
270 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
272 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
273 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
274 vm_offset_t kernel_vm_end = 0;
277 * Data for the pv entry allocation mechanism.
279 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
280 static struct mtx pv_chunks_mutex;
281 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
282 static struct md_page *pv_table;
283 static struct md_page pv_dummy;
285 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
286 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
287 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
289 /* This code assumes all L1 DMAP entries will be used */
290 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
291 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
293 extern pt_entry_t pagetable_l0_ttbr1[];
295 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
296 static vm_paddr_t physmap[PHYSMAP_SIZE];
297 static u_int physmap_idx;
299 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
300 "VM/pmap parameters");
303 * This ASID allocator uses a bit vector ("asid_set") to remember which ASIDs
304 * that it has currently allocated to a pmap, a cursor ("asid_next") to
305 * optimize its search for a free ASID in the bit vector, and an epoch number
306 * ("asid_epoch") to indicate when it has reclaimed all previously allocated
307 * ASIDs that are not currently active on a processor.
309 * The current epoch number is always in the range [0, INT_MAX). Negative
310 * numbers and INT_MAX are reserved for special cases that are described
319 struct mtx asid_set_mutex;
322 static struct asid_set asids;
323 static struct asid_set vmids;
325 static SYSCTL_NODE(_vm_pmap, OID_AUTO, asid, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
327 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, bits, CTLFLAG_RD, &asids.asid_bits, 0,
328 "The number of bits in an ASID");
329 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, next, CTLFLAG_RD, &asids.asid_next, 0,
330 "The last allocated ASID plus one");
331 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, epoch, CTLFLAG_RD, &asids.asid_epoch, 0,
332 "The current epoch number");
334 static SYSCTL_NODE(_vm_pmap, OID_AUTO, vmid, CTLFLAG_RD, 0, "VMID allocator");
335 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, bits, CTLFLAG_RD, &vmids.asid_bits, 0,
336 "The number of bits in an VMID");
337 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, next, CTLFLAG_RD, &vmids.asid_next, 0,
338 "The last allocated VMID plus one");
339 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, epoch, CTLFLAG_RD, &vmids.asid_epoch, 0,
340 "The current epoch number");
342 void (*pmap_clean_stage2_tlbi)(void);
343 void (*pmap_invalidate_vpipt_icache)(void);
346 * A pmap's cookie encodes an ASID and epoch number. Cookies for reserved
347 * ASIDs have a negative epoch number, specifically, INT_MIN. Cookies for
348 * dynamically allocated ASIDs have a non-negative epoch number.
350 * An invalid ASID is represented by -1.
352 * There are two special-case cookie values: (1) COOKIE_FROM(-1, INT_MIN),
353 * which indicates that an ASID should never be allocated to the pmap, and
354 * (2) COOKIE_FROM(-1, INT_MAX), which indicates that an ASID should be
355 * allocated when the pmap is next activated.
357 #define COOKIE_FROM(asid, epoch) ((long)((u_int)(asid) | \
358 ((u_long)(epoch) << 32)))
359 #define COOKIE_TO_ASID(cookie) ((int)(cookie))
360 #define COOKIE_TO_EPOCH(cookie) ((int)((u_long)(cookie) >> 32))
362 #define TLBI_VA_SHIFT 12
363 #define TLBI_VA_MASK ((1ul << 44) - 1)
364 #define TLBI_VA(addr) (((addr) >> TLBI_VA_SHIFT) & TLBI_VA_MASK)
365 #define TLBI_VA_L3_INCR (L3_SIZE >> TLBI_VA_SHIFT)
367 static int superpages_enabled = 1;
368 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
369 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
370 "Are large page mappings enabled?");
373 * Internal flags for pmap_enter()'s helper functions.
375 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
376 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
378 static void free_pv_chunk(struct pv_chunk *pc);
379 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
380 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
381 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
382 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
383 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
386 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
387 static bool pmap_activate_int(pmap_t pmap);
388 static void pmap_alloc_asid(pmap_t pmap);
389 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
390 vm_prot_t prot, int mode, bool skip_unmapped);
391 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
392 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
393 vm_offset_t va, struct rwlock **lockp);
394 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
395 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
396 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
397 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
398 u_int flags, vm_page_t m, struct rwlock **lockp);
399 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
400 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
401 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
402 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
403 static void pmap_reset_asid_set(pmap_t pmap);
404 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
405 vm_page_t m, struct rwlock **lockp);
407 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
408 struct rwlock **lockp);
410 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
411 struct spglist *free);
412 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
413 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
416 * These load the old table data and store the new value.
417 * They need to be atomic as the System MMU may write to the table at
418 * the same time as the CPU.
420 #define pmap_clear(table) atomic_store_64(table, 0)
421 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
422 #define pmap_load(table) (*table)
423 #define pmap_load_clear(table) atomic_swap_64(table, 0)
424 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
425 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
426 #define pmap_store(table, entry) atomic_store_64(table, entry)
428 /********************/
429 /* Inline functions */
430 /********************/
433 pagecopy(void *s, void *d)
436 memcpy(d, s, PAGE_SIZE);
439 static __inline pd_entry_t *
440 pmap_l0(pmap_t pmap, vm_offset_t va)
443 return (&pmap->pm_l0[pmap_l0_index(va)]);
446 static __inline pd_entry_t *
447 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
451 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
452 return (&l1[pmap_l1_index(va)]);
455 static __inline pd_entry_t *
456 pmap_l1(pmap_t pmap, vm_offset_t va)
460 l0 = pmap_l0(pmap, va);
461 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
464 return (pmap_l0_to_l1(l0, va));
467 static __inline pd_entry_t *
468 pmap_l1_to_l2(pd_entry_t *l1p, vm_offset_t va)
474 KASSERT(ADDR_IS_CANONICAL(va),
475 ("%s: Address not in canonical form: %lx", __func__, va));
477 * The valid bit may be clear if pmap_update_entry() is concurrently
478 * modifying the entry, so for KVA only the entry type may be checked.
480 KASSERT(ADDR_IS_KERNEL(va) || (l1 & ATTR_DESCR_VALID) != 0,
481 ("%s: L1 entry %#lx for %#lx is invalid", __func__, l1, va));
482 KASSERT((l1 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE,
483 ("%s: L1 entry %#lx for %#lx is a leaf", __func__, l1, va));
484 l2p = (pd_entry_t *)PHYS_TO_DMAP(l1 & ~ATTR_MASK);
485 return (&l2p[pmap_l2_index(va)]);
488 static __inline pd_entry_t *
489 pmap_l2(pmap_t pmap, vm_offset_t va)
493 l1 = pmap_l1(pmap, va);
494 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
497 return (pmap_l1_to_l2(l1, va));
500 static __inline pt_entry_t *
501 pmap_l2_to_l3(pd_entry_t *l2p, vm_offset_t va)
508 KASSERT(ADDR_IS_CANONICAL(va),
509 ("%s: Address not in canonical form: %lx", __func__, va));
511 * The valid bit may be clear if pmap_update_entry() is concurrently
512 * modifying the entry, so for KVA only the entry type may be checked.
514 KASSERT(ADDR_IS_KERNEL(va) || (l2 & ATTR_DESCR_VALID) != 0,
515 ("%s: L2 entry %#lx for %#lx is invalid", __func__, l2, va));
516 KASSERT((l2 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE,
517 ("%s: L2 entry %#lx for %#lx is a leaf", __func__, l2, va));
518 l3p = (pt_entry_t *)PHYS_TO_DMAP(l2 & ~ATTR_MASK);
519 return (&l3p[pmap_l3_index(va)]);
523 * Returns the lowest valid pde for a given virtual address.
524 * The next level may or may not point to a valid page or block.
526 static __inline pd_entry_t *
527 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
529 pd_entry_t *l0, *l1, *l2, desc;
531 l0 = pmap_l0(pmap, va);
532 desc = pmap_load(l0) & ATTR_DESCR_MASK;
533 if (desc != L0_TABLE) {
538 l1 = pmap_l0_to_l1(l0, va);
539 desc = pmap_load(l1) & ATTR_DESCR_MASK;
540 if (desc != L1_TABLE) {
545 l2 = pmap_l1_to_l2(l1, va);
546 desc = pmap_load(l2) & ATTR_DESCR_MASK;
547 if (desc != L2_TABLE) {
557 * Returns the lowest valid pte block or table entry for a given virtual
558 * address. If there are no valid entries return NULL and set the level to
559 * the first invalid level.
561 static __inline pt_entry_t *
562 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
564 pd_entry_t *l1, *l2, desc;
567 l1 = pmap_l1(pmap, va);
572 desc = pmap_load(l1) & ATTR_DESCR_MASK;
573 if (desc == L1_BLOCK) {
578 if (desc != L1_TABLE) {
583 l2 = pmap_l1_to_l2(l1, va);
584 desc = pmap_load(l2) & ATTR_DESCR_MASK;
585 if (desc == L2_BLOCK) {
590 if (desc != L2_TABLE) {
596 l3 = pmap_l2_to_l3(l2, va);
597 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
604 pmap_ps_enabled(pmap_t pmap)
607 * Promotion requires a hypervisor call when the kernel is running
608 * in EL1. To stop this disable superpage support on non-stage 1
611 if (pmap->pm_stage != PM_STAGE1)
614 return (superpages_enabled != 0);
618 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
619 pd_entry_t **l2, pt_entry_t **l3)
621 pd_entry_t *l0p, *l1p, *l2p;
623 if (pmap->pm_l0 == NULL)
626 l0p = pmap_l0(pmap, va);
629 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
632 l1p = pmap_l0_to_l1(l0p, va);
635 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
641 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
644 l2p = pmap_l1_to_l2(l1p, va);
647 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
652 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
655 *l3 = pmap_l2_to_l3(l2p, va);
661 pmap_l3_valid(pt_entry_t l3)
664 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
667 CTASSERT(L1_BLOCK == L2_BLOCK);
670 pmap_pte_memattr(pmap_t pmap, vm_memattr_t memattr)
674 if (pmap->pm_stage == PM_STAGE1) {
675 val = ATTR_S1_IDX(memattr);
676 if (memattr == VM_MEMATTR_DEVICE)
684 case VM_MEMATTR_DEVICE:
685 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_DEVICE_nGnRnE) |
686 ATTR_S2_XN(ATTR_S2_XN_ALL));
687 case VM_MEMATTR_UNCACHEABLE:
688 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_NC));
689 case VM_MEMATTR_WRITE_BACK:
690 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WB));
691 case VM_MEMATTR_WRITE_THROUGH:
692 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WT));
694 panic("%s: invalid memory attribute %x", __func__, memattr);
699 pmap_pte_prot(pmap_t pmap, vm_prot_t prot)
704 if (pmap->pm_stage == PM_STAGE1) {
705 if ((prot & VM_PROT_EXECUTE) == 0)
707 if ((prot & VM_PROT_WRITE) == 0)
708 val |= ATTR_S1_AP(ATTR_S1_AP_RO);
710 if ((prot & VM_PROT_WRITE) != 0)
711 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
712 if ((prot & VM_PROT_READ) != 0)
713 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_READ);
714 if ((prot & VM_PROT_EXECUTE) == 0)
715 val |= ATTR_S2_XN(ATTR_S2_XN_ALL);
722 * Checks if the PTE is dirty.
725 pmap_pte_dirty(pmap_t pmap, pt_entry_t pte)
728 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
730 if (pmap->pm_stage == PM_STAGE1) {
731 KASSERT((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) != 0,
732 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
734 return ((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
735 (ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_SW_DBM));
738 return ((pte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
739 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE));
743 pmap_resident_count_inc(pmap_t pmap, int count)
746 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
747 pmap->pm_stats.resident_count += count;
751 pmap_resident_count_dec(pmap_t pmap, int count)
754 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
755 KASSERT(pmap->pm_stats.resident_count >= count,
756 ("pmap %p resident count underflow %ld %d", pmap,
757 pmap->pm_stats.resident_count, count));
758 pmap->pm_stats.resident_count -= count;
762 pmap_early_vtophys(vm_offset_t va)
766 pa_page = arm64_address_translate_s1e1r(va) & PAR_PA_MASK;
767 return (pa_page | (va & PAR_LOW_MASK));
770 /* State of the bootstrapped DMAP page tables */
771 struct dmap_bootstrap_state {
780 vm_offset_t freemempos;
784 pmap_bootstrap_dmap_l0_table(struct dmap_bootstrap_state *state)
789 /* Link the level 0 table to a level 1 table */
790 l0_slot = pmap_l0_index(state->va);
791 if (l0_slot != state->l0_slot) {
792 MPASS(state->l0_slot < l0_slot ||
793 state->l0_slot == L0_ENTRIES);
795 /* Create a new L0 table entry */
796 state->l0_slot = l0_slot;
797 state->l1 = (pt_entry_t *)state->freemempos;
798 memset(state->l1, 0, PAGE_SIZE);
799 state->freemempos += PAGE_SIZE;
801 /* Reset lower levels */
804 state->l1_slot = Ln_ENTRIES;
805 state->l2_slot = Ln_ENTRIES;
807 l1_pa = pmap_early_vtophys((vm_offset_t)state->l1);
808 MPASS((l1_pa & Ln_TABLE_MASK) == 0);
809 MPASS(pagetable_l0_ttbr1[l0_slot] == 0);
810 pmap_store(&pagetable_l0_ttbr1[l0_slot], l1_pa |
811 TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0 | L0_TABLE);
813 KASSERT(state->l1 != NULL, ("%s: NULL l1", __func__));
817 pmap_bootstrap_dmap_l1_table(struct dmap_bootstrap_state *state)
822 /* Make sure there is a valid L0 -> L1 table */
823 pmap_bootstrap_dmap_l0_table(state);
825 /* Link the level 1 table to a level 2 table */
826 l1_slot = pmap_l1_index(state->va);
827 if (l1_slot != state->l1_slot) {
828 MPASS(state->l1_slot < l1_slot ||
829 state->l1_slot == Ln_ENTRIES);
831 /* Create a new L1 table entry */
832 state->l1_slot = l1_slot;
833 state->l2 = (pt_entry_t *)state->freemempos;
834 memset(state->l2, 0, PAGE_SIZE);
835 state->freemempos += PAGE_SIZE;
837 /* Reset lower levels */
839 state->l2_slot = Ln_ENTRIES;
841 l2_pa = pmap_early_vtophys((vm_offset_t)state->l2);
842 MPASS((l2_pa & Ln_TABLE_MASK) == 0);
843 MPASS(state->l1[l1_slot] == 0);
844 pmap_store(&state->l1[l1_slot], l2_pa | TATTR_PXN_TABLE |
847 KASSERT(state->l2 != NULL, ("%s: NULL l2", __func__));
851 pmap_bootstrap_dmap_l2_table(struct dmap_bootstrap_state *state)
856 /* Make sure there is a valid L1 -> L2 table */
857 pmap_bootstrap_dmap_l1_table(state);
859 /* Link the level 2 table to a level 3 table */
860 l2_slot = pmap_l2_index(state->va);
861 if (l2_slot != state->l2_slot) {
862 MPASS(state->l2_slot < l2_slot ||
863 state->l2_slot == Ln_ENTRIES);
865 /* Create a new L2 table entry */
866 state->l2_slot = l2_slot;
867 state->l3 = (pt_entry_t *)state->freemempos;
868 memset(state->l3, 0, PAGE_SIZE);
869 state->freemempos += PAGE_SIZE;
871 l3_pa = pmap_early_vtophys((vm_offset_t)state->l3);
872 MPASS((l3_pa & Ln_TABLE_MASK) == 0);
873 MPASS(state->l2[l2_slot] == 0);
874 pmap_store(&state->l2[l2_slot], l3_pa | TATTR_PXN_TABLE |
877 KASSERT(state->l3 != NULL, ("%s: NULL l3", __func__));
881 pmap_bootstrap_dmap_l2_block(struct dmap_bootstrap_state *state, int i)
886 if ((physmap[i + 1] - state->pa) < L2_SIZE)
889 /* Make sure there is a valid L1 table */
890 pmap_bootstrap_dmap_l1_table(state);
892 MPASS((state->va & L2_OFFSET) == 0);
894 state->va < DMAP_MAX_ADDRESS &&
895 (physmap[i + 1] - state->pa) >= L2_SIZE;
896 state->va += L2_SIZE, state->pa += L2_SIZE) {
898 * Stop if we are about to walk off the end of what the
899 * current L1 slot can address.
901 if (!first && (state->pa & L1_OFFSET) == 0)
905 l2_slot = pmap_l2_index(state->va);
906 MPASS((state->pa & L2_OFFSET) == 0);
907 MPASS(state->l2[l2_slot] == 0);
908 pmap_store(&state->l2[l2_slot], state->pa | ATTR_DEFAULT |
909 ATTR_S1_XN | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
912 MPASS(state->va == (state->pa - dmap_phys_base + DMAP_MIN_ADDRESS));
916 pmap_bootstrap_dmap_l3_page(struct dmap_bootstrap_state *state, int i)
921 if ((physmap[i + 1] - state->pa) < L3_SIZE)
924 /* Make sure there is a valid L2 table */
925 pmap_bootstrap_dmap_l2_table(state);
927 MPASS((state->va & L3_OFFSET) == 0);
929 state->va < DMAP_MAX_ADDRESS &&
930 (physmap[i + 1] - state->pa) >= L3_SIZE;
931 state->va += L3_SIZE, state->pa += L3_SIZE) {
933 * Stop if we are about to walk off the end of what the
934 * current L2 slot can address.
936 if (!first && (state->pa & L2_OFFSET) == 0)
940 l3_slot = pmap_l3_index(state->va);
941 MPASS((state->pa & L3_OFFSET) == 0);
942 MPASS(state->l3[l3_slot] == 0);
943 pmap_store(&state->l3[l3_slot], state->pa | ATTR_DEFAULT |
944 ATTR_S1_XN | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
947 MPASS(state->va == (state->pa - dmap_phys_base + DMAP_MIN_ADDRESS));
951 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
952 vm_offset_t freemempos)
954 struct dmap_bootstrap_state state;
957 dmap_phys_base = min_pa & ~L1_OFFSET;
961 state.l1 = state.l2 = state.l3 = NULL;
962 state.l0_slot = L0_ENTRIES;
963 state.l1_slot = Ln_ENTRIES;
964 state.l2_slot = Ln_ENTRIES;
965 state.freemempos = freemempos;
967 for (i = 0; i < (physmap_idx * 2); i += 2) {
968 state.pa = physmap[i] & ~L3_OFFSET;
969 state.va = state.pa - dmap_phys_base + DMAP_MIN_ADDRESS;
971 /* Create L3 mappings at the start of the region */
972 if ((state.pa & L2_OFFSET) != 0)
973 pmap_bootstrap_dmap_l3_page(&state, i);
974 MPASS(state.pa <= physmap[i + 1]);
976 /* Create L2 mappings at the start of the region */
977 if ((state.pa & L1_OFFSET) != 0)
978 pmap_bootstrap_dmap_l2_block(&state, i);
979 MPASS(state.pa <= physmap[i + 1]);
981 /* Create the main L1 block mappings */
982 for (; state.va < DMAP_MAX_ADDRESS &&
983 (physmap[i + 1] - state.pa) >= L1_SIZE;
984 state.va += L1_SIZE, state.pa += L1_SIZE) {
985 /* Make sure there is a valid L1 table */
986 pmap_bootstrap_dmap_l0_table(&state);
987 MPASS((state.pa & L1_OFFSET) == 0);
988 pmap_store(&state.l1[pmap_l1_index(state.va)],
989 state.pa | ATTR_DEFAULT | ATTR_S1_XN |
990 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
993 MPASS(state.pa <= physmap[i + 1]);
995 /* Create L2 mappings at the end of the region */
996 pmap_bootstrap_dmap_l2_block(&state, i);
997 MPASS(state.pa <= physmap[i + 1]);
999 /* Create L3 mappings at the end of the region */
1000 pmap_bootstrap_dmap_l3_page(&state, i);
1001 MPASS(state.pa == physmap[i + 1]);
1003 if (state.pa > dmap_phys_max) {
1004 dmap_phys_max = state.pa;
1005 dmap_max_addr = state.va;
1011 return (state.freemempos);
1015 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
1022 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
1024 l1 = (pd_entry_t *)l1pt;
1025 l1_slot = pmap_l1_index(va);
1028 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
1029 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
1031 pa = pmap_early_vtophys(l2pt);
1032 pmap_store(&l1[l1_slot],
1033 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
1037 /* Clean the L2 page table */
1038 memset((void *)l2_start, 0, l2pt - l2_start);
1044 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
1051 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
1053 l2 = pmap_l2(kernel_pmap, va);
1054 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
1055 l2_slot = pmap_l2_index(va);
1058 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
1059 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
1061 pa = pmap_early_vtophys(l3pt);
1062 pmap_store(&l2[l2_slot],
1063 (pa & ~Ln_TABLE_MASK) | ATTR_S1_UXN | L2_TABLE);
1067 /* Clean the L2 page table */
1068 memset((void *)l3_start, 0, l3pt - l3_start);
1074 * Bootstrap the system enough to run with virtual memory.
1077 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
1080 vm_offset_t freemempos;
1081 vm_offset_t dpcpu, msgbufpv;
1082 vm_paddr_t start_pa, pa, min_pa;
1083 uint64_t kern_delta;
1086 /* Verify that the ASID is set through TTBR0. */
1087 KASSERT((READ_SPECIALREG(tcr_el1) & TCR_A1) == 0,
1088 ("pmap_bootstrap: TCR_EL1.A1 != 0"));
1090 kern_delta = KERNBASE - kernstart;
1092 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
1093 printf("%lx\n", l1pt);
1094 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
1096 /* Set this early so we can use the pagetable walking functions */
1097 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
1098 PMAP_LOCK_INIT(kernel_pmap);
1099 kernel_pmap->pm_l0_paddr = l0pt - kern_delta;
1100 kernel_pmap->pm_cookie = COOKIE_FROM(-1, INT_MIN);
1101 kernel_pmap->pm_stage = PM_STAGE1;
1102 kernel_pmap->pm_levels = 4;
1103 kernel_pmap->pm_ttbr = kernel_pmap->pm_l0_paddr;
1104 kernel_pmap->pm_asid_set = &asids;
1106 /* Assume the address we were loaded to is a valid physical address */
1107 min_pa = KERNBASE - kern_delta;
1109 physmap_idx = physmem_avail(physmap, nitems(physmap));
1113 * Find the minimum physical address. physmap is sorted,
1114 * but may contain empty ranges.
1116 for (i = 0; i < physmap_idx * 2; i += 2) {
1117 if (physmap[i] == physmap[i + 1])
1119 if (physmap[i] <= min_pa)
1120 min_pa = physmap[i];
1123 freemempos = KERNBASE + kernlen;
1124 freemempos = roundup2(freemempos, PAGE_SIZE);
1126 /* Create a direct map region early so we can use it for pa -> va */
1127 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
1129 start_pa = pa = KERNBASE - kern_delta;
1132 * Create the l2 tables up to VM_MAX_KERNEL_ADDRESS. We assume that the
1133 * loader allocated the first and only l2 page table page used to map
1134 * the kernel, preloaded files and module metadata.
1136 freemempos = pmap_bootstrap_l2(l1pt, KERNBASE + L1_SIZE, freemempos);
1137 /* And the l3 tables for the early devmap */
1138 freemempos = pmap_bootstrap_l3(l1pt,
1139 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
1143 #define alloc_pages(var, np) \
1144 (var) = freemempos; \
1145 freemempos += (np * PAGE_SIZE); \
1146 memset((char *)(var), 0, ((np) * PAGE_SIZE));
1148 /* Allocate dynamic per-cpu area. */
1149 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
1150 dpcpu_init((void *)dpcpu, 0);
1152 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
1153 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
1154 msgbufp = (void *)msgbufpv;
1156 /* Reserve some VA space for early BIOS/ACPI mapping */
1157 preinit_map_va = roundup2(freemempos, L2_SIZE);
1159 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
1160 virtual_avail = roundup2(virtual_avail, L1_SIZE);
1161 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
1162 kernel_vm_end = virtual_avail;
1164 pa = pmap_early_vtophys(freemempos);
1166 physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
1172 * Initialize a vm_page's machine-dependent fields.
1175 pmap_page_init(vm_page_t m)
1178 TAILQ_INIT(&m->md.pv_list);
1179 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
1183 pmap_init_asids(struct asid_set *set, int bits)
1187 set->asid_bits = bits;
1190 * We may be too early in the overall initialization process to use
1193 set->asid_set_size = 1 << set->asid_bits;
1194 set->asid_set = (bitstr_t *)kmem_malloc(bitstr_size(set->asid_set_size),
1196 for (i = 0; i < ASID_FIRST_AVAILABLE; i++)
1197 bit_set(set->asid_set, i);
1198 set->asid_next = ASID_FIRST_AVAILABLE;
1199 mtx_init(&set->asid_set_mutex, "asid set", NULL, MTX_SPIN);
1203 * Initialize the pmap module.
1204 * Called by vm_init, to initialize any structures that the pmap
1205 * system needs to map virtual memory.
1210 struct vm_phys_seg *seg, *next_seg;
1211 struct md_page *pvh;
1214 int i, pv_npg, vmid_bits;
1217 * Are large page mappings enabled?
1219 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
1220 if (superpages_enabled) {
1221 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1222 ("pmap_init: can't assign to pagesizes[1]"));
1223 pagesizes[1] = L2_SIZE;
1224 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0,
1225 ("pmap_init: can't assign to pagesizes[2]"));
1226 pagesizes[2] = L1_SIZE;
1230 * Initialize the ASID allocator.
1232 pmap_init_asids(&asids,
1233 (READ_SPECIALREG(tcr_el1) & TCR_ASID_16) != 0 ? 16 : 8);
1236 mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1);
1239 if (ID_AA64MMFR1_VMIDBits_VAL(mmfr1) ==
1240 ID_AA64MMFR1_VMIDBits_16)
1242 pmap_init_asids(&vmids, vmid_bits);
1246 * Initialize the pv chunk list mutex.
1248 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1251 * Initialize the pool of pv list locks.
1253 for (i = 0; i < NPV_LIST_LOCKS; i++)
1254 rw_init(&pv_list_locks[i], "pmap pv list");
1257 * Calculate the size of the pv head table for superpages.
1260 for (i = 0; i < vm_phys_nsegs; i++) {
1261 seg = &vm_phys_segs[i];
1262 pv_npg += pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) -
1263 pmap_l2_pindex(seg->start);
1267 * Allocate memory for the pv head table for superpages.
1269 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1271 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1272 for (i = 0; i < pv_npg; i++)
1273 TAILQ_INIT(&pv_table[i].pv_list);
1274 TAILQ_INIT(&pv_dummy.pv_list);
1277 * Set pointers from vm_phys_segs to pv_table.
1279 for (i = 0, pvh = pv_table; i < vm_phys_nsegs; i++) {
1280 seg = &vm_phys_segs[i];
1281 seg->md_first = pvh;
1282 pvh += pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) -
1283 pmap_l2_pindex(seg->start);
1286 * If there is a following segment, and the final
1287 * superpage of this segment and the initial superpage
1288 * of the next segment are the same then adjust the
1289 * pv_table entry for that next segment down by one so
1290 * that the pv_table entries will be shared.
1292 if (i + 1 < vm_phys_nsegs) {
1293 next_seg = &vm_phys_segs[i + 1];
1294 if (pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) - 1 ==
1295 pmap_l2_pindex(next_seg->start)) {
1304 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1305 "2MB page mapping counters");
1307 static u_long pmap_l2_demotions;
1308 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
1309 &pmap_l2_demotions, 0, "2MB page demotions");
1311 static u_long pmap_l2_mappings;
1312 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
1313 &pmap_l2_mappings, 0, "2MB page mappings");
1315 static u_long pmap_l2_p_failures;
1316 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
1317 &pmap_l2_p_failures, 0, "2MB page promotion failures");
1319 static u_long pmap_l2_promotions;
1320 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
1321 &pmap_l2_promotions, 0, "2MB page promotions");
1324 * If the given value for "final_only" is false, then any cached intermediate-
1325 * level entries, i.e., L{0,1,2}_TABLE entries, are invalidated in addition to
1326 * any cached final-level entry, i.e., either an L{1,2}_BLOCK or L3_PAGE entry.
1327 * Otherwise, just the cached final-level entry is invalidated.
1329 static __inline void
1330 pmap_invalidate_kernel(uint64_t r, bool final_only)
1333 __asm __volatile("tlbi vaale1is, %0" : : "r" (r));
1335 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1338 static __inline void
1339 pmap_invalidate_user(uint64_t r, bool final_only)
1342 __asm __volatile("tlbi vale1is, %0" : : "r" (r));
1344 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1348 * Invalidates any cached final- and optionally intermediate-level TLB entries
1349 * for the specified virtual address in the given virtual address space.
1351 static __inline void
1352 pmap_invalidate_page(pmap_t pmap, vm_offset_t va, bool final_only)
1356 PMAP_ASSERT_STAGE1(pmap);
1360 if (pmap == kernel_pmap) {
1361 pmap_invalidate_kernel(r, final_only);
1363 r |= ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1364 pmap_invalidate_user(r, final_only);
1371 * Invalidates any cached final- and optionally intermediate-level TLB entries
1372 * for the specified virtual address range in the given virtual address space.
1374 static __inline void
1375 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1378 uint64_t end, r, start;
1380 PMAP_ASSERT_STAGE1(pmap);
1383 if (pmap == kernel_pmap) {
1384 start = TLBI_VA(sva);
1386 for (r = start; r < end; r += TLBI_VA_L3_INCR)
1387 pmap_invalidate_kernel(r, final_only);
1389 start = end = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1390 start |= TLBI_VA(sva);
1391 end |= TLBI_VA(eva);
1392 for (r = start; r < end; r += TLBI_VA_L3_INCR)
1393 pmap_invalidate_user(r, final_only);
1400 * Invalidates all cached intermediate- and final-level TLB entries for the
1401 * given virtual address space.
1403 static __inline void
1404 pmap_invalidate_all(pmap_t pmap)
1408 PMAP_ASSERT_STAGE1(pmap);
1411 if (pmap == kernel_pmap) {
1412 __asm __volatile("tlbi vmalle1is");
1414 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1415 __asm __volatile("tlbi aside1is, %0" : : "r" (r));
1422 * Routine: pmap_extract
1424 * Extract the physical page address associated
1425 * with the given map/virtual_address pair.
1428 pmap_extract(pmap_t pmap, vm_offset_t va)
1430 pt_entry_t *pte, tpte;
1437 * Find the block or page map for this virtual address. pmap_pte
1438 * will return either a valid block/page entry, or NULL.
1440 pte = pmap_pte(pmap, va, &lvl);
1442 tpte = pmap_load(pte);
1443 pa = tpte & ~ATTR_MASK;
1446 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1447 ("pmap_extract: Invalid L1 pte found: %lx",
1448 tpte & ATTR_DESCR_MASK));
1449 pa |= (va & L1_OFFSET);
1452 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1453 ("pmap_extract: Invalid L2 pte found: %lx",
1454 tpte & ATTR_DESCR_MASK));
1455 pa |= (va & L2_OFFSET);
1458 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1459 ("pmap_extract: Invalid L3 pte found: %lx",
1460 tpte & ATTR_DESCR_MASK));
1461 pa |= (va & L3_OFFSET);
1470 * Routine: pmap_extract_and_hold
1472 * Atomically extract and hold the physical page
1473 * with the given pmap and virtual address pair
1474 * if that mapping permits the given protection.
1477 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1479 pt_entry_t *pte, tpte;
1487 pte = pmap_pte(pmap, va, &lvl);
1489 tpte = pmap_load(pte);
1491 KASSERT(lvl > 0 && lvl <= 3,
1492 ("pmap_extract_and_hold: Invalid level %d", lvl));
1493 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1494 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1495 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1496 tpte & ATTR_DESCR_MASK));
1499 if ((prot & VM_PROT_WRITE) == 0)
1501 else if (pmap->pm_stage == PM_STAGE1 &&
1502 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW))
1504 else if (pmap->pm_stage == PM_STAGE2 &&
1505 ((tpte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
1506 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)))
1512 off = va & L1_OFFSET;
1515 off = va & L2_OFFSET;
1521 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1522 if (m != NULL && !vm_page_wire_mapped(m))
1531 * Walks the page tables to translate a kernel virtual address to a
1532 * physical address. Returns true if the kva is valid and stores the
1533 * physical address in pa if it is not NULL.
1536 pmap_klookup(vm_offset_t va, vm_paddr_t *pa)
1538 pt_entry_t *pte, tpte;
1543 * Disable interrupts so we don't get interrupted between asking
1544 * for address translation, and getting the result back.
1546 intr = intr_disable();
1547 par = arm64_address_translate_s1e1r(va);
1550 if (PAR_SUCCESS(par)) {
1552 *pa = (par & PAR_PA_MASK) | (va & PAR_LOW_MASK);
1557 * Fall back to walking the page table. The address translation
1558 * instruction may fail when the page is in a break-before-make
1559 * sequence. As we only clear the valid bit in said sequence we
1560 * can walk the page table to find the physical address.
1563 pte = pmap_l1(kernel_pmap, va);
1568 * A concurrent pmap_update_entry() will clear the entry's valid bit
1569 * but leave the rest of the entry unchanged. Therefore, we treat a
1570 * non-zero entry as being valid, and we ignore the valid bit when
1571 * determining whether the entry maps a block, page, or table.
1573 tpte = pmap_load(pte);
1576 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
1578 *pa = (tpte & ~ATTR_MASK) | (va & L1_OFFSET);
1581 pte = pmap_l1_to_l2(&tpte, va);
1582 tpte = pmap_load(pte);
1585 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
1587 *pa = (tpte & ~ATTR_MASK) | (va & L2_OFFSET);
1590 pte = pmap_l2_to_l3(&tpte, va);
1591 tpte = pmap_load(pte);
1595 *pa = (tpte & ~ATTR_MASK) | (va & L3_OFFSET);
1600 pmap_kextract(vm_offset_t va)
1604 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
1605 return (DMAP_TO_PHYS(va));
1607 if (pmap_klookup(va, &pa) == false)
1612 /***************************************************
1613 * Low level mapping routines.....
1614 ***************************************************/
1617 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1620 pt_entry_t *pte, attr;
1624 KASSERT((pa & L3_OFFSET) == 0,
1625 ("pmap_kenter: Invalid physical address"));
1626 KASSERT((sva & L3_OFFSET) == 0,
1627 ("pmap_kenter: Invalid virtual address"));
1628 KASSERT((size & PAGE_MASK) == 0,
1629 ("pmap_kenter: Mapping is not page-sized"));
1631 attr = ATTR_DEFAULT | ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1632 ATTR_S1_IDX(mode) | L3_PAGE;
1635 pde = pmap_pde(kernel_pmap, va, &lvl);
1636 KASSERT(pde != NULL,
1637 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1638 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1640 pte = pmap_l2_to_l3(pde, va);
1641 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1647 pmap_invalidate_range(kernel_pmap, sva, va, true);
1651 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1654 pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
1658 * Remove a page from the kernel pagetables.
1661 pmap_kremove(vm_offset_t va)
1666 pte = pmap_pte(kernel_pmap, va, &lvl);
1667 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1668 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1671 pmap_invalidate_page(kernel_pmap, va, true);
1675 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1681 KASSERT((sva & L3_OFFSET) == 0,
1682 ("pmap_kremove_device: Invalid virtual address"));
1683 KASSERT((size & PAGE_MASK) == 0,
1684 ("pmap_kremove_device: Mapping is not page-sized"));
1688 pte = pmap_pte(kernel_pmap, va, &lvl);
1689 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1691 ("Invalid device pagetable level: %d != 3", lvl));
1697 pmap_invalidate_range(kernel_pmap, sva, va, true);
1701 * Used to map a range of physical addresses into kernel
1702 * virtual address space.
1704 * The value passed in '*virt' is a suggested virtual address for
1705 * the mapping. Architectures which can support a direct-mapped
1706 * physical to virtual region can return the appropriate address
1707 * within that region, leaving '*virt' unchanged. Other
1708 * architectures should map the pages starting at '*virt' and
1709 * update '*virt' with the first usable address after the mapped
1713 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1715 return PHYS_TO_DMAP(start);
1719 * Add a list of wired pages to the kva
1720 * this routine is only used for temporary
1721 * kernel mappings that do not need to have
1722 * page modification or references recorded.
1723 * Note that old mappings are simply written
1724 * over. The page *must* be wired.
1725 * Note: SMP coherent. Uses a ranged shootdown IPI.
1728 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1731 pt_entry_t *pte, pa;
1737 for (i = 0; i < count; i++) {
1738 pde = pmap_pde(kernel_pmap, va, &lvl);
1739 KASSERT(pde != NULL,
1740 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1742 ("pmap_qenter: Invalid level %d", lvl));
1745 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
1746 ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1747 ATTR_S1_IDX(m->md.pv_memattr) | L3_PAGE;
1748 pte = pmap_l2_to_l3(pde, va);
1749 pmap_load_store(pte, pa);
1753 pmap_invalidate_range(kernel_pmap, sva, va, true);
1757 * This routine tears out page mappings from the
1758 * kernel -- it is meant only for temporary mappings.
1761 pmap_qremove(vm_offset_t sva, int count)
1767 KASSERT(ADDR_IS_CANONICAL(sva),
1768 ("%s: Address not in canonical form: %lx", __func__, sva));
1769 KASSERT(ADDR_IS_KERNEL(sva), ("usermode va %lx", sva));
1772 while (count-- > 0) {
1773 pte = pmap_pte(kernel_pmap, va, &lvl);
1775 ("Invalid device pagetable level: %d != 3", lvl));
1782 pmap_invalidate_range(kernel_pmap, sva, va, true);
1785 /***************************************************
1786 * Page table page management routines.....
1787 ***************************************************/
1789 * Schedule the specified unused page table page to be freed. Specifically,
1790 * add the page to the specified list of pages that will be released to the
1791 * physical memory manager after the TLB has been updated.
1793 static __inline void
1794 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1795 boolean_t set_PG_ZERO)
1799 m->flags |= PG_ZERO;
1801 m->flags &= ~PG_ZERO;
1802 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1806 * Decrements a page table page's reference count, which is used to record the
1807 * number of valid page table entries within the page. If the reference count
1808 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1809 * page table page was unmapped and FALSE otherwise.
1811 static inline boolean_t
1812 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1816 if (m->ref_count == 0) {
1817 _pmap_unwire_l3(pmap, va, m, free);
1824 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1827 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1829 * unmap the page table page
1831 if (m->pindex >= (NUL2E + NUL1E)) {
1835 l0 = pmap_l0(pmap, va);
1837 } else if (m->pindex >= NUL2E) {
1841 l1 = pmap_l1(pmap, va);
1847 l2 = pmap_l2(pmap, va);
1850 pmap_resident_count_dec(pmap, 1);
1851 if (m->pindex < NUL2E) {
1852 /* We just released an l3, unhold the matching l2 */
1853 pd_entry_t *l1, tl1;
1856 l1 = pmap_l1(pmap, va);
1857 tl1 = pmap_load(l1);
1858 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1859 pmap_unwire_l3(pmap, va, l2pg, free);
1860 } else if (m->pindex < (NUL2E + NUL1E)) {
1861 /* We just released an l2, unhold the matching l1 */
1862 pd_entry_t *l0, tl0;
1865 l0 = pmap_l0(pmap, va);
1866 tl0 = pmap_load(l0);
1867 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1868 pmap_unwire_l3(pmap, va, l1pg, free);
1870 pmap_invalidate_page(pmap, va, false);
1873 * Put page on a list so that it is released after
1874 * *ALL* TLB shootdown is done
1876 pmap_add_delayed_free_list(m, free, TRUE);
1880 * After removing a page table entry, this routine is used to
1881 * conditionally free the page, and manage the reference count.
1884 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1885 struct spglist *free)
1889 KASSERT(ADDR_IS_CANONICAL(va),
1890 ("%s: Address not in canonical form: %lx", __func__, va));
1891 if (ADDR_IS_KERNEL(va))
1893 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1894 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1895 return (pmap_unwire_l3(pmap, va, mpte, free));
1899 * Release a page table page reference after a failed attempt to create a
1903 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
1905 struct spglist free;
1908 if (pmap_unwire_l3(pmap, va, mpte, &free))
1909 vm_page_free_pages_toq(&free, true);
1913 pmap_pinit0(pmap_t pmap)
1916 PMAP_LOCK_INIT(pmap);
1917 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1918 pmap->pm_l0_paddr = READ_SPECIALREG(ttbr0_el1);
1919 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1920 vm_radix_init(&pmap->pm_root);
1921 pmap->pm_cookie = COOKIE_FROM(ASID_RESERVED_FOR_PID_0, INT_MIN);
1922 pmap->pm_stage = PM_STAGE1;
1923 pmap->pm_levels = 4;
1924 pmap->pm_ttbr = pmap->pm_l0_paddr;
1925 pmap->pm_asid_set = &asids;
1927 PCPU_SET(curpmap, pmap);
1931 pmap_pinit_stage(pmap_t pmap, enum pmap_stage stage, int levels)
1936 * allocate the l0 page
1938 m = vm_page_alloc_noobj(VM_ALLOC_WAITOK | VM_ALLOC_WIRED |
1940 pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(m);
1941 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1943 vm_radix_init(&pmap->pm_root);
1944 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1945 pmap->pm_cookie = COOKIE_FROM(-1, INT_MAX);
1947 MPASS(levels == 3 || levels == 4);
1948 pmap->pm_levels = levels;
1949 pmap->pm_stage = stage;
1952 pmap->pm_asid_set = &asids;
1955 pmap->pm_asid_set = &vmids;
1958 panic("%s: Invalid pmap type %d", __func__, stage);
1962 /* XXX Temporarily disable deferred ASID allocation. */
1963 pmap_alloc_asid(pmap);
1966 * Allocate the level 1 entry to use as the root. This will increase
1967 * the refcount on the level 1 page so it won't be removed until
1968 * pmap_release() is called.
1970 if (pmap->pm_levels == 3) {
1972 m = _pmap_alloc_l3(pmap, NUL2E + NUL1E, NULL);
1975 pmap->pm_ttbr = VM_PAGE_TO_PHYS(m);
1981 pmap_pinit(pmap_t pmap)
1984 return (pmap_pinit_stage(pmap, PM_STAGE1, 4));
1988 * This routine is called if the desired page table page does not exist.
1990 * If page table page allocation fails, this routine may sleep before
1991 * returning NULL. It sleeps only if a lock pointer was given.
1993 * Note: If a page allocation fails at page table level two or three,
1994 * one or two pages may be held during the wait, only to be released
1995 * afterwards. This conservative approach is easily argued to avoid
1999 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
2001 vm_page_t m, l1pg, l2pg;
2003 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2006 * Allocate a page table page.
2008 if ((m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2009 if (lockp != NULL) {
2010 RELEASE_PV_LIST_LOCK(lockp);
2017 * Indicate the need to retry. While waiting, the page table
2018 * page may have been allocated.
2022 m->pindex = ptepindex;
2025 * Because of AArch64's weak memory consistency model, we must have a
2026 * barrier here to ensure that the stores for zeroing "m", whether by
2027 * pmap_zero_page() or an earlier function, are visible before adding
2028 * "m" to the page table. Otherwise, a page table walk by another
2029 * processor's MMU could see the mapping to "m" and a stale, non-zero
2035 * Map the pagetable page into the process address space, if
2036 * it isn't already there.
2039 if (ptepindex >= (NUL2E + NUL1E)) {
2040 pd_entry_t *l0p, l0e;
2041 vm_pindex_t l0index;
2043 l0index = ptepindex - (NUL2E + NUL1E);
2044 l0p = &pmap->pm_l0[l0index];
2045 KASSERT((pmap_load(l0p) & ATTR_DESCR_VALID) == 0,
2046 ("%s: L0 entry %#lx is valid", __func__, pmap_load(l0p)));
2047 l0e = VM_PAGE_TO_PHYS(m) | L0_TABLE;
2050 * Mark all kernel memory as not accessible from userspace
2051 * and userspace memory as not executable from the kernel.
2052 * This has been done for the bootstrap L0 entries in
2055 if (pmap == kernel_pmap)
2056 l0e |= TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0;
2058 l0e |= TATTR_PXN_TABLE;
2059 pmap_store(l0p, l0e);
2060 } else if (ptepindex >= NUL2E) {
2061 vm_pindex_t l0index, l1index;
2062 pd_entry_t *l0, *l1;
2065 l1index = ptepindex - NUL2E;
2066 l0index = l1index >> Ln_ENTRIES_SHIFT;
2068 l0 = &pmap->pm_l0[l0index];
2069 tl0 = pmap_load(l0);
2071 /* recurse for allocating page dir */
2072 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
2074 vm_page_unwire_noq(m);
2075 vm_page_free_zero(m);
2079 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
2083 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
2084 l1 = &l1[ptepindex & Ln_ADDR_MASK];
2085 KASSERT((pmap_load(l1) & ATTR_DESCR_VALID) == 0,
2086 ("%s: L1 entry %#lx is valid", __func__, pmap_load(l1)));
2087 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
2089 vm_pindex_t l0index, l1index;
2090 pd_entry_t *l0, *l1, *l2;
2091 pd_entry_t tl0, tl1;
2093 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
2094 l0index = l1index >> Ln_ENTRIES_SHIFT;
2096 l0 = &pmap->pm_l0[l0index];
2097 tl0 = pmap_load(l0);
2099 /* recurse for allocating page dir */
2100 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
2102 vm_page_unwire_noq(m);
2103 vm_page_free_zero(m);
2106 tl0 = pmap_load(l0);
2107 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
2108 l1 = &l1[l1index & Ln_ADDR_MASK];
2110 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
2111 l1 = &l1[l1index & Ln_ADDR_MASK];
2112 tl1 = pmap_load(l1);
2114 /* recurse for allocating page dir */
2115 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
2117 vm_page_unwire_noq(m);
2118 vm_page_free_zero(m);
2122 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
2127 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
2128 l2 = &l2[ptepindex & Ln_ADDR_MASK];
2129 KASSERT((pmap_load(l2) & ATTR_DESCR_VALID) == 0,
2130 ("%s: L2 entry %#lx is valid", __func__, pmap_load(l2)));
2131 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
2134 pmap_resident_count_inc(pmap, 1);
2140 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, vm_page_t *l2pgp,
2141 struct rwlock **lockp)
2143 pd_entry_t *l1, *l2;
2145 vm_pindex_t l2pindex;
2147 KASSERT(ADDR_IS_CANONICAL(va),
2148 ("%s: Address not in canonical form: %lx", __func__, va));
2151 l1 = pmap_l1(pmap, va);
2152 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
2153 l2 = pmap_l1_to_l2(l1, va);
2154 if (!ADDR_IS_KERNEL(va)) {
2155 /* Add a reference to the L2 page. */
2156 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
2160 } else if (!ADDR_IS_KERNEL(va)) {
2161 /* Allocate a L2 page. */
2162 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
2163 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
2170 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
2171 l2 = &l2[pmap_l2_index(va)];
2173 panic("pmap_alloc_l2: missing page table page for va %#lx",
2180 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2182 vm_pindex_t ptepindex;
2183 pd_entry_t *pde, tpde;
2191 * Calculate pagetable page index
2193 ptepindex = pmap_l2_pindex(va);
2196 * Get the page directory entry
2198 pde = pmap_pde(pmap, va, &lvl);
2201 * If the page table page is mapped, we just increment the hold count,
2202 * and activate it. If we get a level 2 pde it will point to a level 3
2210 pte = pmap_l0_to_l1(pde, va);
2211 KASSERT(pmap_load(pte) == 0,
2212 ("pmap_alloc_l3: TODO: l0 superpages"));
2217 pte = pmap_l1_to_l2(pde, va);
2218 KASSERT(pmap_load(pte) == 0,
2219 ("pmap_alloc_l3: TODO: l1 superpages"));
2223 tpde = pmap_load(pde);
2225 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
2231 panic("pmap_alloc_l3: Invalid level %d", lvl);
2235 * Here if the pte page isn't mapped, or if it has been deallocated.
2237 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
2238 if (m == NULL && lockp != NULL)
2244 /***************************************************
2245 * Pmap allocation/deallocation routines.
2246 ***************************************************/
2249 * Release any resources held by the given physical map.
2250 * Called when a pmap initialized by pmap_pinit is being released.
2251 * Should only be called if the map contains no valid mappings.
2254 pmap_release(pmap_t pmap)
2257 struct spglist free;
2258 struct asid_set *set;
2262 if (pmap->pm_levels != 4) {
2263 PMAP_ASSERT_STAGE2(pmap);
2264 KASSERT(pmap->pm_stats.resident_count == 1,
2265 ("pmap_release: pmap resident count %ld != 0",
2266 pmap->pm_stats.resident_count));
2267 KASSERT((pmap->pm_l0[0] & ATTR_DESCR_VALID) == ATTR_DESCR_VALID,
2268 ("pmap_release: Invalid l0 entry: %lx", pmap->pm_l0[0]));
2271 m = PHYS_TO_VM_PAGE(pmap->pm_ttbr);
2273 rv = pmap_unwire_l3(pmap, 0, m, &free);
2276 vm_page_free_pages_toq(&free, true);
2279 KASSERT(pmap->pm_stats.resident_count == 0,
2280 ("pmap_release: pmap resident count %ld != 0",
2281 pmap->pm_stats.resident_count));
2282 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2283 ("pmap_release: pmap has reserved page table page(s)"));
2285 set = pmap->pm_asid_set;
2286 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
2289 * Allow the ASID to be reused. In stage 2 VMIDs we don't invalidate
2290 * the entries when removing them so rely on a later tlb invalidation.
2291 * this will happen when updating the VMID generation. Because of this
2292 * we don't reuse VMIDs within a generation.
2294 if (pmap->pm_stage == PM_STAGE1) {
2295 mtx_lock_spin(&set->asid_set_mutex);
2296 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch) {
2297 asid = COOKIE_TO_ASID(pmap->pm_cookie);
2298 KASSERT(asid >= ASID_FIRST_AVAILABLE &&
2299 asid < set->asid_set_size,
2300 ("pmap_release: pmap cookie has out-of-range asid"));
2301 bit_clear(set->asid_set, asid);
2303 mtx_unlock_spin(&set->asid_set_mutex);
2306 m = PHYS_TO_VM_PAGE(pmap->pm_l0_paddr);
2307 vm_page_unwire_noq(m);
2308 vm_page_free_zero(m);
2312 kvm_size(SYSCTL_HANDLER_ARGS)
2314 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
2316 return sysctl_handle_long(oidp, &ksize, 0, req);
2318 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
2319 0, 0, kvm_size, "LU",
2323 kvm_free(SYSCTL_HANDLER_ARGS)
2325 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2327 return sysctl_handle_long(oidp, &kfree, 0, req);
2329 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
2330 0, 0, kvm_free, "LU",
2331 "Amount of KVM free");
2334 * grow the number of kernel page table entries, if needed
2337 pmap_growkernel(vm_offset_t addr)
2341 pd_entry_t *l0, *l1, *l2;
2343 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2345 addr = roundup2(addr, L2_SIZE);
2346 if (addr - 1 >= vm_map_max(kernel_map))
2347 addr = vm_map_max(kernel_map);
2348 while (kernel_vm_end < addr) {
2349 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
2350 KASSERT(pmap_load(l0) != 0,
2351 ("pmap_growkernel: No level 0 kernel entry"));
2353 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
2354 if (pmap_load(l1) == 0) {
2355 /* We need a new PDP entry */
2356 nkpg = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT |
2357 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2359 panic("pmap_growkernel: no memory to grow kernel");
2360 nkpg->pindex = kernel_vm_end >> L1_SHIFT;
2361 /* See the dmb() in _pmap_alloc_l3(). */
2363 paddr = VM_PAGE_TO_PHYS(nkpg);
2364 pmap_store(l1, paddr | L1_TABLE);
2365 continue; /* try again */
2367 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
2368 if (pmap_load(l2) != 0) {
2369 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2370 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2371 kernel_vm_end = vm_map_max(kernel_map);
2377 nkpg = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED |
2380 panic("pmap_growkernel: no memory to grow kernel");
2381 nkpg->pindex = kernel_vm_end >> L2_SHIFT;
2382 /* See the dmb() in _pmap_alloc_l3(). */
2384 paddr = VM_PAGE_TO_PHYS(nkpg);
2385 pmap_store(l2, paddr | L2_TABLE);
2387 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2388 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2389 kernel_vm_end = vm_map_max(kernel_map);
2395 /***************************************************
2396 * page management routines.
2397 ***************************************************/
2399 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2400 CTASSERT(_NPCM == 3);
2401 CTASSERT(_NPCPV == 168);
2403 static __inline struct pv_chunk *
2404 pv_to_chunk(pv_entry_t pv)
2407 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2410 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2412 #define PC_FREE0 0xfffffffffffffffful
2413 #define PC_FREE1 0xfffffffffffffffful
2414 #define PC_FREE2 0x000000fffffffffful
2416 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2419 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2421 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2422 "Current number of pv entry chunks");
2423 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2424 "Current number of pv entry chunks allocated");
2425 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2426 "Current number of pv entry chunks frees");
2427 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2428 "Number of times tried to get a chunk page but failed.");
2430 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2431 static int pv_entry_spare;
2433 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2434 "Current number of pv entry frees");
2435 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2436 "Current number of pv entry allocs");
2437 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2438 "Current number of pv entries");
2439 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2440 "Current number of spare pv entries");
2444 * We are in a serious low memory condition. Resort to
2445 * drastic measures to free some pages so we can allocate
2446 * another pv entry chunk.
2448 * Returns NULL if PV entries were reclaimed from the specified pmap.
2450 * We do not, however, unmap 2mpages because subsequent accesses will
2451 * allocate per-page pv entries until repromotion occurs, thereby
2452 * exacerbating the shortage of free pv entries.
2455 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2457 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
2458 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
2459 struct md_page *pvh;
2461 pmap_t next_pmap, pmap;
2462 pt_entry_t *pte, tpte;
2466 struct spglist free;
2468 int bit, field, freed, lvl;
2469 static int active_reclaims = 0;
2471 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2472 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2477 bzero(&pc_marker_b, sizeof(pc_marker_b));
2478 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
2479 pc_marker = (struct pv_chunk *)&pc_marker_b;
2480 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
2482 mtx_lock(&pv_chunks_mutex);
2484 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
2485 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
2486 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
2487 SLIST_EMPTY(&free)) {
2488 next_pmap = pc->pc_pmap;
2489 if (next_pmap == NULL) {
2491 * The next chunk is a marker. However, it is
2492 * not our marker, so active_reclaims must be
2493 * > 1. Consequently, the next_chunk code
2494 * will not rotate the pv_chunks list.
2498 mtx_unlock(&pv_chunks_mutex);
2501 * A pv_chunk can only be removed from the pc_lru list
2502 * when both pv_chunks_mutex is owned and the
2503 * corresponding pmap is locked.
2505 if (pmap != next_pmap) {
2506 if (pmap != NULL && pmap != locked_pmap)
2509 /* Avoid deadlock and lock recursion. */
2510 if (pmap > locked_pmap) {
2511 RELEASE_PV_LIST_LOCK(lockp);
2513 mtx_lock(&pv_chunks_mutex);
2515 } else if (pmap != locked_pmap) {
2516 if (PMAP_TRYLOCK(pmap)) {
2517 mtx_lock(&pv_chunks_mutex);
2520 pmap = NULL; /* pmap is not locked */
2521 mtx_lock(&pv_chunks_mutex);
2522 pc = TAILQ_NEXT(pc_marker, pc_lru);
2524 pc->pc_pmap != next_pmap)
2532 * Destroy every non-wired, 4 KB page mapping in the chunk.
2535 for (field = 0; field < _NPCM; field++) {
2536 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2537 inuse != 0; inuse &= ~(1UL << bit)) {
2538 bit = ffsl(inuse) - 1;
2539 pv = &pc->pc_pventry[field * 64 + bit];
2541 pde = pmap_pde(pmap, va, &lvl);
2544 pte = pmap_l2_to_l3(pde, va);
2545 tpte = pmap_load(pte);
2546 if ((tpte & ATTR_SW_WIRED) != 0)
2548 tpte = pmap_load_clear(pte);
2549 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
2550 if (pmap_pte_dirty(pmap, tpte))
2552 if ((tpte & ATTR_AF) != 0) {
2553 pmap_invalidate_page(pmap, va, true);
2554 vm_page_aflag_set(m, PGA_REFERENCED);
2556 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2557 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2559 if (TAILQ_EMPTY(&m->md.pv_list) &&
2560 (m->flags & PG_FICTITIOUS) == 0) {
2561 pvh = page_to_pvh(m);
2562 if (TAILQ_EMPTY(&pvh->pv_list)) {
2563 vm_page_aflag_clear(m,
2567 pc->pc_map[field] |= 1UL << bit;
2568 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
2573 mtx_lock(&pv_chunks_mutex);
2576 /* Every freed mapping is for a 4 KB page. */
2577 pmap_resident_count_dec(pmap, freed);
2578 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2579 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2580 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2581 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2582 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2583 pc->pc_map[2] == PC_FREE2) {
2584 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2585 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2586 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2587 /* Entire chunk is free; return it. */
2588 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2589 dump_drop_page(m_pc->phys_addr);
2590 mtx_lock(&pv_chunks_mutex);
2591 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2594 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2595 mtx_lock(&pv_chunks_mutex);
2596 /* One freed pv entry in locked_pmap is sufficient. */
2597 if (pmap == locked_pmap)
2601 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2602 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2603 if (active_reclaims == 1 && pmap != NULL) {
2605 * Rotate the pv chunks list so that we do not
2606 * scan the same pv chunks that could not be
2607 * freed (because they contained a wired
2608 * and/or superpage mapping) on every
2609 * invocation of reclaim_pv_chunk().
2611 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2612 MPASS(pc->pc_pmap != NULL);
2613 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2614 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2618 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2619 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2621 mtx_unlock(&pv_chunks_mutex);
2622 if (pmap != NULL && pmap != locked_pmap)
2624 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2625 m_pc = SLIST_FIRST(&free);
2626 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2627 /* Recycle a freed page table page. */
2628 m_pc->ref_count = 1;
2630 vm_page_free_pages_toq(&free, true);
2635 * free the pv_entry back to the free list
2638 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2640 struct pv_chunk *pc;
2641 int idx, field, bit;
2643 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2644 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2645 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2646 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2647 pc = pv_to_chunk(pv);
2648 idx = pv - &pc->pc_pventry[0];
2651 pc->pc_map[field] |= 1ul << bit;
2652 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2653 pc->pc_map[2] != PC_FREE2) {
2654 /* 98% of the time, pc is already at the head of the list. */
2655 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2656 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2657 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2661 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2666 free_pv_chunk(struct pv_chunk *pc)
2670 mtx_lock(&pv_chunks_mutex);
2671 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2672 mtx_unlock(&pv_chunks_mutex);
2673 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2674 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2675 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2676 /* entire chunk is free, return it */
2677 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2678 dump_drop_page(m->phys_addr);
2679 vm_page_unwire_noq(m);
2684 * Returns a new PV entry, allocating a new PV chunk from the system when
2685 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2686 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2689 * The given PV list lock may be released.
2692 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2696 struct pv_chunk *pc;
2699 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2700 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2702 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2704 for (field = 0; field < _NPCM; field++) {
2705 if (pc->pc_map[field]) {
2706 bit = ffsl(pc->pc_map[field]) - 1;
2710 if (field < _NPCM) {
2711 pv = &pc->pc_pventry[field * 64 + bit];
2712 pc->pc_map[field] &= ~(1ul << bit);
2713 /* If this was the last item, move it to tail */
2714 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2715 pc->pc_map[2] == 0) {
2716 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2717 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2720 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2721 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2725 /* No free items, allocate another chunk */
2726 m = vm_page_alloc_noobj(VM_ALLOC_WIRED);
2728 if (lockp == NULL) {
2729 PV_STAT(pc_chunk_tryfail++);
2732 m = reclaim_pv_chunk(pmap, lockp);
2736 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2737 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2738 dump_add_page(m->phys_addr);
2739 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2741 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2742 pc->pc_map[1] = PC_FREE1;
2743 pc->pc_map[2] = PC_FREE2;
2744 mtx_lock(&pv_chunks_mutex);
2745 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2746 mtx_unlock(&pv_chunks_mutex);
2747 pv = &pc->pc_pventry[0];
2748 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2749 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2750 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2755 * Ensure that the number of spare PV entries in the specified pmap meets or
2756 * exceeds the given count, "needed".
2758 * The given PV list lock may be released.
2761 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2763 struct pch new_tail;
2764 struct pv_chunk *pc;
2769 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2770 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2773 * Newly allocated PV chunks must be stored in a private list until
2774 * the required number of PV chunks have been allocated. Otherwise,
2775 * reclaim_pv_chunk() could recycle one of these chunks. In
2776 * contrast, these chunks must be added to the pmap upon allocation.
2778 TAILQ_INIT(&new_tail);
2781 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2782 bit_count((bitstr_t *)pc->pc_map, 0,
2783 sizeof(pc->pc_map) * NBBY, &free);
2787 if (avail >= needed)
2790 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2791 m = vm_page_alloc_noobj(VM_ALLOC_WIRED);
2793 m = reclaim_pv_chunk(pmap, lockp);
2798 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2799 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2800 dump_add_page(m->phys_addr);
2801 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2803 pc->pc_map[0] = PC_FREE0;
2804 pc->pc_map[1] = PC_FREE1;
2805 pc->pc_map[2] = PC_FREE2;
2806 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2807 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2808 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2811 * The reclaim might have freed a chunk from the current pmap.
2812 * If that chunk contained available entries, we need to
2813 * re-count the number of available entries.
2818 if (!TAILQ_EMPTY(&new_tail)) {
2819 mtx_lock(&pv_chunks_mutex);
2820 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2821 mtx_unlock(&pv_chunks_mutex);
2826 * First find and then remove the pv entry for the specified pmap and virtual
2827 * address from the specified pv list. Returns the pv entry if found and NULL
2828 * otherwise. This operation can be performed on pv lists for either 4KB or
2829 * 2MB page mappings.
2831 static __inline pv_entry_t
2832 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2836 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2837 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2838 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2847 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2848 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2849 * entries for each of the 4KB page mappings.
2852 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2853 struct rwlock **lockp)
2855 struct md_page *pvh;
2856 struct pv_chunk *pc;
2858 vm_offset_t va_last;
2862 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2863 KASSERT((va & L2_OFFSET) == 0,
2864 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
2865 KASSERT((pa & L2_OFFSET) == 0,
2866 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2867 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2870 * Transfer the 2mpage's pv entry for this mapping to the first
2871 * page's pv list. Once this transfer begins, the pv list lock
2872 * must not be released until the last pv entry is reinstantiated.
2874 pvh = pa_to_pvh(pa);
2875 pv = pmap_pvh_remove(pvh, pmap, va);
2876 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2877 m = PHYS_TO_VM_PAGE(pa);
2878 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2880 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2881 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2882 va_last = va + L2_SIZE - PAGE_SIZE;
2884 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2885 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2886 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2887 for (field = 0; field < _NPCM; field++) {
2888 while (pc->pc_map[field]) {
2889 bit = ffsl(pc->pc_map[field]) - 1;
2890 pc->pc_map[field] &= ~(1ul << bit);
2891 pv = &pc->pc_pventry[field * 64 + bit];
2895 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2896 ("pmap_pv_demote_l2: page %p is not managed", m));
2897 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2903 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2904 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2907 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2908 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2909 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2911 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2912 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2916 * First find and then destroy the pv entry for the specified pmap and virtual
2917 * address. This operation can be performed on pv lists for either 4KB or 2MB
2921 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2925 pv = pmap_pvh_remove(pvh, pmap, va);
2926 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2927 free_pv_entry(pmap, pv);
2931 * Conditionally create the PV entry for a 4KB page mapping if the required
2932 * memory can be allocated without resorting to reclamation.
2935 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2936 struct rwlock **lockp)
2940 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2941 /* Pass NULL instead of the lock pointer to disable reclamation. */
2942 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2944 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2945 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2953 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2954 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2955 * false if the PV entry cannot be allocated without resorting to reclamation.
2958 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2959 struct rwlock **lockp)
2961 struct md_page *pvh;
2965 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2966 /* Pass NULL instead of the lock pointer to disable reclamation. */
2967 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2968 NULL : lockp)) == NULL)
2971 pa = l2e & ~ATTR_MASK;
2972 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2973 pvh = pa_to_pvh(pa);
2974 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2980 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2982 pt_entry_t newl2, oldl2;
2986 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2987 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2988 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2990 ml3 = pmap_remove_pt_page(pmap, va);
2992 panic("pmap_remove_kernel_l2: Missing pt page");
2994 ml3pa = VM_PAGE_TO_PHYS(ml3);
2995 newl2 = ml3pa | L2_TABLE;
2998 * If this page table page was unmapped by a promotion, then it
2999 * contains valid mappings. Zero it to invalidate those mappings.
3001 if (ml3->valid != 0)
3002 pagezero((void *)PHYS_TO_DMAP(ml3pa));
3005 * Demote the mapping. The caller must have already invalidated the
3006 * mapping (i.e., the "break" in break-before-make).
3008 oldl2 = pmap_load_store(l2, newl2);
3009 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
3010 __func__, l2, oldl2));
3014 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
3017 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
3018 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
3020 struct md_page *pvh;
3022 vm_page_t m, ml3, mt;
3024 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3025 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
3026 old_l2 = pmap_load_clear(l2);
3027 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
3028 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
3031 * Since a promotion must break the 4KB page mappings before making
3032 * the 2MB page mapping, a pmap_invalidate_page() suffices.
3034 pmap_invalidate_page(pmap, sva, true);
3036 if (old_l2 & ATTR_SW_WIRED)
3037 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
3038 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
3039 if (old_l2 & ATTR_SW_MANAGED) {
3040 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
3041 pvh = page_to_pvh(m);
3042 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
3043 pmap_pvh_free(pvh, pmap, sva);
3044 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) {
3045 if (pmap_pte_dirty(pmap, old_l2))
3047 if (old_l2 & ATTR_AF)
3048 vm_page_aflag_set(mt, PGA_REFERENCED);
3049 if (TAILQ_EMPTY(&mt->md.pv_list) &&
3050 TAILQ_EMPTY(&pvh->pv_list))
3051 vm_page_aflag_clear(mt, PGA_WRITEABLE);
3054 if (pmap == kernel_pmap) {
3055 pmap_remove_kernel_l2(pmap, l2, sva);
3057 ml3 = pmap_remove_pt_page(pmap, sva);
3059 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
3060 ("pmap_remove_l2: l3 page not promoted"));
3061 pmap_resident_count_dec(pmap, 1);
3062 KASSERT(ml3->ref_count == NL3PG,
3063 ("pmap_remove_l2: l3 page ref count error"));
3065 pmap_add_delayed_free_list(ml3, free, FALSE);
3068 return (pmap_unuse_pt(pmap, sva, l1e, free));
3072 * pmap_remove_l3: do the things to unmap a page in a process
3075 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
3076 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
3078 struct md_page *pvh;
3082 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3083 old_l3 = pmap_load_clear(l3);
3084 pmap_invalidate_page(pmap, va, true);
3085 if (old_l3 & ATTR_SW_WIRED)
3086 pmap->pm_stats.wired_count -= 1;
3087 pmap_resident_count_dec(pmap, 1);
3088 if (old_l3 & ATTR_SW_MANAGED) {
3089 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
3090 if (pmap_pte_dirty(pmap, old_l3))
3092 if (old_l3 & ATTR_AF)
3093 vm_page_aflag_set(m, PGA_REFERENCED);
3094 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3095 pmap_pvh_free(&m->md, pmap, va);
3096 if (TAILQ_EMPTY(&m->md.pv_list) &&
3097 (m->flags & PG_FICTITIOUS) == 0) {
3098 pvh = page_to_pvh(m);
3099 if (TAILQ_EMPTY(&pvh->pv_list))
3100 vm_page_aflag_clear(m, PGA_WRITEABLE);
3103 return (pmap_unuse_pt(pmap, va, l2e, free));
3107 * Remove the specified range of addresses from the L3 page table that is
3108 * identified by the given L2 entry.
3111 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
3112 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
3114 struct md_page *pvh;
3115 struct rwlock *new_lock;
3116 pt_entry_t *l3, old_l3;
3120 KASSERT(ADDR_IS_CANONICAL(sva),
3121 ("%s: Start address not in canonical form: %lx", __func__, sva));
3122 KASSERT(ADDR_IS_CANONICAL(eva) || eva == VM_MAX_USER_ADDRESS,
3123 ("%s: End address not in canonical form: %lx", __func__, eva));
3125 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3126 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
3127 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
3128 l3pg = !ADDR_IS_KERNEL(sva) ? PHYS_TO_VM_PAGE(l2e & ~ATTR_MASK) : NULL;
3130 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
3131 if (!pmap_l3_valid(pmap_load(l3))) {
3133 pmap_invalidate_range(pmap, va, sva, true);
3138 old_l3 = pmap_load_clear(l3);
3139 if ((old_l3 & ATTR_SW_WIRED) != 0)
3140 pmap->pm_stats.wired_count--;
3141 pmap_resident_count_dec(pmap, 1);
3142 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
3143 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
3144 if (pmap_pte_dirty(pmap, old_l3))
3146 if ((old_l3 & ATTR_AF) != 0)
3147 vm_page_aflag_set(m, PGA_REFERENCED);
3148 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
3149 if (new_lock != *lockp) {
3150 if (*lockp != NULL) {
3152 * Pending TLB invalidations must be
3153 * performed before the PV list lock is
3154 * released. Otherwise, a concurrent
3155 * pmap_remove_all() on a physical page
3156 * could return while a stale TLB entry
3157 * still provides access to that page.
3160 pmap_invalidate_range(pmap, va,
3169 pmap_pvh_free(&m->md, pmap, sva);
3170 if (TAILQ_EMPTY(&m->md.pv_list) &&
3171 (m->flags & PG_FICTITIOUS) == 0) {
3172 pvh = page_to_pvh(m);
3173 if (TAILQ_EMPTY(&pvh->pv_list))
3174 vm_page_aflag_clear(m, PGA_WRITEABLE);
3177 if (l3pg != NULL && pmap_unwire_l3(pmap, sva, l3pg, free)) {
3179 * _pmap_unwire_l3() has already invalidated the TLB
3180 * entries at all levels for "sva". So, we need not
3181 * perform "sva += L3_SIZE;" here. Moreover, we need
3182 * not perform "va = sva;" if "sva" is at the start
3183 * of a new valid range consisting of a single page.
3191 pmap_invalidate_range(pmap, va, sva, true);
3195 * Remove the given range of addresses from the specified map.
3197 * It is assumed that the start and end are properly
3198 * rounded to the page size.
3201 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3203 struct rwlock *lock;
3204 vm_offset_t va_next;
3205 pd_entry_t *l0, *l1, *l2;
3206 pt_entry_t l3_paddr;
3207 struct spglist free;
3210 * Perform an unsynchronized read. This is, however, safe.
3212 if (pmap->pm_stats.resident_count == 0)
3220 for (; sva < eva; sva = va_next) {
3221 if (pmap->pm_stats.resident_count == 0)
3224 l0 = pmap_l0(pmap, sva);
3225 if (pmap_load(l0) == 0) {
3226 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3232 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3235 l1 = pmap_l0_to_l1(l0, sva);
3236 if (pmap_load(l1) == 0)
3238 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
3239 KASSERT(va_next <= eva,
3240 ("partial update of non-transparent 1G page "
3241 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
3242 pmap_load(l1), sva, eva, va_next));
3243 MPASS(pmap != kernel_pmap);
3244 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0);
3246 pmap_invalidate_page(pmap, sva, true);
3247 pmap_resident_count_dec(pmap, L1_SIZE / PAGE_SIZE);
3248 pmap_unuse_pt(pmap, sva, pmap_load(l0), &free);
3253 * Calculate index for next page table.
3255 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3259 l2 = pmap_l1_to_l2(l1, sva);
3263 l3_paddr = pmap_load(l2);
3265 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
3266 if (sva + L2_SIZE == va_next && eva >= va_next) {
3267 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
3270 } else if (pmap_demote_l2_locked(pmap, l2, sva,
3273 l3_paddr = pmap_load(l2);
3277 * Weed out invalid mappings.
3279 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
3283 * Limit our scan to either the end of the va represented
3284 * by the current page table page, or to the end of the
3285 * range being removed.
3290 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
3296 vm_page_free_pages_toq(&free, true);
3300 * Routine: pmap_remove_all
3302 * Removes this physical page from
3303 * all physical maps in which it resides.
3304 * Reflects back modify bits to the pager.
3307 * Original versions of this routine were very
3308 * inefficient because they iteratively called
3309 * pmap_remove (slow...)
3313 pmap_remove_all(vm_page_t m)
3315 struct md_page *pvh;
3318 struct rwlock *lock;
3319 pd_entry_t *pde, tpde;
3320 pt_entry_t *pte, tpte;
3322 struct spglist free;
3323 int lvl, pvh_gen, md_gen;
3325 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3326 ("pmap_remove_all: page %p is not managed", m));
3328 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3329 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
3332 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3334 if (!PMAP_TRYLOCK(pmap)) {
3335 pvh_gen = pvh->pv_gen;
3339 if (pvh_gen != pvh->pv_gen) {
3345 pte = pmap_pte(pmap, va, &lvl);
3346 KASSERT(pte != NULL,
3347 ("pmap_remove_all: no page table entry found"));
3349 ("pmap_remove_all: invalid pte level %d", lvl));
3350 pmap_demote_l2_locked(pmap, pte, va, &lock);
3353 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3355 PMAP_ASSERT_STAGE1(pmap);
3356 if (!PMAP_TRYLOCK(pmap)) {
3357 pvh_gen = pvh->pv_gen;
3358 md_gen = m->md.pv_gen;
3362 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
3367 pmap_resident_count_dec(pmap, 1);
3369 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3370 KASSERT(pde != NULL,
3371 ("pmap_remove_all: no page directory entry found"));
3373 ("pmap_remove_all: invalid pde level %d", lvl));
3374 tpde = pmap_load(pde);
3376 pte = pmap_l2_to_l3(pde, pv->pv_va);
3377 tpte = pmap_load_clear(pte);
3378 if (tpte & ATTR_SW_WIRED)
3379 pmap->pm_stats.wired_count--;
3380 if ((tpte & ATTR_AF) != 0) {
3381 pmap_invalidate_page(pmap, pv->pv_va, true);
3382 vm_page_aflag_set(m, PGA_REFERENCED);
3386 * Update the vm_page_t clean and reference bits.
3388 if (pmap_pte_dirty(pmap, tpte))
3390 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
3391 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3393 free_pv_entry(pmap, pv);
3396 vm_page_aflag_clear(m, PGA_WRITEABLE);
3398 vm_page_free_pages_toq(&free, true);
3402 * Masks and sets bits in a level 2 page table entries in the specified pmap
3405 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
3411 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3412 PMAP_ASSERT_STAGE1(pmap);
3413 KASSERT((sva & L2_OFFSET) == 0,
3414 ("pmap_protect_l2: sva is not 2mpage aligned"));
3415 old_l2 = pmap_load(l2);
3416 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
3417 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
3420 * Return if the L2 entry already has the desired access restrictions
3423 if ((old_l2 & mask) == nbits)
3426 while (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
3430 * When a dirty read/write superpage mapping is write protected,
3431 * update the dirty field of each of the superpage's constituent 4KB
3434 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
3435 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3436 pmap_pte_dirty(pmap, old_l2)) {
3437 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
3438 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3443 * Since a promotion must break the 4KB page mappings before making
3444 * the 2MB page mapping, a pmap_invalidate_page() suffices.
3446 pmap_invalidate_page(pmap, sva, true);
3450 * Masks and sets bits in last level page table entries in the specified
3454 pmap_mask_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, pt_entry_t mask,
3455 pt_entry_t nbits, bool invalidate)
3457 vm_offset_t va, va_next;
3458 pd_entry_t *l0, *l1, *l2;
3459 pt_entry_t *l3p, l3;
3462 for (; sva < eva; sva = va_next) {
3463 l0 = pmap_l0(pmap, sva);
3464 if (pmap_load(l0) == 0) {
3465 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3471 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3474 l1 = pmap_l0_to_l1(l0, sva);
3475 if (pmap_load(l1) == 0)
3477 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
3478 KASSERT(va_next <= eva,
3479 ("partial update of non-transparent 1G page "
3480 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
3481 pmap_load(l1), sva, eva, va_next));
3482 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0);
3483 if ((pmap_load(l1) & mask) != nbits) {
3484 pmap_store(l1, (pmap_load(l1) & ~mask) | nbits);
3486 pmap_invalidate_page(pmap, sva, true);
3491 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3495 l2 = pmap_l1_to_l2(l1, sva);
3496 if (pmap_load(l2) == 0)
3499 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3500 if (sva + L2_SIZE == va_next && eva >= va_next) {
3501 pmap_protect_l2(pmap, l2, sva, mask, nbits);
3503 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3506 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3507 ("pmap_protect: Invalid L2 entry after demotion"));
3513 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
3515 l3 = pmap_load(l3p);
3518 * Go to the next L3 entry if the current one is
3519 * invalid or already has the desired access
3520 * restrictions in place. (The latter case occurs
3521 * frequently. For example, in a "buildworld"
3522 * workload, almost 1 out of 4 L3 entries already
3523 * have the desired restrictions.)
3525 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
3526 if (va != va_next) {
3528 pmap_invalidate_range(pmap,
3535 while (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) |
3540 * When a dirty read/write mapping is write protected,
3541 * update the page's dirty field.
3543 if ((l3 & ATTR_SW_MANAGED) != 0 &&
3544 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3545 pmap_pte_dirty(pmap, l3))
3546 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK));
3551 if (va != va_next && invalidate)
3552 pmap_invalidate_range(pmap, va, sva, true);
3558 * Set the physical protection on the
3559 * specified range of this map as requested.
3562 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3564 pt_entry_t mask, nbits;
3566 PMAP_ASSERT_STAGE1(pmap);
3567 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3568 if (prot == VM_PROT_NONE) {
3569 pmap_remove(pmap, sva, eva);
3574 if ((prot & VM_PROT_WRITE) == 0) {
3575 mask |= ATTR_S1_AP_RW_BIT | ATTR_SW_DBM;
3576 nbits |= ATTR_S1_AP(ATTR_S1_AP_RO);
3578 if ((prot & VM_PROT_EXECUTE) == 0) {
3580 nbits |= ATTR_S1_XN;
3585 pmap_mask_set(pmap, sva, eva, mask, nbits, true);
3589 pmap_disable_promotion(vm_offset_t sva, vm_size_t size)
3592 MPASS((sva & L3_OFFSET) == 0);
3593 MPASS(((sva + size) & L3_OFFSET) == 0);
3595 pmap_mask_set(kernel_pmap, sva, sva + size, ATTR_SW_NO_PROMOTE,
3596 ATTR_SW_NO_PROMOTE, false);
3600 * Inserts the specified page table page into the specified pmap's collection
3601 * of idle page table pages. Each of a pmap's page table pages is responsible
3602 * for mapping a distinct range of virtual addresses. The pmap's collection is
3603 * ordered by this virtual address range.
3605 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3608 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3611 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3612 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3613 return (vm_radix_insert(&pmap->pm_root, mpte));
3617 * Removes the page table page mapping the specified virtual address from the
3618 * specified pmap's collection of idle page table pages, and returns it.
3619 * Otherwise, returns NULL if there is no page table page corresponding to the
3620 * specified virtual address.
3622 static __inline vm_page_t
3623 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3626 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3627 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
3631 * Performs a break-before-make update of a pmap entry. This is needed when
3632 * either promoting or demoting pages to ensure the TLB doesn't get into an
3633 * inconsistent state.
3636 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
3637 vm_offset_t va, vm_size_t size)
3641 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3643 if ((newpte & ATTR_SW_NO_PROMOTE) != 0)
3644 panic("%s: Updating non-promote pte", __func__);
3647 * Ensure we don't get switched out with the page table in an
3648 * inconsistent state. We also need to ensure no interrupts fire
3649 * as they may make use of an address we are about to invalidate.
3651 intr = intr_disable();
3654 * Clear the old mapping's valid bit, but leave the rest of the entry
3655 * unchanged, so that a lockless, concurrent pmap_kextract() can still
3656 * lookup the physical address.
3658 pmap_clear_bits(pte, ATTR_DESCR_VALID);
3661 * When promoting, the L{1,2}_TABLE entry that is being replaced might
3662 * be cached, so we invalidate intermediate entries as well as final
3665 pmap_invalidate_range(pmap, va, va + size, false);
3667 /* Create the new mapping */
3668 pmap_store(pte, newpte);
3674 #if VM_NRESERVLEVEL > 0
3676 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3677 * replace the many pv entries for the 4KB page mappings by a single pv entry
3678 * for the 2MB page mapping.
3681 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3682 struct rwlock **lockp)
3684 struct md_page *pvh;
3686 vm_offset_t va_last;
3689 KASSERT((pa & L2_OFFSET) == 0,
3690 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
3691 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3694 * Transfer the first page's pv entry for this mapping to the 2mpage's
3695 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3696 * a transfer avoids the possibility that get_pv_entry() calls
3697 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3698 * mappings that is being promoted.
3700 m = PHYS_TO_VM_PAGE(pa);
3701 va = va & ~L2_OFFSET;
3702 pv = pmap_pvh_remove(&m->md, pmap, va);
3703 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
3704 pvh = page_to_pvh(m);
3705 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3707 /* Free the remaining NPTEPG - 1 pv entries. */
3708 va_last = va + L2_SIZE - PAGE_SIZE;
3712 pmap_pvh_free(&m->md, pmap, va);
3713 } while (va < va_last);
3717 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3718 * single level 2 table entry to a single 2MB page mapping. For promotion
3719 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3720 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3721 * identical characteristics.
3724 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
3725 struct rwlock **lockp)
3727 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
3731 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3732 PMAP_ASSERT_STAGE1(pmap);
3734 sva = va & ~L2_OFFSET;
3735 firstl3 = pmap_l2_to_l3(l2, sva);
3736 newl2 = pmap_load(firstl3);
3738 if (((newl2 & (~ATTR_MASK | ATTR_AF)) & L2_OFFSET) != ATTR_AF ||
3739 (newl2 & ATTR_SW_NO_PROMOTE) != 0) {
3740 atomic_add_long(&pmap_l2_p_failures, 1);
3741 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3742 " in pmap %p", va, pmap);
3747 if ((newl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3748 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3750 * When the mapping is clean, i.e., ATTR_S1_AP_RO is set,
3751 * ATTR_SW_DBM can be cleared without a TLB invalidation.
3753 if (!atomic_fcmpset_64(firstl3, &newl2, newl2 & ~ATTR_SW_DBM))
3755 newl2 &= ~ATTR_SW_DBM;
3758 pa = newl2 + L2_SIZE - PAGE_SIZE;
3759 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
3760 oldl3 = pmap_load(l3);
3762 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3763 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3765 * When the mapping is clean, i.e., ATTR_S1_AP_RO is
3766 * set, ATTR_SW_DBM can be cleared without a TLB
3769 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
3772 oldl3 &= ~ATTR_SW_DBM;
3775 atomic_add_long(&pmap_l2_p_failures, 1);
3776 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3777 " in pmap %p", va, pmap);
3784 * Save the page table page in its current state until the L2
3785 * mapping the superpage is demoted by pmap_demote_l2() or
3786 * destroyed by pmap_remove_l3().
3788 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3789 KASSERT(mpte >= vm_page_array &&
3790 mpte < &vm_page_array[vm_page_array_size],
3791 ("pmap_promote_l2: page table page is out of range"));
3792 KASSERT(mpte->pindex == pmap_l2_pindex(va),
3793 ("pmap_promote_l2: page table page's pindex is wrong"));
3794 if (pmap_insert_pt_page(pmap, mpte, true)) {
3795 atomic_add_long(&pmap_l2_p_failures, 1);
3797 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
3802 if ((newl2 & ATTR_SW_MANAGED) != 0)
3803 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
3805 newl2 &= ~ATTR_DESCR_MASK;
3808 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
3810 atomic_add_long(&pmap_l2_promotions, 1);
3811 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
3814 #endif /* VM_NRESERVLEVEL > 0 */
3817 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags,
3820 pd_entry_t *l0p, *l1p, *l2p, origpte;
3823 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3824 KASSERT(psind > 0 && psind < MAXPAGESIZES,
3825 ("psind %d unexpected", psind));
3826 KASSERT(((newpte & ~ATTR_MASK) & (pagesizes[psind] - 1)) == 0,
3827 ("unaligned phys address %#lx newpte %#lx psind %d",
3828 (newpte & ~ATTR_MASK), newpte, psind));
3832 l0p = pmap_l0(pmap, va);
3833 if ((pmap_load(l0p) & ATTR_DESCR_VALID) == 0) {
3834 mp = _pmap_alloc_l3(pmap, pmap_l0_pindex(va), NULL);
3836 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
3837 return (KERN_RESOURCE_SHORTAGE);
3843 l1p = pmap_l0_to_l1(l0p, va);
3844 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va));
3845 origpte = pmap_load(l1p);
3847 l1p = pmap_l0_to_l1(l0p, va);
3848 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va));
3849 origpte = pmap_load(l1p);
3850 if ((origpte & ATTR_DESCR_VALID) == 0) {
3851 mp = PHYS_TO_VM_PAGE(pmap_load(l0p) &
3856 KASSERT((origpte & ATTR_DESCR_VALID) == 0 ||
3857 ((origpte & ATTR_DESCR_MASK) == L1_BLOCK &&
3858 (origpte & ~ATTR_MASK) == (newpte & ~ATTR_MASK)),
3859 ("va %#lx changing 1G phys page l1 %#lx newpte %#lx",
3860 va, origpte, newpte));
3861 pmap_store(l1p, newpte);
3862 } else /* (psind == 1) */ {
3863 l2p = pmap_l2(pmap, va);
3865 mp = _pmap_alloc_l3(pmap, pmap_l1_pindex(va), NULL);
3867 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
3868 return (KERN_RESOURCE_SHORTAGE);
3874 l2p = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
3875 l2p = &l2p[pmap_l2_index(va)];
3876 origpte = pmap_load(l2p);
3878 l1p = pmap_l1(pmap, va);
3879 origpte = pmap_load(l2p);
3880 if ((origpte & ATTR_DESCR_VALID) == 0) {
3881 mp = PHYS_TO_VM_PAGE(pmap_load(l1p) &
3886 KASSERT((origpte & ATTR_DESCR_VALID) == 0 ||
3887 ((origpte & ATTR_DESCR_MASK) == L2_BLOCK &&
3888 (origpte & ~ATTR_MASK) == (newpte & ~ATTR_MASK)),
3889 ("va %#lx changing 2M phys page l2 %#lx newpte %#lx",
3890 va, origpte, newpte));
3891 pmap_store(l2p, newpte);
3895 if ((origpte & ATTR_DESCR_VALID) == 0)
3896 pmap_resident_count_inc(pmap, pagesizes[psind] / PAGE_SIZE);
3897 if ((newpte & ATTR_SW_WIRED) != 0 && (origpte & ATTR_SW_WIRED) == 0)
3898 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE;
3899 else if ((newpte & ATTR_SW_WIRED) == 0 &&
3900 (origpte & ATTR_SW_WIRED) != 0)
3901 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE;
3903 return (KERN_SUCCESS);
3907 * Add a single SMMU entry. This function does not sleep.
3910 pmap_senter(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3911 vm_prot_t prot, u_int flags)
3914 pt_entry_t new_l3, orig_l3;
3920 PMAP_ASSERT_STAGE1(pmap);
3921 KASSERT(va < VM_MAXUSER_ADDRESS, ("wrong address space"));
3923 va = trunc_page(va);
3924 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT |
3925 ATTR_S1_IDX(VM_MEMATTR_DEVICE) | L3_PAGE);
3926 if ((prot & VM_PROT_WRITE) == 0)
3927 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
3928 new_l3 |= ATTR_S1_XN; /* Execute never. */
3929 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER);
3930 new_l3 |= ATTR_S1_nG; /* Non global. */
3932 CTR2(KTR_PMAP, "pmap_senter: %.16lx -> %.16lx", va, pa);
3937 * In the case that a page table page is not
3938 * resident, we are creating it here.
3941 pde = pmap_pde(pmap, va, &lvl);
3942 if (pde != NULL && lvl == 2) {
3943 l3 = pmap_l2_to_l3(pde, va);
3945 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va), NULL);
3947 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3948 rv = KERN_RESOURCE_SHORTAGE;
3954 orig_l3 = pmap_load(l3);
3955 KASSERT(!pmap_l3_valid(orig_l3), ("l3 is valid"));
3958 pmap_store(l3, new_l3);
3959 pmap_resident_count_inc(pmap, 1);
3970 * Remove a single SMMU entry.
3973 pmap_sremove(pmap_t pmap, vm_offset_t va)
3981 pte = pmap_pte(pmap, va, &lvl);
3983 ("Invalid SMMU pagetable level: %d != 3", lvl));
3986 pmap_resident_count_dec(pmap, 1);
3998 * Remove all the allocated L1, L2 pages from SMMU pmap.
3999 * All the L3 entires must be cleared in advance, otherwise
4000 * this function panics.
4003 pmap_sremove_pages(pmap_t pmap)
4005 pd_entry_t l0e, *l1, l1e, *l2, l2e;
4006 pt_entry_t *l3, l3e;
4007 vm_page_t m, m0, m1;
4016 for (sva = VM_MINUSER_ADDRESS, i = pmap_l0_index(sva);
4017 (i < Ln_ENTRIES && sva < VM_MAXUSER_ADDRESS); i++) {
4018 l0e = pmap->pm_l0[i];
4019 if ((l0e & ATTR_DESCR_VALID) == 0) {
4023 pa0 = l0e & ~ATTR_MASK;
4024 m0 = PHYS_TO_VM_PAGE(pa0);
4025 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa0);
4027 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
4029 if ((l1e & ATTR_DESCR_VALID) == 0) {
4033 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
4037 pa1 = l1e & ~ATTR_MASK;
4038 m1 = PHYS_TO_VM_PAGE(pa1);
4039 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa1);
4041 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
4043 if ((l2e & ATTR_DESCR_VALID) == 0) {
4047 pa = l2e & ~ATTR_MASK;
4048 m = PHYS_TO_VM_PAGE(pa);
4049 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
4051 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
4052 l++, sva += L3_SIZE) {
4054 if ((l3e & ATTR_DESCR_VALID) == 0)
4056 panic("%s: l3e found for va %jx\n",
4060 vm_page_unwire_noq(m1);
4061 vm_page_unwire_noq(m);
4062 pmap_resident_count_dec(pmap, 1);
4067 vm_page_unwire_noq(m0);
4068 pmap_resident_count_dec(pmap, 1);
4073 pmap_resident_count_dec(pmap, 1);
4075 pmap_clear(&pmap->pm_l0[i]);
4078 KASSERT(pmap->pm_stats.resident_count == 0,
4079 ("Invalid resident count %jd", pmap->pm_stats.resident_count));
4085 * Insert the given physical page (p) at
4086 * the specified virtual address (v) in the
4087 * target physical map with the protection requested.
4089 * If specified, the page will be wired down, meaning
4090 * that the related pte can not be reclaimed.
4092 * NB: This is the only routine which MAY NOT lazy-evaluate
4093 * or lose information. That is, this routine must actually
4094 * insert this page into the given map NOW.
4097 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4098 u_int flags, int8_t psind)
4100 struct rwlock *lock;
4102 pt_entry_t new_l3, orig_l3;
4103 pt_entry_t *l2, *l3;
4110 KASSERT(ADDR_IS_CANONICAL(va),
4111 ("%s: Address not in canonical form: %lx", __func__, va));
4113 va = trunc_page(va);
4114 if ((m->oflags & VPO_UNMANAGED) == 0)
4115 VM_PAGE_OBJECT_BUSY_ASSERT(m);
4116 pa = VM_PAGE_TO_PHYS(m);
4117 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | L3_PAGE);
4118 new_l3 |= pmap_pte_memattr(pmap, m->md.pv_memattr);
4119 new_l3 |= pmap_pte_prot(pmap, prot);
4121 if ((flags & PMAP_ENTER_WIRED) != 0)
4122 new_l3 |= ATTR_SW_WIRED;
4123 if (pmap->pm_stage == PM_STAGE1) {
4124 if (!ADDR_IS_KERNEL(va))
4125 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4127 new_l3 |= ATTR_S1_UXN;
4128 if (pmap != kernel_pmap)
4129 new_l3 |= ATTR_S1_nG;
4132 * Clear the access flag on executable mappings, this will be
4133 * set later when the page is accessed. The fault handler is
4134 * required to invalidate the I-cache.
4136 * TODO: Switch to the valid flag to allow hardware management
4137 * of the access flag. Much of the pmap code assumes the
4138 * valid flag is set and fails to destroy the old page tables
4139 * correctly if it is clear.
4141 if (prot & VM_PROT_EXECUTE)
4144 if ((m->oflags & VPO_UNMANAGED) == 0) {
4145 new_l3 |= ATTR_SW_MANAGED;
4146 if ((prot & VM_PROT_WRITE) != 0) {
4147 new_l3 |= ATTR_SW_DBM;
4148 if ((flags & VM_PROT_WRITE) == 0) {
4149 if (pmap->pm_stage == PM_STAGE1)
4150 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
4153 ~ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
4158 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
4162 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) {
4163 KASSERT((m->oflags & VPO_UNMANAGED) != 0,
4164 ("managed largepage va %#lx flags %#x", va, flags));
4168 else /* (psind == 1) */
4170 rv = pmap_enter_largepage(pmap, va, new_l3, flags, psind);
4174 /* Assert the required virtual and physical alignment. */
4175 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
4176 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
4177 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
4184 * In the case that a page table page is not
4185 * resident, we are creating it here.
4188 pde = pmap_pde(pmap, va, &lvl);
4189 if (pde != NULL && lvl == 2) {
4190 l3 = pmap_l2_to_l3(pde, va);
4191 if (!ADDR_IS_KERNEL(va) && mpte == NULL) {
4192 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
4196 } else if (pde != NULL && lvl == 1) {
4197 l2 = pmap_l1_to_l2(pde, va);
4198 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
4199 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
4200 l3 = &l3[pmap_l3_index(va)];
4201 if (!ADDR_IS_KERNEL(va)) {
4202 mpte = PHYS_TO_VM_PAGE(
4203 pmap_load(l2) & ~ATTR_MASK);
4208 /* We need to allocate an L3 table. */
4210 if (!ADDR_IS_KERNEL(va)) {
4211 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
4214 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
4215 * to handle the possibility that a superpage mapping for "va"
4216 * was created while we slept.
4218 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
4219 nosleep ? NULL : &lock);
4220 if (mpte == NULL && nosleep) {
4221 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
4222 rv = KERN_RESOURCE_SHORTAGE;
4227 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
4230 orig_l3 = pmap_load(l3);
4231 opa = orig_l3 & ~ATTR_MASK;
4235 * Is the specified virtual address already mapped?
4237 if (pmap_l3_valid(orig_l3)) {
4239 * Only allow adding new entries on stage 2 tables for now.
4240 * This simplifies cache invalidation as we may need to call
4241 * into EL2 to perform such actions.
4243 PMAP_ASSERT_STAGE1(pmap);
4245 * Wiring change, just update stats. We don't worry about
4246 * wiring PT pages as they remain resident as long as there
4247 * are valid mappings in them. Hence, if a user page is wired,
4248 * the PT page will be also.
4250 if ((flags & PMAP_ENTER_WIRED) != 0 &&
4251 (orig_l3 & ATTR_SW_WIRED) == 0)
4252 pmap->pm_stats.wired_count++;
4253 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
4254 (orig_l3 & ATTR_SW_WIRED) != 0)
4255 pmap->pm_stats.wired_count--;
4258 * Remove the extra PT page reference.
4262 KASSERT(mpte->ref_count > 0,
4263 ("pmap_enter: missing reference to page table page,"
4268 * Has the physical page changed?
4272 * No, might be a protection or wiring change.
4274 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
4275 (new_l3 & ATTR_SW_DBM) != 0)
4276 vm_page_aflag_set(m, PGA_WRITEABLE);
4281 * The physical page has changed. Temporarily invalidate
4284 orig_l3 = pmap_load_clear(l3);
4285 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
4286 ("pmap_enter: unexpected pa update for %#lx", va));
4287 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
4288 om = PHYS_TO_VM_PAGE(opa);
4291 * The pmap lock is sufficient to synchronize with
4292 * concurrent calls to pmap_page_test_mappings() and
4293 * pmap_ts_referenced().
4295 if (pmap_pte_dirty(pmap, orig_l3))
4297 if ((orig_l3 & ATTR_AF) != 0) {
4298 pmap_invalidate_page(pmap, va, true);
4299 vm_page_aflag_set(om, PGA_REFERENCED);
4301 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4302 pv = pmap_pvh_remove(&om->md, pmap, va);
4303 if ((m->oflags & VPO_UNMANAGED) != 0)
4304 free_pv_entry(pmap, pv);
4305 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
4306 TAILQ_EMPTY(&om->md.pv_list) &&
4307 ((om->flags & PG_FICTITIOUS) != 0 ||
4308 TAILQ_EMPTY(&page_to_pvh(om)->pv_list)))
4309 vm_page_aflag_clear(om, PGA_WRITEABLE);
4311 KASSERT((orig_l3 & ATTR_AF) != 0,
4312 ("pmap_enter: unmanaged mapping lacks ATTR_AF"));
4313 pmap_invalidate_page(pmap, va, true);
4318 * Increment the counters.
4320 if ((new_l3 & ATTR_SW_WIRED) != 0)
4321 pmap->pm_stats.wired_count++;
4322 pmap_resident_count_inc(pmap, 1);
4325 * Enter on the PV list if part of our managed memory.
4327 if ((m->oflags & VPO_UNMANAGED) == 0) {
4329 pv = get_pv_entry(pmap, &lock);
4332 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4333 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4335 if ((new_l3 & ATTR_SW_DBM) != 0)
4336 vm_page_aflag_set(m, PGA_WRITEABLE);
4340 if (pmap->pm_stage == PM_STAGE1) {
4342 * Sync icache if exec permission and attribute
4343 * VM_MEMATTR_WRITE_BACK is set. Do it now, before the mapping
4344 * is stored and made valid for hardware table walk. If done
4345 * later, then other can access this page before caches are
4346 * properly synced. Don't do it for kernel memory which is
4347 * mapped with exec permission even if the memory isn't going
4348 * to hold executable code. The only time when icache sync is
4349 * needed is after kernel module is loaded and the relocation
4350 * info is processed. And it's done in elf_cpu_load_file().
4352 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4353 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
4354 (opa != pa || (orig_l3 & ATTR_S1_XN))) {
4355 PMAP_ASSERT_STAGE1(pmap);
4356 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4359 cpu_dcache_wb_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4363 * Update the L3 entry
4365 if (pmap_l3_valid(orig_l3)) {
4366 PMAP_ASSERT_STAGE1(pmap);
4367 KASSERT(opa == pa, ("pmap_enter: invalid update"));
4368 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
4369 /* same PA, different attributes */
4370 orig_l3 = pmap_load_store(l3, new_l3);
4371 pmap_invalidate_page(pmap, va, true);
4372 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
4373 pmap_pte_dirty(pmap, orig_l3))
4378 * This can happens if multiple threads simultaneously
4379 * access not yet mapped page. This bad for performance
4380 * since this can cause full demotion-NOP-promotion
4382 * Another possible reasons are:
4383 * - VM and pmap memory layout are diverged
4384 * - tlb flush is missing somewhere and CPU doesn't see
4387 CTR4(KTR_PMAP, "%s: already mapped page - "
4388 "pmap %p va 0x%#lx pte 0x%lx",
4389 __func__, pmap, va, new_l3);
4393 pmap_store(l3, new_l3);
4397 #if VM_NRESERVLEVEL > 0
4399 * Try to promote from level 3 pages to a level 2 superpage. This
4400 * currently only works on stage 1 pmaps as pmap_promote_l2 looks at
4401 * stage 1 specific fields and performs a break-before-make sequence
4402 * that is incorrect a stage 2 pmap.
4404 if ((mpte == NULL || mpte->ref_count == NL3PG) &&
4405 pmap_ps_enabled(pmap) && pmap->pm_stage == PM_STAGE1 &&
4406 (m->flags & PG_FICTITIOUS) == 0 &&
4407 vm_reserv_level_iffullpop(m) == 0) {
4408 pmap_promote_l2(pmap, pde, va, &lock);
4421 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
4422 * if successful. Returns false if (1) a page table page cannot be allocated
4423 * without sleeping, (2) a mapping already exists at the specified virtual
4424 * address, or (3) a PV entry cannot be allocated without reclaiming another
4428 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4429 struct rwlock **lockp)
4433 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4434 PMAP_ASSERT_STAGE1(pmap);
4435 KASSERT(ADDR_IS_CANONICAL(va),
4436 ("%s: Address not in canonical form: %lx", __func__, va));
4438 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
4439 ATTR_S1_IDX(m->md.pv_memattr) | ATTR_S1_AP(ATTR_S1_AP_RO) |
4441 if ((m->oflags & VPO_UNMANAGED) == 0) {
4442 new_l2 |= ATTR_SW_MANAGED;
4445 if ((prot & VM_PROT_EXECUTE) == 0 ||
4446 m->md.pv_memattr == VM_MEMATTR_DEVICE)
4447 new_l2 |= ATTR_S1_XN;
4448 if (!ADDR_IS_KERNEL(va))
4449 new_l2 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4451 new_l2 |= ATTR_S1_UXN;
4452 if (pmap != kernel_pmap)
4453 new_l2 |= ATTR_S1_nG;
4454 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
4455 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, m, lockp) ==
4460 * Returns true if every page table entry in the specified page table is
4464 pmap_every_pte_zero(vm_paddr_t pa)
4466 pt_entry_t *pt_end, *pte;
4468 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
4469 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
4470 for (pt_end = pte + Ln_ENTRIES; pte < pt_end; pte++) {
4478 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
4479 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
4480 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
4481 * a mapping already exists at the specified virtual address. Returns
4482 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
4483 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
4484 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
4487 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
4488 vm_page_t m, struct rwlock **lockp)
4490 struct spglist free;
4491 pd_entry_t *l2, old_l2;
4494 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4495 KASSERT(ADDR_IS_CANONICAL(va),
4496 ("%s: Address not in canonical form: %lx", __func__, va));
4498 if ((l2 = pmap_alloc_l2(pmap, va, &l2pg, (flags &
4499 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
4500 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
4502 return (KERN_RESOURCE_SHORTAGE);
4506 * If there are existing mappings, either abort or remove them.
4508 if ((old_l2 = pmap_load(l2)) != 0) {
4509 KASSERT(l2pg == NULL || l2pg->ref_count > 1,
4510 ("pmap_enter_l2: l2pg's ref count is too low"));
4511 if ((flags & PMAP_ENTER_NOREPLACE) != 0 &&
4512 (!ADDR_IS_KERNEL(va) ||
4513 (old_l2 & ATTR_DESCR_MASK) == L2_BLOCK ||
4514 !pmap_every_pte_zero(old_l2 & ~ATTR_MASK))) {
4517 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx"
4518 " in pmap %p", va, pmap);
4519 return (KERN_FAILURE);
4522 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
4523 (void)pmap_remove_l2(pmap, l2, va,
4524 pmap_load(pmap_l1(pmap, va)), &free, lockp);
4526 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
4528 if (!ADDR_IS_KERNEL(va)) {
4529 vm_page_free_pages_toq(&free, true);
4530 KASSERT(pmap_load(l2) == 0,
4531 ("pmap_enter_l2: non-zero L2 entry %p", l2));
4533 KASSERT(SLIST_EMPTY(&free),
4534 ("pmap_enter_l2: freed kernel page table page"));
4537 * Both pmap_remove_l2() and pmap_remove_l3_range()
4538 * will leave the kernel page table page zero filled.
4539 * Nonetheless, the TLB could have an intermediate
4540 * entry for the kernel page table page, so request
4541 * an invalidation at all levels after clearing
4542 * the L2_TABLE entry.
4544 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
4545 if (pmap_insert_pt_page(pmap, mt, false))
4546 panic("pmap_enter_l2: trie insert failed");
4548 pmap_invalidate_page(pmap, va, false);
4552 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
4554 * Abort this mapping if its PV entry could not be created.
4556 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
4558 pmap_abort_ptp(pmap, va, l2pg);
4560 "pmap_enter_l2: failure for va %#lx in pmap %p",
4562 return (KERN_RESOURCE_SHORTAGE);
4564 if ((new_l2 & ATTR_SW_DBM) != 0)
4565 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4566 vm_page_aflag_set(mt, PGA_WRITEABLE);
4570 * Increment counters.
4572 if ((new_l2 & ATTR_SW_WIRED) != 0)
4573 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
4574 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
4577 * Conditionally sync the icache. See pmap_enter() for details.
4579 if ((new_l2 & ATTR_S1_XN) == 0 && ((new_l2 & ~ATTR_MASK) !=
4580 (old_l2 & ~ATTR_MASK) || (old_l2 & ATTR_S1_XN) != 0) &&
4581 pmap != kernel_pmap && m->md.pv_memattr == VM_MEMATTR_WRITE_BACK) {
4582 cpu_icache_sync_range(PHYS_TO_DMAP(new_l2 & ~ATTR_MASK),
4587 * Map the superpage.
4589 pmap_store(l2, new_l2);
4592 atomic_add_long(&pmap_l2_mappings, 1);
4593 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
4596 return (KERN_SUCCESS);
4600 * Maps a sequence of resident pages belonging to the same object.
4601 * The sequence begins with the given page m_start. This page is
4602 * mapped at the given virtual address start. Each subsequent page is
4603 * mapped at a virtual address that is offset from start by the same
4604 * amount as the page is offset from m_start within the object. The
4605 * last page in the sequence is the page with the largest offset from
4606 * m_start that can be mapped at a virtual address less than the given
4607 * virtual address end. Not every virtual page between start and end
4608 * is mapped; only those for which a resident page exists with the
4609 * corresponding offset from m_start are mapped.
4612 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4613 vm_page_t m_start, vm_prot_t prot)
4615 struct rwlock *lock;
4618 vm_pindex_t diff, psize;
4620 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4622 psize = atop(end - start);
4627 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4628 va = start + ptoa(diff);
4629 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
4630 m->psind == 1 && pmap_ps_enabled(pmap) &&
4631 pmap_enter_2mpage(pmap, va, m, prot, &lock))
4632 m = &m[L2_SIZE / PAGE_SIZE - 1];
4634 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
4636 m = TAILQ_NEXT(m, listq);
4644 * this code makes some *MAJOR* assumptions:
4645 * 1. Current pmap & pmap exists.
4648 * 4. No page table pages.
4649 * but is *MUCH* faster than pmap_enter...
4653 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4655 struct rwlock *lock;
4659 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
4666 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4667 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
4670 pt_entry_t *l1, *l2, *l3, l3_val;
4674 KASSERT(!VA_IS_CLEANMAP(va) ||
4675 (m->oflags & VPO_UNMANAGED) != 0,
4676 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4677 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4678 PMAP_ASSERT_STAGE1(pmap);
4679 KASSERT(ADDR_IS_CANONICAL(va),
4680 ("%s: Address not in canonical form: %lx", __func__, va));
4682 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
4684 * In the case that a page table page is not
4685 * resident, we are creating it here.
4687 if (!ADDR_IS_KERNEL(va)) {
4688 vm_pindex_t l2pindex;
4691 * Calculate pagetable page index
4693 l2pindex = pmap_l2_pindex(va);
4694 if (mpte && (mpte->pindex == l2pindex)) {
4698 * If the page table page is mapped, we just increment
4699 * the hold count, and activate it. Otherwise, we
4700 * attempt to allocate a page table page, passing NULL
4701 * instead of the PV list lock pointer because we don't
4702 * intend to sleep. If this attempt fails, we don't
4703 * retry. Instead, we give up.
4705 l1 = pmap_l1(pmap, va);
4706 if (l1 != NULL && pmap_load(l1) != 0) {
4707 if ((pmap_load(l1) & ATTR_DESCR_MASK) ==
4710 l2 = pmap_l1_to_l2(l1, va);
4711 if (pmap_load(l2) != 0) {
4712 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
4715 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) &
4719 mpte = _pmap_alloc_l3(pmap, l2pindex,
4725 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
4730 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4731 l3 = &l3[pmap_l3_index(va)];
4734 pde = pmap_pde(kernel_pmap, va, &lvl);
4735 KASSERT(pde != NULL,
4736 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
4739 ("pmap_enter_quick_locked: Invalid level %d", lvl));
4740 l3 = pmap_l2_to_l3(pde, va);
4744 * Abort if a mapping already exists.
4746 if (pmap_load(l3) != 0) {
4753 * Enter on the PV list if part of our managed memory.
4755 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4756 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4758 pmap_abort_ptp(pmap, va, mpte);
4763 * Increment counters
4765 pmap_resident_count_inc(pmap, 1);
4767 pa = VM_PAGE_TO_PHYS(m);
4768 l3_val = pa | ATTR_DEFAULT | ATTR_S1_IDX(m->md.pv_memattr) |
4769 ATTR_S1_AP(ATTR_S1_AP_RO) | L3_PAGE;
4770 if ((prot & VM_PROT_EXECUTE) == 0 ||
4771 m->md.pv_memattr == VM_MEMATTR_DEVICE)
4772 l3_val |= ATTR_S1_XN;
4773 if (!ADDR_IS_KERNEL(va))
4774 l3_val |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4776 l3_val |= ATTR_S1_UXN;
4777 if (pmap != kernel_pmap)
4778 l3_val |= ATTR_S1_nG;
4781 * Now validate mapping with RO protection
4783 if ((m->oflags & VPO_UNMANAGED) == 0) {
4784 l3_val |= ATTR_SW_MANAGED;
4788 /* Sync icache before the mapping is stored to PTE */
4789 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4790 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
4791 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4793 pmap_store(l3, l3_val);
4800 * This code maps large physical mmap regions into the
4801 * processor address space. Note that some shortcuts
4802 * are taken, but the code works.
4805 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4806 vm_pindex_t pindex, vm_size_t size)
4809 VM_OBJECT_ASSERT_WLOCKED(object);
4810 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4811 ("pmap_object_init_pt: non-device object"));
4815 * Clear the wired attribute from the mappings for the specified range of
4816 * addresses in the given pmap. Every valid mapping within that range
4817 * must have the wired attribute set. In contrast, invalid mappings
4818 * cannot have the wired attribute set, so they are ignored.
4820 * The wired attribute of the page table entry is not a hardware feature,
4821 * so there is no need to invalidate any TLB entries.
4824 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4826 vm_offset_t va_next;
4827 pd_entry_t *l0, *l1, *l2;
4831 for (; sva < eva; sva = va_next) {
4832 l0 = pmap_l0(pmap, sva);
4833 if (pmap_load(l0) == 0) {
4834 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
4840 l1 = pmap_l0_to_l1(l0, sva);
4841 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
4844 if (pmap_load(l1) == 0)
4847 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
4848 KASSERT(va_next <= eva,
4849 ("partial update of non-transparent 1G page "
4850 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
4851 pmap_load(l1), sva, eva, va_next));
4852 MPASS(pmap != kernel_pmap);
4853 MPASS((pmap_load(l1) & (ATTR_SW_MANAGED |
4854 ATTR_SW_WIRED)) == ATTR_SW_WIRED);
4855 pmap_clear_bits(l1, ATTR_SW_WIRED);
4856 pmap->pm_stats.wired_count -= L1_SIZE / PAGE_SIZE;
4860 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
4864 l2 = pmap_l1_to_l2(l1, sva);
4865 if (pmap_load(l2) == 0)
4868 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
4869 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
4870 panic("pmap_unwire: l2 %#jx is missing "
4871 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
4874 * Are we unwiring the entire large page? If not,
4875 * demote the mapping and fall through.
4877 if (sva + L2_SIZE == va_next && eva >= va_next) {
4878 pmap_clear_bits(l2, ATTR_SW_WIRED);
4879 pmap->pm_stats.wired_count -= L2_SIZE /
4882 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
4883 panic("pmap_unwire: demotion failed");
4885 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
4886 ("pmap_unwire: Invalid l2 entry after demotion"));
4890 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
4892 if (pmap_load(l3) == 0)
4894 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
4895 panic("pmap_unwire: l3 %#jx is missing "
4896 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
4899 * ATTR_SW_WIRED must be cleared atomically. Although
4900 * the pmap lock synchronizes access to ATTR_SW_WIRED,
4901 * the System MMU may write to the entry concurrently.
4903 pmap_clear_bits(l3, ATTR_SW_WIRED);
4904 pmap->pm_stats.wired_count--;
4911 * Copy the range specified by src_addr/len
4912 * from the source map to the range dst_addr/len
4913 * in the destination map.
4915 * This routine is only advisory and need not do anything.
4917 * Because the executable mappings created by this routine are copied,
4918 * it should not have to flush the instruction cache.
4921 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4922 vm_offset_t src_addr)
4924 struct rwlock *lock;
4925 pd_entry_t *l0, *l1, *l2, srcptepaddr;
4926 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
4927 vm_offset_t addr, end_addr, va_next;
4928 vm_page_t dst_m, dstmpte, srcmpte;
4930 PMAP_ASSERT_STAGE1(dst_pmap);
4931 PMAP_ASSERT_STAGE1(src_pmap);
4933 if (dst_addr != src_addr)
4935 end_addr = src_addr + len;
4937 if (dst_pmap < src_pmap) {
4938 PMAP_LOCK(dst_pmap);
4939 PMAP_LOCK(src_pmap);
4941 PMAP_LOCK(src_pmap);
4942 PMAP_LOCK(dst_pmap);
4944 for (addr = src_addr; addr < end_addr; addr = va_next) {
4945 l0 = pmap_l0(src_pmap, addr);
4946 if (pmap_load(l0) == 0) {
4947 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
4953 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
4956 l1 = pmap_l0_to_l1(l0, addr);
4957 if (pmap_load(l1) == 0)
4959 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
4960 KASSERT(va_next <= end_addr,
4961 ("partial update of non-transparent 1G page "
4962 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx",
4963 pmap_load(l1), addr, end_addr, va_next));
4964 srcptepaddr = pmap_load(l1);
4965 l1 = pmap_l1(dst_pmap, addr);
4967 if (_pmap_alloc_l3(dst_pmap,
4968 pmap_l0_pindex(addr), NULL) == NULL)
4970 l1 = pmap_l1(dst_pmap, addr);
4972 l0 = pmap_l0(dst_pmap, addr);
4973 dst_m = PHYS_TO_VM_PAGE(pmap_load(l0) &
4977 KASSERT(pmap_load(l1) == 0,
4978 ("1G mapping present in dst pmap "
4979 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx",
4980 pmap_load(l1), addr, end_addr, va_next));
4981 pmap_store(l1, srcptepaddr & ~ATTR_SW_WIRED);
4982 pmap_resident_count_inc(dst_pmap, L1_SIZE / PAGE_SIZE);
4986 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
4989 l2 = pmap_l1_to_l2(l1, addr);
4990 srcptepaddr = pmap_load(l2);
4991 if (srcptepaddr == 0)
4993 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
4995 * We can only virtual copy whole superpages.
4997 if ((addr & L2_OFFSET) != 0 ||
4998 addr + L2_SIZE > end_addr)
5000 l2 = pmap_alloc_l2(dst_pmap, addr, &dst_m, NULL);
5003 if (pmap_load(l2) == 0 &&
5004 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
5005 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
5006 PMAP_ENTER_NORECLAIM, &lock))) {
5008 * We leave the dirty bit unchanged because
5009 * managed read/write superpage mappings are
5010 * required to be dirty. However, managed
5011 * superpage mappings are not required to
5012 * have their accessed bit set, so we clear
5013 * it because we don't know if this mapping
5016 srcptepaddr &= ~ATTR_SW_WIRED;
5017 if ((srcptepaddr & ATTR_SW_MANAGED) != 0)
5018 srcptepaddr &= ~ATTR_AF;
5019 pmap_store(l2, srcptepaddr);
5020 pmap_resident_count_inc(dst_pmap, L2_SIZE /
5022 atomic_add_long(&pmap_l2_mappings, 1);
5024 pmap_abort_ptp(dst_pmap, addr, dst_m);
5027 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
5028 ("pmap_copy: invalid L2 entry"));
5029 srcptepaddr &= ~ATTR_MASK;
5030 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
5031 KASSERT(srcmpte->ref_count > 0,
5032 ("pmap_copy: source page table page is unused"));
5033 if (va_next > end_addr)
5035 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
5036 src_pte = &src_pte[pmap_l3_index(addr)];
5038 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
5039 ptetemp = pmap_load(src_pte);
5042 * We only virtual copy managed pages.
5044 if ((ptetemp & ATTR_SW_MANAGED) == 0)
5047 if (dstmpte != NULL) {
5048 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
5049 ("dstmpte pindex/addr mismatch"));
5050 dstmpte->ref_count++;
5051 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
5054 dst_pte = (pt_entry_t *)
5055 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
5056 dst_pte = &dst_pte[pmap_l3_index(addr)];
5057 if (pmap_load(dst_pte) == 0 &&
5058 pmap_try_insert_pv_entry(dst_pmap, addr,
5059 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
5061 * Clear the wired, modified, and accessed
5062 * (referenced) bits during the copy.
5064 mask = ATTR_AF | ATTR_SW_WIRED;
5066 if ((ptetemp & ATTR_SW_DBM) != 0)
5067 nbits |= ATTR_S1_AP_RW_BIT;
5068 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
5069 pmap_resident_count_inc(dst_pmap, 1);
5071 pmap_abort_ptp(dst_pmap, addr, dstmpte);
5074 /* Have we copied all of the valid mappings? */
5075 if (dstmpte->ref_count >= srcmpte->ref_count)
5081 * XXX This barrier may not be needed because the destination pmap is
5088 PMAP_UNLOCK(src_pmap);
5089 PMAP_UNLOCK(dst_pmap);
5093 * pmap_zero_page zeros the specified hardware page by mapping
5094 * the page into KVM and using bzero to clear its contents.
5097 pmap_zero_page(vm_page_t m)
5099 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5101 pagezero((void *)va);
5105 * pmap_zero_page_area zeros the specified hardware page by mapping
5106 * the page into KVM and using bzero to clear its contents.
5108 * off and size may not cover an area beyond a single hardware page.
5111 pmap_zero_page_area(vm_page_t m, int off, int size)
5113 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5115 if (off == 0 && size == PAGE_SIZE)
5116 pagezero((void *)va);
5118 bzero((char *)va + off, size);
5122 * pmap_copy_page copies the specified (machine independent)
5123 * page by mapping the page into virtual memory and using
5124 * bcopy to copy the page, one machine dependent page at a
5128 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
5130 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
5131 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
5133 pagecopy((void *)src, (void *)dst);
5136 int unmapped_buf_allowed = 1;
5139 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5140 vm_offset_t b_offset, int xfersize)
5144 vm_paddr_t p_a, p_b;
5145 vm_offset_t a_pg_offset, b_pg_offset;
5148 while (xfersize > 0) {
5149 a_pg_offset = a_offset & PAGE_MASK;
5150 m_a = ma[a_offset >> PAGE_SHIFT];
5151 p_a = m_a->phys_addr;
5152 b_pg_offset = b_offset & PAGE_MASK;
5153 m_b = mb[b_offset >> PAGE_SHIFT];
5154 p_b = m_b->phys_addr;
5155 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5156 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5157 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
5158 panic("!DMAP a %lx", p_a);
5160 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
5162 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
5163 panic("!DMAP b %lx", p_b);
5165 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
5167 bcopy(a_cp, b_cp, cnt);
5175 pmap_quick_enter_page(vm_page_t m)
5178 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
5182 pmap_quick_remove_page(vm_offset_t addr)
5187 * Returns true if the pmap's pv is one of the first
5188 * 16 pvs linked to from this page. This count may
5189 * be changed upwards or downwards in the future; it
5190 * is only necessary that true be returned for a small
5191 * subset of pmaps for proper page aging.
5194 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5196 struct md_page *pvh;
5197 struct rwlock *lock;
5202 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5203 ("pmap_page_exists_quick: page %p is not managed", m));
5205 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5207 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5208 if (PV_PMAP(pv) == pmap) {
5216 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5217 pvh = page_to_pvh(m);
5218 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5219 if (PV_PMAP(pv) == pmap) {
5233 * pmap_page_wired_mappings:
5235 * Return the number of managed mappings to the given physical page
5239 pmap_page_wired_mappings(vm_page_t m)
5241 struct rwlock *lock;
5242 struct md_page *pvh;
5246 int count, lvl, md_gen, pvh_gen;
5248 if ((m->oflags & VPO_UNMANAGED) != 0)
5250 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5254 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5256 if (!PMAP_TRYLOCK(pmap)) {
5257 md_gen = m->md.pv_gen;
5261 if (md_gen != m->md.pv_gen) {
5266 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5267 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
5271 if ((m->flags & PG_FICTITIOUS) == 0) {
5272 pvh = page_to_pvh(m);
5273 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5275 if (!PMAP_TRYLOCK(pmap)) {
5276 md_gen = m->md.pv_gen;
5277 pvh_gen = pvh->pv_gen;
5281 if (md_gen != m->md.pv_gen ||
5282 pvh_gen != pvh->pv_gen) {
5287 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5289 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
5299 * Returns true if the given page is mapped individually or as part of
5300 * a 2mpage. Otherwise, returns false.
5303 pmap_page_is_mapped(vm_page_t m)
5305 struct rwlock *lock;
5308 if ((m->oflags & VPO_UNMANAGED) != 0)
5310 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5312 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5313 ((m->flags & PG_FICTITIOUS) == 0 &&
5314 !TAILQ_EMPTY(&page_to_pvh(m)->pv_list));
5320 * Destroy all managed, non-wired mappings in the given user-space
5321 * pmap. This pmap cannot be active on any processor besides the
5324 * This function cannot be applied to the kernel pmap. Moreover, it
5325 * is not intended for general use. It is only to be used during
5326 * process termination. Consequently, it can be implemented in ways
5327 * that make it faster than pmap_remove(). First, it can more quickly
5328 * destroy mappings by iterating over the pmap's collection of PV
5329 * entries, rather than searching the page table. Second, it doesn't
5330 * have to test and clear the page table entries atomically, because
5331 * no processor is currently accessing the user address space. In
5332 * particular, a page table entry's dirty bit won't change state once
5333 * this function starts.
5336 pmap_remove_pages(pmap_t pmap)
5339 pt_entry_t *pte, tpte;
5340 struct spglist free;
5341 vm_page_t m, ml3, mt;
5343 struct md_page *pvh;
5344 struct pv_chunk *pc, *npc;
5345 struct rwlock *lock;
5347 uint64_t inuse, bitmask;
5348 int allfree, field, freed, idx, lvl;
5355 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5358 for (field = 0; field < _NPCM; field++) {
5359 inuse = ~pc->pc_map[field] & pc_freemask[field];
5360 while (inuse != 0) {
5361 bit = ffsl(inuse) - 1;
5362 bitmask = 1UL << bit;
5363 idx = field * 64 + bit;
5364 pv = &pc->pc_pventry[idx];
5367 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5368 KASSERT(pde != NULL,
5369 ("Attempting to remove an unmapped page"));
5373 pte = pmap_l1_to_l2(pde, pv->pv_va);
5374 tpte = pmap_load(pte);
5375 KASSERT((tpte & ATTR_DESCR_MASK) ==
5377 ("Attempting to remove an invalid "
5378 "block: %lx", tpte));
5381 pte = pmap_l2_to_l3(pde, pv->pv_va);
5382 tpte = pmap_load(pte);
5383 KASSERT((tpte & ATTR_DESCR_MASK) ==
5385 ("Attempting to remove an invalid "
5386 "page: %lx", tpte));
5390 "Invalid page directory level: %d",
5395 * We cannot remove wired pages from a process' mapping at this time
5397 if (tpte & ATTR_SW_WIRED) {
5403 pc->pc_map[field] |= bitmask;
5406 * Because this pmap is not active on other
5407 * processors, the dirty bit cannot have
5408 * changed state since we last loaded pte.
5412 pa = tpte & ~ATTR_MASK;
5414 m = PHYS_TO_VM_PAGE(pa);
5415 KASSERT(m->phys_addr == pa,
5416 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
5417 m, (uintmax_t)m->phys_addr,
5420 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
5421 m < &vm_page_array[vm_page_array_size],
5422 ("pmap_remove_pages: bad pte %#jx",
5426 * Update the vm_page_t clean/reference bits.
5428 if (pmap_pte_dirty(pmap, tpte)) {
5431 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
5440 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
5444 pmap_resident_count_dec(pmap,
5445 L2_SIZE / PAGE_SIZE);
5446 pvh = page_to_pvh(m);
5447 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
5449 if (TAILQ_EMPTY(&pvh->pv_list)) {
5450 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
5451 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
5452 TAILQ_EMPTY(&mt->md.pv_list))
5453 vm_page_aflag_clear(mt, PGA_WRITEABLE);
5455 ml3 = pmap_remove_pt_page(pmap,
5458 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
5459 ("pmap_remove_pages: l3 page not promoted"));
5460 pmap_resident_count_dec(pmap,1);
5461 KASSERT(ml3->ref_count == NL3PG,
5462 ("pmap_remove_pages: l3 page ref count error"));
5464 pmap_add_delayed_free_list(ml3,
5469 pmap_resident_count_dec(pmap, 1);
5470 TAILQ_REMOVE(&m->md.pv_list, pv,
5473 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
5474 TAILQ_EMPTY(&m->md.pv_list) &&
5475 (m->flags & PG_FICTITIOUS) == 0) {
5476 pvh = page_to_pvh(m);
5477 if (TAILQ_EMPTY(&pvh->pv_list))
5478 vm_page_aflag_clear(m,
5483 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
5488 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
5489 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
5490 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
5492 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5498 pmap_invalidate_all(pmap);
5500 vm_page_free_pages_toq(&free, true);
5504 * This is used to check if a page has been accessed or modified.
5507 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
5509 struct rwlock *lock;
5511 struct md_page *pvh;
5512 pt_entry_t *pte, mask, value;
5514 int lvl, md_gen, pvh_gen;
5518 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5521 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5523 PMAP_ASSERT_STAGE1(pmap);
5524 if (!PMAP_TRYLOCK(pmap)) {
5525 md_gen = m->md.pv_gen;
5529 if (md_gen != m->md.pv_gen) {
5534 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5536 ("pmap_page_test_mappings: Invalid level %d", lvl));
5540 mask |= ATTR_S1_AP_RW_BIT;
5541 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
5544 mask |= ATTR_AF | ATTR_DESCR_MASK;
5545 value |= ATTR_AF | L3_PAGE;
5547 rv = (pmap_load(pte) & mask) == value;
5552 if ((m->flags & PG_FICTITIOUS) == 0) {
5553 pvh = page_to_pvh(m);
5554 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5556 PMAP_ASSERT_STAGE1(pmap);
5557 if (!PMAP_TRYLOCK(pmap)) {
5558 md_gen = m->md.pv_gen;
5559 pvh_gen = pvh->pv_gen;
5563 if (md_gen != m->md.pv_gen ||
5564 pvh_gen != pvh->pv_gen) {
5569 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5571 ("pmap_page_test_mappings: Invalid level %d", lvl));
5575 mask |= ATTR_S1_AP_RW_BIT;
5576 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
5579 mask |= ATTR_AF | ATTR_DESCR_MASK;
5580 value |= ATTR_AF | L2_BLOCK;
5582 rv = (pmap_load(pte) & mask) == value;
5596 * Return whether or not the specified physical page was modified
5597 * in any physical maps.
5600 pmap_is_modified(vm_page_t m)
5603 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5604 ("pmap_is_modified: page %p is not managed", m));
5607 * If the page is not busied then this check is racy.
5609 if (!pmap_page_is_write_mapped(m))
5611 return (pmap_page_test_mappings(m, FALSE, TRUE));
5615 * pmap_is_prefaultable:
5617 * Return whether or not the specified virtual address is eligible
5621 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5629 pte = pmap_pte(pmap, addr, &lvl);
5630 if (pte != NULL && pmap_load(pte) != 0) {
5638 * pmap_is_referenced:
5640 * Return whether or not the specified physical page was referenced
5641 * in any physical maps.
5644 pmap_is_referenced(vm_page_t m)
5647 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5648 ("pmap_is_referenced: page %p is not managed", m));
5649 return (pmap_page_test_mappings(m, TRUE, FALSE));
5653 * Clear the write and modified bits in each of the given page's mappings.
5656 pmap_remove_write(vm_page_t m)
5658 struct md_page *pvh;
5660 struct rwlock *lock;
5661 pv_entry_t next_pv, pv;
5662 pt_entry_t oldpte, *pte;
5664 int lvl, md_gen, pvh_gen;
5666 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5667 ("pmap_remove_write: page %p is not managed", m));
5668 vm_page_assert_busied(m);
5670 if (!pmap_page_is_write_mapped(m))
5672 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5673 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
5676 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5678 PMAP_ASSERT_STAGE1(pmap);
5679 if (!PMAP_TRYLOCK(pmap)) {
5680 pvh_gen = pvh->pv_gen;
5684 if (pvh_gen != pvh->pv_gen) {
5690 pte = pmap_pte(pmap, va, &lvl);
5691 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
5692 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
5693 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5694 ("inconsistent pv lock %p %p for page %p",
5695 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5698 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5700 PMAP_ASSERT_STAGE1(pmap);
5701 if (!PMAP_TRYLOCK(pmap)) {
5702 pvh_gen = pvh->pv_gen;
5703 md_gen = m->md.pv_gen;
5707 if (pvh_gen != pvh->pv_gen ||
5708 md_gen != m->md.pv_gen) {
5713 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5714 oldpte = pmap_load(pte);
5715 if ((oldpte & ATTR_SW_DBM) != 0) {
5716 while (!atomic_fcmpset_64(pte, &oldpte,
5717 (oldpte | ATTR_S1_AP_RW_BIT) & ~ATTR_SW_DBM))
5719 if ((oldpte & ATTR_S1_AP_RW_BIT) ==
5720 ATTR_S1_AP(ATTR_S1_AP_RW))
5722 pmap_invalidate_page(pmap, pv->pv_va, true);
5727 vm_page_aflag_clear(m, PGA_WRITEABLE);
5731 * pmap_ts_referenced:
5733 * Return a count of reference bits for a page, clearing those bits.
5734 * It is not necessary for every reference bit to be cleared, but it
5735 * is necessary that 0 only be returned when there are truly no
5736 * reference bits set.
5738 * As an optimization, update the page's dirty field if a modified bit is
5739 * found while counting reference bits. This opportunistic update can be
5740 * performed at low cost and can eliminate the need for some future calls
5741 * to pmap_is_modified(). However, since this function stops after
5742 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5743 * dirty pages. Those dirty pages will only be detected by a future call
5744 * to pmap_is_modified().
5747 pmap_ts_referenced(vm_page_t m)
5749 struct md_page *pvh;
5752 struct rwlock *lock;
5753 pd_entry_t *pde, tpde;
5754 pt_entry_t *pte, tpte;
5757 int cleared, lvl, md_gen, not_cleared, pvh_gen;
5758 struct spglist free;
5760 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5761 ("pmap_ts_referenced: page %p is not managed", m));
5764 pa = VM_PAGE_TO_PHYS(m);
5765 lock = PHYS_TO_PV_LIST_LOCK(pa);
5766 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
5770 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5771 goto small_mappings;
5777 if (!PMAP_TRYLOCK(pmap)) {
5778 pvh_gen = pvh->pv_gen;
5782 if (pvh_gen != pvh->pv_gen) {
5788 pde = pmap_pde(pmap, va, &lvl);
5789 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
5791 ("pmap_ts_referenced: invalid pde level %d", lvl));
5792 tpde = pmap_load(pde);
5793 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
5794 ("pmap_ts_referenced: found an invalid l1 table"));
5795 pte = pmap_l1_to_l2(pde, va);
5796 tpte = pmap_load(pte);
5797 if (pmap_pte_dirty(pmap, tpte)) {
5799 * Although "tpte" is mapping a 2MB page, because
5800 * this function is called at a 4KB page granularity,
5801 * we only update the 4KB page under test.
5806 if ((tpte & ATTR_AF) != 0) {
5808 * Since this reference bit is shared by 512 4KB pages,
5809 * it should not be cleared every time it is tested.
5810 * Apply a simple "hash" function on the physical page
5811 * number, the virtual superpage number, and the pmap
5812 * address to select one 4KB page out of the 512 on
5813 * which testing the reference bit will result in
5814 * clearing that reference bit. This function is
5815 * designed to avoid the selection of the same 4KB page
5816 * for every 2MB page mapping.
5818 * On demotion, a mapping that hasn't been referenced
5819 * is simply destroyed. To avoid the possibility of a
5820 * subsequent page fault on a demoted wired mapping,
5821 * always leave its reference bit set. Moreover,
5822 * since the superpage is wired, the current state of
5823 * its reference bit won't affect page replacement.
5825 if ((((pa >> PAGE_SHIFT) ^ (va >> L2_SHIFT) ^
5826 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
5827 (tpte & ATTR_SW_WIRED) == 0) {
5828 pmap_clear_bits(pte, ATTR_AF);
5829 pmap_invalidate_page(pmap, va, true);
5835 /* Rotate the PV list if it has more than one entry. */
5836 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5837 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5838 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5841 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5843 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5845 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5852 if (!PMAP_TRYLOCK(pmap)) {
5853 pvh_gen = pvh->pv_gen;
5854 md_gen = m->md.pv_gen;
5858 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5863 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5864 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
5866 ("pmap_ts_referenced: invalid pde level %d", lvl));
5867 tpde = pmap_load(pde);
5868 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
5869 ("pmap_ts_referenced: found an invalid l2 table"));
5870 pte = pmap_l2_to_l3(pde, pv->pv_va);
5871 tpte = pmap_load(pte);
5872 if (pmap_pte_dirty(pmap, tpte))
5874 if ((tpte & ATTR_AF) != 0) {
5875 if ((tpte & ATTR_SW_WIRED) == 0) {
5876 pmap_clear_bits(pte, ATTR_AF);
5877 pmap_invalidate_page(pmap, pv->pv_va, true);
5883 /* Rotate the PV list if it has more than one entry. */
5884 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5885 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5886 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5889 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
5890 not_cleared < PMAP_TS_REFERENCED_MAX);
5893 vm_page_free_pages_toq(&free, true);
5894 return (cleared + not_cleared);
5898 * Apply the given advice to the specified range of addresses within the
5899 * given pmap. Depending on the advice, clear the referenced and/or
5900 * modified flags in each mapping and set the mapped page's dirty field.
5903 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5905 struct rwlock *lock;
5906 vm_offset_t va, va_next;
5908 pd_entry_t *l0, *l1, *l2, oldl2;
5909 pt_entry_t *l3, oldl3;
5911 PMAP_ASSERT_STAGE1(pmap);
5913 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5917 for (; sva < eva; sva = va_next) {
5918 l0 = pmap_l0(pmap, sva);
5919 if (pmap_load(l0) == 0) {
5920 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
5926 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
5929 l1 = pmap_l0_to_l1(l0, sva);
5930 if (pmap_load(l1) == 0)
5932 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK)
5935 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
5938 l2 = pmap_l1_to_l2(l1, sva);
5939 oldl2 = pmap_load(l2);
5942 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
5943 if ((oldl2 & ATTR_SW_MANAGED) == 0)
5946 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
5951 * The 2MB page mapping was destroyed.
5957 * Unless the page mappings are wired, remove the
5958 * mapping to a single page so that a subsequent
5959 * access may repromote. Choosing the last page
5960 * within the address range [sva, min(va_next, eva))
5961 * generally results in more repromotions. Since the
5962 * underlying page table page is fully populated, this
5963 * removal never frees a page table page.
5965 if ((oldl2 & ATTR_SW_WIRED) == 0) {
5971 ("pmap_advise: no address gap"));
5972 l3 = pmap_l2_to_l3(l2, va);
5973 KASSERT(pmap_load(l3) != 0,
5974 ("pmap_advise: invalid PTE"));
5975 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
5981 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
5982 ("pmap_advise: invalid L2 entry after demotion"));
5986 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
5988 oldl3 = pmap_load(l3);
5989 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
5990 (ATTR_SW_MANAGED | L3_PAGE))
5992 else if (pmap_pte_dirty(pmap, oldl3)) {
5993 if (advice == MADV_DONTNEED) {
5995 * Future calls to pmap_is_modified()
5996 * can be avoided by making the page
5999 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK);
6002 while (!atomic_fcmpset_long(l3, &oldl3,
6003 (oldl3 & ~ATTR_AF) |
6004 ATTR_S1_AP(ATTR_S1_AP_RO)))
6006 } else if ((oldl3 & ATTR_AF) != 0)
6007 pmap_clear_bits(l3, ATTR_AF);
6014 if (va != va_next) {
6015 pmap_invalidate_range(pmap, va, sva, true);
6020 pmap_invalidate_range(pmap, va, sva, true);
6026 * Clear the modify bits on the specified physical page.
6029 pmap_clear_modify(vm_page_t m)
6031 struct md_page *pvh;
6032 struct rwlock *lock;
6034 pv_entry_t next_pv, pv;
6035 pd_entry_t *l2, oldl2;
6036 pt_entry_t *l3, oldl3;
6038 int md_gen, pvh_gen;
6040 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6041 ("pmap_clear_modify: page %p is not managed", m));
6042 vm_page_assert_busied(m);
6044 if (!pmap_page_is_write_mapped(m))
6046 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
6047 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6050 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6052 PMAP_ASSERT_STAGE1(pmap);
6053 if (!PMAP_TRYLOCK(pmap)) {
6054 pvh_gen = pvh->pv_gen;
6058 if (pvh_gen != pvh->pv_gen) {
6064 l2 = pmap_l2(pmap, va);
6065 oldl2 = pmap_load(l2);
6066 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */
6067 if ((oldl2 & ATTR_SW_DBM) != 0 &&
6068 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
6069 (oldl2 & ATTR_SW_WIRED) == 0) {
6071 * Write protect the mapping to a single page so that
6072 * a subsequent write access may repromote.
6074 va += VM_PAGE_TO_PHYS(m) - (oldl2 & ~ATTR_MASK);
6075 l3 = pmap_l2_to_l3(l2, va);
6076 oldl3 = pmap_load(l3);
6077 while (!atomic_fcmpset_long(l3, &oldl3,
6078 (oldl3 & ~ATTR_SW_DBM) | ATTR_S1_AP(ATTR_S1_AP_RO)))
6081 pmap_invalidate_page(pmap, va, true);
6085 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6087 PMAP_ASSERT_STAGE1(pmap);
6088 if (!PMAP_TRYLOCK(pmap)) {
6089 md_gen = m->md.pv_gen;
6090 pvh_gen = pvh->pv_gen;
6094 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6099 l2 = pmap_l2(pmap, pv->pv_va);
6100 l3 = pmap_l2_to_l3(l2, pv->pv_va);
6101 oldl3 = pmap_load(l3);
6102 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM){
6103 pmap_set_bits(l3, ATTR_S1_AP(ATTR_S1_AP_RO));
6104 pmap_invalidate_page(pmap, pv->pv_va, true);
6112 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6114 struct pmap_preinit_mapping *ppim;
6115 vm_offset_t va, offset;
6118 int i, lvl, l2_blocks, free_l2_count, start_idx;
6120 if (!vm_initialized) {
6122 * No L3 ptables so map entire L2 blocks where start VA is:
6123 * preinit_map_va + start_idx * L2_SIZE
6124 * There may be duplicate mappings (multiple VA -> same PA) but
6125 * ARM64 dcache is always PIPT so that's acceptable.
6130 /* Calculate how many L2 blocks are needed for the mapping */
6131 l2_blocks = (roundup2(pa + size, L2_SIZE) -
6132 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
6134 offset = pa & L2_OFFSET;
6136 if (preinit_map_va == 0)
6139 /* Map 2MiB L2 blocks from reserved VA space */
6143 /* Find enough free contiguous VA space */
6144 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6145 ppim = pmap_preinit_mapping + i;
6146 if (free_l2_count > 0 && ppim->pa != 0) {
6147 /* Not enough space here */
6153 if (ppim->pa == 0) {
6155 if (start_idx == -1)
6158 if (free_l2_count == l2_blocks)
6162 if (free_l2_count != l2_blocks)
6163 panic("%s: too many preinit mappings", __func__);
6165 va = preinit_map_va + (start_idx * L2_SIZE);
6166 for (i = start_idx; i < start_idx + l2_blocks; i++) {
6167 /* Mark entries as allocated */
6168 ppim = pmap_preinit_mapping + i;
6170 ppim->va = va + offset;
6175 pa = rounddown2(pa, L2_SIZE);
6176 for (i = 0; i < l2_blocks; i++) {
6177 pde = pmap_pde(kernel_pmap, va, &lvl);
6178 KASSERT(pde != NULL,
6179 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
6182 ("pmap_mapbios: Invalid level %d", lvl));
6184 /* Insert L2_BLOCK */
6185 l2 = pmap_l1_to_l2(pde, va);
6187 pa | ATTR_DEFAULT | ATTR_S1_XN |
6188 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
6193 pmap_invalidate_all(kernel_pmap);
6195 va = preinit_map_va + (start_idx * L2_SIZE);
6198 /* kva_alloc may be used to map the pages */
6199 offset = pa & PAGE_MASK;
6200 size = round_page(offset + size);
6202 va = kva_alloc(size);
6204 panic("%s: Couldn't allocate KVA", __func__);
6206 pde = pmap_pde(kernel_pmap, va, &lvl);
6207 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
6209 /* L3 table is linked */
6210 va = trunc_page(va);
6211 pa = trunc_page(pa);
6212 pmap_kenter(va, size, pa, memory_mapping_mode(pa));
6215 return ((void *)(va + offset));
6219 pmap_unmapbios(vm_offset_t va, vm_size_t size)
6221 struct pmap_preinit_mapping *ppim;
6222 vm_offset_t offset, tmpsize, va_trunc;
6225 int i, lvl, l2_blocks, block;
6229 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
6230 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
6232 /* Remove preinit mapping */
6233 preinit_map = false;
6235 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6236 ppim = pmap_preinit_mapping + i;
6237 if (ppim->va == va) {
6238 KASSERT(ppim->size == size,
6239 ("pmap_unmapbios: size mismatch"));
6244 offset = block * L2_SIZE;
6245 va_trunc = rounddown2(va, L2_SIZE) + offset;
6247 /* Remove L2_BLOCK */
6248 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
6249 KASSERT(pde != NULL,
6250 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
6252 l2 = pmap_l1_to_l2(pde, va_trunc);
6255 if (block == (l2_blocks - 1))
6261 pmap_invalidate_all(kernel_pmap);
6265 /* Unmap the pages reserved with kva_alloc. */
6266 if (vm_initialized) {
6267 offset = va & PAGE_MASK;
6268 size = round_page(offset + size);
6269 va = trunc_page(va);
6271 pde = pmap_pde(kernel_pmap, va, &lvl);
6272 KASSERT(pde != NULL,
6273 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
6274 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
6276 /* Unmap and invalidate the pages */
6277 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6278 pmap_kremove(va + tmpsize);
6285 * Sets the memory attribute for the specified page.
6288 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
6291 m->md.pv_memattr = ma;
6294 * If "m" is a normal page, update its direct mapping. This update
6295 * can be relied upon to perform any cache operations that are
6296 * required for data coherence.
6298 if ((m->flags & PG_FICTITIOUS) == 0 &&
6299 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
6300 m->md.pv_memattr) != 0)
6301 panic("memory attribute change on the direct map failed");
6305 * Changes the specified virtual address range's memory type to that given by
6306 * the parameter "mode". The specified virtual address range must be
6307 * completely contained within either the direct map or the kernel map. If
6308 * the virtual address range is contained within the kernel map, then the
6309 * memory type for each of the corresponding ranges of the direct map is also
6310 * changed. (The corresponding ranges of the direct map are those ranges that
6311 * map the same physical pages as the specified virtual address range.) These
6312 * changes to the direct map are necessary because Intel describes the
6313 * behavior of their processors as "undefined" if two or more mappings to the
6314 * same physical page have different memory types.
6316 * Returns zero if the change completed successfully, and either EINVAL or
6317 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
6318 * of the virtual address range was not mapped, and ENOMEM is returned if
6319 * there was insufficient memory available to complete the change. In the
6320 * latter case, the memory type may have been changed on some part of the
6321 * virtual address range or the direct map.
6324 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
6328 PMAP_LOCK(kernel_pmap);
6329 error = pmap_change_props_locked(va, size, PROT_NONE, mode, false);
6330 PMAP_UNLOCK(kernel_pmap);
6335 * Changes the specified virtual address range's protections to those
6336 * specified by "prot". Like pmap_change_attr(), protections for aliases
6337 * in the direct map are updated as well. Protections on aliasing mappings may
6338 * be a subset of the requested protections; for example, mappings in the direct
6339 * map are never executable.
6342 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
6346 /* Only supported within the kernel map. */
6347 if (va < VM_MIN_KERNEL_ADDRESS)
6350 PMAP_LOCK(kernel_pmap);
6351 error = pmap_change_props_locked(va, size, prot, -1, false);
6352 PMAP_UNLOCK(kernel_pmap);
6357 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
6358 int mode, bool skip_unmapped)
6360 vm_offset_t base, offset, tmpva;
6363 pt_entry_t pte, *ptep, *newpte;
6364 pt_entry_t bits, mask;
6367 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
6368 base = trunc_page(va);
6369 offset = va & PAGE_MASK;
6370 size = round_page(offset + size);
6372 if (!VIRT_IN_DMAP(base) &&
6373 !(base >= VM_MIN_KERNEL_ADDRESS && base < VM_MAX_KERNEL_ADDRESS))
6379 bits = ATTR_S1_IDX(mode);
6380 mask = ATTR_S1_IDX_MASK;
6381 if (mode == VM_MEMATTR_DEVICE) {
6386 if (prot != VM_PROT_NONE) {
6387 /* Don't mark the DMAP as executable. It never is on arm64. */
6388 if (VIRT_IN_DMAP(base)) {
6389 prot &= ~VM_PROT_EXECUTE;
6391 * XXX Mark the DMAP as writable for now. We rely
6392 * on this in ddb & dtrace to insert breakpoint
6395 prot |= VM_PROT_WRITE;
6398 if ((prot & VM_PROT_WRITE) == 0) {
6399 bits |= ATTR_S1_AP(ATTR_S1_AP_RO);
6401 if ((prot & VM_PROT_EXECUTE) == 0) {
6402 bits |= ATTR_S1_PXN;
6404 bits |= ATTR_S1_UXN;
6405 mask |= ATTR_S1_AP_MASK | ATTR_S1_XN;
6408 for (tmpva = base; tmpva < base + size; ) {
6409 ptep = pmap_pte(kernel_pmap, tmpva, &lvl);
6410 if (ptep == NULL && !skip_unmapped) {
6412 } else if ((ptep == NULL && skip_unmapped) ||
6413 (pmap_load(ptep) & mask) == bits) {
6415 * We already have the correct attribute or there
6416 * is no memory mapped at this address and we are
6417 * skipping unmapped memory.
6421 panic("Invalid DMAP table level: %d\n", lvl);
6423 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
6426 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
6433 /* We can't demote/promote this entry */
6434 MPASS((pmap_load(ptep) & ATTR_SW_NO_PROMOTE) == 0);
6437 * Split the entry to an level 3 table, then
6438 * set the new attribute.
6442 panic("Invalid DMAP table level: %d\n", lvl);
6444 if ((tmpva & L1_OFFSET) == 0 &&
6445 (base + size - tmpva) >= L1_SIZE) {
6449 newpte = pmap_demote_l1(kernel_pmap, ptep,
6450 tmpva & ~L1_OFFSET);
6453 ptep = pmap_l1_to_l2(ptep, tmpva);
6456 if ((tmpva & L2_OFFSET) == 0 &&
6457 (base + size - tmpva) >= L2_SIZE) {
6461 newpte = pmap_demote_l2(kernel_pmap, ptep,
6465 ptep = pmap_l2_to_l3(ptep, tmpva);
6468 pte_size = PAGE_SIZE;
6472 /* Update the entry */
6473 pte = pmap_load(ptep);
6477 pmap_update_entry(kernel_pmap, ptep, pte, tmpva,
6480 pa = pte & ~ATTR_MASK;
6481 if (!VIRT_IN_DMAP(tmpva) && PHYS_IN_DMAP(pa)) {
6483 * Keep the DMAP memory in sync.
6485 rv = pmap_change_props_locked(
6486 PHYS_TO_DMAP(pa), pte_size,
6493 * If moving to a non-cacheable entry flush
6496 if (mode == VM_MEMATTR_UNCACHEABLE)
6497 cpu_dcache_wbinv_range(tmpva, pte_size);
6506 * Create an L2 table to map all addresses within an L1 mapping.
6509 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
6511 pt_entry_t *l2, newl2, oldl1;
6513 vm_paddr_t l2phys, phys;
6517 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6518 oldl1 = pmap_load(l1);
6519 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
6520 ("pmap_demote_l1: Demoting a non-block entry"));
6521 KASSERT((va & L1_OFFSET) == 0,
6522 ("pmap_demote_l1: Invalid virtual address %#lx", va));
6523 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
6524 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
6525 KASSERT((oldl1 & ATTR_SW_NO_PROMOTE) == 0,
6526 ("pmap_demote_l1: Demoting entry with no-demote flag set"));
6529 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
6530 tmpl1 = kva_alloc(PAGE_SIZE);
6535 if ((ml2 = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED)) ==
6537 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
6538 " in pmap %p", va, pmap);
6543 l2phys = VM_PAGE_TO_PHYS(ml2);
6544 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
6546 /* Address the range points at */
6547 phys = oldl1 & ~ATTR_MASK;
6548 /* The attributed from the old l1 table to be copied */
6549 newl2 = oldl1 & ATTR_MASK;
6551 /* Create the new entries */
6552 for (i = 0; i < Ln_ENTRIES; i++) {
6553 l2[i] = newl2 | phys;
6556 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
6557 ("Invalid l2 page (%lx != %lx)", l2[0],
6558 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
6561 pmap_kenter(tmpl1, PAGE_SIZE,
6562 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET,
6563 VM_MEMATTR_WRITE_BACK);
6564 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
6567 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
6571 pmap_kremove(tmpl1);
6572 kva_free(tmpl1, PAGE_SIZE);
6579 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
6583 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
6590 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
6591 struct rwlock **lockp)
6593 struct spglist free;
6596 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
6598 vm_page_free_pages_toq(&free, true);
6602 * Create an L3 table to map all addresses within an L2 mapping.
6605 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
6606 struct rwlock **lockp)
6608 pt_entry_t *l3, newl3, oldl2;
6613 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6614 PMAP_ASSERT_STAGE1(pmap);
6615 KASSERT(ADDR_IS_CANONICAL(va),
6616 ("%s: Address not in canonical form: %lx", __func__, va));
6619 oldl2 = pmap_load(l2);
6620 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
6621 ("pmap_demote_l2: Demoting a non-block entry"));
6622 KASSERT((oldl2 & ATTR_SW_NO_PROMOTE) == 0,
6623 ("pmap_demote_l2: Demoting entry with no-demote flag set"));
6627 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
6628 tmpl2 = kva_alloc(PAGE_SIZE);
6634 * Invalidate the 2MB page mapping and return "failure" if the
6635 * mapping was never accessed.
6637 if ((oldl2 & ATTR_AF) == 0) {
6638 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
6639 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
6640 pmap_demote_l2_abort(pmap, va, l2, lockp);
6641 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
6646 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
6647 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
6648 ("pmap_demote_l2: page table page for a wired mapping"
6652 * If the page table page is missing and the mapping
6653 * is for a kernel address, the mapping must belong to
6654 * either the direct map or the early kernel memory.
6655 * Page table pages are preallocated for every other
6656 * part of the kernel address space, so the direct map
6657 * region and early kernel memory are the only parts of the
6658 * kernel address space that must be handled here.
6660 KASSERT(!ADDR_IS_KERNEL(va) || VIRT_IN_DMAP(va) ||
6661 (va >= VM_MIN_KERNEL_ADDRESS && va < kernel_vm_end),
6662 ("pmap_demote_l2: No saved mpte for va %#lx", va));
6665 * If the 2MB page mapping belongs to the direct map
6666 * region of the kernel's address space, then the page
6667 * allocation request specifies the highest possible
6668 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
6669 * priority is normal.
6671 ml3 = vm_page_alloc_noobj(
6672 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : 0) |
6676 * If the allocation of the new page table page fails,
6677 * invalidate the 2MB page mapping and return "failure".
6680 pmap_demote_l2_abort(pmap, va, l2, lockp);
6681 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
6682 " in pmap %p", va, pmap);
6685 ml3->pindex = pmap_l2_pindex(va);
6687 if (!ADDR_IS_KERNEL(va)) {
6688 ml3->ref_count = NL3PG;
6689 pmap_resident_count_inc(pmap, 1);
6692 l3phys = VM_PAGE_TO_PHYS(ml3);
6693 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
6694 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
6695 KASSERT((oldl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) !=
6696 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM),
6697 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
6700 * If the page table page is not leftover from an earlier promotion,
6701 * or the mapping attributes have changed, (re)initialize the L3 table.
6703 * When pmap_update_entry() clears the old L2 mapping, it (indirectly)
6704 * performs a dsb(). That dsb() ensures that the stores for filling
6705 * "l3" are visible before "l3" is added to the page table.
6707 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK))
6708 pmap_fill_l3(l3, newl3);
6711 * Map the temporary page so we don't lose access to the l2 table.
6714 pmap_kenter(tmpl2, PAGE_SIZE,
6715 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET,
6716 VM_MEMATTR_WRITE_BACK);
6717 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
6721 * The spare PV entries must be reserved prior to demoting the
6722 * mapping, that is, prior to changing the PDE. Otherwise, the state
6723 * of the L2 and the PV lists will be inconsistent, which can result
6724 * in reclaim_pv_chunk() attempting to remove a PV entry from the
6725 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
6726 * PV entry for the 2MB page mapping that is being demoted.
6728 if ((oldl2 & ATTR_SW_MANAGED) != 0)
6729 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
6732 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
6733 * the 2MB page mapping.
6735 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
6738 * Demote the PV entry.
6740 if ((oldl2 & ATTR_SW_MANAGED) != 0)
6741 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
6743 atomic_add_long(&pmap_l2_demotions, 1);
6744 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
6745 " in pmap %p %lx", va, pmap, l3[0]);
6749 pmap_kremove(tmpl2);
6750 kva_free(tmpl2, PAGE_SIZE);
6758 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
6760 struct rwlock *lock;
6764 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
6771 * Perform the pmap work for mincore(2). If the page is not both referenced and
6772 * modified by this pmap, returns its physical address so that the caller can
6773 * find other mappings.
6776 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
6778 pt_entry_t *pte, tpte;
6779 vm_paddr_t mask, pa;
6783 PMAP_ASSERT_STAGE1(pmap);
6785 pte = pmap_pte(pmap, addr, &lvl);
6787 tpte = pmap_load(pte);
6800 panic("pmap_mincore: invalid level %d", lvl);
6803 managed = (tpte & ATTR_SW_MANAGED) != 0;
6804 val = MINCORE_INCORE;
6806 val |= MINCORE_PSIND(3 - lvl);
6807 if ((managed && pmap_pte_dirty(pmap, tpte)) || (!managed &&
6808 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW)))
6809 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6810 if ((tpte & ATTR_AF) == ATTR_AF)
6811 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6813 pa = (tpte & ~ATTR_MASK) | (addr & mask);
6819 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6820 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
6828 * Garbage collect every ASID that is neither active on a processor nor
6832 pmap_reset_asid_set(pmap_t pmap)
6835 int asid, cpuid, epoch;
6836 struct asid_set *set;
6837 enum pmap_stage stage;
6839 set = pmap->pm_asid_set;
6840 stage = pmap->pm_stage;
6842 set = pmap->pm_asid_set;
6843 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6844 mtx_assert(&set->asid_set_mutex, MA_OWNED);
6847 * Ensure that the store to asid_epoch is globally visible before the
6848 * loads from pc_curpmap are performed.
6850 epoch = set->asid_epoch + 1;
6851 if (epoch == INT_MAX)
6853 set->asid_epoch = epoch;
6855 if (stage == PM_STAGE1) {
6856 __asm __volatile("tlbi vmalle1is");
6858 KASSERT(pmap_clean_stage2_tlbi != NULL,
6859 ("%s: Unset stage 2 tlb invalidation callback\n",
6861 pmap_clean_stage2_tlbi();
6864 bit_nclear(set->asid_set, ASID_FIRST_AVAILABLE,
6865 set->asid_set_size - 1);
6866 CPU_FOREACH(cpuid) {
6867 if (cpuid == curcpu)
6869 if (stage == PM_STAGE1) {
6870 curpmap = pcpu_find(cpuid)->pc_curpmap;
6871 PMAP_ASSERT_STAGE1(pmap);
6873 curpmap = pcpu_find(cpuid)->pc_curvmpmap;
6874 if (curpmap == NULL)
6876 PMAP_ASSERT_STAGE2(pmap);
6878 KASSERT(curpmap->pm_asid_set == set, ("Incorrect set"));
6879 asid = COOKIE_TO_ASID(curpmap->pm_cookie);
6882 bit_set(set->asid_set, asid);
6883 curpmap->pm_cookie = COOKIE_FROM(asid, epoch);
6888 * Allocate a new ASID for the specified pmap.
6891 pmap_alloc_asid(pmap_t pmap)
6893 struct asid_set *set;
6896 set = pmap->pm_asid_set;
6897 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6899 mtx_lock_spin(&set->asid_set_mutex);
6902 * While this processor was waiting to acquire the asid set mutex,
6903 * pmap_reset_asid_set() running on another processor might have
6904 * updated this pmap's cookie to the current epoch. In which case, we
6905 * don't need to allocate a new ASID.
6907 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch)
6910 bit_ffc_at(set->asid_set, set->asid_next, set->asid_set_size,
6912 if (new_asid == -1) {
6913 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
6914 set->asid_next, &new_asid);
6915 if (new_asid == -1) {
6916 pmap_reset_asid_set(pmap);
6917 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
6918 set->asid_set_size, &new_asid);
6919 KASSERT(new_asid != -1, ("ASID allocation failure"));
6922 bit_set(set->asid_set, new_asid);
6923 set->asid_next = new_asid + 1;
6924 pmap->pm_cookie = COOKIE_FROM(new_asid, set->asid_epoch);
6926 mtx_unlock_spin(&set->asid_set_mutex);
6929 static uint64_t __read_mostly ttbr_flags;
6932 * Compute the value that should be stored in ttbr0 to activate the specified
6933 * pmap. This value may change from time to time.
6936 pmap_to_ttbr0(pmap_t pmap)
6940 ttbr = pmap->pm_ttbr;
6941 ttbr |= ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
6948 pmap_set_cnp(void *arg)
6950 uint64_t ttbr0, ttbr1;
6953 cpuid = *(u_int *)arg;
6954 if (cpuid == curcpu) {
6956 * Set the flags while all CPUs are handling the
6957 * smp_rendezvous so will not call pmap_to_ttbr0. Any calls
6958 * to pmap_to_ttbr0 after this will have the CnP flag set.
6959 * The dsb after invalidating the TLB will act as a barrier
6960 * to ensure all CPUs can observe this change.
6962 ttbr_flags |= TTBR_CnP;
6965 ttbr0 = READ_SPECIALREG(ttbr0_el1);
6968 ttbr1 = READ_SPECIALREG(ttbr1_el1);
6971 /* Update ttbr{0,1}_el1 with the CnP flag */
6972 WRITE_SPECIALREG(ttbr0_el1, ttbr0);
6973 WRITE_SPECIALREG(ttbr1_el1, ttbr1);
6975 __asm __volatile("tlbi vmalle1is");
6981 * Defer enabling CnP until we have read the ID registers to know if it's
6982 * supported on all CPUs.
6985 pmap_init_cnp(void *dummy __unused)
6990 if (!get_kernel_reg(ID_AA64MMFR2_EL1, ®))
6993 if (ID_AA64MMFR2_CnP_VAL(reg) != ID_AA64MMFR2_CnP_NONE) {
6995 printf("Enabling CnP\n");
6997 smp_rendezvous(NULL, pmap_set_cnp, NULL, &cpuid);
7001 SYSINIT(pmap_init_cnp, SI_SUB_SMP, SI_ORDER_ANY, pmap_init_cnp, NULL);
7004 pmap_activate_int(pmap_t pmap)
7006 struct asid_set *set;
7009 KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap"));
7010 KASSERT(pmap != kernel_pmap, ("kernel pmap activation"));
7012 if ((pmap->pm_stage == PM_STAGE1 && pmap == PCPU_GET(curpmap)) ||
7013 (pmap->pm_stage == PM_STAGE2 && pmap == PCPU_GET(curvmpmap))) {
7015 * Handle the possibility that the old thread was preempted
7016 * after an "ic" or "tlbi" instruction but before it performed
7017 * a "dsb" instruction. If the old thread migrates to a new
7018 * processor, its completion of a "dsb" instruction on that
7019 * new processor does not guarantee that the "ic" or "tlbi"
7020 * instructions performed on the old processor have completed.
7026 set = pmap->pm_asid_set;
7027 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
7030 * Ensure that the store to curpmap is globally visible before the
7031 * load from asid_epoch is performed.
7033 if (pmap->pm_stage == PM_STAGE1)
7034 PCPU_SET(curpmap, pmap);
7036 PCPU_SET(curvmpmap, pmap);
7038 epoch = COOKIE_TO_EPOCH(pmap->pm_cookie);
7039 if (epoch >= 0 && epoch != set->asid_epoch)
7040 pmap_alloc_asid(pmap);
7042 if (pmap->pm_stage == PM_STAGE1) {
7043 set_ttbr0(pmap_to_ttbr0(pmap));
7044 if (PCPU_GET(bcast_tlbi_workaround) != 0)
7045 invalidate_local_icache();
7051 pmap_activate_vm(pmap_t pmap)
7054 PMAP_ASSERT_STAGE2(pmap);
7056 (void)pmap_activate_int(pmap);
7060 pmap_activate(struct thread *td)
7064 pmap = vmspace_pmap(td->td_proc->p_vmspace);
7065 PMAP_ASSERT_STAGE1(pmap);
7067 (void)pmap_activate_int(pmap);
7072 * To eliminate the unused parameter "old", we would have to add an instruction
7076 pmap_switch(struct thread *old __unused, struct thread *new)
7078 pcpu_bp_harden bp_harden;
7081 /* Store the new curthread */
7082 PCPU_SET(curthread, new);
7083 #if defined(PERTHREAD_SSP)
7084 /* Set the new threads SSP canary */
7085 __asm("msr sp_el0, %0" :: "r"(&new->td_md.md_canary));
7088 /* And the new pcb */
7090 PCPU_SET(curpcb, pcb);
7093 * TODO: We may need to flush the cache here if switching
7094 * to a user process.
7097 if (pmap_activate_int(vmspace_pmap(new->td_proc->p_vmspace))) {
7099 * Stop userspace from training the branch predictor against
7100 * other processes. This will call into a CPU specific
7101 * function that clears the branch predictor state.
7103 bp_harden = PCPU_GET(bp_harden);
7104 if (bp_harden != NULL)
7112 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
7115 PMAP_ASSERT_STAGE1(pmap);
7116 KASSERT(ADDR_IS_CANONICAL(va),
7117 ("%s: Address not in canonical form: %lx", __func__, va));
7119 if (ADDR_IS_KERNEL(va)) {
7120 cpu_icache_sync_range(va, sz);
7125 /* Find the length of data in this page to flush */
7126 offset = va & PAGE_MASK;
7127 len = imin(PAGE_SIZE - offset, sz);
7130 /* Extract the physical address & find it in the DMAP */
7131 pa = pmap_extract(pmap, va);
7133 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
7135 /* Move to the next page */
7138 /* Set the length for the next iteration */
7139 len = imin(PAGE_SIZE, sz);
7145 pmap_stage2_fault(pmap_t pmap, uint64_t esr, uint64_t far)
7148 pt_entry_t *ptep, pte;
7151 PMAP_ASSERT_STAGE2(pmap);
7154 /* Data and insn aborts use same encoding for FSC field. */
7155 dfsc = esr & ISS_DATA_DFSC_MASK;
7157 case ISS_DATA_DFSC_TF_L0:
7158 case ISS_DATA_DFSC_TF_L1:
7159 case ISS_DATA_DFSC_TF_L2:
7160 case ISS_DATA_DFSC_TF_L3:
7162 pdep = pmap_pde(pmap, far, &lvl);
7163 if (pdep == NULL || lvl != (dfsc - ISS_DATA_DFSC_TF_L1)) {
7170 ptep = pmap_l0_to_l1(pdep, far);
7173 ptep = pmap_l1_to_l2(pdep, far);
7176 ptep = pmap_l2_to_l3(pdep, far);
7179 panic("%s: Invalid pde level %d", __func__,lvl);
7183 case ISS_DATA_DFSC_AFF_L1:
7184 case ISS_DATA_DFSC_AFF_L2:
7185 case ISS_DATA_DFSC_AFF_L3:
7187 ptep = pmap_pte(pmap, far, &lvl);
7189 if (ptep != NULL && (pte = pmap_load(ptep)) != 0) {
7191 pmap_invalidate_vpipt_icache();
7194 * If accessing an executable page invalidate
7195 * the I-cache so it will be valid when we
7196 * continue execution in the guest. The D-cache
7197 * is assumed to already be clean to the Point
7200 if ((pte & ATTR_S2_XN_MASK) !=
7201 ATTR_S2_XN(ATTR_S2_XN_NONE)) {
7202 invalidate_icache();
7205 pmap_set_bits(ptep, ATTR_AF | ATTR_DESCR_VALID);
7216 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
7218 pt_entry_t pte, *ptep;
7225 ec = ESR_ELx_EXCEPTION(esr);
7227 case EXCP_INSN_ABORT_L:
7228 case EXCP_INSN_ABORT:
7229 case EXCP_DATA_ABORT_L:
7230 case EXCP_DATA_ABORT:
7236 if (pmap->pm_stage == PM_STAGE2)
7237 return (pmap_stage2_fault(pmap, esr, far));
7239 /* Data and insn aborts use same encoding for FSC field. */
7240 switch (esr & ISS_DATA_DFSC_MASK) {
7241 case ISS_DATA_DFSC_AFF_L1:
7242 case ISS_DATA_DFSC_AFF_L2:
7243 case ISS_DATA_DFSC_AFF_L3:
7245 ptep = pmap_pte(pmap, far, &lvl);
7247 pmap_set_bits(ptep, ATTR_AF);
7250 * XXXMJ as an optimization we could mark the entry
7251 * dirty if this is a write fault.
7256 case ISS_DATA_DFSC_PF_L1:
7257 case ISS_DATA_DFSC_PF_L2:
7258 case ISS_DATA_DFSC_PF_L3:
7259 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
7260 (esr & ISS_DATA_WnR) == 0)
7263 ptep = pmap_pte(pmap, far, &lvl);
7265 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
7266 if ((pte & ATTR_S1_AP_RW_BIT) ==
7267 ATTR_S1_AP(ATTR_S1_AP_RO)) {
7268 pmap_clear_bits(ptep, ATTR_S1_AP_RW_BIT);
7269 pmap_invalidate_page(pmap, far, true);
7275 case ISS_DATA_DFSC_TF_L0:
7276 case ISS_DATA_DFSC_TF_L1:
7277 case ISS_DATA_DFSC_TF_L2:
7278 case ISS_DATA_DFSC_TF_L3:
7280 * Retry the translation. A break-before-make sequence can
7281 * produce a transient fault.
7283 if (pmap == kernel_pmap) {
7285 * The translation fault may have occurred within a
7286 * critical section. Therefore, we must check the
7287 * address without acquiring the kernel pmap's lock.
7289 if (pmap_klookup(far, NULL))
7293 /* Ask the MMU to check the address. */
7294 intr = intr_disable();
7295 par = arm64_address_translate_s1e0r(far);
7300 * If the translation was successful, then we can
7301 * return success to the trap handler.
7303 if (PAR_SUCCESS(par))
7313 * Increase the starting virtual address of the given mapping if a
7314 * different alignment might result in more superpage mappings.
7317 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
7318 vm_offset_t *addr, vm_size_t size)
7320 vm_offset_t superpage_offset;
7324 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
7325 offset += ptoa(object->pg_color);
7326 superpage_offset = offset & L2_OFFSET;
7327 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
7328 (*addr & L2_OFFSET) == superpage_offset)
7330 if ((*addr & L2_OFFSET) < superpage_offset)
7331 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
7333 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
7337 * Get the kernel virtual address of a set of physical pages. If there are
7338 * physical addresses not covered by the DMAP perform a transient mapping
7339 * that will be removed when calling pmap_unmap_io_transient.
7341 * \param page The pages the caller wishes to obtain the virtual
7342 * address on the kernel memory map.
7343 * \param vaddr On return contains the kernel virtual memory address
7344 * of the pages passed in the page parameter.
7345 * \param count Number of pages passed in.
7346 * \param can_fault TRUE if the thread using the mapped pages can take
7347 * page faults, FALSE otherwise.
7349 * \returns TRUE if the caller must call pmap_unmap_io_transient when
7350 * finished or FALSE otherwise.
7354 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7355 boolean_t can_fault)
7358 boolean_t needs_mapping;
7362 * Allocate any KVA space that we need, this is done in a separate
7363 * loop to prevent calling vmem_alloc while pinned.
7365 needs_mapping = FALSE;
7366 for (i = 0; i < count; i++) {
7367 paddr = VM_PAGE_TO_PHYS(page[i]);
7368 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
7369 error = vmem_alloc(kernel_arena, PAGE_SIZE,
7370 M_BESTFIT | M_WAITOK, &vaddr[i]);
7371 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
7372 needs_mapping = TRUE;
7374 vaddr[i] = PHYS_TO_DMAP(paddr);
7378 /* Exit early if everything is covered by the DMAP */
7384 for (i = 0; i < count; i++) {
7385 paddr = VM_PAGE_TO_PHYS(page[i]);
7386 if (!PHYS_IN_DMAP(paddr)) {
7388 "pmap_map_io_transient: TODO: Map out of DMAP data");
7392 return (needs_mapping);
7396 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7397 boolean_t can_fault)
7404 for (i = 0; i < count; i++) {
7405 paddr = VM_PAGE_TO_PHYS(page[i]);
7406 if (!PHYS_IN_DMAP(paddr)) {
7407 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
7413 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
7416 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);
7420 * Track a range of the kernel's virtual address space that is contiguous
7421 * in various mapping attributes.
7423 struct pmap_kernel_map_range {
7433 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
7439 if (eva <= range->sva)
7442 index = range->attrs & ATTR_S1_IDX_MASK;
7444 case ATTR_S1_IDX(VM_MEMATTR_DEVICE):
7447 case ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE):
7450 case ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK):
7453 case ATTR_S1_IDX(VM_MEMATTR_WRITE_THROUGH):
7458 "%s: unknown memory type %x for range 0x%016lx-0x%016lx\n",
7459 __func__, index, range->sva, eva);
7464 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %3s %d %d %d %d\n",
7466 (range->attrs & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP_RW ? 'w' : '-',
7467 (range->attrs & ATTR_S1_PXN) != 0 ? '-' : 'x',
7468 (range->attrs & ATTR_S1_UXN) != 0 ? '-' : 'X',
7469 (range->attrs & ATTR_S1_AP(ATTR_S1_AP_USER)) != 0 ? 'u' : 's',
7470 mode, range->l1blocks, range->l2blocks, range->l3contig,
7473 /* Reset to sentinel value. */
7474 range->sva = 0xfffffffffffffffful;
7478 * Determine whether the attributes specified by a page table entry match those
7479 * being tracked by the current range.
7482 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
7485 return (range->attrs == attrs);
7489 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
7493 memset(range, 0, sizeof(*range));
7495 range->attrs = attrs;
7498 /* Get the block/page attributes that correspond to the table attributes */
7500 sysctl_kmaps_table_attrs(pd_entry_t table)
7505 if ((table & TATTR_UXN_TABLE) != 0)
7506 attrs |= ATTR_S1_UXN;
7507 if ((table & TATTR_PXN_TABLE) != 0)
7508 attrs |= ATTR_S1_PXN;
7509 if ((table & TATTR_AP_TABLE_RO) != 0)
7510 attrs |= ATTR_S1_AP(ATTR_S1_AP_RO);
7515 /* Read the block/page attributes we care about */
7517 sysctl_kmaps_block_attrs(pt_entry_t block)
7519 return (block & (ATTR_S1_AP_MASK | ATTR_S1_XN | ATTR_S1_IDX_MASK));
7523 * Given a leaf PTE, derive the mapping's attributes. If they do not match
7524 * those of the current run, dump the address range and its attributes, and
7528 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
7529 vm_offset_t va, pd_entry_t l0e, pd_entry_t l1e, pd_entry_t l2e,
7534 attrs = sysctl_kmaps_table_attrs(l0e);
7536 if ((l1e & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
7537 attrs |= sysctl_kmaps_block_attrs(l1e);
7540 attrs |= sysctl_kmaps_table_attrs(l1e);
7542 if ((l2e & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
7543 attrs |= sysctl_kmaps_block_attrs(l2e);
7546 attrs |= sysctl_kmaps_table_attrs(l2e);
7547 attrs |= sysctl_kmaps_block_attrs(l3e);
7550 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
7551 sysctl_kmaps_dump(sb, range, va);
7552 sysctl_kmaps_reinit(range, va, attrs);
7557 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
7559 struct pmap_kernel_map_range range;
7560 struct sbuf sbuf, *sb;
7561 pd_entry_t l0e, *l1, l1e, *l2, l2e;
7562 pt_entry_t *l3, l3e;
7565 int error, i, j, k, l;
7567 error = sysctl_wire_old_buffer(req, 0);
7571 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
7573 /* Sentinel value. */
7574 range.sva = 0xfffffffffffffffful;
7577 * Iterate over the kernel page tables without holding the kernel pmap
7578 * lock. Kernel page table pages are never freed, so at worst we will
7579 * observe inconsistencies in the output.
7581 for (sva = 0xffff000000000000ul, i = pmap_l0_index(sva); i < Ln_ENTRIES;
7583 if (i == pmap_l0_index(DMAP_MIN_ADDRESS))
7584 sbuf_printf(sb, "\nDirect map:\n");
7585 else if (i == pmap_l0_index(VM_MIN_KERNEL_ADDRESS))
7586 sbuf_printf(sb, "\nKernel map:\n");
7588 l0e = kernel_pmap->pm_l0[i];
7589 if ((l0e & ATTR_DESCR_VALID) == 0) {
7590 sysctl_kmaps_dump(sb, &range, sva);
7594 pa = l0e & ~ATTR_MASK;
7595 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa);
7597 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
7599 if ((l1e & ATTR_DESCR_VALID) == 0) {
7600 sysctl_kmaps_dump(sb, &range, sva);
7604 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
7605 sysctl_kmaps_check(sb, &range, sva, l0e, l1e,
7611 pa = l1e & ~ATTR_MASK;
7612 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa);
7614 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
7616 if ((l2e & ATTR_DESCR_VALID) == 0) {
7617 sysctl_kmaps_dump(sb, &range, sva);
7621 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK) {
7622 sysctl_kmaps_check(sb, &range, sva,
7628 pa = l2e & ~ATTR_MASK;
7629 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
7631 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
7632 l++, sva += L3_SIZE) {
7634 if ((l3e & ATTR_DESCR_VALID) == 0) {
7635 sysctl_kmaps_dump(sb, &range,
7639 sysctl_kmaps_check(sb, &range, sva,
7640 l0e, l1e, l2e, l3e);
7641 if ((l3e & ATTR_CONTIGUOUS) != 0)
7642 range.l3contig += l % 16 == 0 ?
7651 error = sbuf_finish(sb);
7655 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
7656 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP,
7657 NULL, 0, sysctl_kmaps, "A",
7658 "Dump kernel address layout");