2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
108 #include <sys/param.h>
110 #include <sys/systm.h>
111 #include <sys/kernel.h>
113 #include <sys/lock.h>
114 #include <sys/malloc.h>
115 #include <sys/mman.h>
116 #include <sys/msgbuf.h>
117 #include <sys/mutex.h>
118 #include <sys/proc.h>
119 #include <sys/rwlock.h>
121 #include <sys/vmem.h>
122 #include <sys/vmmeter.h>
123 #include <sys/sched.h>
124 #include <sys/sysctl.h>
125 #include <sys/_unrhdr.h>
129 #include <vm/vm_param.h>
130 #include <vm/vm_kern.h>
131 #include <vm/vm_page.h>
132 #include <vm/vm_map.h>
133 #include <vm/vm_object.h>
134 #include <vm/vm_extern.h>
135 #include <vm/vm_pageout.h>
136 #include <vm/vm_pager.h>
137 #include <vm/vm_radix.h>
138 #include <vm/vm_reserv.h>
141 #include <machine/machdep.h>
142 #include <machine/md_var.h>
143 #include <machine/pcb.h>
145 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
146 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
147 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
148 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
150 #define NUL0E L0_ENTRIES
151 #define NUL1E (NUL0E * NL1PG)
152 #define NUL2E (NUL1E * NL2PG)
154 #if !defined(DIAGNOSTIC)
155 #ifdef __GNUC_GNU_INLINE__
156 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
158 #define PMAP_INLINE extern inline
165 * These are configured by the mair_el1 register. This is set up in locore.S
167 #define DEVICE_MEMORY 0
168 #define UNCACHED_MEMORY 1
169 #define CACHED_MEMORY 2
173 #define PV_STAT(x) do { x ; } while (0)
175 #define PV_STAT(x) do { } while (0)
178 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
180 #define NPV_LIST_LOCKS MAXCPU
182 #define PHYS_TO_PV_LIST_LOCK(pa) \
183 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
185 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
186 struct rwlock **_lockp = (lockp); \
187 struct rwlock *_new_lock; \
189 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
190 if (_new_lock != *_lockp) { \
191 if (*_lockp != NULL) \
192 rw_wunlock(*_lockp); \
193 *_lockp = _new_lock; \
198 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
199 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
201 #define RELEASE_PV_LIST_LOCK(lockp) do { \
202 struct rwlock **_lockp = (lockp); \
204 if (*_lockp != NULL) { \
205 rw_wunlock(*_lockp); \
210 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
211 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
213 struct pmap kernel_pmap_store;
215 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
216 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
217 vm_offset_t kernel_vm_end = 0;
219 struct msgbuf *msgbufp = NULL;
221 static struct rwlock_padalign pvh_global_lock;
223 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
224 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
225 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
227 /* This code assumes all L1 DMAP entries will be used */
228 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
229 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
231 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
232 extern pt_entry_t pagetable_dmap[];
235 * Data for the pv entry allocation mechanism
237 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
238 static struct mtx pv_chunks_mutex;
239 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
241 static void free_pv_chunk(struct pv_chunk *pc);
242 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
243 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
244 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
245 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
246 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
248 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
249 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
250 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
251 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
252 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
253 vm_page_t m, struct rwlock **lockp);
255 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
256 struct rwlock **lockp);
258 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
259 struct spglist *free);
260 static int pmap_unuse_l3(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
263 * These load the old table data and store the new value.
264 * They need to be atomic as the System MMU may write to the table at
265 * the same time as the CPU.
267 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
268 #define pmap_set(table, mask) atomic_set_64(table, mask)
269 #define pmap_load_clear(table) atomic_swap_64(table, 0)
270 #define pmap_load(table) (*table)
272 /********************/
273 /* Inline functions */
274 /********************/
277 pagecopy(void *s, void *d)
280 memcpy(d, s, PAGE_SIZE);
283 #define pmap_l0_index(va) (((va) >> L0_SHIFT) & L0_ADDR_MASK)
284 #define pmap_l1_index(va) (((va) >> L1_SHIFT) & Ln_ADDR_MASK)
285 #define pmap_l2_index(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK)
286 #define pmap_l3_index(va) (((va) >> L3_SHIFT) & Ln_ADDR_MASK)
288 static __inline pd_entry_t *
289 pmap_l0(pmap_t pmap, vm_offset_t va)
292 return (&pmap->pm_l0[pmap_l0_index(va)]);
295 static __inline pd_entry_t *
296 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
300 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
301 return (&l1[pmap_l1_index(va)]);
304 static __inline pd_entry_t *
305 pmap_l1(pmap_t pmap, vm_offset_t va)
309 l0 = pmap_l0(pmap, va);
310 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
313 return (pmap_l0_to_l1(l0, va));
316 static __inline pd_entry_t *
317 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
321 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
322 return (&l2[pmap_l2_index(va)]);
325 static __inline pd_entry_t *
326 pmap_l2(pmap_t pmap, vm_offset_t va)
330 l1 = pmap_l1(pmap, va);
331 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
334 return (pmap_l1_to_l2(l1, va));
337 static __inline pt_entry_t *
338 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
342 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
343 return (&l3[pmap_l3_index(va)]);
347 * Returns the lowest valid pde for a given virtual address.
348 * The next level may or may not point to a valid page or block.
350 static __inline pd_entry_t *
351 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
353 pd_entry_t *l0, *l1, *l2, desc;
355 l0 = pmap_l0(pmap, va);
356 desc = pmap_load(l0) & ATTR_DESCR_MASK;
357 if (desc != L0_TABLE) {
362 l1 = pmap_l0_to_l1(l0, va);
363 desc = pmap_load(l1) & ATTR_DESCR_MASK;
364 if (desc != L1_TABLE) {
369 l2 = pmap_l1_to_l2(l1, va);
370 desc = pmap_load(l2) & ATTR_DESCR_MASK;
371 if (desc != L2_TABLE) {
381 * Returns the lowest valid pte block or table entry for a given virtual
382 * address. If there are no valid entries return NULL and set the level to
383 * the first invalid level.
385 static __inline pt_entry_t *
386 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
388 pd_entry_t *l1, *l2, desc;
391 l1 = pmap_l1(pmap, va);
396 desc = pmap_load(l1) & ATTR_DESCR_MASK;
397 if (desc == L1_BLOCK) {
402 if (desc != L1_TABLE) {
407 l2 = pmap_l1_to_l2(l1, va);
408 desc = pmap_load(l2) & ATTR_DESCR_MASK;
409 if (desc == L2_BLOCK) {
414 if (desc != L2_TABLE) {
420 l3 = pmap_l2_to_l3(l2, va);
421 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
428 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
429 pd_entry_t **l2, pt_entry_t **l3)
431 pd_entry_t *l0p, *l1p, *l2p;
433 if (pmap->pm_l0 == NULL)
436 l0p = pmap_l0(pmap, va);
439 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
442 l1p = pmap_l0_to_l1(l0p, va);
445 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
451 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
454 l2p = pmap_l1_to_l2(l1p, va);
457 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
462 *l3 = pmap_l2_to_l3(l2p, va);
468 pmap_is_current(pmap_t pmap)
471 return ((pmap == pmap_kernel()) ||
472 (pmap == curthread->td_proc->p_vmspace->vm_map.pmap));
476 pmap_l3_valid(pt_entry_t l3)
479 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
483 pmap_l3_valid_cacheable(pt_entry_t l3)
486 return (((l3 & ATTR_DESCR_MASK) == L3_PAGE) &&
487 ((l3 & ATTR_IDX_MASK) == ATTR_IDX(CACHED_MEMORY)));
490 #define PTE_SYNC(pte) cpu_dcache_wb_range((vm_offset_t)pte, sizeof(*pte))
493 * Checks if the page is dirty. We currently lack proper tracking of this on
494 * arm64 so for now assume is a page mapped as rw was accessed it is.
497 pmap_page_dirty(pt_entry_t pte)
500 return ((pte & (ATTR_AF | ATTR_AP_RW_BIT)) ==
501 (ATTR_AF | ATTR_AP(ATTR_AP_RW)));
505 pmap_resident_count_inc(pmap_t pmap, int count)
508 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
509 pmap->pm_stats.resident_count += count;
513 pmap_resident_count_dec(pmap_t pmap, int count)
516 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
517 KASSERT(pmap->pm_stats.resident_count >= count,
518 ("pmap %p resident count underflow %ld %d", pmap,
519 pmap->pm_stats.resident_count, count));
520 pmap->pm_stats.resident_count -= count;
524 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
530 l1 = (pd_entry_t *)l1pt;
531 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
533 /* Check locore has used a table L1 map */
534 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
535 ("Invalid bootstrap L1 table"));
536 /* Find the address of the L2 table */
537 l2 = (pt_entry_t *)init_pt_va;
538 *l2_slot = pmap_l2_index(va);
544 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
546 u_int l1_slot, l2_slot;
549 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
551 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
555 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa, vm_paddr_t max_pa)
561 pa = dmap_phys_base = min_pa & ~L1_OFFSET;
562 va = DMAP_MIN_ADDRESS;
563 for (; va < DMAP_MAX_ADDRESS && pa < max_pa;
564 pa += L1_SIZE, va += L1_SIZE, l1_slot++) {
565 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
567 pmap_load_store(&pagetable_dmap[l1_slot],
568 (pa & ~L1_OFFSET) | ATTR_DEFAULT |
569 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
572 /* Set the upper limit of the DMAP region */
576 cpu_dcache_wb_range((vm_offset_t)pagetable_dmap,
577 PAGE_SIZE * DMAP_TABLES);
582 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
589 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
591 l1 = (pd_entry_t *)l1pt;
592 l1_slot = pmap_l1_index(va);
595 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
596 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
598 pa = pmap_early_vtophys(l1pt, l2pt);
599 pmap_load_store(&l1[l1_slot],
600 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
604 /* Clean the L2 page table */
605 memset((void *)l2_start, 0, l2pt - l2_start);
606 cpu_dcache_wb_range(l2_start, l2pt - l2_start);
608 /* Flush the l1 table to ram */
609 cpu_dcache_wb_range((vm_offset_t)l1, PAGE_SIZE);
615 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
617 vm_offset_t l2pt, l3pt;
622 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
624 l2 = pmap_l2(kernel_pmap, va);
625 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
626 l2pt = (vm_offset_t)l2;
627 l2_slot = pmap_l2_index(va);
630 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
631 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
633 pa = pmap_early_vtophys(l1pt, l3pt);
634 pmap_load_store(&l2[l2_slot],
635 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
639 /* Clean the L2 page table */
640 memset((void *)l3_start, 0, l3pt - l3_start);
641 cpu_dcache_wb_range(l3_start, l3pt - l3_start);
643 cpu_dcache_wb_range((vm_offset_t)l2, PAGE_SIZE);
649 * Bootstrap the system enough to run with virtual memory.
652 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
655 u_int l1_slot, l2_slot, avail_slot, map_slot, used_map_slot;
658 vm_offset_t va, freemempos;
659 vm_offset_t dpcpu, msgbufpv;
660 vm_paddr_t pa, max_pa, min_pa;
663 kern_delta = KERNBASE - kernstart;
666 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
667 printf("%lx\n", l1pt);
668 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
670 /* Set this early so we can use the pagetable walking functions */
671 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
672 PMAP_LOCK_INIT(kernel_pmap);
675 * Initialize the global pv list lock.
677 rw_init(&pvh_global_lock, "pmap pv global");
679 /* Assume the address we were loaded to is a valid physical address */
680 min_pa = max_pa = KERNBASE - kern_delta;
683 * Find the minimum physical address. physmap is sorted,
684 * but may contain empty ranges.
686 for (i = 0; i < (physmap_idx * 2); i += 2) {
687 if (physmap[i] == physmap[i + 1])
689 if (physmap[i] <= min_pa)
691 if (physmap[i + 1] > max_pa)
692 max_pa = physmap[i + 1];
695 /* Create a direct map region early so we can use it for pa -> va */
696 pmap_bootstrap_dmap(l1pt, min_pa, max_pa);
699 pa = KERNBASE - kern_delta;
702 * Start to initialise phys_avail by copying from physmap
703 * up to the physical address KERNBASE points at.
705 map_slot = avail_slot = 0;
706 for (; map_slot < (physmap_idx * 2) &&
707 avail_slot < (PHYS_AVAIL_SIZE - 2); map_slot += 2) {
708 if (physmap[map_slot] == physmap[map_slot + 1])
711 if (physmap[map_slot] <= pa &&
712 physmap[map_slot + 1] > pa)
715 phys_avail[avail_slot] = physmap[map_slot];
716 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
717 physmem += (phys_avail[avail_slot + 1] -
718 phys_avail[avail_slot]) >> PAGE_SHIFT;
722 /* Add the memory before the kernel */
723 if (physmap[avail_slot] < pa && avail_slot < (PHYS_AVAIL_SIZE - 2)) {
724 phys_avail[avail_slot] = physmap[map_slot];
725 phys_avail[avail_slot + 1] = pa;
726 physmem += (phys_avail[avail_slot + 1] -
727 phys_avail[avail_slot]) >> PAGE_SHIFT;
730 used_map_slot = map_slot;
733 * Read the page table to find out what is already mapped.
734 * This assumes we have mapped a block of memory from KERNBASE
735 * using a single L1 entry.
737 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
739 /* Sanity check the index, KERNBASE should be the first VA */
740 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
742 /* Find how many pages we have mapped */
743 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
744 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
747 /* Check locore used L2 blocks */
748 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
749 ("Invalid bootstrap L2 table"));
750 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
751 ("Incorrect PA in L2 table"));
757 va = roundup2(va, L1_SIZE);
759 freemempos = KERNBASE + kernlen;
760 freemempos = roundup2(freemempos, PAGE_SIZE);
761 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
762 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
763 /* And the l3 tables for the early devmap */
764 freemempos = pmap_bootstrap_l3(l1pt,
765 VM_MAX_KERNEL_ADDRESS - L2_SIZE, freemempos);
769 #define alloc_pages(var, np) \
770 (var) = freemempos; \
771 freemempos += (np * PAGE_SIZE); \
772 memset((char *)(var), 0, ((np) * PAGE_SIZE));
774 /* Allocate dynamic per-cpu area. */
775 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
776 dpcpu_init((void *)dpcpu, 0);
778 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
779 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
780 msgbufp = (void *)msgbufpv;
782 virtual_avail = roundup2(freemempos, L1_SIZE);
783 virtual_end = VM_MAX_KERNEL_ADDRESS - L2_SIZE;
784 kernel_vm_end = virtual_avail;
786 pa = pmap_early_vtophys(l1pt, freemempos);
788 /* Finish initialising physmap */
789 map_slot = used_map_slot;
790 for (; avail_slot < (PHYS_AVAIL_SIZE - 2) &&
791 map_slot < (physmap_idx * 2); map_slot += 2) {
792 if (physmap[map_slot] == physmap[map_slot + 1])
795 /* Have we used the current range? */
796 if (physmap[map_slot + 1] <= pa)
799 /* Do we need to split the entry? */
800 if (physmap[map_slot] < pa) {
801 phys_avail[avail_slot] = pa;
802 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
804 phys_avail[avail_slot] = physmap[map_slot];
805 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
807 physmem += (phys_avail[avail_slot + 1] -
808 phys_avail[avail_slot]) >> PAGE_SHIFT;
812 phys_avail[avail_slot] = 0;
813 phys_avail[avail_slot + 1] = 0;
816 * Maxmem isn't the "maximum memory", it's one larger than the
817 * highest page of the physical address space. It should be
818 * called something like "Maxphyspage".
820 Maxmem = atop(phys_avail[avail_slot - 1]);
826 * Initialize a vm_page's machine-dependent fields.
829 pmap_page_init(vm_page_t m)
832 TAILQ_INIT(&m->md.pv_list);
833 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
837 * Initialize the pmap module.
838 * Called by vm_init, to initialize any structures that the pmap
839 * system needs to map virtual memory.
847 * Initialize the pv chunk list mutex.
849 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
852 * Initialize the pool of pv list locks.
854 for (i = 0; i < NPV_LIST_LOCKS; i++)
855 rw_init(&pv_list_locks[i], "pmap pv list");
859 * Invalidate a single TLB entry.
862 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
868 "tlbi vaae1is, %0 \n"
871 : : "r"(va >> PAGE_SHIFT));
876 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
882 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
884 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
893 pmap_invalidate_all(pmap_t pmap)
906 * Routine: pmap_extract
908 * Extract the physical page address associated
909 * with the given map/virtual_address pair.
912 pmap_extract(pmap_t pmap, vm_offset_t va)
914 pt_entry_t *pte, tpte;
921 * Find the block or page map for this virtual address. pmap_pte
922 * will return either a valid block/page entry, or NULL.
924 pte = pmap_pte(pmap, va, &lvl);
926 tpte = pmap_load(pte);
927 pa = tpte & ~ATTR_MASK;
930 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
931 ("pmap_extract: Invalid L1 pte found: %lx",
932 tpte & ATTR_DESCR_MASK));
933 pa |= (va & L1_OFFSET);
936 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
937 ("pmap_extract: Invalid L2 pte found: %lx",
938 tpte & ATTR_DESCR_MASK));
939 pa |= (va & L2_OFFSET);
942 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
943 ("pmap_extract: Invalid L3 pte found: %lx",
944 tpte & ATTR_DESCR_MASK));
945 pa |= (va & L3_OFFSET);
954 * Routine: pmap_extract_and_hold
956 * Atomically extract and hold the physical page
957 * with the given pmap and virtual address pair
958 * if that mapping permits the given protection.
961 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
963 pt_entry_t *pte, tpte;
972 pte = pmap_pte(pmap, va, &lvl);
974 tpte = pmap_load(pte);
976 KASSERT(lvl > 0 && lvl <= 3,
977 ("pmap_extract_and_hold: Invalid level %d", lvl));
978 CTASSERT(L1_BLOCK == L2_BLOCK);
979 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
980 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
981 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
982 tpte & ATTR_DESCR_MASK));
983 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
984 ((prot & VM_PROT_WRITE) == 0)) {
985 if (vm_page_pa_tryrelock(pmap, tpte & ~ATTR_MASK, &pa))
987 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
997 pmap_kextract(vm_offset_t va)
999 pt_entry_t *pte, tpte;
1003 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1004 pa = DMAP_TO_PHYS(va);
1007 pte = pmap_pte(kernel_pmap, va, &lvl);
1009 tpte = pmap_load(pte);
1010 pa = tpte & ~ATTR_MASK;
1013 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1014 ("pmap_kextract: Invalid L1 pte found: %lx",
1015 tpte & ATTR_DESCR_MASK));
1016 pa |= (va & L1_OFFSET);
1019 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1020 ("pmap_kextract: Invalid L2 pte found: %lx",
1021 tpte & ATTR_DESCR_MASK));
1022 pa |= (va & L2_OFFSET);
1025 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1026 ("pmap_kextract: Invalid L3 pte found: %lx",
1027 tpte & ATTR_DESCR_MASK));
1028 pa |= (va & L3_OFFSET);
1036 /***************************************************
1037 * Low level mapping routines.....
1038 ***************************************************/
1041 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1048 KASSERT((pa & L3_OFFSET) == 0,
1049 ("pmap_kenter: Invalid physical address"));
1050 KASSERT((sva & L3_OFFSET) == 0,
1051 ("pmap_kenter: Invalid virtual address"));
1052 KASSERT((size & PAGE_MASK) == 0,
1053 ("pmap_kenter: Mapping is not page-sized"));
1057 pde = pmap_pde(kernel_pmap, va, &lvl);
1058 KASSERT(pde != NULL,
1059 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1060 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1062 pte = pmap_l2_to_l3(pde, va);
1063 pmap_load_store(pte, (pa & ~L3_OFFSET) | ATTR_DEFAULT |
1064 ATTR_IDX(mode) | L3_PAGE);
1071 pmap_invalidate_range(kernel_pmap, sva, va);
1075 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1078 pmap_kenter(sva, size, pa, DEVICE_MEMORY);
1082 * Remove a page from the kernel pagetables.
1085 pmap_kremove(vm_offset_t va)
1090 pte = pmap_pte(kernel_pmap, va, &lvl);
1091 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1092 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1094 if (pmap_l3_valid_cacheable(pmap_load(pte)))
1095 cpu_dcache_wb_range(va, L3_SIZE);
1096 pmap_load_clear(pte);
1098 pmap_invalidate_page(kernel_pmap, va);
1102 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1108 KASSERT((sva & L3_OFFSET) == 0,
1109 ("pmap_kremove_device: Invalid virtual address"));
1110 KASSERT((size & PAGE_MASK) == 0,
1111 ("pmap_kremove_device: Mapping is not page-sized"));
1115 pte = pmap_pte(kernel_pmap, va, &lvl);
1116 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1118 ("Invalid device pagetable level: %d != 3", lvl));
1119 pmap_load_clear(pte);
1125 pmap_invalidate_range(kernel_pmap, sva, va);
1129 * Used to map a range of physical addresses into kernel
1130 * virtual address space.
1132 * The value passed in '*virt' is a suggested virtual address for
1133 * the mapping. Architectures which can support a direct-mapped
1134 * physical to virtual region can return the appropriate address
1135 * within that region, leaving '*virt' unchanged. Other
1136 * architectures should map the pages starting at '*virt' and
1137 * update '*virt' with the first usable address after the mapped
1141 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1143 return PHYS_TO_DMAP(start);
1148 * Add a list of wired pages to the kva
1149 * this routine is only used for temporary
1150 * kernel mappings that do not need to have
1151 * page modification or references recorded.
1152 * Note that old mappings are simply written
1153 * over. The page *must* be wired.
1154 * Note: SMP coherent. Uses a ranged shootdown IPI.
1157 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1160 pt_entry_t *pte, pa;
1166 for (i = 0; i < count; i++) {
1167 pde = pmap_pde(kernel_pmap, va, &lvl);
1168 KASSERT(pde != NULL,
1169 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1171 ("pmap_qenter: Invalid level %d", lvl));
1174 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1175 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1176 pte = pmap_l2_to_l3(pde, va);
1177 pmap_load_store(pte, pa);
1182 pmap_invalidate_range(kernel_pmap, sva, va);
1186 * This routine tears out page mappings from the
1187 * kernel -- it is meant only for temporary mappings.
1190 pmap_qremove(vm_offset_t sva, int count)
1196 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1199 while (count-- > 0) {
1200 pte = pmap_pte(kernel_pmap, va, &lvl);
1202 ("Invalid device pagetable level: %d != 3", lvl));
1204 if (pmap_l3_valid_cacheable(pmap_load(pte)))
1205 cpu_dcache_wb_range(va, L3_SIZE);
1206 pmap_load_clear(pte);
1212 pmap_invalidate_range(kernel_pmap, sva, va);
1215 /***************************************************
1216 * Page table page management routines.....
1217 ***************************************************/
1218 static __inline void
1219 pmap_free_zero_pages(struct spglist *free)
1223 while ((m = SLIST_FIRST(free)) != NULL) {
1224 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1225 /* Preserve the page's PG_ZERO setting. */
1226 vm_page_free_toq(m);
1231 * Schedule the specified unused page table page to be freed. Specifically,
1232 * add the page to the specified list of pages that will be released to the
1233 * physical memory manager after the TLB has been updated.
1235 static __inline void
1236 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1237 boolean_t set_PG_ZERO)
1241 m->flags |= PG_ZERO;
1243 m->flags &= ~PG_ZERO;
1244 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1248 * Decrements a page table page's wire count, which is used to record the
1249 * number of valid page table entries within the page. If the wire count
1250 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1251 * page table page was unmapped and FALSE otherwise.
1253 static inline boolean_t
1254 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1258 if (m->wire_count == 0) {
1259 _pmap_unwire_l3(pmap, va, m, free);
1266 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1269 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1271 * unmap the page table page
1273 if (m->pindex >= (NUL2E + NUL1E)) {
1277 l0 = pmap_l0(pmap, va);
1278 pmap_load_clear(l0);
1280 } else if (m->pindex >= NUL2E) {
1284 l1 = pmap_l1(pmap, va);
1285 pmap_load_clear(l1);
1291 l2 = pmap_l2(pmap, va);
1292 pmap_load_clear(l2);
1295 pmap_resident_count_dec(pmap, 1);
1296 if (m->pindex < NUL2E) {
1297 /* We just released an l3, unhold the matching l2 */
1298 pd_entry_t *l1, tl1;
1301 l1 = pmap_l1(pmap, va);
1302 tl1 = pmap_load(l1);
1303 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1304 pmap_unwire_l3(pmap, va, l2pg, free);
1305 } else if (m->pindex < (NUL2E + NUL1E)) {
1306 /* We just released an l2, unhold the matching l1 */
1307 pd_entry_t *l0, tl0;
1310 l0 = pmap_l0(pmap, va);
1311 tl0 = pmap_load(l0);
1312 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1313 pmap_unwire_l3(pmap, va, l1pg, free);
1315 pmap_invalidate_page(pmap, va);
1318 * This is a release store so that the ordinary store unmapping
1319 * the page table page is globally performed before TLB shoot-
1322 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
1325 * Put page on a list so that it is released after
1326 * *ALL* TLB shootdown is done
1328 pmap_add_delayed_free_list(m, free, TRUE);
1332 * After removing an l3 entry, this routine is used to
1333 * conditionally free the page, and manage the hold/wire counts.
1336 pmap_unuse_l3(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1337 struct spglist *free)
1341 if (va >= VM_MAXUSER_ADDRESS)
1343 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1344 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1345 return (pmap_unwire_l3(pmap, va, mpte, free));
1349 pmap_pinit0(pmap_t pmap)
1352 PMAP_LOCK_INIT(pmap);
1353 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1354 pmap->pm_l0 = kernel_pmap->pm_l0;
1358 pmap_pinit(pmap_t pmap)
1364 * allocate the l0 page
1366 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1367 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1370 l0phys = VM_PAGE_TO_PHYS(l0pt);
1371 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1373 if ((l0pt->flags & PG_ZERO) == 0)
1374 pagezero(pmap->pm_l0);
1376 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1382 * This routine is called if the desired page table page does not exist.
1384 * If page table page allocation fails, this routine may sleep before
1385 * returning NULL. It sleeps only if a lock pointer was given.
1387 * Note: If a page allocation fails at page table level two or three,
1388 * one or two pages may be held during the wait, only to be released
1389 * afterwards. This conservative approach is easily argued to avoid
1393 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1395 vm_page_t m, l1pg, l2pg;
1397 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1400 * Allocate a page table page.
1402 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1403 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1404 if (lockp != NULL) {
1405 RELEASE_PV_LIST_LOCK(lockp);
1407 rw_runlock(&pvh_global_lock);
1409 rw_rlock(&pvh_global_lock);
1414 * Indicate the need to retry. While waiting, the page table
1415 * page may have been allocated.
1419 if ((m->flags & PG_ZERO) == 0)
1423 * Map the pagetable page into the process address space, if
1424 * it isn't already there.
1427 if (ptepindex >= (NUL2E + NUL1E)) {
1429 vm_pindex_t l0index;
1431 l0index = ptepindex - (NUL2E + NUL1E);
1432 l0 = &pmap->pm_l0[l0index];
1433 pmap_load_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1435 } else if (ptepindex >= NUL2E) {
1436 vm_pindex_t l0index, l1index;
1437 pd_entry_t *l0, *l1;
1440 l1index = ptepindex - NUL2E;
1441 l0index = l1index >> L0_ENTRIES_SHIFT;
1443 l0 = &pmap->pm_l0[l0index];
1444 tl0 = pmap_load(l0);
1446 /* recurse for allocating page dir */
1447 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1450 /* XXX: release mem barrier? */
1451 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1452 vm_page_free_zero(m);
1456 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1460 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1461 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1462 pmap_load_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1465 vm_pindex_t l0index, l1index;
1466 pd_entry_t *l0, *l1, *l2;
1467 pd_entry_t tl0, tl1;
1469 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1470 l0index = l1index >> L0_ENTRIES_SHIFT;
1472 l0 = &pmap->pm_l0[l0index];
1473 tl0 = pmap_load(l0);
1475 /* recurse for allocating page dir */
1476 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1479 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1480 vm_page_free_zero(m);
1483 tl0 = pmap_load(l0);
1484 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1485 l1 = &l1[l1index & Ln_ADDR_MASK];
1487 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1488 l1 = &l1[l1index & Ln_ADDR_MASK];
1489 tl1 = pmap_load(l1);
1491 /* recurse for allocating page dir */
1492 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1495 /* XXX: release mem barrier? */
1496 atomic_subtract_int(
1497 &vm_cnt.v_wire_count, 1);
1498 vm_page_free_zero(m);
1502 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1507 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1508 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1509 pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1513 pmap_resident_count_inc(pmap, 1);
1519 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1521 vm_pindex_t ptepindex;
1522 pd_entry_t *pde, tpde;
1527 * Calculate pagetable page index
1529 ptepindex = pmap_l2_pindex(va);
1532 * Get the page directory entry
1534 pde = pmap_pde(pmap, va, &lvl);
1537 * If the page table page is mapped, we just increment the hold count,
1538 * and activate it. If we get a level 2 pde it will point to a level 3
1542 tpde = pmap_load(pde);
1544 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1551 * Here if the pte page isn't mapped, or if it has been deallocated.
1553 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1554 if (m == NULL && lockp != NULL)
1561 /***************************************************
1562 * Pmap allocation/deallocation routines.
1563 ***************************************************/
1566 * Release any resources held by the given physical map.
1567 * Called when a pmap initialized by pmap_pinit is being released.
1568 * Should only be called if the map contains no valid mappings.
1571 pmap_release(pmap_t pmap)
1575 KASSERT(pmap->pm_stats.resident_count == 0,
1576 ("pmap_release: pmap resident count %ld != 0",
1577 pmap->pm_stats.resident_count));
1579 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1582 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1583 vm_page_free_zero(m);
1588 kvm_size(SYSCTL_HANDLER_ARGS)
1590 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1592 return sysctl_handle_long(oidp, &ksize, 0, req);
1594 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1595 0, 0, kvm_size, "LU", "Size of KVM");
1598 kvm_free(SYSCTL_HANDLER_ARGS)
1600 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1602 return sysctl_handle_long(oidp, &kfree, 0, req);
1604 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1605 0, 0, kvm_free, "LU", "Amount of KVM free");
1609 * grow the number of kernel page table entries, if needed
1612 pmap_growkernel(vm_offset_t addr)
1616 pd_entry_t *l0, *l1, *l2;
1618 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1620 addr = roundup2(addr, L2_SIZE);
1621 if (addr - 1 >= kernel_map->max_offset)
1622 addr = kernel_map->max_offset;
1623 while (kernel_vm_end < addr) {
1624 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1625 KASSERT(pmap_load(l0) != 0,
1626 ("pmap_growkernel: No level 0 kernel entry"));
1628 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1629 if (pmap_load(l1) == 0) {
1630 /* We need a new PDP entry */
1631 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1632 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1633 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1635 panic("pmap_growkernel: no memory to grow kernel");
1636 if ((nkpg->flags & PG_ZERO) == 0)
1637 pmap_zero_page(nkpg);
1638 paddr = VM_PAGE_TO_PHYS(nkpg);
1639 pmap_load_store(l1, paddr | L1_TABLE);
1641 continue; /* try again */
1643 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1644 if ((pmap_load(l2) & ATTR_AF) != 0) {
1645 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1646 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1647 kernel_vm_end = kernel_map->max_offset;
1653 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1654 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1657 panic("pmap_growkernel: no memory to grow kernel");
1658 if ((nkpg->flags & PG_ZERO) == 0)
1659 pmap_zero_page(nkpg);
1660 paddr = VM_PAGE_TO_PHYS(nkpg);
1661 pmap_load_store(l2, paddr | L2_TABLE);
1663 pmap_invalidate_page(kernel_pmap, kernel_vm_end);
1665 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1666 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1667 kernel_vm_end = kernel_map->max_offset;
1674 /***************************************************
1675 * page management routines.
1676 ***************************************************/
1678 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1679 CTASSERT(_NPCM == 3);
1680 CTASSERT(_NPCPV == 168);
1682 static __inline struct pv_chunk *
1683 pv_to_chunk(pv_entry_t pv)
1686 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1689 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1691 #define PC_FREE0 0xfffffffffffffffful
1692 #define PC_FREE1 0xfffffffffffffffful
1693 #define PC_FREE2 0x000000fffffffffful
1695 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1699 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1701 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1702 "Current number of pv entry chunks");
1703 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1704 "Current number of pv entry chunks allocated");
1705 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1706 "Current number of pv entry chunks frees");
1707 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1708 "Number of times tried to get a chunk page but failed.");
1710 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1711 static int pv_entry_spare;
1713 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1714 "Current number of pv entry frees");
1715 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1716 "Current number of pv entry allocs");
1717 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1718 "Current number of pv entries");
1719 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1720 "Current number of spare pv entries");
1725 * We are in a serious low memory condition. Resort to
1726 * drastic measures to free some pages so we can allocate
1727 * another pv entry chunk.
1729 * Returns NULL if PV entries were reclaimed from the specified pmap.
1731 * We do not, however, unmap 2mpages because subsequent accesses will
1732 * allocate per-page pv entries until repromotion occurs, thereby
1733 * exacerbating the shortage of free pv entries.
1736 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1739 panic("ARM64TODO: reclaim_pv_chunk");
1743 * free the pv_entry back to the free list
1746 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1748 struct pv_chunk *pc;
1749 int idx, field, bit;
1751 rw_assert(&pvh_global_lock, RA_LOCKED);
1752 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1753 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
1754 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
1755 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
1756 pc = pv_to_chunk(pv);
1757 idx = pv - &pc->pc_pventry[0];
1760 pc->pc_map[field] |= 1ul << bit;
1761 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
1762 pc->pc_map[2] != PC_FREE2) {
1763 /* 98% of the time, pc is already at the head of the list. */
1764 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
1765 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1766 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1770 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1775 free_pv_chunk(struct pv_chunk *pc)
1779 mtx_lock(&pv_chunks_mutex);
1780 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1781 mtx_unlock(&pv_chunks_mutex);
1782 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1783 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1784 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1785 /* entire chunk is free, return it */
1786 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1787 dump_drop_page(m->phys_addr);
1788 vm_page_unwire(m, PQ_NONE);
1793 * Returns a new PV entry, allocating a new PV chunk from the system when
1794 * needed. If this PV chunk allocation fails and a PV list lock pointer was
1795 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
1798 * The given PV list lock may be released.
1801 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
1805 struct pv_chunk *pc;
1808 rw_assert(&pvh_global_lock, RA_LOCKED);
1809 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1810 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
1812 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1814 for (field = 0; field < _NPCM; field++) {
1815 if (pc->pc_map[field]) {
1816 bit = ffsl(pc->pc_map[field]) - 1;
1820 if (field < _NPCM) {
1821 pv = &pc->pc_pventry[field * 64 + bit];
1822 pc->pc_map[field] &= ~(1ul << bit);
1823 /* If this was the last item, move it to tail */
1824 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
1825 pc->pc_map[2] == 0) {
1826 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1827 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
1830 PV_STAT(atomic_add_long(&pv_entry_count, 1));
1831 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
1835 /* No free items, allocate another chunk */
1836 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1839 if (lockp == NULL) {
1840 PV_STAT(pc_chunk_tryfail++);
1843 m = reclaim_pv_chunk(pmap, lockp);
1847 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
1848 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
1849 dump_add_page(m->phys_addr);
1850 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
1852 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
1853 pc->pc_map[1] = PC_FREE1;
1854 pc->pc_map[2] = PC_FREE2;
1855 mtx_lock(&pv_chunks_mutex);
1856 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
1857 mtx_unlock(&pv_chunks_mutex);
1858 pv = &pc->pc_pventry[0];
1859 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1860 PV_STAT(atomic_add_long(&pv_entry_count, 1));
1861 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
1866 * First find and then remove the pv entry for the specified pmap and virtual
1867 * address from the specified pv list. Returns the pv entry if found and NULL
1868 * otherwise. This operation can be performed on pv lists for either 4KB or
1869 * 2MB page mappings.
1871 static __inline pv_entry_t
1872 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1876 rw_assert(&pvh_global_lock, RA_LOCKED);
1877 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
1878 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
1879 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
1888 * First find and then destroy the pv entry for the specified pmap and virtual
1889 * address. This operation can be performed on pv lists for either 4KB or 2MB
1893 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1897 pv = pmap_pvh_remove(pvh, pmap, va);
1898 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
1899 free_pv_entry(pmap, pv);
1903 * Conditionally create the PV entry for a 4KB page mapping if the required
1904 * memory can be allocated without resorting to reclamation.
1907 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
1908 struct rwlock **lockp)
1912 rw_assert(&pvh_global_lock, RA_LOCKED);
1913 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1914 /* Pass NULL instead of the lock pointer to disable reclamation. */
1915 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
1917 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1918 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
1926 * pmap_remove_l3: do the things to unmap a page in a process
1929 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
1930 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
1935 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1936 if (pmap_is_current(pmap) && pmap_l3_valid_cacheable(pmap_load(l3)))
1937 cpu_dcache_wb_range(va, L3_SIZE);
1938 old_l3 = pmap_load_clear(l3);
1940 pmap_invalidate_page(pmap, va);
1941 if (old_l3 & ATTR_SW_WIRED)
1942 pmap->pm_stats.wired_count -= 1;
1943 pmap_resident_count_dec(pmap, 1);
1944 if (old_l3 & ATTR_SW_MANAGED) {
1945 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
1946 if (pmap_page_dirty(old_l3))
1948 if (old_l3 & ATTR_AF)
1949 vm_page_aflag_set(m, PGA_REFERENCED);
1950 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1951 pmap_pvh_free(&m->md, pmap, va);
1953 return (pmap_unuse_l3(pmap, va, l2e, free));
1957 * Remove the given range of addresses from the specified map.
1959 * It is assumed that the start and end are properly
1960 * rounded to the page size.
1963 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1965 struct rwlock *lock;
1966 vm_offset_t va, va_next;
1967 pd_entry_t *l0, *l1, *l2;
1968 pt_entry_t l3_paddr, *l3;
1969 struct spglist free;
1973 * Perform an unsynchronized read. This is, however, safe.
1975 if (pmap->pm_stats.resident_count == 0)
1981 rw_rlock(&pvh_global_lock);
1985 for (; sva < eva; sva = va_next) {
1987 if (pmap->pm_stats.resident_count == 0)
1990 l0 = pmap_l0(pmap, sva);
1991 if (pmap_load(l0) == 0) {
1992 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
1998 l1 = pmap_l0_to_l1(l0, sva);
1999 if (pmap_load(l1) == 0) {
2000 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2007 * Calculate index for next page table.
2009 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2013 l2 = pmap_l1_to_l2(l1, sva);
2017 l3_paddr = pmap_load(l2);
2020 * Weed out invalid mappings.
2022 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2026 * Limit our scan to either the end of the va represented
2027 * by the current page table page, or to the end of the
2028 * range being removed.
2034 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2037 panic("l3 == NULL");
2038 if (pmap_load(l3) == 0) {
2039 if (va != va_next) {
2040 pmap_invalidate_range(pmap, va, sva);
2047 if (pmap_remove_l3(pmap, l3, sva, l3_paddr, &free,
2054 pmap_invalidate_range(pmap, va, sva);
2059 pmap_invalidate_all(pmap);
2060 rw_runlock(&pvh_global_lock);
2062 pmap_free_zero_pages(&free);
2066 * Routine: pmap_remove_all
2068 * Removes this physical page from
2069 * all physical maps in which it resides.
2070 * Reflects back modify bits to the pager.
2073 * Original versions of this routine were very
2074 * inefficient because they iteratively called
2075 * pmap_remove (slow...)
2079 pmap_remove_all(vm_page_t m)
2083 pd_entry_t *pde, tpde;
2084 pt_entry_t *pte, tpte;
2085 struct spglist free;
2088 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2089 ("pmap_remove_all: page %p is not managed", m));
2091 rw_wlock(&pvh_global_lock);
2092 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2095 pmap_resident_count_dec(pmap, 1);
2097 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2098 KASSERT(pde != NULL,
2099 ("pmap_remove_all: no page directory entry found"));
2101 ("pmap_remove_all: invalid pde level %d", lvl));
2102 tpde = pmap_load(pde);
2104 pte = pmap_l2_to_l3(pde, pv->pv_va);
2105 tpte = pmap_load(pte);
2106 if (pmap_is_current(pmap) &&
2107 pmap_l3_valid_cacheable(tpte))
2108 cpu_dcache_wb_range(pv->pv_va, L3_SIZE);
2109 pmap_load_clear(pte);
2111 pmap_invalidate_page(pmap, pv->pv_va);
2112 if (tpte & ATTR_SW_WIRED)
2113 pmap->pm_stats.wired_count--;
2114 if ((tpte & ATTR_AF) != 0)
2115 vm_page_aflag_set(m, PGA_REFERENCED);
2118 * Update the vm_page_t clean and reference bits.
2120 if (pmap_page_dirty(tpte))
2122 pmap_unuse_l3(pmap, pv->pv_va, tpde, &free);
2123 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2125 free_pv_entry(pmap, pv);
2128 vm_page_aflag_clear(m, PGA_WRITEABLE);
2129 rw_wunlock(&pvh_global_lock);
2130 pmap_free_zero_pages(&free);
2134 * Set the physical protection on the
2135 * specified range of this map as requested.
2138 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2140 vm_offset_t va, va_next;
2141 pd_entry_t *l0, *l1, *l2;
2142 pt_entry_t *l3p, l3;
2144 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2145 pmap_remove(pmap, sva, eva);
2149 if ((prot & VM_PROT_WRITE) == VM_PROT_WRITE)
2153 for (; sva < eva; sva = va_next) {
2155 l0 = pmap_l0(pmap, sva);
2156 if (pmap_load(l0) == 0) {
2157 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2163 l1 = pmap_l0_to_l1(l0, sva);
2164 if (pmap_load(l1) == 0) {
2165 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2171 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2175 l2 = pmap_l1_to_l2(l1, sva);
2176 if (l2 == NULL || (pmap_load(l2) & ATTR_DESCR_MASK) != L2_TABLE)
2183 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2185 l3 = pmap_load(l3p);
2186 if (pmap_l3_valid(l3)) {
2187 pmap_set(l3p, ATTR_AP(ATTR_AP_RO));
2189 /* XXX: Use pmap_invalidate_range */
2190 pmap_invalidate_page(pmap, va);
2196 /* TODO: Only invalidate entries we are touching */
2197 pmap_invalidate_all(pmap);
2201 * Insert the given physical page (p) at
2202 * the specified virtual address (v) in the
2203 * target physical map with the protection requested.
2205 * If specified, the page will be wired down, meaning
2206 * that the related pte can not be reclaimed.
2208 * NB: This is the only routine which MAY NOT lazy-evaluate
2209 * or lose information. That is, this routine must actually
2210 * insert this page into the given map NOW.
2213 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2214 u_int flags, int8_t psind __unused)
2216 struct rwlock *lock;
2218 pt_entry_t new_l3, orig_l3;
2221 vm_paddr_t opa, pa, l1_pa, l2_pa, l3_pa;
2222 vm_page_t mpte, om, l1_m, l2_m, l3_m;
2226 va = trunc_page(va);
2227 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2228 VM_OBJECT_ASSERT_LOCKED(m->object);
2229 pa = VM_PAGE_TO_PHYS(m);
2230 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
2232 if ((prot & VM_PROT_WRITE) == 0)
2233 new_l3 |= ATTR_AP(ATTR_AP_RO);
2234 if ((flags & PMAP_ENTER_WIRED) != 0)
2235 new_l3 |= ATTR_SW_WIRED;
2236 if ((va >> 63) == 0)
2237 new_l3 |= ATTR_AP(ATTR_AP_USER);
2239 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
2244 rw_rlock(&pvh_global_lock);
2247 if (va < VM_MAXUSER_ADDRESS) {
2248 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
2249 mpte = pmap_alloc_l3(pmap, va, nosleep ? NULL : &lock);
2250 if (mpte == NULL && nosleep) {
2251 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
2254 rw_runlock(&pvh_global_lock);
2256 return (KERN_RESOURCE_SHORTAGE);
2258 pde = pmap_pde(pmap, va, &lvl);
2259 KASSERT(pde != NULL,
2260 ("pmap_enter: Invalid page entry, va: 0x%lx", va));
2262 ("pmap_enter: Invalid level %d", lvl));
2264 l3 = pmap_l2_to_l3(pde, va);
2266 pde = pmap_pde(pmap, va, &lvl);
2268 * If we get a level 2 pde it must point to a level 3 entry
2269 * otherwise we will need to create the intermediate tables
2275 /* Get the l0 pde to update */
2276 pde = pmap_l0(pmap, va);
2277 KASSERT(pde != NULL, ("..."));
2279 l1_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2280 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2283 panic("pmap_enter: l1 pte_m == NULL");
2284 if ((l1_m->flags & PG_ZERO) == 0)
2285 pmap_zero_page(l1_m);
2287 l1_pa = VM_PAGE_TO_PHYS(l1_m);
2288 pmap_load_store(pde, l1_pa | L0_TABLE);
2292 /* Get the l1 pde to update */
2293 pde = pmap_l1_to_l2(pde, va);
2294 KASSERT(pde != NULL, ("..."));
2296 l2_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2297 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2300 panic("pmap_enter: l2 pte_m == NULL");
2301 if ((l2_m->flags & PG_ZERO) == 0)
2302 pmap_zero_page(l2_m);
2304 l2_pa = VM_PAGE_TO_PHYS(l2_m);
2305 pmap_load_store(pde, l2_pa | L1_TABLE);
2309 /* Get the l2 pde to update */
2310 pde = pmap_l1_to_l2(pde, va);
2312 l3_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2313 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2316 panic("pmap_enter: l3 pte_m == NULL");
2317 if ((l3_m->flags & PG_ZERO) == 0)
2318 pmap_zero_page(l3_m);
2320 l3_pa = VM_PAGE_TO_PHYS(l3_m);
2321 pmap_load_store(pde, l3_pa | L2_TABLE);
2326 l3 = pmap_l2_to_l3(pde, va);
2327 pmap_invalidate_page(pmap, va);
2331 orig_l3 = pmap_load(l3);
2332 opa = orig_l3 & ~ATTR_MASK;
2335 * Is the specified virtual address already mapped?
2337 if (pmap_l3_valid(orig_l3)) {
2339 * Wiring change, just update stats. We don't worry about
2340 * wiring PT pages as they remain resident as long as there
2341 * are valid mappings in them. Hence, if a user page is wired,
2342 * the PT page will be also.
2344 if ((flags & PMAP_ENTER_WIRED) != 0 &&
2345 (orig_l3 & ATTR_SW_WIRED) == 0)
2346 pmap->pm_stats.wired_count++;
2347 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
2348 (orig_l3 & ATTR_SW_WIRED) != 0)
2349 pmap->pm_stats.wired_count--;
2352 * Remove the extra PT page reference.
2356 KASSERT(mpte->wire_count > 0,
2357 ("pmap_enter: missing reference to page table page,"
2362 * Has the physical page changed?
2366 * No, might be a protection or wiring change.
2368 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
2369 new_l3 |= ATTR_SW_MANAGED;
2370 if ((new_l3 & ATTR_AP(ATTR_AP_RW)) ==
2371 ATTR_AP(ATTR_AP_RW)) {
2372 vm_page_aflag_set(m, PGA_WRITEABLE);
2378 /* Flush the cache, there might be uncommitted data in it */
2379 if (pmap_is_current(pmap) && pmap_l3_valid_cacheable(orig_l3))
2380 cpu_dcache_wb_range(va, L3_SIZE);
2383 * Increment the counters.
2385 if ((new_l3 & ATTR_SW_WIRED) != 0)
2386 pmap->pm_stats.wired_count++;
2387 pmap_resident_count_inc(pmap, 1);
2390 * Enter on the PV list if part of our managed memory.
2392 if ((m->oflags & VPO_UNMANAGED) == 0) {
2393 new_l3 |= ATTR_SW_MANAGED;
2394 pv = get_pv_entry(pmap, &lock);
2396 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
2397 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2399 if ((new_l3 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
2400 vm_page_aflag_set(m, PGA_WRITEABLE);
2404 * Update the L3 entry.
2408 orig_l3 = pmap_load_store(l3, new_l3);
2410 opa = orig_l3 & ~ATTR_MASK;
2413 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
2414 om = PHYS_TO_VM_PAGE(opa);
2415 if (pmap_page_dirty(orig_l3))
2417 if ((orig_l3 & ATTR_AF) != 0)
2418 vm_page_aflag_set(om, PGA_REFERENCED);
2419 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
2420 pmap_pvh_free(&om->md, pmap, va);
2422 } else if (pmap_page_dirty(orig_l3)) {
2423 if ((orig_l3 & ATTR_SW_MANAGED) != 0)
2427 pmap_load_store(l3, new_l3);
2430 pmap_invalidate_page(pmap, va);
2431 if ((pmap != pmap_kernel()) && (pmap == &curproc->p_vmspace->vm_pmap))
2432 cpu_icache_sync_range(va, PAGE_SIZE);
2436 rw_runlock(&pvh_global_lock);
2438 return (KERN_SUCCESS);
2442 * Maps a sequence of resident pages belonging to the same object.
2443 * The sequence begins with the given page m_start. This page is
2444 * mapped at the given virtual address start. Each subsequent page is
2445 * mapped at a virtual address that is offset from start by the same
2446 * amount as the page is offset from m_start within the object. The
2447 * last page in the sequence is the page with the largest offset from
2448 * m_start that can be mapped at a virtual address less than the given
2449 * virtual address end. Not every virtual page between start and end
2450 * is mapped; only those for which a resident page exists with the
2451 * corresponding offset from m_start are mapped.
2454 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
2455 vm_page_t m_start, vm_prot_t prot)
2457 struct rwlock *lock;
2460 vm_pindex_t diff, psize;
2462 VM_OBJECT_ASSERT_LOCKED(m_start->object);
2464 psize = atop(end - start);
2468 rw_rlock(&pvh_global_lock);
2470 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2471 va = start + ptoa(diff);
2472 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte, &lock);
2473 m = TAILQ_NEXT(m, listq);
2477 rw_runlock(&pvh_global_lock);
2482 * this code makes some *MAJOR* assumptions:
2483 * 1. Current pmap & pmap exists.
2486 * 4. No page table pages.
2487 * but is *MUCH* faster than pmap_enter...
2491 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
2493 struct rwlock *lock;
2496 rw_rlock(&pvh_global_lock);
2498 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
2501 rw_runlock(&pvh_global_lock);
2506 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
2507 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
2509 struct spglist free;
2515 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
2516 (m->oflags & VPO_UNMANAGED) != 0,
2517 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
2518 rw_assert(&pvh_global_lock, RA_LOCKED);
2519 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2521 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
2523 * In the case that a page table page is not
2524 * resident, we are creating it here.
2526 if (va < VM_MAXUSER_ADDRESS) {
2527 vm_pindex_t l2pindex;
2530 * Calculate pagetable page index
2532 l2pindex = pmap_l2_pindex(va);
2533 if (mpte && (mpte->pindex == l2pindex)) {
2539 pde = pmap_pde(pmap, va, &lvl);
2542 * If the page table page is mapped, we just increment
2543 * the hold count, and activate it. Otherwise, we
2544 * attempt to allocate a page table page. If this
2545 * attempt fails, we don't retry. Instead, we give up.
2547 if (lvl == 2 && pmap_load(pde) != 0) {
2549 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
2553 * Pass NULL instead of the PV list lock
2554 * pointer, because we don't intend to sleep.
2556 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
2561 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
2562 l3 = &l3[pmap_l3_index(va)];
2565 pde = pmap_pde(kernel_pmap, va, &lvl);
2566 KASSERT(pde != NULL,
2567 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
2570 ("pmap_enter_quick_locked: Invalid level %d", lvl));
2571 l3 = pmap_l2_to_l3(pde, va);
2574 if (pmap_load(l3) != 0) {
2583 * Enter on the PV list if part of our managed memory.
2585 if ((m->oflags & VPO_UNMANAGED) == 0 &&
2586 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
2589 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
2590 pmap_invalidate_page(pmap, va);
2591 pmap_free_zero_pages(&free);
2599 * Increment counters
2601 pmap_resident_count_inc(pmap, 1);
2603 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
2604 ATTR_AP(ATTR_AP_RW) | L3_PAGE;
2607 * Now validate mapping with RO protection
2609 if ((m->oflags & VPO_UNMANAGED) == 0)
2610 pa |= ATTR_SW_MANAGED;
2611 pmap_load_store(l3, pa);
2613 pmap_invalidate_page(pmap, va);
2618 * This code maps large physical mmap regions into the
2619 * processor address space. Note that some shortcuts
2620 * are taken, but the code works.
2623 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
2624 vm_pindex_t pindex, vm_size_t size)
2627 VM_OBJECT_ASSERT_WLOCKED(object);
2628 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2629 ("pmap_object_init_pt: non-device object"));
2633 * Clear the wired attribute from the mappings for the specified range of
2634 * addresses in the given pmap. Every valid mapping within that range
2635 * must have the wired attribute set. In contrast, invalid mappings
2636 * cannot have the wired attribute set, so they are ignored.
2638 * The wired attribute of the page table entry is not a hardware feature,
2639 * so there is no need to invalidate any TLB entries.
2642 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2644 vm_offset_t va_next;
2645 pd_entry_t *l0, *l1, *l2;
2647 boolean_t pv_lists_locked;
2649 pv_lists_locked = FALSE;
2651 for (; sva < eva; sva = va_next) {
2652 l0 = pmap_l0(pmap, sva);
2653 if (pmap_load(l0) == 0) {
2654 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2660 l1 = pmap_l0_to_l1(l0, sva);
2661 if (pmap_load(l1) == 0) {
2662 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2668 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2672 l2 = pmap_l1_to_l2(l1, sva);
2673 if (pmap_load(l2) == 0)
2678 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2680 if (pmap_load(l3) == 0)
2682 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
2683 panic("pmap_unwire: l3 %#jx is missing "
2684 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
2687 * PG_W must be cleared atomically. Although the pmap
2688 * lock synchronizes access to PG_W, another processor
2689 * could be setting PG_M and/or PG_A concurrently.
2691 atomic_clear_long(l3, ATTR_SW_WIRED);
2692 pmap->pm_stats.wired_count--;
2695 if (pv_lists_locked)
2696 rw_runlock(&pvh_global_lock);
2701 * Copy the range specified by src_addr/len
2702 * from the source map to the range dst_addr/len
2703 * in the destination map.
2705 * This routine is only advisory and need not do anything.
2709 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
2710 vm_offset_t src_addr)
2715 * pmap_zero_page zeros the specified hardware page by mapping
2716 * the page into KVM and using bzero to clear its contents.
2719 pmap_zero_page(vm_page_t m)
2721 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
2723 pagezero((void *)va);
2727 * pmap_zero_page_area zeros the specified hardware page by mapping
2728 * the page into KVM and using bzero to clear its contents.
2730 * off and size may not cover an area beyond a single hardware page.
2733 pmap_zero_page_area(vm_page_t m, int off, int size)
2735 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
2737 if (off == 0 && size == PAGE_SIZE)
2738 pagezero((void *)va);
2740 bzero((char *)va + off, size);
2744 * pmap_zero_page_idle zeros the specified hardware page by mapping
2745 * the page into KVM and using bzero to clear its contents. This
2746 * is intended to be called from the vm_pagezero process only and
2750 pmap_zero_page_idle(vm_page_t m)
2752 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
2754 pagezero((void *)va);
2758 * pmap_copy_page copies the specified (machine independent)
2759 * page by mapping the page into virtual memory and using
2760 * bcopy to copy the page, one machine dependent page at a
2764 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
2766 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
2767 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
2769 pagecopy((void *)src, (void *)dst);
2772 int unmapped_buf_allowed = 1;
2775 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
2776 vm_offset_t b_offset, int xfersize)
2780 vm_paddr_t p_a, p_b;
2781 vm_offset_t a_pg_offset, b_pg_offset;
2784 while (xfersize > 0) {
2785 a_pg_offset = a_offset & PAGE_MASK;
2786 m_a = ma[a_offset >> PAGE_SHIFT];
2787 p_a = m_a->phys_addr;
2788 b_pg_offset = b_offset & PAGE_MASK;
2789 m_b = mb[b_offset >> PAGE_SHIFT];
2790 p_b = m_b->phys_addr;
2791 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2792 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2793 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
2794 panic("!DMAP a %lx", p_a);
2796 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
2798 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
2799 panic("!DMAP b %lx", p_b);
2801 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
2803 bcopy(a_cp, b_cp, cnt);
2811 pmap_quick_enter_page(vm_page_t m)
2814 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
2818 pmap_quick_remove_page(vm_offset_t addr)
2823 * Returns true if the pmap's pv is one of the first
2824 * 16 pvs linked to from this page. This count may
2825 * be changed upwards or downwards in the future; it
2826 * is only necessary that true be returned for a small
2827 * subset of pmaps for proper page aging.
2830 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
2832 struct rwlock *lock;
2837 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2838 ("pmap_page_exists_quick: page %p is not managed", m));
2840 rw_rlock(&pvh_global_lock);
2841 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2843 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
2844 if (PV_PMAP(pv) == pmap) {
2853 rw_runlock(&pvh_global_lock);
2858 * pmap_page_wired_mappings:
2860 * Return the number of managed mappings to the given physical page
2864 pmap_page_wired_mappings(vm_page_t m)
2866 struct rwlock *lock;
2870 int count, lvl, md_gen;
2872 if ((m->oflags & VPO_UNMANAGED) != 0)
2874 rw_rlock(&pvh_global_lock);
2875 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2879 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
2881 if (!PMAP_TRYLOCK(pmap)) {
2882 md_gen = m->md.pv_gen;
2886 if (md_gen != m->md.pv_gen) {
2891 pte = pmap_pte(pmap, pv->pv_va, &lvl);
2892 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
2897 rw_runlock(&pvh_global_lock);
2902 * Destroy all managed, non-wired mappings in the given user-space
2903 * pmap. This pmap cannot be active on any processor besides the
2906 * This function cannot be applied to the kernel pmap. Moreover, it
2907 * is not intended for general use. It is only to be used during
2908 * process termination. Consequently, it can be implemented in ways
2909 * that make it faster than pmap_remove(). First, it can more quickly
2910 * destroy mappings by iterating over the pmap's collection of PV
2911 * entries, rather than searching the page table. Second, it doesn't
2912 * have to test and clear the page table entries atomically, because
2913 * no processor is currently accessing the user address space. In
2914 * particular, a page table entry's dirty bit won't change state once
2915 * this function starts.
2918 pmap_remove_pages(pmap_t pmap)
2921 pt_entry_t *pte, tpte;
2922 struct spglist free;
2925 struct pv_chunk *pc, *npc;
2926 struct rwlock *lock;
2928 uint64_t inuse, bitmask;
2929 int allfree, field, freed, idx, lvl;
2935 rw_rlock(&pvh_global_lock);
2937 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
2940 for (field = 0; field < _NPCM; field++) {
2941 inuse = ~pc->pc_map[field] & pc_freemask[field];
2942 while (inuse != 0) {
2943 bit = ffsl(inuse) - 1;
2944 bitmask = 1UL << bit;
2945 idx = field * 64 + bit;
2946 pv = &pc->pc_pventry[idx];
2949 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2950 KASSERT(pde != NULL,
2951 ("Attempting to remove an unmapped page"));
2953 ("Invalid page directory level: %d", lvl));
2955 pte = pmap_l2_to_l3(pde, pv->pv_va);
2956 KASSERT(pte != NULL,
2957 ("Attempting to remove an unmapped page"));
2959 tpte = pmap_load(pte);
2962 * We cannot remove wired pages from a process' mapping at this time
2964 if (tpte & ATTR_SW_WIRED) {
2969 pa = tpte & ~ATTR_MASK;
2971 m = PHYS_TO_VM_PAGE(pa);
2972 KASSERT(m->phys_addr == pa,
2973 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
2974 m, (uintmax_t)m->phys_addr,
2977 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
2978 m < &vm_page_array[vm_page_array_size],
2979 ("pmap_remove_pages: bad pte %#jx",
2982 /* XXX: assumes tpte is level 3 */
2983 if (pmap_is_current(pmap) &&
2984 pmap_l3_valid_cacheable(tpte))
2985 cpu_dcache_wb_range(pv->pv_va, L3_SIZE);
2986 pmap_load_clear(pte);
2988 pmap_invalidate_page(pmap, pv->pv_va);
2991 * Update the vm_page_t clean/reference bits.
2993 if ((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
2996 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
2999 pc->pc_map[field] |= bitmask;
3001 pmap_resident_count_dec(pmap, 1);
3002 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3005 pmap_unuse_l3(pmap, pv->pv_va, pmap_load(pde),
3010 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3011 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3012 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3014 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3018 pmap_invalidate_all(pmap);
3021 rw_runlock(&pvh_global_lock);
3023 pmap_free_zero_pages(&free);
3027 * This is used to check if a page has been accessed or modified. As we
3028 * don't have a bit to see if it has been modified we have to assume it
3029 * has been if the page is read/write.
3032 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
3034 struct rwlock *lock;
3036 pt_entry_t *pte, mask, value;
3042 rw_rlock(&pvh_global_lock);
3043 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3046 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3048 if (!PMAP_TRYLOCK(pmap)) {
3049 md_gen = m->md.pv_gen;
3053 if (md_gen != m->md.pv_gen) {
3058 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3060 ("pmap_page_test_mappings: Invalid level %d", lvl));
3064 mask |= ATTR_AP_RW_BIT;
3065 value |= ATTR_AP(ATTR_AP_RW);
3068 mask |= ATTR_AF | ATTR_DESCR_MASK;
3069 value |= ATTR_AF | L3_PAGE;
3071 rv = (pmap_load(pte) & mask) == value;
3078 rw_runlock(&pvh_global_lock);
3085 * Return whether or not the specified physical page was modified
3086 * in any physical maps.
3089 pmap_is_modified(vm_page_t m)
3092 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3093 ("pmap_is_modified: page %p is not managed", m));
3096 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3097 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
3098 * is clear, no PTEs can have PG_M set.
3100 VM_OBJECT_ASSERT_WLOCKED(m->object);
3101 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3103 return (pmap_page_test_mappings(m, FALSE, TRUE));
3107 * pmap_is_prefaultable:
3109 * Return whether or not the specified virtual address is eligible
3113 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3121 pte = pmap_pte(pmap, addr, &lvl);
3122 if (pte != NULL && pmap_load(pte) != 0) {
3130 * pmap_is_referenced:
3132 * Return whether or not the specified physical page was referenced
3133 * in any physical maps.
3136 pmap_is_referenced(vm_page_t m)
3139 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3140 ("pmap_is_referenced: page %p is not managed", m));
3141 return (pmap_page_test_mappings(m, TRUE, FALSE));
3145 * Clear the write and modified bits in each of the given page's mappings.
3148 pmap_remove_write(vm_page_t m)
3151 struct rwlock *lock;
3153 pt_entry_t oldpte, *pte;
3156 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3157 ("pmap_remove_write: page %p is not managed", m));
3160 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3161 * set by another thread while the object is locked. Thus,
3162 * if PGA_WRITEABLE is clear, no page table entries need updating.
3164 VM_OBJECT_ASSERT_WLOCKED(m->object);
3165 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3167 rw_rlock(&pvh_global_lock);
3168 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3171 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3173 if (!PMAP_TRYLOCK(pmap)) {
3174 md_gen = m->md.pv_gen;
3178 if (md_gen != m->md.pv_gen) {
3184 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3186 oldpte = pmap_load(pte);
3187 if ((oldpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) {
3188 if (!atomic_cmpset_long(pte, oldpte,
3189 oldpte | ATTR_AP(ATTR_AP_RO)))
3191 if ((oldpte & ATTR_AF) != 0)
3193 pmap_invalidate_page(pmap, pv->pv_va);
3198 vm_page_aflag_clear(m, PGA_WRITEABLE);
3199 rw_runlock(&pvh_global_lock);
3202 static __inline boolean_t
3203 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
3209 #define PMAP_TS_REFERENCED_MAX 5
3212 * pmap_ts_referenced:
3214 * Return a count of reference bits for a page, clearing those bits.
3215 * It is not necessary for every reference bit to be cleared, but it
3216 * is necessary that 0 only be returned when there are truly no
3217 * reference bits set.
3219 * XXX: The exact number of bits to check and clear is a matter that
3220 * should be tested and standardized at some point in the future for
3221 * optimal aging of shared pages.
3224 pmap_ts_referenced(vm_page_t m)
3228 struct rwlock *lock;
3229 pd_entry_t *pde, tpde;
3230 pt_entry_t *pte, tpte;
3232 int cleared, md_gen, not_cleared, lvl;
3233 struct spglist free;
3235 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3236 ("pmap_ts_referenced: page %p is not managed", m));
3239 pa = VM_PAGE_TO_PHYS(m);
3240 lock = PHYS_TO_PV_LIST_LOCK(pa);
3241 rw_rlock(&pvh_global_lock);
3245 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
3252 if (!PMAP_TRYLOCK(pmap)) {
3253 md_gen = m->md.pv_gen;
3257 if (md_gen != m->md.pv_gen) {
3262 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3263 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
3265 ("pmap_ts_referenced: invalid pde level %d", lvl));
3266 tpde = pmap_load(pde);
3267 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
3268 ("pmap_ts_referenced: found an invalid l2 table"));
3269 pte = pmap_l2_to_l3(pde, pv->pv_va);
3270 tpte = pmap_load(pte);
3271 if ((tpte & ATTR_AF) != 0) {
3272 if (safe_to_clear_referenced(pmap, tpte)) {
3274 * TODO: We don't handle the access flag
3275 * at all. We need to be able to set it in
3276 * the exception handler.
3278 panic("ARM64TODO: safe_to_clear_referenced\n");
3279 } else if ((tpte & ATTR_SW_WIRED) == 0) {
3281 * Wired pages cannot be paged out so
3282 * doing accessed bit emulation for
3283 * them is wasted effort. We do the
3284 * hard work for unwired pages only.
3286 pmap_remove_l3(pmap, pte, pv->pv_va, tpde,
3288 pmap_invalidate_page(pmap, pv->pv_va);
3293 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
3294 ("inconsistent pv lock %p %p for page %p",
3295 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
3300 /* Rotate the PV list if it has more than one entry. */
3301 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
3302 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3303 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3306 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
3307 not_cleared < PMAP_TS_REFERENCED_MAX);
3310 rw_runlock(&pvh_global_lock);
3311 pmap_free_zero_pages(&free);
3312 return (cleared + not_cleared);
3316 * Apply the given advice to the specified range of addresses within the
3317 * given pmap. Depending on the advice, clear the referenced and/or
3318 * modified flags in each mapping and set the mapped page's dirty field.
3321 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
3326 * Clear the modify bits on the specified physical page.
3329 pmap_clear_modify(vm_page_t m)
3332 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3333 ("pmap_clear_modify: page %p is not managed", m));
3334 VM_OBJECT_ASSERT_WLOCKED(m->object);
3335 KASSERT(!vm_page_xbusied(m),
3336 ("pmap_clear_modify: page %p is exclusive busied", m));
3339 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
3340 * If the object containing the page is locked and the page is not
3341 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
3343 if ((m->aflags & PGA_WRITEABLE) == 0)
3346 /* ARM64TODO: We lack support for tracking if a page is modified */
3350 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
3353 return ((void *)PHYS_TO_DMAP(pa));
3357 pmap_unmapbios(vm_paddr_t pa, vm_size_t size)
3362 * Sets the memory attribute for the specified page.
3365 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
3368 m->md.pv_memattr = ma;
3371 * ARM64TODO: Implement the below (from the amd64 pmap)
3372 * If "m" is a normal page, update its direct mapping. This update
3373 * can be relied upon to perform any cache operations that are
3374 * required for data coherence.
3376 if ((m->flags & PG_FICTITIOUS) == 0 &&
3377 PHYS_IN_DMAP(VM_PAGE_TO_PHYS(m)))
3378 panic("ARM64TODO: pmap_page_set_memattr");
3382 * perform the pmap work for mincore
3385 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
3387 pd_entry_t *l1p, l1;
3388 pd_entry_t *l2p, l2;
3389 pt_entry_t *l3p, l3;
3400 l1p = pmap_l1(pmap, addr);
3401 if (l1p == NULL) /* No l1 */
3404 l1 = pmap_load(l1p);
3405 if ((l1 & ATTR_DESCR_MASK) == L1_INVAL)
3408 if ((l1 & ATTR_DESCR_MASK) == L1_BLOCK) {
3409 pa = (l1 & ~ATTR_MASK) | (addr & L1_OFFSET);
3410 managed = (l1 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
3411 val = MINCORE_SUPER | MINCORE_INCORE;
3412 if (pmap_page_dirty(l1))
3413 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3414 if ((l1 & ATTR_AF) == ATTR_AF)
3415 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3419 l2p = pmap_l1_to_l2(l1p, addr);
3420 if (l2p == NULL) /* No l2 */
3423 l2 = pmap_load(l2p);
3424 if ((l2 & ATTR_DESCR_MASK) == L2_INVAL)
3427 if ((l2 & ATTR_DESCR_MASK) == L2_BLOCK) {
3428 pa = (l2 & ~ATTR_MASK) | (addr & L2_OFFSET);
3429 managed = (l2 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
3430 val = MINCORE_SUPER | MINCORE_INCORE;
3431 if (pmap_page_dirty(l2))
3432 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3433 if ((l2 & ATTR_AF) == ATTR_AF)
3434 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3438 l3p = pmap_l2_to_l3(l2p, addr);
3439 if (l3p == NULL) /* No l3 */
3442 l3 = pmap_load(l2p);
3443 if ((l3 & ATTR_DESCR_MASK) == L3_INVAL)
3446 if ((l3 & ATTR_DESCR_MASK) == L3_PAGE) {
3447 pa = (l3 & ~ATTR_MASK) | (addr & L3_OFFSET);
3448 managed = (l3 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
3449 val = MINCORE_INCORE;
3450 if (pmap_page_dirty(l3))
3451 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3452 if ((l3 & ATTR_AF) == ATTR_AF)
3453 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3457 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
3458 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
3459 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
3460 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
3463 PA_UNLOCK_COND(*locked_pa);
3470 pmap_activate(struct thread *td)
3475 pmap = vmspace_pmap(td->td_proc->p_vmspace);
3476 td->td_pcb->pcb_l0addr = vtophys(pmap->pm_l0);
3477 __asm __volatile("msr ttbr0_el1, %0" : : "r"(td->td_pcb->pcb_l0addr));
3478 pmap_invalidate_all(pmap);
3483 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
3486 if (va >= VM_MIN_KERNEL_ADDRESS) {
3487 cpu_icache_sync_range(va, sz);
3492 /* Find the length of data in this page to flush */
3493 offset = va & PAGE_MASK;
3494 len = imin(PAGE_SIZE - offset, sz);
3497 /* Extract the physical address & find it in the DMAP */
3498 pa = pmap_extract(pmap, va);
3500 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
3502 /* Move to the next page */
3505 /* Set the length for the next iteration */
3506 len = imin(PAGE_SIZE, sz);
3512 * Increase the starting virtual address of the given mapping if a
3513 * different alignment might result in more superpage mappings.
3516 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
3517 vm_offset_t *addr, vm_size_t size)
3522 * Get the kernel virtual address of a set of physical pages. If there are
3523 * physical addresses not covered by the DMAP perform a transient mapping
3524 * that will be removed when calling pmap_unmap_io_transient.
3526 * \param page The pages the caller wishes to obtain the virtual
3527 * address on the kernel memory map.
3528 * \param vaddr On return contains the kernel virtual memory address
3529 * of the pages passed in the page parameter.
3530 * \param count Number of pages passed in.
3531 * \param can_fault TRUE if the thread using the mapped pages can take
3532 * page faults, FALSE otherwise.
3534 * \returns TRUE if the caller must call pmap_unmap_io_transient when
3535 * finished or FALSE otherwise.
3539 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
3540 boolean_t can_fault)
3543 boolean_t needs_mapping;
3547 * Allocate any KVA space that we need, this is done in a separate
3548 * loop to prevent calling vmem_alloc while pinned.
3550 needs_mapping = FALSE;
3551 for (i = 0; i < count; i++) {
3552 paddr = VM_PAGE_TO_PHYS(page[i]);
3553 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
3554 error = vmem_alloc(kernel_arena, PAGE_SIZE,
3555 M_BESTFIT | M_WAITOK, &vaddr[i]);
3556 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3557 needs_mapping = TRUE;
3559 vaddr[i] = PHYS_TO_DMAP(paddr);
3563 /* Exit early if everything is covered by the DMAP */
3569 for (i = 0; i < count; i++) {
3570 paddr = VM_PAGE_TO_PHYS(page[i]);
3571 if (!PHYS_IN_DMAP(paddr)) {
3573 "pmap_map_io_transient: TODO: Map out of DMAP data");
3577 return (needs_mapping);
3581 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
3582 boolean_t can_fault)
3589 for (i = 0; i < count; i++) {
3590 paddr = VM_PAGE_TO_PHYS(page[i]);
3591 if (!PHYS_IN_DMAP(paddr)) {
3592 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");