2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/msgbuf.h>
120 #include <sys/mutex.h>
121 #include <sys/proc.h>
122 #include <sys/rwlock.h>
124 #include <sys/vmem.h>
125 #include <sys/vmmeter.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/_unrhdr.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/vm_pager.h>
140 #include <vm/vm_phys.h>
141 #include <vm/vm_radix.h>
142 #include <vm/vm_reserv.h>
145 #include <machine/machdep.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
149 #include <arm/include/physmem.h>
151 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
152 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
153 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
154 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
156 #define NUL0E L0_ENTRIES
157 #define NUL1E (NUL0E * NL1PG)
158 #define NUL2E (NUL1E * NL2PG)
160 #if !defined(DIAGNOSTIC)
161 #ifdef __GNUC_GNU_INLINE__
162 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
164 #define PMAP_INLINE extern inline
171 * These are configured by the mair_el1 register. This is set up in locore.S
173 #define DEVICE_MEMORY 0
174 #define UNCACHED_MEMORY 1
175 #define CACHED_MEMORY 2
179 #define PV_STAT(x) do { x ; } while (0)
181 #define PV_STAT(x) do { } while (0)
184 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
185 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
187 #define NPV_LIST_LOCKS MAXCPU
189 #define PHYS_TO_PV_LIST_LOCK(pa) \
190 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
192 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
193 struct rwlock **_lockp = (lockp); \
194 struct rwlock *_new_lock; \
196 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
197 if (_new_lock != *_lockp) { \
198 if (*_lockp != NULL) \
199 rw_wunlock(*_lockp); \
200 *_lockp = _new_lock; \
205 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
206 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
208 #define RELEASE_PV_LIST_LOCK(lockp) do { \
209 struct rwlock **_lockp = (lockp); \
211 if (*_lockp != NULL) { \
212 rw_wunlock(*_lockp); \
217 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
218 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
221 * The presence of this flag indicates that the mapping is writeable.
222 * If the ATTR_AP_RO bit is also set, then the mapping is clean, otherwise it is
223 * dirty. This flag may only be set on managed mappings.
225 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
226 * as a software managed bit.
228 #define ATTR_SW_DBM ATTR_DBM
230 struct pmap kernel_pmap_store;
232 /* Used for mapping ACPI memory before VM is initialized */
233 #define PMAP_PREINIT_MAPPING_COUNT 32
234 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
235 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
236 static int vm_initialized = 0; /* No need to use pre-init maps when set */
239 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
240 * Always map entire L2 block for simplicity.
241 * VA of L2 block = preinit_map_va + i * L2_SIZE
243 static struct pmap_preinit_mapping {
247 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
249 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
250 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
251 vm_offset_t kernel_vm_end = 0;
254 * Data for the pv entry allocation mechanism.
256 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
257 static struct mtx pv_chunks_mutex;
258 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
259 static struct md_page *pv_table;
260 static struct md_page pv_dummy;
262 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
263 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
264 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
266 /* This code assumes all L1 DMAP entries will be used */
267 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
268 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
270 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
271 extern pt_entry_t pagetable_dmap[];
273 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
274 static vm_paddr_t physmap[PHYSMAP_SIZE];
275 static u_int physmap_idx;
277 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
279 static int superpages_enabled = 1;
280 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
281 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
282 "Are large page mappings enabled?");
285 * Internal flags for pmap_enter()'s helper functions.
287 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
288 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
290 static void free_pv_chunk(struct pv_chunk *pc);
291 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
292 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
293 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
294 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
295 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
298 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
299 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
300 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
301 vm_offset_t va, struct rwlock **lockp);
302 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
303 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
304 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
305 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
306 u_int flags, vm_page_t m, struct rwlock **lockp);
307 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
308 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
309 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
310 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
311 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
312 vm_page_t m, struct rwlock **lockp);
314 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
315 struct rwlock **lockp);
317 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
318 struct spglist *free);
319 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
320 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
323 * These load the old table data and store the new value.
324 * They need to be atomic as the System MMU may write to the table at
325 * the same time as the CPU.
327 #define pmap_clear(table) atomic_store_64(table, 0)
328 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
329 #define pmap_load(table) (*table)
330 #define pmap_load_clear(table) atomic_swap_64(table, 0)
331 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
332 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
333 #define pmap_store(table, entry) atomic_store_64(table, entry)
335 /********************/
336 /* Inline functions */
337 /********************/
340 pagecopy(void *s, void *d)
343 memcpy(d, s, PAGE_SIZE);
346 static __inline pd_entry_t *
347 pmap_l0(pmap_t pmap, vm_offset_t va)
350 return (&pmap->pm_l0[pmap_l0_index(va)]);
353 static __inline pd_entry_t *
354 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
358 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
359 return (&l1[pmap_l1_index(va)]);
362 static __inline pd_entry_t *
363 pmap_l1(pmap_t pmap, vm_offset_t va)
367 l0 = pmap_l0(pmap, va);
368 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
371 return (pmap_l0_to_l1(l0, va));
374 static __inline pd_entry_t *
375 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
379 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
380 return (&l2[pmap_l2_index(va)]);
383 static __inline pd_entry_t *
384 pmap_l2(pmap_t pmap, vm_offset_t va)
388 l1 = pmap_l1(pmap, va);
389 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
392 return (pmap_l1_to_l2(l1, va));
395 static __inline pt_entry_t *
396 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
400 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
401 return (&l3[pmap_l3_index(va)]);
405 * Returns the lowest valid pde for a given virtual address.
406 * The next level may or may not point to a valid page or block.
408 static __inline pd_entry_t *
409 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
411 pd_entry_t *l0, *l1, *l2, desc;
413 l0 = pmap_l0(pmap, va);
414 desc = pmap_load(l0) & ATTR_DESCR_MASK;
415 if (desc != L0_TABLE) {
420 l1 = pmap_l0_to_l1(l0, va);
421 desc = pmap_load(l1) & ATTR_DESCR_MASK;
422 if (desc != L1_TABLE) {
427 l2 = pmap_l1_to_l2(l1, va);
428 desc = pmap_load(l2) & ATTR_DESCR_MASK;
429 if (desc != L2_TABLE) {
439 * Returns the lowest valid pte block or table entry for a given virtual
440 * address. If there are no valid entries return NULL and set the level to
441 * the first invalid level.
443 static __inline pt_entry_t *
444 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
446 pd_entry_t *l1, *l2, desc;
449 l1 = pmap_l1(pmap, va);
454 desc = pmap_load(l1) & ATTR_DESCR_MASK;
455 if (desc == L1_BLOCK) {
460 if (desc != L1_TABLE) {
465 l2 = pmap_l1_to_l2(l1, va);
466 desc = pmap_load(l2) & ATTR_DESCR_MASK;
467 if (desc == L2_BLOCK) {
472 if (desc != L2_TABLE) {
478 l3 = pmap_l2_to_l3(l2, va);
479 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
486 pmap_ps_enabled(pmap_t pmap __unused)
489 return (superpages_enabled != 0);
493 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
494 pd_entry_t **l2, pt_entry_t **l3)
496 pd_entry_t *l0p, *l1p, *l2p;
498 if (pmap->pm_l0 == NULL)
501 l0p = pmap_l0(pmap, va);
504 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
507 l1p = pmap_l0_to_l1(l0p, va);
510 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
516 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
519 l2p = pmap_l1_to_l2(l1p, va);
522 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
527 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
530 *l3 = pmap_l2_to_l3(l2p, va);
536 pmap_l3_valid(pt_entry_t l3)
539 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
543 CTASSERT(L1_BLOCK == L2_BLOCK);
546 * Checks if the PTE is dirty.
549 pmap_pte_dirty(pt_entry_t pte)
552 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
553 KASSERT((pte & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) != 0,
554 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
556 return ((pte & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
557 (ATTR_AP(ATTR_AP_RW) | ATTR_SW_DBM));
561 pmap_resident_count_inc(pmap_t pmap, int count)
564 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
565 pmap->pm_stats.resident_count += count;
569 pmap_resident_count_dec(pmap_t pmap, int count)
572 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
573 KASSERT(pmap->pm_stats.resident_count >= count,
574 ("pmap %p resident count underflow %ld %d", pmap,
575 pmap->pm_stats.resident_count, count));
576 pmap->pm_stats.resident_count -= count;
580 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
586 l1 = (pd_entry_t *)l1pt;
587 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
589 /* Check locore has used a table L1 map */
590 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
591 ("Invalid bootstrap L1 table"));
592 /* Find the address of the L2 table */
593 l2 = (pt_entry_t *)init_pt_va;
594 *l2_slot = pmap_l2_index(va);
600 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
602 u_int l1_slot, l2_slot;
605 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
607 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
611 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
612 vm_offset_t freemempos)
616 vm_paddr_t l2_pa, pa;
617 u_int l1_slot, l2_slot, prev_l1_slot;
620 dmap_phys_base = min_pa & ~L1_OFFSET;
626 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
627 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
629 for (i = 0; i < (physmap_idx * 2); i += 2) {
630 pa = physmap[i] & ~L2_OFFSET;
631 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
633 /* Create L2 mappings at the start of the region */
634 if ((pa & L1_OFFSET) != 0) {
635 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
636 if (l1_slot != prev_l1_slot) {
637 prev_l1_slot = l1_slot;
638 l2 = (pt_entry_t *)freemempos;
639 l2_pa = pmap_early_vtophys(kern_l1,
641 freemempos += PAGE_SIZE;
643 pmap_store(&pagetable_dmap[l1_slot],
644 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
646 memset(l2, 0, PAGE_SIZE);
649 ("pmap_bootstrap_dmap: NULL l2 map"));
650 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
651 pa += L2_SIZE, va += L2_SIZE) {
653 * We are on a boundary, stop to
654 * create a level 1 block
656 if ((pa & L1_OFFSET) == 0)
659 l2_slot = pmap_l2_index(va);
660 KASSERT(l2_slot != 0, ("..."));
661 pmap_store(&l2[l2_slot],
662 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
663 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
665 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
669 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
670 (physmap[i + 1] - pa) >= L1_SIZE;
671 pa += L1_SIZE, va += L1_SIZE) {
672 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
673 pmap_store(&pagetable_dmap[l1_slot],
674 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
675 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
678 /* Create L2 mappings at the end of the region */
679 if (pa < physmap[i + 1]) {
680 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
681 if (l1_slot != prev_l1_slot) {
682 prev_l1_slot = l1_slot;
683 l2 = (pt_entry_t *)freemempos;
684 l2_pa = pmap_early_vtophys(kern_l1,
686 freemempos += PAGE_SIZE;
688 pmap_store(&pagetable_dmap[l1_slot],
689 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
691 memset(l2, 0, PAGE_SIZE);
694 ("pmap_bootstrap_dmap: NULL l2 map"));
695 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
696 pa += L2_SIZE, va += L2_SIZE) {
697 l2_slot = pmap_l2_index(va);
698 pmap_store(&l2[l2_slot],
699 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
700 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
704 if (pa > dmap_phys_max) {
716 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
723 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
725 l1 = (pd_entry_t *)l1pt;
726 l1_slot = pmap_l1_index(va);
729 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
730 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
732 pa = pmap_early_vtophys(l1pt, l2pt);
733 pmap_store(&l1[l1_slot],
734 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
738 /* Clean the L2 page table */
739 memset((void *)l2_start, 0, l2pt - l2_start);
745 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
752 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
754 l2 = pmap_l2(kernel_pmap, va);
755 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
756 l2_slot = pmap_l2_index(va);
759 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
760 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
762 pa = pmap_early_vtophys(l1pt, l3pt);
763 pmap_store(&l2[l2_slot],
764 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
768 /* Clean the L2 page table */
769 memset((void *)l3_start, 0, l3pt - l3_start);
775 * Bootstrap the system enough to run with virtual memory.
778 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
781 u_int l1_slot, l2_slot;
783 vm_offset_t va, freemempos;
784 vm_offset_t dpcpu, msgbufpv;
785 vm_paddr_t start_pa, pa, min_pa;
789 kern_delta = KERNBASE - kernstart;
791 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
792 printf("%lx\n", l1pt);
793 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
795 /* Set this early so we can use the pagetable walking functions */
796 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
797 PMAP_LOCK_INIT(kernel_pmap);
799 /* Assume the address we were loaded to is a valid physical address */
800 min_pa = KERNBASE - kern_delta;
802 physmap_idx = arm_physmem_avail(physmap, nitems(physmap));
806 * Find the minimum physical address. physmap is sorted,
807 * but may contain empty ranges.
809 for (i = 0; i < (physmap_idx * 2); i += 2) {
810 if (physmap[i] == physmap[i + 1])
812 if (physmap[i] <= min_pa)
816 freemempos = KERNBASE + kernlen;
817 freemempos = roundup2(freemempos, PAGE_SIZE);
819 /* Create a direct map region early so we can use it for pa -> va */
820 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
823 start_pa = pa = KERNBASE - kern_delta;
826 * Read the page table to find out what is already mapped.
827 * This assumes we have mapped a block of memory from KERNBASE
828 * using a single L1 entry.
830 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
832 /* Sanity check the index, KERNBASE should be the first VA */
833 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
835 /* Find how many pages we have mapped */
836 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
837 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
840 /* Check locore used L2 blocks */
841 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
842 ("Invalid bootstrap L2 table"));
843 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
844 ("Incorrect PA in L2 table"));
850 va = roundup2(va, L1_SIZE);
852 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
853 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
854 /* And the l3 tables for the early devmap */
855 freemempos = pmap_bootstrap_l3(l1pt,
856 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
860 #define alloc_pages(var, np) \
861 (var) = freemempos; \
862 freemempos += (np * PAGE_SIZE); \
863 memset((char *)(var), 0, ((np) * PAGE_SIZE));
865 /* Allocate dynamic per-cpu area. */
866 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
867 dpcpu_init((void *)dpcpu, 0);
869 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
870 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
871 msgbufp = (void *)msgbufpv;
873 /* Reserve some VA space for early BIOS/ACPI mapping */
874 preinit_map_va = roundup2(freemempos, L2_SIZE);
876 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
877 virtual_avail = roundup2(virtual_avail, L1_SIZE);
878 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
879 kernel_vm_end = virtual_avail;
881 pa = pmap_early_vtophys(l1pt, freemempos);
883 arm_physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
889 * Initialize a vm_page's machine-dependent fields.
892 pmap_page_init(vm_page_t m)
895 TAILQ_INIT(&m->md.pv_list);
896 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
900 * Initialize the pmap module.
901 * Called by vm_init, to initialize any structures that the pmap
902 * system needs to map virtual memory.
911 * Are large page mappings enabled?
913 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
914 if (superpages_enabled) {
915 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
916 ("pmap_init: can't assign to pagesizes[1]"));
917 pagesizes[1] = L2_SIZE;
921 * Initialize the pv chunk list mutex.
923 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
926 * Initialize the pool of pv list locks.
928 for (i = 0; i < NPV_LIST_LOCKS; i++)
929 rw_init(&pv_list_locks[i], "pmap pv list");
932 * Calculate the size of the pv head table for superpages.
934 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
937 * Allocate memory for the pv head table for superpages.
939 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
941 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
942 for (i = 0; i < pv_npg; i++)
943 TAILQ_INIT(&pv_table[i].pv_list);
944 TAILQ_INIT(&pv_dummy.pv_list);
949 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
950 "2MB page mapping counters");
952 static u_long pmap_l2_demotions;
953 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
954 &pmap_l2_demotions, 0, "2MB page demotions");
956 static u_long pmap_l2_mappings;
957 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
958 &pmap_l2_mappings, 0, "2MB page mappings");
960 static u_long pmap_l2_p_failures;
961 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
962 &pmap_l2_p_failures, 0, "2MB page promotion failures");
964 static u_long pmap_l2_promotions;
965 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
966 &pmap_l2_promotions, 0, "2MB page promotions");
969 * Invalidate a single TLB entry.
972 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
978 "tlbi vaae1is, %0 \n"
981 : : "r"(va >> PAGE_SHIFT));
986 pmap_invalidate_range_nopin(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
991 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
993 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
1000 static __inline void
1001 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1005 pmap_invalidate_range_nopin(pmap, sva, eva);
1009 static __inline void
1010 pmap_invalidate_all(pmap_t pmap)
1023 * Routine: pmap_extract
1025 * Extract the physical page address associated
1026 * with the given map/virtual_address pair.
1029 pmap_extract(pmap_t pmap, vm_offset_t va)
1031 pt_entry_t *pte, tpte;
1038 * Find the block or page map for this virtual address. pmap_pte
1039 * will return either a valid block/page entry, or NULL.
1041 pte = pmap_pte(pmap, va, &lvl);
1043 tpte = pmap_load(pte);
1044 pa = tpte & ~ATTR_MASK;
1047 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1048 ("pmap_extract: Invalid L1 pte found: %lx",
1049 tpte & ATTR_DESCR_MASK));
1050 pa |= (va & L1_OFFSET);
1053 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1054 ("pmap_extract: Invalid L2 pte found: %lx",
1055 tpte & ATTR_DESCR_MASK));
1056 pa |= (va & L2_OFFSET);
1059 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1060 ("pmap_extract: Invalid L3 pte found: %lx",
1061 tpte & ATTR_DESCR_MASK));
1062 pa |= (va & L3_OFFSET);
1071 * Routine: pmap_extract_and_hold
1073 * Atomically extract and hold the physical page
1074 * with the given pmap and virtual address pair
1075 * if that mapping permits the given protection.
1078 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1080 pt_entry_t *pte, tpte;
1087 pte = pmap_pte(pmap, va, &lvl);
1089 tpte = pmap_load(pte);
1091 KASSERT(lvl > 0 && lvl <= 3,
1092 ("pmap_extract_and_hold: Invalid level %d", lvl));
1093 CTASSERT(L1_BLOCK == L2_BLOCK);
1094 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1095 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1096 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1097 tpte & ATTR_DESCR_MASK));
1098 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1099 ((prot & VM_PROT_WRITE) == 0)) {
1102 off = va & L1_OFFSET;
1105 off = va & L2_OFFSET;
1111 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1112 if (!vm_page_wire_mapped(m))
1121 pmap_kextract(vm_offset_t va)
1123 pt_entry_t *pte, tpte;
1125 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
1126 return (DMAP_TO_PHYS(va));
1127 pte = pmap_l1(kernel_pmap, va);
1132 * A concurrent pmap_update_entry() will clear the entry's valid bit
1133 * but leave the rest of the entry unchanged. Therefore, we treat a
1134 * non-zero entry as being valid, and we ignore the valid bit when
1135 * determining whether the entry maps a block, page, or table.
1137 tpte = pmap_load(pte);
1140 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1141 return ((tpte & ~ATTR_MASK) | (va & L1_OFFSET));
1142 pte = pmap_l1_to_l2(&tpte, va);
1143 tpte = pmap_load(pte);
1146 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1147 return ((tpte & ~ATTR_MASK) | (va & L2_OFFSET));
1148 pte = pmap_l2_to_l3(&tpte, va);
1149 tpte = pmap_load(pte);
1152 return ((tpte & ~ATTR_MASK) | (va & L3_OFFSET));
1155 /***************************************************
1156 * Low level mapping routines.....
1157 ***************************************************/
1160 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1163 pt_entry_t *pte, attr;
1167 KASSERT((pa & L3_OFFSET) == 0,
1168 ("pmap_kenter: Invalid physical address"));
1169 KASSERT((sva & L3_OFFSET) == 0,
1170 ("pmap_kenter: Invalid virtual address"));
1171 KASSERT((size & PAGE_MASK) == 0,
1172 ("pmap_kenter: Mapping is not page-sized"));
1174 attr = ATTR_DEFAULT | ATTR_IDX(mode) | L3_PAGE;
1175 if (mode == DEVICE_MEMORY)
1180 pde = pmap_pde(kernel_pmap, va, &lvl);
1181 KASSERT(pde != NULL,
1182 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1183 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1185 pte = pmap_l2_to_l3(pde, va);
1186 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1192 pmap_invalidate_range(kernel_pmap, sva, va);
1196 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1199 pmap_kenter(sva, size, pa, DEVICE_MEMORY);
1203 * Remove a page from the kernel pagetables.
1206 pmap_kremove(vm_offset_t va)
1211 pte = pmap_pte(kernel_pmap, va, &lvl);
1212 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1213 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1216 pmap_invalidate_page(kernel_pmap, va);
1220 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1226 KASSERT((sva & L3_OFFSET) == 0,
1227 ("pmap_kremove_device: Invalid virtual address"));
1228 KASSERT((size & PAGE_MASK) == 0,
1229 ("pmap_kremove_device: Mapping is not page-sized"));
1233 pte = pmap_pte(kernel_pmap, va, &lvl);
1234 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1236 ("Invalid device pagetable level: %d != 3", lvl));
1242 pmap_invalidate_range(kernel_pmap, sva, va);
1246 * Used to map a range of physical addresses into kernel
1247 * virtual address space.
1249 * The value passed in '*virt' is a suggested virtual address for
1250 * the mapping. Architectures which can support a direct-mapped
1251 * physical to virtual region can return the appropriate address
1252 * within that region, leaving '*virt' unchanged. Other
1253 * architectures should map the pages starting at '*virt' and
1254 * update '*virt' with the first usable address after the mapped
1258 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1260 return PHYS_TO_DMAP(start);
1265 * Add a list of wired pages to the kva
1266 * this routine is only used for temporary
1267 * kernel mappings that do not need to have
1268 * page modification or references recorded.
1269 * Note that old mappings are simply written
1270 * over. The page *must* be wired.
1271 * Note: SMP coherent. Uses a ranged shootdown IPI.
1274 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1277 pt_entry_t *pte, pa;
1283 for (i = 0; i < count; i++) {
1284 pde = pmap_pde(kernel_pmap, va, &lvl);
1285 KASSERT(pde != NULL,
1286 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1288 ("pmap_qenter: Invalid level %d", lvl));
1291 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1292 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1293 if (m->md.pv_memattr == DEVICE_MEMORY)
1295 pte = pmap_l2_to_l3(pde, va);
1296 pmap_load_store(pte, pa);
1300 pmap_invalidate_range(kernel_pmap, sva, va);
1304 * This routine tears out page mappings from the
1305 * kernel -- it is meant only for temporary mappings.
1308 pmap_qremove(vm_offset_t sva, int count)
1314 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1317 while (count-- > 0) {
1318 pte = pmap_pte(kernel_pmap, va, &lvl);
1320 ("Invalid device pagetable level: %d != 3", lvl));
1327 pmap_invalidate_range(kernel_pmap, sva, va);
1330 /***************************************************
1331 * Page table page management routines.....
1332 ***************************************************/
1334 * Schedule the specified unused page table page to be freed. Specifically,
1335 * add the page to the specified list of pages that will be released to the
1336 * physical memory manager after the TLB has been updated.
1338 static __inline void
1339 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1340 boolean_t set_PG_ZERO)
1344 m->flags |= PG_ZERO;
1346 m->flags &= ~PG_ZERO;
1347 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1351 * Decrements a page table page's wire count, which is used to record the
1352 * number of valid page table entries within the page. If the wire count
1353 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1354 * page table page was unmapped and FALSE otherwise.
1356 static inline boolean_t
1357 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1361 if (m->wire_count == 0) {
1362 _pmap_unwire_l3(pmap, va, m, free);
1369 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1372 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1374 * unmap the page table page
1376 if (m->pindex >= (NUL2E + NUL1E)) {
1380 l0 = pmap_l0(pmap, va);
1382 } else if (m->pindex >= NUL2E) {
1386 l1 = pmap_l1(pmap, va);
1392 l2 = pmap_l2(pmap, va);
1395 pmap_resident_count_dec(pmap, 1);
1396 if (m->pindex < NUL2E) {
1397 /* We just released an l3, unhold the matching l2 */
1398 pd_entry_t *l1, tl1;
1401 l1 = pmap_l1(pmap, va);
1402 tl1 = pmap_load(l1);
1403 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1404 pmap_unwire_l3(pmap, va, l2pg, free);
1405 } else if (m->pindex < (NUL2E + NUL1E)) {
1406 /* We just released an l2, unhold the matching l1 */
1407 pd_entry_t *l0, tl0;
1410 l0 = pmap_l0(pmap, va);
1411 tl0 = pmap_load(l0);
1412 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1413 pmap_unwire_l3(pmap, va, l1pg, free);
1415 pmap_invalidate_page(pmap, va);
1418 * Put page on a list so that it is released after
1419 * *ALL* TLB shootdown is done
1421 pmap_add_delayed_free_list(m, free, TRUE);
1425 * After removing a page table entry, this routine is used to
1426 * conditionally free the page, and manage the hold/wire counts.
1429 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1430 struct spglist *free)
1434 if (va >= VM_MAXUSER_ADDRESS)
1436 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1437 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1438 return (pmap_unwire_l3(pmap, va, mpte, free));
1442 pmap_pinit0(pmap_t pmap)
1445 PMAP_LOCK_INIT(pmap);
1446 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1447 pmap->pm_l0 = kernel_pmap->pm_l0;
1448 pmap->pm_root.rt_root = 0;
1452 pmap_pinit(pmap_t pmap)
1458 * allocate the l0 page
1460 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1461 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1464 l0phys = VM_PAGE_TO_PHYS(l0pt);
1465 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1467 if ((l0pt->flags & PG_ZERO) == 0)
1468 pagezero(pmap->pm_l0);
1470 pmap->pm_root.rt_root = 0;
1471 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1477 * This routine is called if the desired page table page does not exist.
1479 * If page table page allocation fails, this routine may sleep before
1480 * returning NULL. It sleeps only if a lock pointer was given.
1482 * Note: If a page allocation fails at page table level two or three,
1483 * one or two pages may be held during the wait, only to be released
1484 * afterwards. This conservative approach is easily argued to avoid
1488 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1490 vm_page_t m, l1pg, l2pg;
1492 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1495 * Allocate a page table page.
1497 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1498 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1499 if (lockp != NULL) {
1500 RELEASE_PV_LIST_LOCK(lockp);
1507 * Indicate the need to retry. While waiting, the page table
1508 * page may have been allocated.
1512 if ((m->flags & PG_ZERO) == 0)
1516 * Because of AArch64's weak memory consistency model, we must have a
1517 * barrier here to ensure that the stores for zeroing "m", whether by
1518 * pmap_zero_page() or an earlier function, are visible before adding
1519 * "m" to the page table. Otherwise, a page table walk by another
1520 * processor's MMU could see the mapping to "m" and a stale, non-zero
1526 * Map the pagetable page into the process address space, if
1527 * it isn't already there.
1530 if (ptepindex >= (NUL2E + NUL1E)) {
1532 vm_pindex_t l0index;
1534 l0index = ptepindex - (NUL2E + NUL1E);
1535 l0 = &pmap->pm_l0[l0index];
1536 pmap_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1537 } else if (ptepindex >= NUL2E) {
1538 vm_pindex_t l0index, l1index;
1539 pd_entry_t *l0, *l1;
1542 l1index = ptepindex - NUL2E;
1543 l0index = l1index >> L0_ENTRIES_SHIFT;
1545 l0 = &pmap->pm_l0[l0index];
1546 tl0 = pmap_load(l0);
1548 /* recurse for allocating page dir */
1549 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1551 vm_page_unwire_noq(m);
1552 vm_page_free_zero(m);
1556 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1560 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1561 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1562 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1564 vm_pindex_t l0index, l1index;
1565 pd_entry_t *l0, *l1, *l2;
1566 pd_entry_t tl0, tl1;
1568 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1569 l0index = l1index >> L0_ENTRIES_SHIFT;
1571 l0 = &pmap->pm_l0[l0index];
1572 tl0 = pmap_load(l0);
1574 /* recurse for allocating page dir */
1575 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1577 vm_page_unwire_noq(m);
1578 vm_page_free_zero(m);
1581 tl0 = pmap_load(l0);
1582 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1583 l1 = &l1[l1index & Ln_ADDR_MASK];
1585 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1586 l1 = &l1[l1index & Ln_ADDR_MASK];
1587 tl1 = pmap_load(l1);
1589 /* recurse for allocating page dir */
1590 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1592 vm_page_unwire_noq(m);
1593 vm_page_free_zero(m);
1597 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1602 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1603 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1604 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1607 pmap_resident_count_inc(pmap, 1);
1613 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1617 vm_pindex_t l2pindex;
1620 l1 = pmap_l1(pmap, va);
1621 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1622 /* Add a reference to the L2 page. */
1623 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1626 /* Allocate a L2 page. */
1627 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1628 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1629 if (l2pg == NULL && lockp != NULL)
1636 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1638 vm_pindex_t ptepindex;
1639 pd_entry_t *pde, tpde;
1647 * Calculate pagetable page index
1649 ptepindex = pmap_l2_pindex(va);
1652 * Get the page directory entry
1654 pde = pmap_pde(pmap, va, &lvl);
1657 * If the page table page is mapped, we just increment the hold count,
1658 * and activate it. If we get a level 2 pde it will point to a level 3
1666 pte = pmap_l0_to_l1(pde, va);
1667 KASSERT(pmap_load(pte) == 0,
1668 ("pmap_alloc_l3: TODO: l0 superpages"));
1673 pte = pmap_l1_to_l2(pde, va);
1674 KASSERT(pmap_load(pte) == 0,
1675 ("pmap_alloc_l3: TODO: l1 superpages"));
1679 tpde = pmap_load(pde);
1681 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1687 panic("pmap_alloc_l3: Invalid level %d", lvl);
1691 * Here if the pte page isn't mapped, or if it has been deallocated.
1693 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1694 if (m == NULL && lockp != NULL)
1700 /***************************************************
1701 * Pmap allocation/deallocation routines.
1702 ***************************************************/
1705 * Release any resources held by the given physical map.
1706 * Called when a pmap initialized by pmap_pinit is being released.
1707 * Should only be called if the map contains no valid mappings.
1710 pmap_release(pmap_t pmap)
1714 KASSERT(pmap->pm_stats.resident_count == 0,
1715 ("pmap_release: pmap resident count %ld != 0",
1716 pmap->pm_stats.resident_count));
1717 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1718 ("pmap_release: pmap has reserved page table page(s)"));
1720 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1722 vm_page_unwire_noq(m);
1723 vm_page_free_zero(m);
1727 kvm_size(SYSCTL_HANDLER_ARGS)
1729 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1731 return sysctl_handle_long(oidp, &ksize, 0, req);
1733 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1734 0, 0, kvm_size, "LU", "Size of KVM");
1737 kvm_free(SYSCTL_HANDLER_ARGS)
1739 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1741 return sysctl_handle_long(oidp, &kfree, 0, req);
1743 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1744 0, 0, kvm_free, "LU", "Amount of KVM free");
1747 * grow the number of kernel page table entries, if needed
1750 pmap_growkernel(vm_offset_t addr)
1754 pd_entry_t *l0, *l1, *l2;
1756 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1758 addr = roundup2(addr, L2_SIZE);
1759 if (addr - 1 >= vm_map_max(kernel_map))
1760 addr = vm_map_max(kernel_map);
1761 while (kernel_vm_end < addr) {
1762 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1763 KASSERT(pmap_load(l0) != 0,
1764 ("pmap_growkernel: No level 0 kernel entry"));
1766 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1767 if (pmap_load(l1) == 0) {
1768 /* We need a new PDP entry */
1769 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1770 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1771 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1773 panic("pmap_growkernel: no memory to grow kernel");
1774 if ((nkpg->flags & PG_ZERO) == 0)
1775 pmap_zero_page(nkpg);
1776 /* See the dmb() in _pmap_alloc_l3(). */
1778 paddr = VM_PAGE_TO_PHYS(nkpg);
1779 pmap_store(l1, paddr | L1_TABLE);
1780 continue; /* try again */
1782 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1783 if (pmap_load(l2) != 0) {
1784 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1785 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1786 kernel_vm_end = vm_map_max(kernel_map);
1792 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1793 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1796 panic("pmap_growkernel: no memory to grow kernel");
1797 if ((nkpg->flags & PG_ZERO) == 0)
1798 pmap_zero_page(nkpg);
1799 /* See the dmb() in _pmap_alloc_l3(). */
1801 paddr = VM_PAGE_TO_PHYS(nkpg);
1802 pmap_store(l2, paddr | L2_TABLE);
1804 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1805 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1806 kernel_vm_end = vm_map_max(kernel_map);
1813 /***************************************************
1814 * page management routines.
1815 ***************************************************/
1817 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1818 CTASSERT(_NPCM == 3);
1819 CTASSERT(_NPCPV == 168);
1821 static __inline struct pv_chunk *
1822 pv_to_chunk(pv_entry_t pv)
1825 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1828 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1830 #define PC_FREE0 0xfffffffffffffffful
1831 #define PC_FREE1 0xfffffffffffffffful
1832 #define PC_FREE2 0x000000fffffffffful
1834 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1838 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1840 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1841 "Current number of pv entry chunks");
1842 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1843 "Current number of pv entry chunks allocated");
1844 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1845 "Current number of pv entry chunks frees");
1846 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1847 "Number of times tried to get a chunk page but failed.");
1849 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1850 static int pv_entry_spare;
1852 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1853 "Current number of pv entry frees");
1854 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1855 "Current number of pv entry allocs");
1856 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1857 "Current number of pv entries");
1858 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1859 "Current number of spare pv entries");
1864 * We are in a serious low memory condition. Resort to
1865 * drastic measures to free some pages so we can allocate
1866 * another pv entry chunk.
1868 * Returns NULL if PV entries were reclaimed from the specified pmap.
1870 * We do not, however, unmap 2mpages because subsequent accesses will
1871 * allocate per-page pv entries until repromotion occurs, thereby
1872 * exacerbating the shortage of free pv entries.
1875 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1877 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
1878 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
1879 struct md_page *pvh;
1881 pmap_t next_pmap, pmap;
1882 pt_entry_t *pte, tpte;
1886 struct spglist free;
1888 int bit, field, freed, lvl;
1889 static int active_reclaims = 0;
1891 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1892 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
1897 bzero(&pc_marker_b, sizeof(pc_marker_b));
1898 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
1899 pc_marker = (struct pv_chunk *)&pc_marker_b;
1900 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
1902 mtx_lock(&pv_chunks_mutex);
1904 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
1905 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
1906 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
1907 SLIST_EMPTY(&free)) {
1908 next_pmap = pc->pc_pmap;
1909 if (next_pmap == NULL) {
1911 * The next chunk is a marker. However, it is
1912 * not our marker, so active_reclaims must be
1913 * > 1. Consequently, the next_chunk code
1914 * will not rotate the pv_chunks list.
1918 mtx_unlock(&pv_chunks_mutex);
1921 * A pv_chunk can only be removed from the pc_lru list
1922 * when both pv_chunks_mutex is owned and the
1923 * corresponding pmap is locked.
1925 if (pmap != next_pmap) {
1926 if (pmap != NULL && pmap != locked_pmap)
1929 /* Avoid deadlock and lock recursion. */
1930 if (pmap > locked_pmap) {
1931 RELEASE_PV_LIST_LOCK(lockp);
1933 mtx_lock(&pv_chunks_mutex);
1935 } else if (pmap != locked_pmap) {
1936 if (PMAP_TRYLOCK(pmap)) {
1937 mtx_lock(&pv_chunks_mutex);
1940 pmap = NULL; /* pmap is not locked */
1941 mtx_lock(&pv_chunks_mutex);
1942 pc = TAILQ_NEXT(pc_marker, pc_lru);
1944 pc->pc_pmap != next_pmap)
1952 * Destroy every non-wired, 4 KB page mapping in the chunk.
1955 for (field = 0; field < _NPCM; field++) {
1956 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1957 inuse != 0; inuse &= ~(1UL << bit)) {
1958 bit = ffsl(inuse) - 1;
1959 pv = &pc->pc_pventry[field * 64 + bit];
1961 pde = pmap_pde(pmap, va, &lvl);
1964 pte = pmap_l2_to_l3(pde, va);
1965 tpte = pmap_load(pte);
1966 if ((tpte & ATTR_SW_WIRED) != 0)
1968 tpte = pmap_load_clear(pte);
1969 pmap_invalidate_page(pmap, va);
1970 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
1971 if (pmap_pte_dirty(tpte))
1973 if ((tpte & ATTR_AF) != 0)
1974 vm_page_aflag_set(m, PGA_REFERENCED);
1975 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1976 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
1978 if (TAILQ_EMPTY(&m->md.pv_list) &&
1979 (m->flags & PG_FICTITIOUS) == 0) {
1980 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
1981 if (TAILQ_EMPTY(&pvh->pv_list)) {
1982 vm_page_aflag_clear(m,
1986 pc->pc_map[field] |= 1UL << bit;
1987 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
1992 mtx_lock(&pv_chunks_mutex);
1995 /* Every freed mapping is for a 4 KB page. */
1996 pmap_resident_count_dec(pmap, freed);
1997 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
1998 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
1999 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2000 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2001 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2002 pc->pc_map[2] == PC_FREE2) {
2003 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2004 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2005 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2006 /* Entire chunk is free; return it. */
2007 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2008 dump_drop_page(m_pc->phys_addr);
2009 mtx_lock(&pv_chunks_mutex);
2010 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2013 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2014 mtx_lock(&pv_chunks_mutex);
2015 /* One freed pv entry in locked_pmap is sufficient. */
2016 if (pmap == locked_pmap)
2020 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2021 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2022 if (active_reclaims == 1 && pmap != NULL) {
2024 * Rotate the pv chunks list so that we do not
2025 * scan the same pv chunks that could not be
2026 * freed (because they contained a wired
2027 * and/or superpage mapping) on every
2028 * invocation of reclaim_pv_chunk().
2030 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2031 MPASS(pc->pc_pmap != NULL);
2032 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2033 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2037 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2038 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2040 mtx_unlock(&pv_chunks_mutex);
2041 if (pmap != NULL && pmap != locked_pmap)
2043 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2044 m_pc = SLIST_FIRST(&free);
2045 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2046 /* Recycle a freed page table page. */
2047 m_pc->wire_count = 1;
2049 vm_page_free_pages_toq(&free, true);
2054 * free the pv_entry back to the free list
2057 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2059 struct pv_chunk *pc;
2060 int idx, field, bit;
2062 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2063 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2064 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2065 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2066 pc = pv_to_chunk(pv);
2067 idx = pv - &pc->pc_pventry[0];
2070 pc->pc_map[field] |= 1ul << bit;
2071 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2072 pc->pc_map[2] != PC_FREE2) {
2073 /* 98% of the time, pc is already at the head of the list. */
2074 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2075 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2076 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2080 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2085 free_pv_chunk(struct pv_chunk *pc)
2089 mtx_lock(&pv_chunks_mutex);
2090 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2091 mtx_unlock(&pv_chunks_mutex);
2092 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2093 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2094 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2095 /* entire chunk is free, return it */
2096 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2097 dump_drop_page(m->phys_addr);
2098 vm_page_unwire_noq(m);
2103 * Returns a new PV entry, allocating a new PV chunk from the system when
2104 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2105 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2108 * The given PV list lock may be released.
2111 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2115 struct pv_chunk *pc;
2118 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2119 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2121 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2123 for (field = 0; field < _NPCM; field++) {
2124 if (pc->pc_map[field]) {
2125 bit = ffsl(pc->pc_map[field]) - 1;
2129 if (field < _NPCM) {
2130 pv = &pc->pc_pventry[field * 64 + bit];
2131 pc->pc_map[field] &= ~(1ul << bit);
2132 /* If this was the last item, move it to tail */
2133 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2134 pc->pc_map[2] == 0) {
2135 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2136 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2139 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2140 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2144 /* No free items, allocate another chunk */
2145 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2148 if (lockp == NULL) {
2149 PV_STAT(pc_chunk_tryfail++);
2152 m = reclaim_pv_chunk(pmap, lockp);
2156 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2157 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2158 dump_add_page(m->phys_addr);
2159 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2161 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2162 pc->pc_map[1] = PC_FREE1;
2163 pc->pc_map[2] = PC_FREE2;
2164 mtx_lock(&pv_chunks_mutex);
2165 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2166 mtx_unlock(&pv_chunks_mutex);
2167 pv = &pc->pc_pventry[0];
2168 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2169 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2170 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2175 * Ensure that the number of spare PV entries in the specified pmap meets or
2176 * exceeds the given count, "needed".
2178 * The given PV list lock may be released.
2181 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2183 struct pch new_tail;
2184 struct pv_chunk *pc;
2189 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2190 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2193 * Newly allocated PV chunks must be stored in a private list until
2194 * the required number of PV chunks have been allocated. Otherwise,
2195 * reclaim_pv_chunk() could recycle one of these chunks. In
2196 * contrast, these chunks must be added to the pmap upon allocation.
2198 TAILQ_INIT(&new_tail);
2201 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2202 bit_count((bitstr_t *)pc->pc_map, 0,
2203 sizeof(pc->pc_map) * NBBY, &free);
2207 if (avail >= needed)
2210 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2211 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2214 m = reclaim_pv_chunk(pmap, lockp);
2219 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2220 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2221 dump_add_page(m->phys_addr);
2222 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2224 pc->pc_map[0] = PC_FREE0;
2225 pc->pc_map[1] = PC_FREE1;
2226 pc->pc_map[2] = PC_FREE2;
2227 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2228 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2229 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2232 * The reclaim might have freed a chunk from the current pmap.
2233 * If that chunk contained available entries, we need to
2234 * re-count the number of available entries.
2239 if (!TAILQ_EMPTY(&new_tail)) {
2240 mtx_lock(&pv_chunks_mutex);
2241 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2242 mtx_unlock(&pv_chunks_mutex);
2247 * First find and then remove the pv entry for the specified pmap and virtual
2248 * address from the specified pv list. Returns the pv entry if found and NULL
2249 * otherwise. This operation can be performed on pv lists for either 4KB or
2250 * 2MB page mappings.
2252 static __inline pv_entry_t
2253 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2257 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2258 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2259 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2268 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2269 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2270 * entries for each of the 4KB page mappings.
2273 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2274 struct rwlock **lockp)
2276 struct md_page *pvh;
2277 struct pv_chunk *pc;
2279 vm_offset_t va_last;
2283 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2284 KASSERT((va & L2_OFFSET) == 0,
2285 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
2286 KASSERT((pa & L2_OFFSET) == 0,
2287 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2288 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2291 * Transfer the 2mpage's pv entry for this mapping to the first
2292 * page's pv list. Once this transfer begins, the pv list lock
2293 * must not be released until the last pv entry is reinstantiated.
2295 pvh = pa_to_pvh(pa);
2296 pv = pmap_pvh_remove(pvh, pmap, va);
2297 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2298 m = PHYS_TO_VM_PAGE(pa);
2299 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2301 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2302 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2303 va_last = va + L2_SIZE - PAGE_SIZE;
2305 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2306 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2307 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2308 for (field = 0; field < _NPCM; field++) {
2309 while (pc->pc_map[field]) {
2310 bit = ffsl(pc->pc_map[field]) - 1;
2311 pc->pc_map[field] &= ~(1ul << bit);
2312 pv = &pc->pc_pventry[field * 64 + bit];
2316 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2317 ("pmap_pv_demote_l2: page %p is not managed", m));
2318 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2324 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2325 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2328 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2329 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2330 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2332 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2333 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2337 * First find and then destroy the pv entry for the specified pmap and virtual
2338 * address. This operation can be performed on pv lists for either 4KB or 2MB
2342 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2346 pv = pmap_pvh_remove(pvh, pmap, va);
2347 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2348 free_pv_entry(pmap, pv);
2352 * Conditionally create the PV entry for a 4KB page mapping if the required
2353 * memory can be allocated without resorting to reclamation.
2356 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2357 struct rwlock **lockp)
2361 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2362 /* Pass NULL instead of the lock pointer to disable reclamation. */
2363 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2365 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2366 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2374 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2375 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2376 * false if the PV entry cannot be allocated without resorting to reclamation.
2379 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2380 struct rwlock **lockp)
2382 struct md_page *pvh;
2386 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2387 /* Pass NULL instead of the lock pointer to disable reclamation. */
2388 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2389 NULL : lockp)) == NULL)
2392 pa = l2e & ~ATTR_MASK;
2393 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2394 pvh = pa_to_pvh(pa);
2395 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2401 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2403 pt_entry_t newl2, oldl2;
2407 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2408 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2409 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2411 ml3 = pmap_remove_pt_page(pmap, va);
2413 panic("pmap_remove_kernel_l2: Missing pt page");
2415 ml3pa = VM_PAGE_TO_PHYS(ml3);
2416 newl2 = ml3pa | L2_TABLE;
2419 * If this page table page was unmapped by a promotion, then it
2420 * contains valid mappings. Zero it to invalidate those mappings.
2422 if (ml3->valid != 0)
2423 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2426 * Demote the mapping. The caller must have already invalidated the
2427 * mapping (i.e., the "break" in break-before-make).
2429 oldl2 = pmap_load_store(l2, newl2);
2430 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
2431 __func__, l2, oldl2));
2435 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
2438 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2439 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2441 struct md_page *pvh;
2443 vm_offset_t eva, va;
2446 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2447 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2448 old_l2 = pmap_load_clear(l2);
2449 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2450 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2453 * Since a promotion must break the 4KB page mappings before making
2454 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2456 pmap_invalidate_page(pmap, sva);
2458 if (old_l2 & ATTR_SW_WIRED)
2459 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2460 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2461 if (old_l2 & ATTR_SW_MANAGED) {
2462 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2463 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2464 pmap_pvh_free(pvh, pmap, sva);
2465 eva = sva + L2_SIZE;
2466 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2467 va < eva; va += PAGE_SIZE, m++) {
2468 if (pmap_pte_dirty(old_l2))
2470 if (old_l2 & ATTR_AF)
2471 vm_page_aflag_set(m, PGA_REFERENCED);
2472 if (TAILQ_EMPTY(&m->md.pv_list) &&
2473 TAILQ_EMPTY(&pvh->pv_list))
2474 vm_page_aflag_clear(m, PGA_WRITEABLE);
2477 if (pmap == kernel_pmap) {
2478 pmap_remove_kernel_l2(pmap, l2, sva);
2480 ml3 = pmap_remove_pt_page(pmap, sva);
2482 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
2483 ("pmap_remove_l2: l3 page not promoted"));
2484 pmap_resident_count_dec(pmap, 1);
2485 KASSERT(ml3->wire_count == NL3PG,
2486 ("pmap_remove_l2: l3 page wire count error"));
2487 ml3->wire_count = 0;
2488 pmap_add_delayed_free_list(ml3, free, FALSE);
2491 return (pmap_unuse_pt(pmap, sva, l1e, free));
2495 * pmap_remove_l3: do the things to unmap a page in a process
2498 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2499 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2501 struct md_page *pvh;
2505 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2506 old_l3 = pmap_load_clear(l3);
2507 pmap_invalidate_page(pmap, va);
2508 if (old_l3 & ATTR_SW_WIRED)
2509 pmap->pm_stats.wired_count -= 1;
2510 pmap_resident_count_dec(pmap, 1);
2511 if (old_l3 & ATTR_SW_MANAGED) {
2512 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2513 if (pmap_pte_dirty(old_l3))
2515 if (old_l3 & ATTR_AF)
2516 vm_page_aflag_set(m, PGA_REFERENCED);
2517 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2518 pmap_pvh_free(&m->md, pmap, va);
2519 if (TAILQ_EMPTY(&m->md.pv_list) &&
2520 (m->flags & PG_FICTITIOUS) == 0) {
2521 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2522 if (TAILQ_EMPTY(&pvh->pv_list))
2523 vm_page_aflag_clear(m, PGA_WRITEABLE);
2526 return (pmap_unuse_pt(pmap, va, l2e, free));
2530 * Remove the specified range of addresses from the L3 page table that is
2531 * identified by the given L2 entry.
2534 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
2535 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
2537 struct md_page *pvh;
2538 struct rwlock *new_lock;
2539 pt_entry_t *l3, old_l3;
2543 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2544 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
2545 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
2547 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
2548 if (!pmap_l3_valid(pmap_load(l3))) {
2550 pmap_invalidate_range(pmap, va, sva);
2555 old_l3 = pmap_load_clear(l3);
2556 if ((old_l3 & ATTR_SW_WIRED) != 0)
2557 pmap->pm_stats.wired_count--;
2558 pmap_resident_count_dec(pmap, 1);
2559 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
2560 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2561 if (pmap_pte_dirty(old_l3))
2563 if ((old_l3 & ATTR_AF) != 0)
2564 vm_page_aflag_set(m, PGA_REFERENCED);
2565 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
2566 if (new_lock != *lockp) {
2567 if (*lockp != NULL) {
2569 * Pending TLB invalidations must be
2570 * performed before the PV list lock is
2571 * released. Otherwise, a concurrent
2572 * pmap_remove_all() on a physical page
2573 * could return while a stale TLB entry
2574 * still provides access to that page.
2577 pmap_invalidate_range(pmap, va,
2586 pmap_pvh_free(&m->md, pmap, sva);
2587 if (TAILQ_EMPTY(&m->md.pv_list) &&
2588 (m->flags & PG_FICTITIOUS) == 0) {
2589 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2590 if (TAILQ_EMPTY(&pvh->pv_list))
2591 vm_page_aflag_clear(m, PGA_WRITEABLE);
2596 if (pmap_unuse_pt(pmap, sva, l2e, free)) {
2602 pmap_invalidate_range(pmap, va, sva);
2606 * Remove the given range of addresses from the specified map.
2608 * It is assumed that the start and end are properly
2609 * rounded to the page size.
2612 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2614 struct rwlock *lock;
2615 vm_offset_t va_next;
2616 pd_entry_t *l0, *l1, *l2;
2617 pt_entry_t l3_paddr;
2618 struct spglist free;
2621 * Perform an unsynchronized read. This is, however, safe.
2623 if (pmap->pm_stats.resident_count == 0)
2631 for (; sva < eva; sva = va_next) {
2633 if (pmap->pm_stats.resident_count == 0)
2636 l0 = pmap_l0(pmap, sva);
2637 if (pmap_load(l0) == 0) {
2638 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2644 l1 = pmap_l0_to_l1(l0, sva);
2645 if (pmap_load(l1) == 0) {
2646 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2653 * Calculate index for next page table.
2655 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2659 l2 = pmap_l1_to_l2(l1, sva);
2663 l3_paddr = pmap_load(l2);
2665 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2666 if (sva + L2_SIZE == va_next && eva >= va_next) {
2667 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2670 } else if (pmap_demote_l2_locked(pmap, l2, sva,
2673 l3_paddr = pmap_load(l2);
2677 * Weed out invalid mappings.
2679 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2683 * Limit our scan to either the end of the va represented
2684 * by the current page table page, or to the end of the
2685 * range being removed.
2690 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
2696 vm_page_free_pages_toq(&free, true);
2700 * Routine: pmap_remove_all
2702 * Removes this physical page from
2703 * all physical maps in which it resides.
2704 * Reflects back modify bits to the pager.
2707 * Original versions of this routine were very
2708 * inefficient because they iteratively called
2709 * pmap_remove (slow...)
2713 pmap_remove_all(vm_page_t m)
2715 struct md_page *pvh;
2718 struct rwlock *lock;
2719 pd_entry_t *pde, tpde;
2720 pt_entry_t *pte, tpte;
2722 struct spglist free;
2723 int lvl, pvh_gen, md_gen;
2725 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2726 ("pmap_remove_all: page %p is not managed", m));
2728 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2729 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2730 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2733 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2735 if (!PMAP_TRYLOCK(pmap)) {
2736 pvh_gen = pvh->pv_gen;
2740 if (pvh_gen != pvh->pv_gen) {
2747 pte = pmap_pte(pmap, va, &lvl);
2748 KASSERT(pte != NULL,
2749 ("pmap_remove_all: no page table entry found"));
2751 ("pmap_remove_all: invalid pte level %d", lvl));
2753 pmap_demote_l2_locked(pmap, pte, va, &lock);
2756 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2758 if (!PMAP_TRYLOCK(pmap)) {
2759 pvh_gen = pvh->pv_gen;
2760 md_gen = m->md.pv_gen;
2764 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2770 pmap_resident_count_dec(pmap, 1);
2772 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2773 KASSERT(pde != NULL,
2774 ("pmap_remove_all: no page directory entry found"));
2776 ("pmap_remove_all: invalid pde level %d", lvl));
2777 tpde = pmap_load(pde);
2779 pte = pmap_l2_to_l3(pde, pv->pv_va);
2780 tpte = pmap_load_clear(pte);
2781 pmap_invalidate_page(pmap, pv->pv_va);
2782 if (tpte & ATTR_SW_WIRED)
2783 pmap->pm_stats.wired_count--;
2784 if ((tpte & ATTR_AF) != 0)
2785 vm_page_aflag_set(m, PGA_REFERENCED);
2788 * Update the vm_page_t clean and reference bits.
2790 if (pmap_pte_dirty(tpte))
2792 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2793 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2795 free_pv_entry(pmap, pv);
2798 vm_page_aflag_clear(m, PGA_WRITEABLE);
2800 vm_page_free_pages_toq(&free, true);
2804 * pmap_protect_l2: do the things to protect a 2MB page in a pmap
2807 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
2813 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2814 KASSERT((sva & L2_OFFSET) == 0,
2815 ("pmap_protect_l2: sva is not 2mpage aligned"));
2816 old_l2 = pmap_load(l2);
2817 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2818 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
2821 * Return if the L2 entry already has the desired access restrictions
2825 if ((old_l2 & mask) == nbits)
2829 * When a dirty read/write superpage mapping is write protected,
2830 * update the dirty field of each of the superpage's constituent 4KB
2833 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
2834 (nbits & ATTR_AP(ATTR_AP_RO)) != 0 && pmap_pte_dirty(old_l2)) {
2835 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2836 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
2840 if (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
2844 * Since a promotion must break the 4KB page mappings before making
2845 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2847 pmap_invalidate_page(pmap, sva);
2851 * Set the physical protection on the
2852 * specified range of this map as requested.
2855 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2857 vm_offset_t va, va_next;
2858 pd_entry_t *l0, *l1, *l2;
2859 pt_entry_t *l3p, l3, mask, nbits;
2861 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
2862 if (prot == VM_PROT_NONE) {
2863 pmap_remove(pmap, sva, eva);
2868 if ((prot & VM_PROT_WRITE) == 0) {
2869 mask |= ATTR_AP_RW_BIT | ATTR_SW_DBM;
2870 nbits |= ATTR_AP(ATTR_AP_RO);
2872 if ((prot & VM_PROT_EXECUTE) == 0) {
2880 for (; sva < eva; sva = va_next) {
2882 l0 = pmap_l0(pmap, sva);
2883 if (pmap_load(l0) == 0) {
2884 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2890 l1 = pmap_l0_to_l1(l0, sva);
2891 if (pmap_load(l1) == 0) {
2892 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2898 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2902 l2 = pmap_l1_to_l2(l1, sva);
2903 if (pmap_load(l2) == 0)
2906 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
2907 if (sva + L2_SIZE == va_next && eva >= va_next) {
2908 pmap_protect_l2(pmap, l2, sva, mask, nbits);
2910 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
2913 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
2914 ("pmap_protect: Invalid L2 entry after demotion"));
2920 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2922 l3 = pmap_load(l3p);
2925 * Go to the next L3 entry if the current one is
2926 * invalid or already has the desired access
2927 * restrictions in place. (The latter case occurs
2928 * frequently. For example, in a "buildworld"
2929 * workload, almost 1 out of 4 L3 entries already
2930 * have the desired restrictions.)
2932 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
2933 if (va != va_next) {
2934 pmap_invalidate_range(pmap, va, sva);
2941 * When a dirty read/write mapping is write protected,
2942 * update the page's dirty field.
2944 if ((l3 & ATTR_SW_MANAGED) != 0 &&
2945 (nbits & ATTR_AP(ATTR_AP_RO)) != 0 &&
2947 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK));
2949 if (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) | nbits))
2955 pmap_invalidate_range(pmap, va, sva);
2961 * Inserts the specified page table page into the specified pmap's collection
2962 * of idle page table pages. Each of a pmap's page table pages is responsible
2963 * for mapping a distinct range of virtual addresses. The pmap's collection is
2964 * ordered by this virtual address range.
2966 * If "promoted" is false, then the page table page "mpte" must be zero filled.
2969 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
2972 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2973 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
2974 return (vm_radix_insert(&pmap->pm_root, mpte));
2978 * Removes the page table page mapping the specified virtual address from the
2979 * specified pmap's collection of idle page table pages, and returns it.
2980 * Otherwise, returns NULL if there is no page table page corresponding to the
2981 * specified virtual address.
2983 static __inline vm_page_t
2984 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2987 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2988 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
2992 * Performs a break-before-make update of a pmap entry. This is needed when
2993 * either promoting or demoting pages to ensure the TLB doesn't get into an
2994 * inconsistent state.
2997 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
2998 vm_offset_t va, vm_size_t size)
3002 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3005 * Ensure we don't get switched out with the page table in an
3006 * inconsistent state. We also need to ensure no interrupts fire
3007 * as they may make use of an address we are about to invalidate.
3009 intr = intr_disable();
3013 * Clear the old mapping's valid bit, but leave the rest of the entry
3014 * unchanged, so that a lockless, concurrent pmap_kextract() can still
3015 * lookup the physical address.
3017 pmap_clear_bits(pte, ATTR_DESCR_VALID);
3018 pmap_invalidate_range_nopin(pmap, va, va + size);
3020 /* Create the new mapping */
3021 pmap_store(pte, newpte);
3028 #if VM_NRESERVLEVEL > 0
3030 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3031 * replace the many pv entries for the 4KB page mappings by a single pv entry
3032 * for the 2MB page mapping.
3035 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3036 struct rwlock **lockp)
3038 struct md_page *pvh;
3040 vm_offset_t va_last;
3043 KASSERT((pa & L2_OFFSET) == 0,
3044 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
3045 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3048 * Transfer the first page's pv entry for this mapping to the 2mpage's
3049 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3050 * a transfer avoids the possibility that get_pv_entry() calls
3051 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3052 * mappings that is being promoted.
3054 m = PHYS_TO_VM_PAGE(pa);
3055 va = va & ~L2_OFFSET;
3056 pv = pmap_pvh_remove(&m->md, pmap, va);
3057 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
3058 pvh = pa_to_pvh(pa);
3059 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3061 /* Free the remaining NPTEPG - 1 pv entries. */
3062 va_last = va + L2_SIZE - PAGE_SIZE;
3066 pmap_pvh_free(&m->md, pmap, va);
3067 } while (va < va_last);
3071 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3072 * single level 2 table entry to a single 2MB page mapping. For promotion
3073 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3074 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3075 * identical characteristics.
3078 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
3079 struct rwlock **lockp)
3081 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
3085 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3087 sva = va & ~L2_OFFSET;
3088 firstl3 = pmap_l2_to_l3(l2, sva);
3089 newl2 = pmap_load(firstl3);
3092 if (((newl2 & (~ATTR_MASK | ATTR_AF)) & L2_OFFSET) != ATTR_AF) {
3093 atomic_add_long(&pmap_l2_p_failures, 1);
3094 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3095 " in pmap %p", va, pmap);
3099 if ((newl2 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
3100 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM)) {
3101 if (!atomic_fcmpset_64(l2, &newl2, newl2 & ~ATTR_SW_DBM))
3103 newl2 &= ~ATTR_SW_DBM;
3106 pa = newl2 + L2_SIZE - PAGE_SIZE;
3107 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
3108 oldl3 = pmap_load(l3);
3110 if ((oldl3 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
3111 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM)) {
3112 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
3115 oldl3 &= ~ATTR_SW_DBM;
3118 atomic_add_long(&pmap_l2_p_failures, 1);
3119 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3120 " in pmap %p", va, pmap);
3127 * Save the page table page in its current state until the L2
3128 * mapping the superpage is demoted by pmap_demote_l2() or
3129 * destroyed by pmap_remove_l3().
3131 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3132 KASSERT(mpte >= vm_page_array &&
3133 mpte < &vm_page_array[vm_page_array_size],
3134 ("pmap_promote_l2: page table page is out of range"));
3135 KASSERT(mpte->pindex == pmap_l2_pindex(va),
3136 ("pmap_promote_l2: page table page's pindex is wrong"));
3137 if (pmap_insert_pt_page(pmap, mpte, true)) {
3138 atomic_add_long(&pmap_l2_p_failures, 1);
3140 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
3145 if ((newl2 & ATTR_SW_MANAGED) != 0)
3146 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
3148 newl2 &= ~ATTR_DESCR_MASK;
3151 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
3153 atomic_add_long(&pmap_l2_promotions, 1);
3154 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
3157 #endif /* VM_NRESERVLEVEL > 0 */
3160 * Insert the given physical page (p) at
3161 * the specified virtual address (v) in the
3162 * target physical map with the protection requested.
3164 * If specified, the page will be wired down, meaning
3165 * that the related pte can not be reclaimed.
3167 * NB: This is the only routine which MAY NOT lazy-evaluate
3168 * or lose information. That is, this routine must actually
3169 * insert this page into the given map NOW.
3172 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3173 u_int flags, int8_t psind)
3175 struct rwlock *lock;
3177 pt_entry_t new_l3, orig_l3;
3178 pt_entry_t *l2, *l3;
3185 va = trunc_page(va);
3186 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3187 VM_OBJECT_ASSERT_LOCKED(m->object);
3188 pa = VM_PAGE_TO_PHYS(m);
3189 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3191 if ((prot & VM_PROT_WRITE) == 0)
3192 new_l3 |= ATTR_AP(ATTR_AP_RO);
3193 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3195 if ((flags & PMAP_ENTER_WIRED) != 0)
3196 new_l3 |= ATTR_SW_WIRED;
3197 if (va < VM_MAXUSER_ADDRESS)
3198 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3199 if ((m->oflags & VPO_UNMANAGED) == 0) {
3200 new_l3 |= ATTR_SW_MANAGED;
3201 if ((prot & VM_PROT_WRITE) != 0) {
3202 new_l3 |= ATTR_SW_DBM;
3203 if ((flags & VM_PROT_WRITE) == 0)
3204 new_l3 |= ATTR_AP(ATTR_AP_RO);
3208 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3213 /* Assert the required virtual and physical alignment. */
3214 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3215 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3216 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3223 * In the case that a page table page is not
3224 * resident, we are creating it here.
3227 pde = pmap_pde(pmap, va, &lvl);
3228 if (pde != NULL && lvl == 2) {
3229 l3 = pmap_l2_to_l3(pde, va);
3230 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3231 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3235 } else if (pde != NULL && lvl == 1) {
3236 l2 = pmap_l1_to_l2(pde, va);
3237 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3238 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
3239 l3 = &l3[pmap_l3_index(va)];
3240 if (va < VM_MAXUSER_ADDRESS) {
3241 mpte = PHYS_TO_VM_PAGE(
3242 pmap_load(l2) & ~ATTR_MASK);
3247 /* We need to allocate an L3 table. */
3249 if (va < VM_MAXUSER_ADDRESS) {
3250 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
3253 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
3254 * to handle the possibility that a superpage mapping for "va"
3255 * was created while we slept.
3257 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
3258 nosleep ? NULL : &lock);
3259 if (mpte == NULL && nosleep) {
3260 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3261 rv = KERN_RESOURCE_SHORTAGE;
3266 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
3269 orig_l3 = pmap_load(l3);
3270 opa = orig_l3 & ~ATTR_MASK;
3274 * Is the specified virtual address already mapped?
3276 if (pmap_l3_valid(orig_l3)) {
3278 * Wiring change, just update stats. We don't worry about
3279 * wiring PT pages as they remain resident as long as there
3280 * are valid mappings in them. Hence, if a user page is wired,
3281 * the PT page will be also.
3283 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3284 (orig_l3 & ATTR_SW_WIRED) == 0)
3285 pmap->pm_stats.wired_count++;
3286 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3287 (orig_l3 & ATTR_SW_WIRED) != 0)
3288 pmap->pm_stats.wired_count--;
3291 * Remove the extra PT page reference.
3295 KASSERT(mpte->wire_count > 0,
3296 ("pmap_enter: missing reference to page table page,"
3301 * Has the physical page changed?
3305 * No, might be a protection or wiring change.
3307 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3308 (new_l3 & ATTR_SW_DBM) != 0)
3309 vm_page_aflag_set(m, PGA_WRITEABLE);
3314 * The physical page has changed. Temporarily invalidate
3317 orig_l3 = pmap_load_clear(l3);
3318 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
3319 ("pmap_enter: unexpected pa update for %#lx", va));
3320 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3321 om = PHYS_TO_VM_PAGE(opa);
3324 * The pmap lock is sufficient to synchronize with
3325 * concurrent calls to pmap_page_test_mappings() and
3326 * pmap_ts_referenced().
3328 if (pmap_pte_dirty(orig_l3))
3330 if ((orig_l3 & ATTR_AF) != 0)
3331 vm_page_aflag_set(om, PGA_REFERENCED);
3332 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3333 pv = pmap_pvh_remove(&om->md, pmap, va);
3334 if ((m->oflags & VPO_UNMANAGED) != 0)
3335 free_pv_entry(pmap, pv);
3336 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3337 TAILQ_EMPTY(&om->md.pv_list) &&
3338 ((om->flags & PG_FICTITIOUS) != 0 ||
3339 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3340 vm_page_aflag_clear(om, PGA_WRITEABLE);
3342 pmap_invalidate_page(pmap, va);
3346 * Increment the counters.
3348 if ((new_l3 & ATTR_SW_WIRED) != 0)
3349 pmap->pm_stats.wired_count++;
3350 pmap_resident_count_inc(pmap, 1);
3353 * Enter on the PV list if part of our managed memory.
3355 if ((m->oflags & VPO_UNMANAGED) == 0) {
3357 pv = get_pv_entry(pmap, &lock);
3360 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3361 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3363 if ((new_l3 & ATTR_SW_DBM) != 0)
3364 vm_page_aflag_set(m, PGA_WRITEABLE);
3369 * Sync icache if exec permission and attribute VM_MEMATTR_WRITE_BACK
3370 * is set. Do it now, before the mapping is stored and made
3371 * valid for hardware table walk. If done later, then other can
3372 * access this page before caches are properly synced.
3373 * Don't do it for kernel memory which is mapped with exec
3374 * permission even if the memory isn't going to hold executable
3375 * code. The only time when icache sync is needed is after
3376 * kernel module is loaded and the relocation info is processed.
3377 * And it's done in elf_cpu_load_file().
3379 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3380 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3381 (opa != pa || (orig_l3 & ATTR_XN)))
3382 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3385 * Update the L3 entry
3387 if (pmap_l3_valid(orig_l3)) {
3388 KASSERT(opa == pa, ("pmap_enter: invalid update"));
3389 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3390 /* same PA, different attributes */
3391 /* XXXMJ need to reload orig_l3 for hardware DBM. */
3392 pmap_load_store(l3, new_l3);
3393 pmap_invalidate_page(pmap, va);
3394 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3395 pmap_pte_dirty(orig_l3))
3400 * This can happens if multiple threads simultaneously
3401 * access not yet mapped page. This bad for performance
3402 * since this can cause full demotion-NOP-promotion
3404 * Another possible reasons are:
3405 * - VM and pmap memory layout are diverged
3406 * - tlb flush is missing somewhere and CPU doesn't see
3409 CTR4(KTR_PMAP, "%s: already mapped page - "
3410 "pmap %p va 0x%#lx pte 0x%lx",
3411 __func__, pmap, va, new_l3);
3415 pmap_store(l3, new_l3);
3419 #if VM_NRESERVLEVEL > 0
3420 if ((mpte == NULL || mpte->wire_count == NL3PG) &&
3421 pmap_ps_enabled(pmap) &&
3422 (m->flags & PG_FICTITIOUS) == 0 &&
3423 vm_reserv_level_iffullpop(m) == 0) {
3424 pmap_promote_l2(pmap, pde, va, &lock);
3437 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
3438 * if successful. Returns false if (1) a page table page cannot be allocated
3439 * without sleeping, (2) a mapping already exists at the specified virtual
3440 * address, or (3) a PV entry cannot be allocated without reclaiming another
3444 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3445 struct rwlock **lockp)
3449 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3451 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
3452 ATTR_IDX(m->md.pv_memattr) | ATTR_AP(ATTR_AP_RO) | L2_BLOCK);
3453 if ((m->oflags & VPO_UNMANAGED) == 0) {
3454 new_l2 |= ATTR_SW_MANAGED;
3457 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3459 if (va < VM_MAXUSER_ADDRESS)
3460 new_l2 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3461 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
3462 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
3467 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
3468 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
3469 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
3470 * a mapping already exists at the specified virtual address. Returns
3471 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
3472 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
3473 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3475 * The parameter "m" is only used when creating a managed, writeable mapping.
3478 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
3479 vm_page_t m, struct rwlock **lockp)
3481 struct spglist free;
3482 pd_entry_t *l2, old_l2;
3485 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3487 if ((l2pg = pmap_alloc_l2(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
3488 NULL : lockp)) == NULL) {
3489 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
3491 return (KERN_RESOURCE_SHORTAGE);
3494 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
3495 l2 = &l2[pmap_l2_index(va)];
3496 if ((old_l2 = pmap_load(l2)) != 0) {
3497 KASSERT(l2pg->wire_count > 1,
3498 ("pmap_enter_l2: l2pg's wire count is too low"));
3499 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3502 "pmap_enter_l2: failure for va %#lx in pmap %p",
3504 return (KERN_FAILURE);
3507 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
3508 (void)pmap_remove_l2(pmap, l2, va,
3509 pmap_load(pmap_l1(pmap, va)), &free, lockp);
3511 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
3513 vm_page_free_pages_toq(&free, true);
3514 if (va >= VM_MAXUSER_ADDRESS) {
3516 * Both pmap_remove_l2() and pmap_remove_l3_range()
3517 * will leave the kernel page table page zero filled.
3518 * Nonetheless, the TLB could have an intermediate
3519 * entry for the kernel page table page.
3521 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3522 if (pmap_insert_pt_page(pmap, mt, false))
3523 panic("pmap_enter_l2: trie insert failed");
3525 pmap_invalidate_page(pmap, va);
3527 KASSERT(pmap_load(l2) == 0,
3528 ("pmap_enter_l2: non-zero L2 entry %p", l2));
3531 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
3533 * Abort this mapping if its PV entry could not be created.
3535 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
3537 if (pmap_unwire_l3(pmap, va, l2pg, &free)) {
3539 * Although "va" is not mapped, the TLB could
3540 * nonetheless have intermediate entries that
3541 * refer to the freed page table pages.
3542 * Invalidate those entries.
3544 * XXX redundant invalidation (See
3545 * _pmap_unwire_l3().)
3547 pmap_invalidate_page(pmap, va);
3548 vm_page_free_pages_toq(&free, true);
3551 "pmap_enter_l2: failure for va %#lx in pmap %p",
3553 return (KERN_RESOURCE_SHORTAGE);
3555 if ((new_l2 & ATTR_SW_DBM) != 0)
3556 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3557 vm_page_aflag_set(mt, PGA_WRITEABLE);
3561 * Increment counters.
3563 if ((new_l2 & ATTR_SW_WIRED) != 0)
3564 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
3565 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
3568 * Map the superpage.
3570 pmap_store(l2, new_l2);
3573 atomic_add_long(&pmap_l2_mappings, 1);
3574 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
3577 return (KERN_SUCCESS);
3581 * Maps a sequence of resident pages belonging to the same object.
3582 * The sequence begins with the given page m_start. This page is
3583 * mapped at the given virtual address start. Each subsequent page is
3584 * mapped at a virtual address that is offset from start by the same
3585 * amount as the page is offset from m_start within the object. The
3586 * last page in the sequence is the page with the largest offset from
3587 * m_start that can be mapped at a virtual address less than the given
3588 * virtual address end. Not every virtual page between start and end
3589 * is mapped; only those for which a resident page exists with the
3590 * corresponding offset from m_start are mapped.
3593 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3594 vm_page_t m_start, vm_prot_t prot)
3596 struct rwlock *lock;
3599 vm_pindex_t diff, psize;
3601 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3603 psize = atop(end - start);
3608 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3609 va = start + ptoa(diff);
3610 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
3611 m->psind == 1 && pmap_ps_enabled(pmap) &&
3612 pmap_enter_2mpage(pmap, va, m, prot, &lock))
3613 m = &m[L2_SIZE / PAGE_SIZE - 1];
3615 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
3617 m = TAILQ_NEXT(m, listq);
3625 * this code makes some *MAJOR* assumptions:
3626 * 1. Current pmap & pmap exists.
3629 * 4. No page table pages.
3630 * but is *MUCH* faster than pmap_enter...
3634 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3636 struct rwlock *lock;
3640 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3647 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3648 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3650 struct spglist free;
3652 pt_entry_t *l2, *l3, l3_val;
3656 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3657 (m->oflags & VPO_UNMANAGED) != 0,
3658 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3659 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3661 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3663 * In the case that a page table page is not
3664 * resident, we are creating it here.
3666 if (va < VM_MAXUSER_ADDRESS) {
3667 vm_pindex_t l2pindex;
3670 * Calculate pagetable page index
3672 l2pindex = pmap_l2_pindex(va);
3673 if (mpte && (mpte->pindex == l2pindex)) {
3679 pde = pmap_pde(pmap, va, &lvl);
3682 * If the page table page is mapped, we just increment
3683 * the hold count, and activate it. Otherwise, we
3684 * attempt to allocate a page table page. If this
3685 * attempt fails, we don't retry. Instead, we give up.
3688 l2 = pmap_l1_to_l2(pde, va);
3689 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3693 if (lvl == 2 && pmap_load(pde) != 0) {
3695 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3699 * Pass NULL instead of the PV list lock
3700 * pointer, because we don't intend to sleep.
3702 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3707 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3708 l3 = &l3[pmap_l3_index(va)];
3711 pde = pmap_pde(kernel_pmap, va, &lvl);
3712 KASSERT(pde != NULL,
3713 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3716 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3717 l3 = pmap_l2_to_l3(pde, va);
3721 * Abort if a mapping already exists.
3723 if (pmap_load(l3) != 0) {
3732 * Enter on the PV list if part of our managed memory.
3734 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3735 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3738 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
3739 pmap_invalidate_page(pmap, va);
3740 vm_page_free_pages_toq(&free, true);
3748 * Increment counters
3750 pmap_resident_count_inc(pmap, 1);
3752 pa = VM_PAGE_TO_PHYS(m);
3753 l3_val = pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3754 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3755 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3757 else if (va < VM_MAXUSER_ADDRESS)
3761 * Now validate mapping with RO protection
3763 if ((m->oflags & VPO_UNMANAGED) == 0) {
3764 l3_val |= ATTR_SW_MANAGED;
3768 /* Sync icache before the mapping is stored to PTE */
3769 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3770 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
3771 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3773 pmap_store(l3, l3_val);
3780 * This code maps large physical mmap regions into the
3781 * processor address space. Note that some shortcuts
3782 * are taken, but the code works.
3785 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3786 vm_pindex_t pindex, vm_size_t size)
3789 VM_OBJECT_ASSERT_WLOCKED(object);
3790 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3791 ("pmap_object_init_pt: non-device object"));
3795 * Clear the wired attribute from the mappings for the specified range of
3796 * addresses in the given pmap. Every valid mapping within that range
3797 * must have the wired attribute set. In contrast, invalid mappings
3798 * cannot have the wired attribute set, so they are ignored.
3800 * The wired attribute of the page table entry is not a hardware feature,
3801 * so there is no need to invalidate any TLB entries.
3804 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3806 vm_offset_t va_next;
3807 pd_entry_t *l0, *l1, *l2;
3811 for (; sva < eva; sva = va_next) {
3812 l0 = pmap_l0(pmap, sva);
3813 if (pmap_load(l0) == 0) {
3814 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3820 l1 = pmap_l0_to_l1(l0, sva);
3821 if (pmap_load(l1) == 0) {
3822 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3828 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3832 l2 = pmap_l1_to_l2(l1, sva);
3833 if (pmap_load(l2) == 0)
3836 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3837 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
3838 panic("pmap_unwire: l2 %#jx is missing "
3839 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
3842 * Are we unwiring the entire large page? If not,
3843 * demote the mapping and fall through.
3845 if (sva + L2_SIZE == va_next && eva >= va_next) {
3846 pmap_clear_bits(l2, ATTR_SW_WIRED);
3847 pmap->pm_stats.wired_count -= L2_SIZE /
3850 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3851 panic("pmap_unwire: demotion failed");
3853 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3854 ("pmap_unwire: Invalid l2 entry after demotion"));
3858 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3860 if (pmap_load(l3) == 0)
3862 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
3863 panic("pmap_unwire: l3 %#jx is missing "
3864 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
3867 * ATTR_SW_WIRED must be cleared atomically. Although
3868 * the pmap lock synchronizes access to ATTR_SW_WIRED,
3869 * the System MMU may write to the entry concurrently.
3871 pmap_clear_bits(l3, ATTR_SW_WIRED);
3872 pmap->pm_stats.wired_count--;
3879 * Copy the range specified by src_addr/len
3880 * from the source map to the range dst_addr/len
3881 * in the destination map.
3883 * This routine is only advisory and need not do anything.
3885 * Because the executable mappings created by this routine are copied,
3886 * it should not have to flush the instruction cache.
3889 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3890 vm_offset_t src_addr)
3892 struct rwlock *lock;
3893 struct spglist free;
3894 pd_entry_t *l0, *l1, *l2, srcptepaddr;
3895 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
3896 vm_offset_t addr, end_addr, va_next;
3897 vm_page_t dst_l2pg, dstmpte, srcmpte;
3899 if (dst_addr != src_addr)
3901 end_addr = src_addr + len;
3903 if (dst_pmap < src_pmap) {
3904 PMAP_LOCK(dst_pmap);
3905 PMAP_LOCK(src_pmap);
3907 PMAP_LOCK(src_pmap);
3908 PMAP_LOCK(dst_pmap);
3910 for (addr = src_addr; addr < end_addr; addr = va_next) {
3911 l0 = pmap_l0(src_pmap, addr);
3912 if (pmap_load(l0) == 0) {
3913 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
3918 l1 = pmap_l0_to_l1(l0, addr);
3919 if (pmap_load(l1) == 0) {
3920 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
3925 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
3928 l2 = pmap_l1_to_l2(l1, addr);
3929 srcptepaddr = pmap_load(l2);
3930 if (srcptepaddr == 0)
3932 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
3933 if ((addr & L2_OFFSET) != 0 ||
3934 addr + L2_SIZE > end_addr)
3936 dst_l2pg = pmap_alloc_l2(dst_pmap, addr, NULL);
3937 if (dst_l2pg == NULL)
3940 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_l2pg));
3941 l2 = &l2[pmap_l2_index(addr)];
3942 if (pmap_load(l2) == 0 &&
3943 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
3944 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
3945 PMAP_ENTER_NORECLAIM, &lock))) {
3946 mask = ATTR_AF | ATTR_SW_WIRED;
3948 if ((srcptepaddr & ATTR_SW_DBM) != 0)
3949 nbits |= ATTR_AP_RW_BIT;
3950 pmap_store(l2, (srcptepaddr & ~mask) | nbits);
3951 pmap_resident_count_inc(dst_pmap, L2_SIZE /
3953 atomic_add_long(&pmap_l2_mappings, 1);
3955 dst_l2pg->wire_count--;
3958 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
3959 ("pmap_copy: invalid L2 entry"));
3960 srcptepaddr &= ~ATTR_MASK;
3961 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
3962 KASSERT(srcmpte->wire_count > 0,
3963 ("pmap_copy: source page table page is unused"));
3964 if (va_next > end_addr)
3966 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
3967 src_pte = &src_pte[pmap_l3_index(addr)];
3969 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
3970 ptetemp = pmap_load(src_pte);
3973 * We only virtual copy managed pages.
3975 if ((ptetemp & ATTR_SW_MANAGED) == 0)
3978 if (dstmpte != NULL) {
3979 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
3980 ("dstmpte pindex/addr mismatch"));
3981 dstmpte->wire_count++;
3982 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
3985 dst_pte = (pt_entry_t *)
3986 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
3987 dst_pte = &dst_pte[pmap_l3_index(addr)];
3988 if (pmap_load(dst_pte) == 0 &&
3989 pmap_try_insert_pv_entry(dst_pmap, addr,
3990 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
3992 * Clear the wired, modified, and accessed
3993 * (referenced) bits during the copy.
3995 mask = ATTR_AF | ATTR_SW_WIRED;
3997 if ((ptetemp & ATTR_SW_DBM) != 0)
3998 nbits |= ATTR_AP_RW_BIT;
3999 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
4000 pmap_resident_count_inc(dst_pmap, 1);
4003 if (pmap_unwire_l3(dst_pmap, addr, dstmpte,
4006 * Although "addr" is not mapped,
4007 * the TLB could nonetheless have
4008 * intermediate entries that refer
4009 * to the freed page table pages.
4010 * Invalidate those entries.
4012 * XXX redundant invalidation
4014 pmap_invalidate_page(dst_pmap, addr);
4015 vm_page_free_pages_toq(&free, true);
4019 /* Have we copied all of the valid mappings? */
4020 if (dstmpte->wire_count >= srcmpte->wire_count)
4026 * XXX This barrier may not be needed because the destination pmap is
4033 PMAP_UNLOCK(src_pmap);
4034 PMAP_UNLOCK(dst_pmap);
4038 * pmap_zero_page zeros the specified hardware page by mapping
4039 * the page into KVM and using bzero to clear its contents.
4042 pmap_zero_page(vm_page_t m)
4044 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4046 pagezero((void *)va);
4050 * pmap_zero_page_area zeros the specified hardware page by mapping
4051 * the page into KVM and using bzero to clear its contents.
4053 * off and size may not cover an area beyond a single hardware page.
4056 pmap_zero_page_area(vm_page_t m, int off, int size)
4058 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4060 if (off == 0 && size == PAGE_SIZE)
4061 pagezero((void *)va);
4063 bzero((char *)va + off, size);
4067 * pmap_copy_page copies the specified (machine independent)
4068 * page by mapping the page into virtual memory and using
4069 * bcopy to copy the page, one machine dependent page at a
4073 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4075 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4076 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4078 pagecopy((void *)src, (void *)dst);
4081 int unmapped_buf_allowed = 1;
4084 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4085 vm_offset_t b_offset, int xfersize)
4089 vm_paddr_t p_a, p_b;
4090 vm_offset_t a_pg_offset, b_pg_offset;
4093 while (xfersize > 0) {
4094 a_pg_offset = a_offset & PAGE_MASK;
4095 m_a = ma[a_offset >> PAGE_SHIFT];
4096 p_a = m_a->phys_addr;
4097 b_pg_offset = b_offset & PAGE_MASK;
4098 m_b = mb[b_offset >> PAGE_SHIFT];
4099 p_b = m_b->phys_addr;
4100 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4101 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4102 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
4103 panic("!DMAP a %lx", p_a);
4105 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
4107 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
4108 panic("!DMAP b %lx", p_b);
4110 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
4112 bcopy(a_cp, b_cp, cnt);
4120 pmap_quick_enter_page(vm_page_t m)
4123 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
4127 pmap_quick_remove_page(vm_offset_t addr)
4132 * Returns true if the pmap's pv is one of the first
4133 * 16 pvs linked to from this page. This count may
4134 * be changed upwards or downwards in the future; it
4135 * is only necessary that true be returned for a small
4136 * subset of pmaps for proper page aging.
4139 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4141 struct md_page *pvh;
4142 struct rwlock *lock;
4147 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4148 ("pmap_page_exists_quick: page %p is not managed", m));
4150 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4152 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4153 if (PV_PMAP(pv) == pmap) {
4161 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4162 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4163 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4164 if (PV_PMAP(pv) == pmap) {
4178 * pmap_page_wired_mappings:
4180 * Return the number of managed mappings to the given physical page
4184 pmap_page_wired_mappings(vm_page_t m)
4186 struct rwlock *lock;
4187 struct md_page *pvh;
4191 int count, lvl, md_gen, pvh_gen;
4193 if ((m->oflags & VPO_UNMANAGED) != 0)
4195 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4199 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4201 if (!PMAP_TRYLOCK(pmap)) {
4202 md_gen = m->md.pv_gen;
4206 if (md_gen != m->md.pv_gen) {
4211 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4212 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4216 if ((m->flags & PG_FICTITIOUS) == 0) {
4217 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4218 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4220 if (!PMAP_TRYLOCK(pmap)) {
4221 md_gen = m->md.pv_gen;
4222 pvh_gen = pvh->pv_gen;
4226 if (md_gen != m->md.pv_gen ||
4227 pvh_gen != pvh->pv_gen) {
4232 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4234 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4244 * Destroy all managed, non-wired mappings in the given user-space
4245 * pmap. This pmap cannot be active on any processor besides the
4248 * This function cannot be applied to the kernel pmap. Moreover, it
4249 * is not intended for general use. It is only to be used during
4250 * process termination. Consequently, it can be implemented in ways
4251 * that make it faster than pmap_remove(). First, it can more quickly
4252 * destroy mappings by iterating over the pmap's collection of PV
4253 * entries, rather than searching the page table. Second, it doesn't
4254 * have to test and clear the page table entries atomically, because
4255 * no processor is currently accessing the user address space. In
4256 * particular, a page table entry's dirty bit won't change state once
4257 * this function starts.
4260 pmap_remove_pages(pmap_t pmap)
4263 pt_entry_t *pte, tpte;
4264 struct spglist free;
4265 vm_page_t m, ml3, mt;
4267 struct md_page *pvh;
4268 struct pv_chunk *pc, *npc;
4269 struct rwlock *lock;
4271 uint64_t inuse, bitmask;
4272 int allfree, field, freed, idx, lvl;
4279 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4282 for (field = 0; field < _NPCM; field++) {
4283 inuse = ~pc->pc_map[field] & pc_freemask[field];
4284 while (inuse != 0) {
4285 bit = ffsl(inuse) - 1;
4286 bitmask = 1UL << bit;
4287 idx = field * 64 + bit;
4288 pv = &pc->pc_pventry[idx];
4291 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4292 KASSERT(pde != NULL,
4293 ("Attempting to remove an unmapped page"));
4297 pte = pmap_l1_to_l2(pde, pv->pv_va);
4298 tpte = pmap_load(pte);
4299 KASSERT((tpte & ATTR_DESCR_MASK) ==
4301 ("Attempting to remove an invalid "
4302 "block: %lx", tpte));
4303 tpte = pmap_load(pte);
4306 pte = pmap_l2_to_l3(pde, pv->pv_va);
4307 tpte = pmap_load(pte);
4308 KASSERT((tpte & ATTR_DESCR_MASK) ==
4310 ("Attempting to remove an invalid "
4311 "page: %lx", tpte));
4315 "Invalid page directory level: %d",
4320 * We cannot remove wired pages from a process' mapping at this time
4322 if (tpte & ATTR_SW_WIRED) {
4327 pa = tpte & ~ATTR_MASK;
4329 m = PHYS_TO_VM_PAGE(pa);
4330 KASSERT(m->phys_addr == pa,
4331 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4332 m, (uintmax_t)m->phys_addr,
4335 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4336 m < &vm_page_array[vm_page_array_size],
4337 ("pmap_remove_pages: bad pte %#jx",
4341 * Because this pmap is not active on other
4342 * processors, the dirty bit cannot have
4343 * changed state since we last loaded pte.
4348 * Update the vm_page_t clean/reference bits.
4350 if (pmap_pte_dirty(tpte)) {
4353 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4362 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4365 pc->pc_map[field] |= bitmask;
4368 pmap_resident_count_dec(pmap,
4369 L2_SIZE / PAGE_SIZE);
4370 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
4371 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
4373 if (TAILQ_EMPTY(&pvh->pv_list)) {
4374 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4375 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
4376 TAILQ_EMPTY(&mt->md.pv_list))
4377 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4379 ml3 = pmap_remove_pt_page(pmap,
4382 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
4383 ("pmap_remove_pages: l3 page not promoted"));
4384 pmap_resident_count_dec(pmap,1);
4385 KASSERT(ml3->wire_count == NL3PG,
4386 ("pmap_remove_pages: l3 page wire count error"));
4387 ml3->wire_count = 0;
4388 pmap_add_delayed_free_list(ml3,
4393 pmap_resident_count_dec(pmap, 1);
4394 TAILQ_REMOVE(&m->md.pv_list, pv,
4397 if ((m->aflags & PGA_WRITEABLE) != 0 &&
4398 TAILQ_EMPTY(&m->md.pv_list) &&
4399 (m->flags & PG_FICTITIOUS) == 0) {
4401 VM_PAGE_TO_PHYS(m));
4402 if (TAILQ_EMPTY(&pvh->pv_list))
4403 vm_page_aflag_clear(m,
4408 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
4413 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4414 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4415 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4417 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4421 pmap_invalidate_all(pmap);
4425 vm_page_free_pages_toq(&free, true);
4429 * This is used to check if a page has been accessed or modified. As we
4430 * don't have a bit to see if it has been modified we have to assume it
4431 * has been if the page is read/write.
4434 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
4436 struct rwlock *lock;
4438 struct md_page *pvh;
4439 pt_entry_t *pte, mask, value;
4441 int lvl, md_gen, pvh_gen;
4445 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4448 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4450 if (!PMAP_TRYLOCK(pmap)) {
4451 md_gen = m->md.pv_gen;
4455 if (md_gen != m->md.pv_gen) {
4460 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4462 ("pmap_page_test_mappings: Invalid level %d", lvl));
4466 mask |= ATTR_AP_RW_BIT;
4467 value |= ATTR_AP(ATTR_AP_RW);
4470 mask |= ATTR_AF | ATTR_DESCR_MASK;
4471 value |= ATTR_AF | L3_PAGE;
4473 rv = (pmap_load(pte) & mask) == value;
4478 if ((m->flags & PG_FICTITIOUS) == 0) {
4479 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4480 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4482 if (!PMAP_TRYLOCK(pmap)) {
4483 md_gen = m->md.pv_gen;
4484 pvh_gen = pvh->pv_gen;
4488 if (md_gen != m->md.pv_gen ||
4489 pvh_gen != pvh->pv_gen) {
4494 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4496 ("pmap_page_test_mappings: Invalid level %d", lvl));
4500 mask |= ATTR_AP_RW_BIT;
4501 value |= ATTR_AP(ATTR_AP_RW);
4504 mask |= ATTR_AF | ATTR_DESCR_MASK;
4505 value |= ATTR_AF | L2_BLOCK;
4507 rv = (pmap_load(pte) & mask) == value;
4521 * Return whether or not the specified physical page was modified
4522 * in any physical maps.
4525 pmap_is_modified(vm_page_t m)
4528 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4529 ("pmap_is_modified: page %p is not managed", m));
4532 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4533 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4534 * is clear, no PTEs can have PG_M set.
4536 VM_OBJECT_ASSERT_WLOCKED(m->object);
4537 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4539 return (pmap_page_test_mappings(m, FALSE, TRUE));
4543 * pmap_is_prefaultable:
4545 * Return whether or not the specified virtual address is eligible
4549 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4557 pte = pmap_pte(pmap, addr, &lvl);
4558 if (pte != NULL && pmap_load(pte) != 0) {
4566 * pmap_is_referenced:
4568 * Return whether or not the specified physical page was referenced
4569 * in any physical maps.
4572 pmap_is_referenced(vm_page_t m)
4575 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4576 ("pmap_is_referenced: page %p is not managed", m));
4577 return (pmap_page_test_mappings(m, TRUE, FALSE));
4581 * Clear the write and modified bits in each of the given page's mappings.
4584 pmap_remove_write(vm_page_t m)
4586 struct md_page *pvh;
4588 struct rwlock *lock;
4589 pv_entry_t next_pv, pv;
4590 pt_entry_t oldpte, *pte;
4592 int lvl, md_gen, pvh_gen;
4594 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4595 ("pmap_remove_write: page %p is not managed", m));
4598 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4599 * set by another thread while the object is locked. Thus,
4600 * if PGA_WRITEABLE is clear, no page table entries need updating.
4602 VM_OBJECT_ASSERT_WLOCKED(m->object);
4603 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4605 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4606 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4607 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4610 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4612 if (!PMAP_TRYLOCK(pmap)) {
4613 pvh_gen = pvh->pv_gen;
4617 if (pvh_gen != pvh->pv_gen) {
4624 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4625 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
4626 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
4627 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4628 ("inconsistent pv lock %p %p for page %p",
4629 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4632 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4634 if (!PMAP_TRYLOCK(pmap)) {
4635 pvh_gen = pvh->pv_gen;
4636 md_gen = m->md.pv_gen;
4640 if (pvh_gen != pvh->pv_gen ||
4641 md_gen != m->md.pv_gen) {
4647 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4648 oldpte = pmap_load(pte);
4650 if ((oldpte & ATTR_SW_DBM) != 0) {
4651 if (!atomic_fcmpset_long(pte, &oldpte,
4652 (oldpte | ATTR_AP_RW_BIT) & ~ATTR_SW_DBM))
4654 if ((oldpte & ATTR_AP_RW_BIT) ==
4655 ATTR_AP(ATTR_AP_RW))
4657 pmap_invalidate_page(pmap, pv->pv_va);
4662 vm_page_aflag_clear(m, PGA_WRITEABLE);
4666 * pmap_ts_referenced:
4668 * Return a count of reference bits for a page, clearing those bits.
4669 * It is not necessary for every reference bit to be cleared, but it
4670 * is necessary that 0 only be returned when there are truly no
4671 * reference bits set.
4673 * As an optimization, update the page's dirty field if a modified bit is
4674 * found while counting reference bits. This opportunistic update can be
4675 * performed at low cost and can eliminate the need for some future calls
4676 * to pmap_is_modified(). However, since this function stops after
4677 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4678 * dirty pages. Those dirty pages will only be detected by a future call
4679 * to pmap_is_modified().
4682 pmap_ts_referenced(vm_page_t m)
4684 struct md_page *pvh;
4687 struct rwlock *lock;
4688 pd_entry_t *pde, tpde;
4689 pt_entry_t *pte, tpte;
4692 int cleared, lvl, md_gen, not_cleared, pvh_gen;
4693 struct spglist free;
4695 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4696 ("pmap_ts_referenced: page %p is not managed", m));
4699 pa = VM_PAGE_TO_PHYS(m);
4700 lock = PHYS_TO_PV_LIST_LOCK(pa);
4701 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4705 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4706 goto small_mappings;
4712 if (!PMAP_TRYLOCK(pmap)) {
4713 pvh_gen = pvh->pv_gen;
4717 if (pvh_gen != pvh->pv_gen) {
4723 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4724 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4726 ("pmap_ts_referenced: invalid pde level %d", lvl));
4727 tpde = pmap_load(pde);
4728 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4729 ("pmap_ts_referenced: found an invalid l1 table"));
4730 pte = pmap_l1_to_l2(pde, pv->pv_va);
4731 tpte = pmap_load(pte);
4732 if (pmap_pte_dirty(tpte)) {
4734 * Although "tpte" is mapping a 2MB page, because
4735 * this function is called at a 4KB page granularity,
4736 * we only update the 4KB page under test.
4741 if ((tpte & ATTR_AF) != 0) {
4743 * Since this reference bit is shared by 512 4KB pages,
4744 * it should not be cleared every time it is tested.
4745 * Apply a simple "hash" function on the physical page
4746 * number, the virtual superpage number, and the pmap
4747 * address to select one 4KB page out of the 512 on
4748 * which testing the reference bit will result in
4749 * clearing that reference bit. This function is
4750 * designed to avoid the selection of the same 4KB page
4751 * for every 2MB page mapping.
4753 * On demotion, a mapping that hasn't been referenced
4754 * is simply destroyed. To avoid the possibility of a
4755 * subsequent page fault on a demoted wired mapping,
4756 * always leave its reference bit set. Moreover,
4757 * since the superpage is wired, the current state of
4758 * its reference bit won't affect page replacement.
4760 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4761 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4762 (tpte & ATTR_SW_WIRED) == 0) {
4763 pmap_clear_bits(pte, ATTR_AF);
4764 pmap_invalidate_page(pmap, pv->pv_va);
4770 /* Rotate the PV list if it has more than one entry. */
4771 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4772 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4773 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4776 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4778 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4780 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4787 if (!PMAP_TRYLOCK(pmap)) {
4788 pvh_gen = pvh->pv_gen;
4789 md_gen = m->md.pv_gen;
4793 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4798 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4799 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4801 ("pmap_ts_referenced: invalid pde level %d", lvl));
4802 tpde = pmap_load(pde);
4803 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4804 ("pmap_ts_referenced: found an invalid l2 table"));
4805 pte = pmap_l2_to_l3(pde, pv->pv_va);
4806 tpte = pmap_load(pte);
4807 if (pmap_pte_dirty(tpte))
4809 if ((tpte & ATTR_AF) != 0) {
4810 if ((tpte & ATTR_SW_WIRED) == 0) {
4811 pmap_clear_bits(pte, ATTR_AF);
4812 pmap_invalidate_page(pmap, pv->pv_va);
4818 /* Rotate the PV list if it has more than one entry. */
4819 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4820 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4821 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4824 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4825 not_cleared < PMAP_TS_REFERENCED_MAX);
4828 vm_page_free_pages_toq(&free, true);
4829 return (cleared + not_cleared);
4833 * Apply the given advice to the specified range of addresses within the
4834 * given pmap. Depending on the advice, clear the referenced and/or
4835 * modified flags in each mapping and set the mapped page's dirty field.
4838 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4840 struct rwlock *lock;
4841 vm_offset_t va, va_next;
4843 pd_entry_t *l0, *l1, *l2, oldl2;
4844 pt_entry_t *l3, oldl3;
4846 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4850 for (; sva < eva; sva = va_next) {
4851 l0 = pmap_l0(pmap, sva);
4852 if (pmap_load(l0) == 0) {
4853 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
4858 l1 = pmap_l0_to_l1(l0, sva);
4859 if (pmap_load(l1) == 0) {
4860 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
4865 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
4868 l2 = pmap_l1_to_l2(l1, sva);
4869 oldl2 = pmap_load(l2);
4872 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
4873 if ((oldl2 & ATTR_SW_MANAGED) == 0)
4876 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
4881 * The 2MB page mapping was destroyed.
4887 * Unless the page mappings are wired, remove the
4888 * mapping to a single page so that a subsequent
4889 * access may repromote. Choosing the last page
4890 * within the address range [sva, min(va_next, eva))
4891 * generally results in more repromotions. Since the
4892 * underlying page table page is fully populated, this
4893 * removal never frees a page table page.
4895 if ((oldl2 & ATTR_SW_WIRED) == 0) {
4901 ("pmap_advise: no address gap"));
4902 l3 = pmap_l2_to_l3(l2, va);
4903 KASSERT(pmap_load(l3) != 0,
4904 ("pmap_advise: invalid PTE"));
4905 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
4911 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
4912 ("pmap_advise: invalid L2 entry after demotion"));
4916 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
4918 oldl3 = pmap_load(l3);
4919 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
4920 (ATTR_SW_MANAGED | L3_PAGE))
4922 else if (pmap_pte_dirty(oldl3)) {
4923 if (advice == MADV_DONTNEED) {
4925 * Future calls to pmap_is_modified()
4926 * can be avoided by making the page
4929 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK);
4932 while (!atomic_fcmpset_long(l3, &oldl3,
4933 (oldl3 & ~ATTR_AF) | ATTR_AP(ATTR_AP_RO)))
4935 } else if ((oldl3 & ATTR_AF) != 0)
4936 pmap_clear_bits(l3, ATTR_AF);
4943 if (va != va_next) {
4944 pmap_invalidate_range(pmap, va, sva);
4949 pmap_invalidate_range(pmap, va, sva);
4955 * Clear the modify bits on the specified physical page.
4958 pmap_clear_modify(vm_page_t m)
4960 struct md_page *pvh;
4961 struct rwlock *lock;
4963 pv_entry_t next_pv, pv;
4964 pd_entry_t *l2, oldl2;
4965 pt_entry_t *l3, oldl3;
4967 int md_gen, pvh_gen;
4969 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4970 ("pmap_clear_modify: page %p is not managed", m));
4971 VM_OBJECT_ASSERT_WLOCKED(m->object);
4972 KASSERT(!vm_page_xbusied(m),
4973 ("pmap_clear_modify: page %p is exclusive busied", m));
4976 * If the page is not PGA_WRITEABLE, then no PTEs can have ATTR_SW_DBM
4977 * set. If the object containing the page is locked and the page is not
4978 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4980 if ((m->aflags & PGA_WRITEABLE) == 0)
4982 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4983 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4984 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4987 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4989 if (!PMAP_TRYLOCK(pmap)) {
4990 pvh_gen = pvh->pv_gen;
4994 if (pvh_gen != pvh->pv_gen) {
5000 l2 = pmap_l2(pmap, va);
5001 oldl2 = pmap_load(l2);
5002 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */
5003 if ((oldl2 & ATTR_SW_DBM) != 0 &&
5004 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
5005 (oldl2 & ATTR_SW_WIRED) == 0) {
5007 * Write protect the mapping to a single page so that
5008 * a subsequent write access may repromote.
5010 va += VM_PAGE_TO_PHYS(m) - (oldl2 & ~ATTR_MASK);
5011 l3 = pmap_l2_to_l3(l2, va);
5012 oldl3 = pmap_load(l3);
5013 while (!atomic_fcmpset_long(l3, &oldl3,
5014 (oldl3 & ~ATTR_SW_DBM) | ATTR_AP(ATTR_AP_RO)))
5017 pmap_invalidate_page(pmap, va);
5021 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5023 if (!PMAP_TRYLOCK(pmap)) {
5024 md_gen = m->md.pv_gen;
5025 pvh_gen = pvh->pv_gen;
5029 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5034 l2 = pmap_l2(pmap, pv->pv_va);
5035 l3 = pmap_l2_to_l3(l2, pv->pv_va);
5036 oldl3 = pmap_load(l3);
5037 if (pmap_l3_valid(oldl3) &&
5038 (oldl3 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM) {
5039 pmap_set_bits(l3, ATTR_AP(ATTR_AP_RO));
5040 pmap_invalidate_page(pmap, pv->pv_va);
5048 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5050 struct pmap_preinit_mapping *ppim;
5051 vm_offset_t va, offset;
5054 int i, lvl, l2_blocks, free_l2_count, start_idx;
5056 if (!vm_initialized) {
5058 * No L3 ptables so map entire L2 blocks where start VA is:
5059 * preinit_map_va + start_idx * L2_SIZE
5060 * There may be duplicate mappings (multiple VA -> same PA) but
5061 * ARM64 dcache is always PIPT so that's acceptable.
5066 /* Calculate how many L2 blocks are needed for the mapping */
5067 l2_blocks = (roundup2(pa + size, L2_SIZE) -
5068 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
5070 offset = pa & L2_OFFSET;
5072 if (preinit_map_va == 0)
5075 /* Map 2MiB L2 blocks from reserved VA space */
5079 /* Find enough free contiguous VA space */
5080 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5081 ppim = pmap_preinit_mapping + i;
5082 if (free_l2_count > 0 && ppim->pa != 0) {
5083 /* Not enough space here */
5089 if (ppim->pa == 0) {
5091 if (start_idx == -1)
5094 if (free_l2_count == l2_blocks)
5098 if (free_l2_count != l2_blocks)
5099 panic("%s: too many preinit mappings", __func__);
5101 va = preinit_map_va + (start_idx * L2_SIZE);
5102 for (i = start_idx; i < start_idx + l2_blocks; i++) {
5103 /* Mark entries as allocated */
5104 ppim = pmap_preinit_mapping + i;
5106 ppim->va = va + offset;
5111 pa = rounddown2(pa, L2_SIZE);
5112 for (i = 0; i < l2_blocks; i++) {
5113 pde = pmap_pde(kernel_pmap, va, &lvl);
5114 KASSERT(pde != NULL,
5115 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
5118 ("pmap_mapbios: Invalid level %d", lvl));
5120 /* Insert L2_BLOCK */
5121 l2 = pmap_l1_to_l2(pde, va);
5123 pa | ATTR_DEFAULT | ATTR_XN |
5124 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
5129 pmap_invalidate_all(kernel_pmap);
5131 va = preinit_map_va + (start_idx * L2_SIZE);
5134 /* kva_alloc may be used to map the pages */
5135 offset = pa & PAGE_MASK;
5136 size = round_page(offset + size);
5138 va = kva_alloc(size);
5140 panic("%s: Couldn't allocate KVA", __func__);
5142 pde = pmap_pde(kernel_pmap, va, &lvl);
5143 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
5145 /* L3 table is linked */
5146 va = trunc_page(va);
5147 pa = trunc_page(pa);
5148 pmap_kenter(va, size, pa, CACHED_MEMORY);
5151 return ((void *)(va + offset));
5155 pmap_unmapbios(vm_offset_t va, vm_size_t size)
5157 struct pmap_preinit_mapping *ppim;
5158 vm_offset_t offset, tmpsize, va_trunc;
5161 int i, lvl, l2_blocks, block;
5165 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
5166 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
5168 /* Remove preinit mapping */
5169 preinit_map = false;
5171 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5172 ppim = pmap_preinit_mapping + i;
5173 if (ppim->va == va) {
5174 KASSERT(ppim->size == size,
5175 ("pmap_unmapbios: size mismatch"));
5180 offset = block * L2_SIZE;
5181 va_trunc = rounddown2(va, L2_SIZE) + offset;
5183 /* Remove L2_BLOCK */
5184 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
5185 KASSERT(pde != NULL,
5186 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
5188 l2 = pmap_l1_to_l2(pde, va_trunc);
5191 if (block == (l2_blocks - 1))
5197 pmap_invalidate_all(kernel_pmap);
5201 /* Unmap the pages reserved with kva_alloc. */
5202 if (vm_initialized) {
5203 offset = va & PAGE_MASK;
5204 size = round_page(offset + size);
5205 va = trunc_page(va);
5207 pde = pmap_pde(kernel_pmap, va, &lvl);
5208 KASSERT(pde != NULL,
5209 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
5210 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
5212 /* Unmap and invalidate the pages */
5213 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5214 pmap_kremove(va + tmpsize);
5221 * Sets the memory attribute for the specified page.
5224 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5227 m->md.pv_memattr = ma;
5230 * If "m" is a normal page, update its direct mapping. This update
5231 * can be relied upon to perform any cache operations that are
5232 * required for data coherence.
5234 if ((m->flags & PG_FICTITIOUS) == 0 &&
5235 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
5236 m->md.pv_memattr) != 0)
5237 panic("memory attribute change on the direct map failed");
5241 * Changes the specified virtual address range's memory type to that given by
5242 * the parameter "mode". The specified virtual address range must be
5243 * completely contained within either the direct map or the kernel map. If
5244 * the virtual address range is contained within the kernel map, then the
5245 * memory type for each of the corresponding ranges of the direct map is also
5246 * changed. (The corresponding ranges of the direct map are those ranges that
5247 * map the same physical pages as the specified virtual address range.) These
5248 * changes to the direct map are necessary because Intel describes the
5249 * behavior of their processors as "undefined" if two or more mappings to the
5250 * same physical page have different memory types.
5252 * Returns zero if the change completed successfully, and either EINVAL or
5253 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5254 * of the virtual address range was not mapped, and ENOMEM is returned if
5255 * there was insufficient memory available to complete the change. In the
5256 * latter case, the memory type may have been changed on some part of the
5257 * virtual address range or the direct map.
5260 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5264 PMAP_LOCK(kernel_pmap);
5265 error = pmap_change_attr_locked(va, size, mode);
5266 PMAP_UNLOCK(kernel_pmap);
5271 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
5273 vm_offset_t base, offset, tmpva;
5274 pt_entry_t l3, *pte, *newpte;
5277 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
5278 base = trunc_page(va);
5279 offset = va & PAGE_MASK;
5280 size = round_page(offset + size);
5282 if (!VIRT_IN_DMAP(base))
5285 for (tmpva = base; tmpva < base + size; ) {
5286 pte = pmap_pte(kernel_pmap, tmpva, &lvl);
5290 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
5292 * We already have the correct attribute,
5293 * ignore this entry.
5297 panic("Invalid DMAP table level: %d\n", lvl);
5299 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
5302 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
5310 * Split the entry to an level 3 table, then
5311 * set the new attribute.
5315 panic("Invalid DMAP table level: %d\n", lvl);
5317 newpte = pmap_demote_l1(kernel_pmap, pte,
5318 tmpva & ~L1_OFFSET);
5321 pte = pmap_l1_to_l2(pte, tmpva);
5323 newpte = pmap_demote_l2(kernel_pmap, pte,
5327 pte = pmap_l2_to_l3(pte, tmpva);
5329 /* Update the entry */
5330 l3 = pmap_load(pte);
5331 l3 &= ~ATTR_IDX_MASK;
5332 l3 |= ATTR_IDX(mode);
5333 if (mode == DEVICE_MEMORY)
5336 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
5340 * If moving to a non-cacheable entry flush
5343 if (mode == VM_MEMATTR_UNCACHEABLE)
5344 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
5356 * Create an L2 table to map all addresses within an L1 mapping.
5359 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
5361 pt_entry_t *l2, newl2, oldl1;
5363 vm_paddr_t l2phys, phys;
5367 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5368 oldl1 = pmap_load(l1);
5369 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
5370 ("pmap_demote_l1: Demoting a non-block entry"));
5371 KASSERT((va & L1_OFFSET) == 0,
5372 ("pmap_demote_l1: Invalid virtual address %#lx", va));
5373 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
5374 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
5377 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
5378 tmpl1 = kva_alloc(PAGE_SIZE);
5383 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
5384 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
5385 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
5386 " in pmap %p", va, pmap);
5390 l2phys = VM_PAGE_TO_PHYS(ml2);
5391 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
5393 /* Address the range points at */
5394 phys = oldl1 & ~ATTR_MASK;
5395 /* The attributed from the old l1 table to be copied */
5396 newl2 = oldl1 & ATTR_MASK;
5398 /* Create the new entries */
5399 for (i = 0; i < Ln_ENTRIES; i++) {
5400 l2[i] = newl2 | phys;
5403 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
5404 ("Invalid l2 page (%lx != %lx)", l2[0],
5405 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
5408 pmap_kenter(tmpl1, PAGE_SIZE,
5409 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY);
5410 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
5413 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
5416 pmap_kremove(tmpl1);
5417 kva_free(tmpl1, PAGE_SIZE);
5424 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
5428 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
5435 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
5436 struct rwlock **lockp)
5438 struct spglist free;
5441 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
5443 vm_page_free_pages_toq(&free, true);
5447 * Create an L3 table to map all addresses within an L2 mapping.
5450 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
5451 struct rwlock **lockp)
5453 pt_entry_t *l3, newl3, oldl2;
5458 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5460 oldl2 = pmap_load(l2);
5461 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
5462 ("pmap_demote_l2: Demoting a non-block entry"));
5466 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
5467 tmpl2 = kva_alloc(PAGE_SIZE);
5473 * Invalidate the 2MB page mapping and return "failure" if the
5474 * mapping was never accessed.
5476 if ((oldl2 & ATTR_AF) == 0) {
5477 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5478 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
5479 pmap_demote_l2_abort(pmap, va, l2, lockp);
5480 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
5485 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
5486 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5487 ("pmap_demote_l2: page table page for a wired mapping"
5491 * If the page table page is missing and the mapping
5492 * is for a kernel address, the mapping must belong to
5493 * the direct map. Page table pages are preallocated
5494 * for every other part of the kernel address space,
5495 * so the direct map region is the only part of the
5496 * kernel address space that must be handled here.
5498 KASSERT(va < VM_MAXUSER_ADDRESS || VIRT_IN_DMAP(va),
5499 ("pmap_demote_l2: No saved mpte for va %#lx", va));
5502 * If the 2MB page mapping belongs to the direct map
5503 * region of the kernel's address space, then the page
5504 * allocation request specifies the highest possible
5505 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5506 * priority is normal.
5508 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
5509 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5510 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5513 * If the allocation of the new page table page fails,
5514 * invalidate the 2MB page mapping and return "failure".
5517 pmap_demote_l2_abort(pmap, va, l2, lockp);
5518 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
5519 " in pmap %p", va, pmap);
5523 if (va < VM_MAXUSER_ADDRESS) {
5524 ml3->wire_count = NL3PG;
5525 pmap_resident_count_inc(pmap, 1);
5528 l3phys = VM_PAGE_TO_PHYS(ml3);
5529 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
5530 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
5531 KASSERT((oldl2 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) !=
5532 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM),
5533 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
5536 * If the page table page is not leftover from an earlier promotion,
5537 * or the mapping attributes have changed, (re)initialize the L3 table.
5539 * When pmap_update_entry() clears the old L2 mapping, it (indirectly)
5540 * performs a dsb(). That dsb() ensures that the stores for filling
5541 * "l3" are visible before "l3" is added to the page table.
5543 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK))
5544 pmap_fill_l3(l3, newl3);
5547 * Map the temporary page so we don't lose access to the l2 table.
5550 pmap_kenter(tmpl2, PAGE_SIZE,
5551 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY);
5552 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
5556 * The spare PV entries must be reserved prior to demoting the
5557 * mapping, that is, prior to changing the PDE. Otherwise, the state
5558 * of the L2 and the PV lists will be inconsistent, which can result
5559 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5560 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
5561 * PV entry for the 2MB page mapping that is being demoted.
5563 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5564 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
5567 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
5568 * the 2MB page mapping.
5570 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
5573 * Demote the PV entry.
5575 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5576 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
5578 atomic_add_long(&pmap_l2_demotions, 1);
5579 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
5580 " in pmap %p %lx", va, pmap, l3[0]);
5584 pmap_kremove(tmpl2);
5585 kva_free(tmpl2, PAGE_SIZE);
5593 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
5595 struct rwlock *lock;
5599 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
5606 * perform the pmap work for mincore
5609 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5611 pt_entry_t *pte, tpte;
5612 vm_paddr_t mask, pa;
5619 pte = pmap_pte(pmap, addr, &lvl);
5621 tpte = pmap_load(pte);
5634 panic("pmap_mincore: invalid level %d", lvl);
5637 managed = (tpte & ATTR_SW_MANAGED) != 0;
5638 val = MINCORE_INCORE;
5640 val |= MINCORE_SUPER;
5641 if ((managed && pmap_pte_dirty(tpte)) || (!managed &&
5642 (tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)))
5643 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5644 if ((tpte & ATTR_AF) == ATTR_AF)
5645 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5647 pa = (tpte & ~ATTR_MASK) | (addr & mask);
5651 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5652 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
5653 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5654 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5657 PA_UNLOCK_COND(*locked_pa);
5664 pmap_activate(struct thread *td)
5669 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5670 td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0);
5672 "msr ttbr0_el1, %0 \n"
5674 : : "r"(td->td_proc->p_md.md_l0addr));
5675 pmap_invalidate_all(pmap);
5680 pmap_switch(struct thread *old, struct thread *new)
5682 pcpu_bp_harden bp_harden;
5685 /* Store the new curthread */
5686 PCPU_SET(curthread, new);
5688 /* And the new pcb */
5690 PCPU_SET(curpcb, pcb);
5693 * TODO: We may need to flush the cache here if switching
5694 * to a user process.
5698 old->td_proc->p_md.md_l0addr != new->td_proc->p_md.md_l0addr) {
5700 /* Switch to the new pmap */
5701 "msr ttbr0_el1, %0 \n"
5704 /* Invalidate the TLB */
5709 : : "r"(new->td_proc->p_md.md_l0addr));
5712 * Stop userspace from training the branch predictor against
5713 * other processes. This will call into a CPU specific
5714 * function that clears the branch predictor state.
5716 bp_harden = PCPU_GET(bp_harden);
5717 if (bp_harden != NULL)
5725 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
5728 if (va >= VM_MIN_KERNEL_ADDRESS) {
5729 cpu_icache_sync_range(va, sz);
5734 /* Find the length of data in this page to flush */
5735 offset = va & PAGE_MASK;
5736 len = imin(PAGE_SIZE - offset, sz);
5739 /* Extract the physical address & find it in the DMAP */
5740 pa = pmap_extract(pmap, va);
5742 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
5744 /* Move to the next page */
5747 /* Set the length for the next iteration */
5748 len = imin(PAGE_SIZE, sz);
5754 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
5756 pt_entry_t pte, *ptep;
5763 ec = ESR_ELx_EXCEPTION(esr);
5765 case EXCP_INSN_ABORT_L:
5766 case EXCP_INSN_ABORT:
5767 case EXCP_DATA_ABORT_L:
5768 case EXCP_DATA_ABORT:
5774 /* Data and insn aborts use same encoding for FSC field. */
5775 switch (esr & ISS_DATA_DFSC_MASK) {
5776 case ISS_DATA_DFSC_AFF_L1:
5777 case ISS_DATA_DFSC_AFF_L2:
5778 case ISS_DATA_DFSC_AFF_L3:
5780 ptep = pmap_pte(pmap, far, &lvl);
5782 pmap_set_bits(ptep, ATTR_AF);
5785 * XXXMJ as an optimization we could mark the entry
5786 * dirty if this is a write fault.
5791 case ISS_DATA_DFSC_PF_L1:
5792 case ISS_DATA_DFSC_PF_L2:
5793 case ISS_DATA_DFSC_PF_L3:
5794 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
5795 (esr & ISS_DATA_WnR) == 0)
5798 ptep = pmap_pte(pmap, far, &lvl);
5800 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
5801 if ((pte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RO)) {
5802 pmap_clear_bits(ptep, ATTR_AP_RW_BIT);
5803 pmap_invalidate_page(pmap, far);
5809 case ISS_DATA_DFSC_TF_L0:
5810 case ISS_DATA_DFSC_TF_L1:
5811 case ISS_DATA_DFSC_TF_L2:
5812 case ISS_DATA_DFSC_TF_L3:
5814 * Retry the translation. A break-before-make sequence can
5815 * produce a transient fault.
5817 if (pmap == kernel_pmap) {
5819 * The translation fault may have occurred within a
5820 * critical section. Therefore, we must check the
5821 * address without acquiring the kernel pmap's lock.
5823 if (pmap_kextract(far) != 0)
5827 /* Ask the MMU to check the address. */
5828 intr = intr_disable();
5829 par = arm64_address_translate_s1e0r(far);
5834 * If the translation was successful, then we can
5835 * return success to the trap handler.
5837 if (PAR_SUCCESS(par))
5847 * Increase the starting virtual address of the given mapping if a
5848 * different alignment might result in more superpage mappings.
5851 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5852 vm_offset_t *addr, vm_size_t size)
5854 vm_offset_t superpage_offset;
5858 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5859 offset += ptoa(object->pg_color);
5860 superpage_offset = offset & L2_OFFSET;
5861 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
5862 (*addr & L2_OFFSET) == superpage_offset)
5864 if ((*addr & L2_OFFSET) < superpage_offset)
5865 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
5867 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
5871 * Get the kernel virtual address of a set of physical pages. If there are
5872 * physical addresses not covered by the DMAP perform a transient mapping
5873 * that will be removed when calling pmap_unmap_io_transient.
5875 * \param page The pages the caller wishes to obtain the virtual
5876 * address on the kernel memory map.
5877 * \param vaddr On return contains the kernel virtual memory address
5878 * of the pages passed in the page parameter.
5879 * \param count Number of pages passed in.
5880 * \param can_fault TRUE if the thread using the mapped pages can take
5881 * page faults, FALSE otherwise.
5883 * \returns TRUE if the caller must call pmap_unmap_io_transient when
5884 * finished or FALSE otherwise.
5888 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
5889 boolean_t can_fault)
5892 boolean_t needs_mapping;
5896 * Allocate any KVA space that we need, this is done in a separate
5897 * loop to prevent calling vmem_alloc while pinned.
5899 needs_mapping = FALSE;
5900 for (i = 0; i < count; i++) {
5901 paddr = VM_PAGE_TO_PHYS(page[i]);
5902 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
5903 error = vmem_alloc(kernel_arena, PAGE_SIZE,
5904 M_BESTFIT | M_WAITOK, &vaddr[i]);
5905 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
5906 needs_mapping = TRUE;
5908 vaddr[i] = PHYS_TO_DMAP(paddr);
5912 /* Exit early if everything is covered by the DMAP */
5918 for (i = 0; i < count; i++) {
5919 paddr = VM_PAGE_TO_PHYS(page[i]);
5920 if (!PHYS_IN_DMAP(paddr)) {
5922 "pmap_map_io_transient: TODO: Map out of DMAP data");
5926 return (needs_mapping);
5930 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
5931 boolean_t can_fault)
5938 for (i = 0; i < count; i++) {
5939 paddr = VM_PAGE_TO_PHYS(page[i]);
5940 if (!PHYS_IN_DMAP(paddr)) {
5941 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
5947 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
5950 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);