2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/msgbuf.h>
120 #include <sys/mutex.h>
121 #include <sys/proc.h>
122 #include <sys/rwlock.h>
124 #include <sys/vmem.h>
125 #include <sys/vmmeter.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/_unrhdr.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/vm_pager.h>
140 #include <vm/vm_phys.h>
141 #include <vm/vm_radix.h>
142 #include <vm/vm_reserv.h>
145 #include <machine/machdep.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
149 #include <arm/include/physmem.h>
151 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
152 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
153 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
154 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
156 #define NUL0E L0_ENTRIES
157 #define NUL1E (NUL0E * NL1PG)
158 #define NUL2E (NUL1E * NL2PG)
160 #if !defined(DIAGNOSTIC)
161 #ifdef __GNUC_GNU_INLINE__
162 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
164 #define PMAP_INLINE extern inline
171 * These are configured by the mair_el1 register. This is set up in locore.S
173 #define DEVICE_MEMORY 0
174 #define UNCACHED_MEMORY 1
175 #define CACHED_MEMORY 2
179 #define PV_STAT(x) do { x ; } while (0)
181 #define PV_STAT(x) do { } while (0)
184 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
185 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
187 #define NPV_LIST_LOCKS MAXCPU
189 #define PHYS_TO_PV_LIST_LOCK(pa) \
190 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
192 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
193 struct rwlock **_lockp = (lockp); \
194 struct rwlock *_new_lock; \
196 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
197 if (_new_lock != *_lockp) { \
198 if (*_lockp != NULL) \
199 rw_wunlock(*_lockp); \
200 *_lockp = _new_lock; \
205 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
206 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
208 #define RELEASE_PV_LIST_LOCK(lockp) do { \
209 struct rwlock **_lockp = (lockp); \
211 if (*_lockp != NULL) { \
212 rw_wunlock(*_lockp); \
217 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
218 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
220 struct pmap kernel_pmap_store;
222 /* Used for mapping ACPI memory before VM is initialized */
223 #define PMAP_PREINIT_MAPPING_COUNT 32
224 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
225 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
226 static int vm_initialized = 0; /* No need to use pre-init maps when set */
229 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
230 * Always map entire L2 block for simplicity.
231 * VA of L2 block = preinit_map_va + i * L2_SIZE
233 static struct pmap_preinit_mapping {
237 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
239 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
240 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
241 vm_offset_t kernel_vm_end = 0;
244 * Data for the pv entry allocation mechanism.
245 * Updates to pv_invl_gen are protected by the pv_list_locks[]
246 * elements, but reads are not.
248 static struct md_page *pv_table;
249 static struct md_page pv_dummy;
251 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
252 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
253 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
255 /* This code assumes all L1 DMAP entries will be used */
256 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
257 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
259 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
260 extern pt_entry_t pagetable_dmap[];
262 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
264 static int superpages_enabled = 1;
265 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
266 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
267 "Are large page mappings enabled?");
270 * Data for the pv entry allocation mechanism
272 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
273 static struct mtx pv_chunks_mutex;
274 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
276 static void free_pv_chunk(struct pv_chunk *pc);
277 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
278 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
279 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
280 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
281 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
284 static int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode);
285 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
286 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
287 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
288 vm_offset_t va, struct rwlock **lockp);
289 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
290 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
291 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
292 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
293 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
294 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
295 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
296 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
297 vm_page_t m, struct rwlock **lockp);
299 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
300 struct rwlock **lockp);
302 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
303 struct spglist *free);
304 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
305 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
308 * These load the old table data and store the new value.
309 * They need to be atomic as the System MMU may write to the table at
310 * the same time as the CPU.
312 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
313 #define pmap_set(table, mask) atomic_set_64(table, mask)
314 #define pmap_load_clear(table) atomic_swap_64(table, 0)
315 #define pmap_load(table) (*table)
317 /********************/
318 /* Inline functions */
319 /********************/
322 pagecopy(void *s, void *d)
325 memcpy(d, s, PAGE_SIZE);
328 static __inline pd_entry_t *
329 pmap_l0(pmap_t pmap, vm_offset_t va)
332 return (&pmap->pm_l0[pmap_l0_index(va)]);
335 static __inline pd_entry_t *
336 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
340 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
341 return (&l1[pmap_l1_index(va)]);
344 static __inline pd_entry_t *
345 pmap_l1(pmap_t pmap, vm_offset_t va)
349 l0 = pmap_l0(pmap, va);
350 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
353 return (pmap_l0_to_l1(l0, va));
356 static __inline pd_entry_t *
357 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
361 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
362 return (&l2[pmap_l2_index(va)]);
365 static __inline pd_entry_t *
366 pmap_l2(pmap_t pmap, vm_offset_t va)
370 l1 = pmap_l1(pmap, va);
371 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
374 return (pmap_l1_to_l2(l1, va));
377 static __inline pt_entry_t *
378 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
382 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
383 return (&l3[pmap_l3_index(va)]);
387 * Returns the lowest valid pde for a given virtual address.
388 * The next level may or may not point to a valid page or block.
390 static __inline pd_entry_t *
391 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
393 pd_entry_t *l0, *l1, *l2, desc;
395 l0 = pmap_l0(pmap, va);
396 desc = pmap_load(l0) & ATTR_DESCR_MASK;
397 if (desc != L0_TABLE) {
402 l1 = pmap_l0_to_l1(l0, va);
403 desc = pmap_load(l1) & ATTR_DESCR_MASK;
404 if (desc != L1_TABLE) {
409 l2 = pmap_l1_to_l2(l1, va);
410 desc = pmap_load(l2) & ATTR_DESCR_MASK;
411 if (desc != L2_TABLE) {
421 * Returns the lowest valid pte block or table entry for a given virtual
422 * address. If there are no valid entries return NULL and set the level to
423 * the first invalid level.
425 static __inline pt_entry_t *
426 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
428 pd_entry_t *l1, *l2, desc;
431 l1 = pmap_l1(pmap, va);
436 desc = pmap_load(l1) & ATTR_DESCR_MASK;
437 if (desc == L1_BLOCK) {
442 if (desc != L1_TABLE) {
447 l2 = pmap_l1_to_l2(l1, va);
448 desc = pmap_load(l2) & ATTR_DESCR_MASK;
449 if (desc == L2_BLOCK) {
454 if (desc != L2_TABLE) {
460 l3 = pmap_l2_to_l3(l2, va);
461 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
468 pmap_superpages_enabled(void)
471 return (superpages_enabled != 0);
475 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
476 pd_entry_t **l2, pt_entry_t **l3)
478 pd_entry_t *l0p, *l1p, *l2p;
480 if (pmap->pm_l0 == NULL)
483 l0p = pmap_l0(pmap, va);
486 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
489 l1p = pmap_l0_to_l1(l0p, va);
492 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
498 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
501 l2p = pmap_l1_to_l2(l1p, va);
504 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
509 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
512 *l3 = pmap_l2_to_l3(l2p, va);
518 pmap_l3_valid(pt_entry_t l3)
521 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
525 CTASSERT(L1_BLOCK == L2_BLOCK);
528 * Checks if the page is dirty. We currently lack proper tracking of this on
529 * arm64 so for now assume is a page mapped as rw was accessed it is.
532 pmap_page_dirty(pt_entry_t pte)
535 return ((pte & (ATTR_AF | ATTR_AP_RW_BIT)) ==
536 (ATTR_AF | ATTR_AP(ATTR_AP_RW)));
540 pmap_resident_count_inc(pmap_t pmap, int count)
543 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
544 pmap->pm_stats.resident_count += count;
548 pmap_resident_count_dec(pmap_t pmap, int count)
551 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
552 KASSERT(pmap->pm_stats.resident_count >= count,
553 ("pmap %p resident count underflow %ld %d", pmap,
554 pmap->pm_stats.resident_count, count));
555 pmap->pm_stats.resident_count -= count;
559 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
565 l1 = (pd_entry_t *)l1pt;
566 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
568 /* Check locore has used a table L1 map */
569 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
570 ("Invalid bootstrap L1 table"));
571 /* Find the address of the L2 table */
572 l2 = (pt_entry_t *)init_pt_va;
573 *l2_slot = pmap_l2_index(va);
579 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
581 u_int l1_slot, l2_slot;
584 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
586 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
590 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa, vm_paddr_t max_pa)
597 dmap_phys_base = min_pa & ~L1_OFFSET;
601 for (i = 0; i < (physmap_idx * 2); i += 2) {
602 pa = physmap[i] & ~L1_OFFSET;
603 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
605 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
606 pa += L1_SIZE, va += L1_SIZE) {
607 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
608 /* We already have an entry */
609 if (pagetable_dmap[l1_slot] != 0)
611 pmap_load_store(&pagetable_dmap[l1_slot],
612 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
613 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
616 if (pa > dmap_phys_max) {
626 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
633 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
635 l1 = (pd_entry_t *)l1pt;
636 l1_slot = pmap_l1_index(va);
639 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
640 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
642 pa = pmap_early_vtophys(l1pt, l2pt);
643 pmap_load_store(&l1[l1_slot],
644 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
648 /* Clean the L2 page table */
649 memset((void *)l2_start, 0, l2pt - l2_start);
655 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
662 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
664 l2 = pmap_l2(kernel_pmap, va);
665 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
666 l2_slot = pmap_l2_index(va);
669 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
670 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
672 pa = pmap_early_vtophys(l1pt, l3pt);
673 pmap_load_store(&l2[l2_slot],
674 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
678 /* Clean the L2 page table */
679 memset((void *)l3_start, 0, l3pt - l3_start);
685 * Bootstrap the system enough to run with virtual memory.
688 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
691 u_int l1_slot, l2_slot;
694 vm_offset_t va, freemempos;
695 vm_offset_t dpcpu, msgbufpv;
696 vm_paddr_t start_pa, pa, max_pa, min_pa;
699 kern_delta = KERNBASE - kernstart;
701 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
702 printf("%lx\n", l1pt);
703 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
705 /* Set this early so we can use the pagetable walking functions */
706 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
707 PMAP_LOCK_INIT(kernel_pmap);
709 /* Assume the address we were loaded to is a valid physical address */
710 min_pa = max_pa = KERNBASE - kern_delta;
713 * Find the minimum physical address. physmap is sorted,
714 * but may contain empty ranges.
716 for (i = 0; i < (physmap_idx * 2); i += 2) {
717 if (physmap[i] == physmap[i + 1])
719 if (physmap[i] <= min_pa)
721 if (physmap[i + 1] > max_pa)
722 max_pa = physmap[i + 1];
725 /* Create a direct map region early so we can use it for pa -> va */
726 pmap_bootstrap_dmap(l1pt, min_pa, max_pa);
729 start_pa = pa = KERNBASE - kern_delta;
732 * Read the page table to find out what is already mapped.
733 * This assumes we have mapped a block of memory from KERNBASE
734 * using a single L1 entry.
736 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
738 /* Sanity check the index, KERNBASE should be the first VA */
739 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
741 /* Find how many pages we have mapped */
742 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
743 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
746 /* Check locore used L2 blocks */
747 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
748 ("Invalid bootstrap L2 table"));
749 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
750 ("Incorrect PA in L2 table"));
756 va = roundup2(va, L1_SIZE);
758 freemempos = KERNBASE + kernlen;
759 freemempos = roundup2(freemempos, PAGE_SIZE);
760 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
761 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
762 /* And the l3 tables for the early devmap */
763 freemempos = pmap_bootstrap_l3(l1pt,
764 VM_MAX_KERNEL_ADDRESS - L2_SIZE, freemempos);
768 #define alloc_pages(var, np) \
769 (var) = freemempos; \
770 freemempos += (np * PAGE_SIZE); \
771 memset((char *)(var), 0, ((np) * PAGE_SIZE));
773 /* Allocate dynamic per-cpu area. */
774 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
775 dpcpu_init((void *)dpcpu, 0);
777 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
778 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
779 msgbufp = (void *)msgbufpv;
781 /* Reserve some VA space for early BIOS/ACPI mapping */
782 preinit_map_va = roundup2(freemempos, L2_SIZE);
784 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
785 virtual_avail = roundup2(virtual_avail, L1_SIZE);
786 virtual_end = VM_MAX_KERNEL_ADDRESS - L2_SIZE;
787 kernel_vm_end = virtual_avail;
789 pa = pmap_early_vtophys(l1pt, freemempos);
791 arm_physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
797 * Initialize a vm_page's machine-dependent fields.
800 pmap_page_init(vm_page_t m)
803 TAILQ_INIT(&m->md.pv_list);
804 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
808 * Initialize the pmap module.
809 * Called by vm_init, to initialize any structures that the pmap
810 * system needs to map virtual memory.
819 * Are large page mappings enabled?
821 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
824 * Initialize the pv chunk list mutex.
826 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
829 * Initialize the pool of pv list locks.
831 for (i = 0; i < NPV_LIST_LOCKS; i++)
832 rw_init(&pv_list_locks[i], "pmap pv list");
835 * Calculate the size of the pv head table for superpages.
837 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
840 * Allocate memory for the pv head table for superpages.
842 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
844 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
846 for (i = 0; i < pv_npg; i++)
847 TAILQ_INIT(&pv_table[i].pv_list);
848 TAILQ_INIT(&pv_dummy.pv_list);
853 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
854 "2MB page mapping counters");
856 static u_long pmap_l2_demotions;
857 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
858 &pmap_l2_demotions, 0, "2MB page demotions");
860 static u_long pmap_l2_p_failures;
861 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
862 &pmap_l2_p_failures, 0, "2MB page promotion failures");
864 static u_long pmap_l2_promotions;
865 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
866 &pmap_l2_promotions, 0, "2MB page promotions");
869 * Invalidate a single TLB entry.
872 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
878 "tlbi vaae1is, %0 \n"
881 : : "r"(va >> PAGE_SHIFT));
886 pmap_invalidate_range_nopin(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
891 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
893 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
901 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
905 pmap_invalidate_range_nopin(pmap, sva, eva);
910 pmap_invalidate_all(pmap_t pmap)
923 * Routine: pmap_extract
925 * Extract the physical page address associated
926 * with the given map/virtual_address pair.
929 pmap_extract(pmap_t pmap, vm_offset_t va)
931 pt_entry_t *pte, tpte;
938 * Find the block or page map for this virtual address. pmap_pte
939 * will return either a valid block/page entry, or NULL.
941 pte = pmap_pte(pmap, va, &lvl);
943 tpte = pmap_load(pte);
944 pa = tpte & ~ATTR_MASK;
947 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
948 ("pmap_extract: Invalid L1 pte found: %lx",
949 tpte & ATTR_DESCR_MASK));
950 pa |= (va & L1_OFFSET);
953 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
954 ("pmap_extract: Invalid L2 pte found: %lx",
955 tpte & ATTR_DESCR_MASK));
956 pa |= (va & L2_OFFSET);
959 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
960 ("pmap_extract: Invalid L3 pte found: %lx",
961 tpte & ATTR_DESCR_MASK));
962 pa |= (va & L3_OFFSET);
971 * Routine: pmap_extract_and_hold
973 * Atomically extract and hold the physical page
974 * with the given pmap and virtual address pair
975 * if that mapping permits the given protection.
978 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
980 pt_entry_t *pte, tpte;
990 pte = pmap_pte(pmap, va, &lvl);
992 tpte = pmap_load(pte);
994 KASSERT(lvl > 0 && lvl <= 3,
995 ("pmap_extract_and_hold: Invalid level %d", lvl));
996 CTASSERT(L1_BLOCK == L2_BLOCK);
997 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
998 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
999 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1000 tpte & ATTR_DESCR_MASK));
1001 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1002 ((prot & VM_PROT_WRITE) == 0)) {
1005 off = va & L1_OFFSET;
1008 off = va & L2_OFFSET;
1014 if (vm_page_pa_tryrelock(pmap,
1015 (tpte & ~ATTR_MASK) | off, &pa))
1017 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1027 pmap_kextract(vm_offset_t va)
1029 pt_entry_t *pte, tpte;
1033 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1034 pa = DMAP_TO_PHYS(va);
1037 pte = pmap_pte(kernel_pmap, va, &lvl);
1039 tpte = pmap_load(pte);
1040 pa = tpte & ~ATTR_MASK;
1043 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1044 ("pmap_kextract: Invalid L1 pte found: %lx",
1045 tpte & ATTR_DESCR_MASK));
1046 pa |= (va & L1_OFFSET);
1049 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1050 ("pmap_kextract: Invalid L2 pte found: %lx",
1051 tpte & ATTR_DESCR_MASK));
1052 pa |= (va & L2_OFFSET);
1055 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1056 ("pmap_kextract: Invalid L3 pte found: %lx",
1057 tpte & ATTR_DESCR_MASK));
1058 pa |= (va & L3_OFFSET);
1066 /***************************************************
1067 * Low level mapping routines.....
1068 ***************************************************/
1071 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1074 pt_entry_t *pte, attr;
1078 KASSERT((pa & L3_OFFSET) == 0,
1079 ("pmap_kenter: Invalid physical address"));
1080 KASSERT((sva & L3_OFFSET) == 0,
1081 ("pmap_kenter: Invalid virtual address"));
1082 KASSERT((size & PAGE_MASK) == 0,
1083 ("pmap_kenter: Mapping is not page-sized"));
1085 attr = ATTR_DEFAULT | ATTR_IDX(mode) | L3_PAGE;
1086 if (mode == DEVICE_MEMORY)
1091 pde = pmap_pde(kernel_pmap, va, &lvl);
1092 KASSERT(pde != NULL,
1093 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1094 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1096 pte = pmap_l2_to_l3(pde, va);
1097 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1103 pmap_invalidate_range(kernel_pmap, sva, va);
1107 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1110 pmap_kenter(sva, size, pa, DEVICE_MEMORY);
1114 * Remove a page from the kernel pagetables.
1117 pmap_kremove(vm_offset_t va)
1122 pte = pmap_pte(kernel_pmap, va, &lvl);
1123 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1124 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1126 pmap_load_clear(pte);
1127 pmap_invalidate_page(kernel_pmap, va);
1131 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1137 KASSERT((sva & L3_OFFSET) == 0,
1138 ("pmap_kremove_device: Invalid virtual address"));
1139 KASSERT((size & PAGE_MASK) == 0,
1140 ("pmap_kremove_device: Mapping is not page-sized"));
1144 pte = pmap_pte(kernel_pmap, va, &lvl);
1145 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1147 ("Invalid device pagetable level: %d != 3", lvl));
1148 pmap_load_clear(pte);
1153 pmap_invalidate_range(kernel_pmap, sva, va);
1157 * Used to map a range of physical addresses into kernel
1158 * virtual address space.
1160 * The value passed in '*virt' is a suggested virtual address for
1161 * the mapping. Architectures which can support a direct-mapped
1162 * physical to virtual region can return the appropriate address
1163 * within that region, leaving '*virt' unchanged. Other
1164 * architectures should map the pages starting at '*virt' and
1165 * update '*virt' with the first usable address after the mapped
1169 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1171 return PHYS_TO_DMAP(start);
1176 * Add a list of wired pages to the kva
1177 * this routine is only used for temporary
1178 * kernel mappings that do not need to have
1179 * page modification or references recorded.
1180 * Note that old mappings are simply written
1181 * over. The page *must* be wired.
1182 * Note: SMP coherent. Uses a ranged shootdown IPI.
1185 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1188 pt_entry_t *pte, pa;
1194 for (i = 0; i < count; i++) {
1195 pde = pmap_pde(kernel_pmap, va, &lvl);
1196 KASSERT(pde != NULL,
1197 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1199 ("pmap_qenter: Invalid level %d", lvl));
1202 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1203 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1204 if (m->md.pv_memattr == DEVICE_MEMORY)
1206 pte = pmap_l2_to_l3(pde, va);
1207 pmap_load_store(pte, pa);
1211 pmap_invalidate_range(kernel_pmap, sva, va);
1215 * This routine tears out page mappings from the
1216 * kernel -- it is meant only for temporary mappings.
1219 pmap_qremove(vm_offset_t sva, int count)
1225 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1228 while (count-- > 0) {
1229 pte = pmap_pte(kernel_pmap, va, &lvl);
1231 ("Invalid device pagetable level: %d != 3", lvl));
1233 pmap_load_clear(pte);
1238 pmap_invalidate_range(kernel_pmap, sva, va);
1241 /***************************************************
1242 * Page table page management routines.....
1243 ***************************************************/
1245 * Schedule the specified unused page table page to be freed. Specifically,
1246 * add the page to the specified list of pages that will be released to the
1247 * physical memory manager after the TLB has been updated.
1249 static __inline void
1250 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1251 boolean_t set_PG_ZERO)
1255 m->flags |= PG_ZERO;
1257 m->flags &= ~PG_ZERO;
1258 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1262 * Decrements a page table page's wire count, which is used to record the
1263 * number of valid page table entries within the page. If the wire count
1264 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1265 * page table page was unmapped and FALSE otherwise.
1267 static inline boolean_t
1268 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1272 if (m->wire_count == 0) {
1273 _pmap_unwire_l3(pmap, va, m, free);
1280 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1283 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1285 * unmap the page table page
1287 if (m->pindex >= (NUL2E + NUL1E)) {
1291 l0 = pmap_l0(pmap, va);
1292 pmap_load_clear(l0);
1293 } else if (m->pindex >= NUL2E) {
1297 l1 = pmap_l1(pmap, va);
1298 pmap_load_clear(l1);
1303 l2 = pmap_l2(pmap, va);
1304 pmap_load_clear(l2);
1306 pmap_resident_count_dec(pmap, 1);
1307 if (m->pindex < NUL2E) {
1308 /* We just released an l3, unhold the matching l2 */
1309 pd_entry_t *l1, tl1;
1312 l1 = pmap_l1(pmap, va);
1313 tl1 = pmap_load(l1);
1314 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1315 pmap_unwire_l3(pmap, va, l2pg, free);
1316 } else if (m->pindex < (NUL2E + NUL1E)) {
1317 /* We just released an l2, unhold the matching l1 */
1318 pd_entry_t *l0, tl0;
1321 l0 = pmap_l0(pmap, va);
1322 tl0 = pmap_load(l0);
1323 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1324 pmap_unwire_l3(pmap, va, l1pg, free);
1326 pmap_invalidate_page(pmap, va);
1331 * Put page on a list so that it is released after
1332 * *ALL* TLB shootdown is done
1334 pmap_add_delayed_free_list(m, free, TRUE);
1338 * After removing a page table entry, this routine is used to
1339 * conditionally free the page, and manage the hold/wire counts.
1342 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1343 struct spglist *free)
1347 if (va >= VM_MAXUSER_ADDRESS)
1349 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1350 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1351 return (pmap_unwire_l3(pmap, va, mpte, free));
1355 pmap_pinit0(pmap_t pmap)
1358 PMAP_LOCK_INIT(pmap);
1359 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1360 pmap->pm_l0 = kernel_pmap->pm_l0;
1361 pmap->pm_root.rt_root = 0;
1365 pmap_pinit(pmap_t pmap)
1371 * allocate the l0 page
1373 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1374 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1377 l0phys = VM_PAGE_TO_PHYS(l0pt);
1378 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1380 if ((l0pt->flags & PG_ZERO) == 0)
1381 pagezero(pmap->pm_l0);
1383 pmap->pm_root.rt_root = 0;
1384 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1390 * This routine is called if the desired page table page does not exist.
1392 * If page table page allocation fails, this routine may sleep before
1393 * returning NULL. It sleeps only if a lock pointer was given.
1395 * Note: If a page allocation fails at page table level two or three,
1396 * one or two pages may be held during the wait, only to be released
1397 * afterwards. This conservative approach is easily argued to avoid
1401 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1403 vm_page_t m, l1pg, l2pg;
1405 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1408 * Allocate a page table page.
1410 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1411 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1412 if (lockp != NULL) {
1413 RELEASE_PV_LIST_LOCK(lockp);
1420 * Indicate the need to retry. While waiting, the page table
1421 * page may have been allocated.
1425 if ((m->flags & PG_ZERO) == 0)
1429 * Map the pagetable page into the process address space, if
1430 * it isn't already there.
1433 if (ptepindex >= (NUL2E + NUL1E)) {
1435 vm_pindex_t l0index;
1437 l0index = ptepindex - (NUL2E + NUL1E);
1438 l0 = &pmap->pm_l0[l0index];
1439 pmap_load_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1440 } else if (ptepindex >= NUL2E) {
1441 vm_pindex_t l0index, l1index;
1442 pd_entry_t *l0, *l1;
1445 l1index = ptepindex - NUL2E;
1446 l0index = l1index >> L0_ENTRIES_SHIFT;
1448 l0 = &pmap->pm_l0[l0index];
1449 tl0 = pmap_load(l0);
1451 /* recurse for allocating page dir */
1452 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1454 vm_page_unwire_noq(m);
1455 vm_page_free_zero(m);
1459 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1463 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1464 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1465 pmap_load_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1467 vm_pindex_t l0index, l1index;
1468 pd_entry_t *l0, *l1, *l2;
1469 pd_entry_t tl0, tl1;
1471 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1472 l0index = l1index >> L0_ENTRIES_SHIFT;
1474 l0 = &pmap->pm_l0[l0index];
1475 tl0 = pmap_load(l0);
1477 /* recurse for allocating page dir */
1478 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1480 vm_page_unwire_noq(m);
1481 vm_page_free_zero(m);
1484 tl0 = pmap_load(l0);
1485 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1486 l1 = &l1[l1index & Ln_ADDR_MASK];
1488 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1489 l1 = &l1[l1index & Ln_ADDR_MASK];
1490 tl1 = pmap_load(l1);
1492 /* recurse for allocating page dir */
1493 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1495 vm_page_unwire_noq(m);
1496 vm_page_free_zero(m);
1500 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1505 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1506 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1507 pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1510 pmap_resident_count_inc(pmap, 1);
1516 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1518 vm_pindex_t ptepindex;
1519 pd_entry_t *pde, tpde;
1527 * Calculate pagetable page index
1529 ptepindex = pmap_l2_pindex(va);
1532 * Get the page directory entry
1534 pde = pmap_pde(pmap, va, &lvl);
1537 * If the page table page is mapped, we just increment the hold count,
1538 * and activate it. If we get a level 2 pde it will point to a level 3
1546 pte = pmap_l0_to_l1(pde, va);
1547 KASSERT(pmap_load(pte) == 0,
1548 ("pmap_alloc_l3: TODO: l0 superpages"));
1553 pte = pmap_l1_to_l2(pde, va);
1554 KASSERT(pmap_load(pte) == 0,
1555 ("pmap_alloc_l3: TODO: l1 superpages"));
1559 tpde = pmap_load(pde);
1561 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1567 panic("pmap_alloc_l3: Invalid level %d", lvl);
1571 * Here if the pte page isn't mapped, or if it has been deallocated.
1573 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1574 if (m == NULL && lockp != NULL)
1581 /***************************************************
1582 * Pmap allocation/deallocation routines.
1583 ***************************************************/
1586 * Release any resources held by the given physical map.
1587 * Called when a pmap initialized by pmap_pinit is being released.
1588 * Should only be called if the map contains no valid mappings.
1591 pmap_release(pmap_t pmap)
1595 KASSERT(pmap->pm_stats.resident_count == 0,
1596 ("pmap_release: pmap resident count %ld != 0",
1597 pmap->pm_stats.resident_count));
1598 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1599 ("pmap_release: pmap has reserved page table page(s)"));
1601 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1603 vm_page_unwire_noq(m);
1604 vm_page_free_zero(m);
1608 kvm_size(SYSCTL_HANDLER_ARGS)
1610 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1612 return sysctl_handle_long(oidp, &ksize, 0, req);
1614 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1615 0, 0, kvm_size, "LU", "Size of KVM");
1618 kvm_free(SYSCTL_HANDLER_ARGS)
1620 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1622 return sysctl_handle_long(oidp, &kfree, 0, req);
1624 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1625 0, 0, kvm_free, "LU", "Amount of KVM free");
1628 * grow the number of kernel page table entries, if needed
1631 pmap_growkernel(vm_offset_t addr)
1635 pd_entry_t *l0, *l1, *l2;
1637 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1639 addr = roundup2(addr, L2_SIZE);
1640 if (addr - 1 >= kernel_map->max_offset)
1641 addr = kernel_map->max_offset;
1642 while (kernel_vm_end < addr) {
1643 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1644 KASSERT(pmap_load(l0) != 0,
1645 ("pmap_growkernel: No level 0 kernel entry"));
1647 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1648 if (pmap_load(l1) == 0) {
1649 /* We need a new PDP entry */
1650 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1651 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1652 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1654 panic("pmap_growkernel: no memory to grow kernel");
1655 if ((nkpg->flags & PG_ZERO) == 0)
1656 pmap_zero_page(nkpg);
1657 paddr = VM_PAGE_TO_PHYS(nkpg);
1658 pmap_load_store(l1, paddr | L1_TABLE);
1659 continue; /* try again */
1661 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1662 if ((pmap_load(l2) & ATTR_AF) != 0) {
1663 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1664 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1665 kernel_vm_end = kernel_map->max_offset;
1671 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1672 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1675 panic("pmap_growkernel: no memory to grow kernel");
1676 if ((nkpg->flags & PG_ZERO) == 0)
1677 pmap_zero_page(nkpg);
1678 paddr = VM_PAGE_TO_PHYS(nkpg);
1679 pmap_load_store(l2, paddr | L2_TABLE);
1680 pmap_invalidate_page(kernel_pmap, kernel_vm_end);
1682 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1683 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1684 kernel_vm_end = kernel_map->max_offset;
1691 /***************************************************
1692 * page management routines.
1693 ***************************************************/
1695 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1696 CTASSERT(_NPCM == 3);
1697 CTASSERT(_NPCPV == 168);
1699 static __inline struct pv_chunk *
1700 pv_to_chunk(pv_entry_t pv)
1703 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1706 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1708 #define PC_FREE0 0xfffffffffffffffful
1709 #define PC_FREE1 0xfffffffffffffffful
1710 #define PC_FREE2 0x000000fffffffffful
1712 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1716 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1718 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1719 "Current number of pv entry chunks");
1720 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1721 "Current number of pv entry chunks allocated");
1722 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1723 "Current number of pv entry chunks frees");
1724 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1725 "Number of times tried to get a chunk page but failed.");
1727 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1728 static int pv_entry_spare;
1730 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1731 "Current number of pv entry frees");
1732 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1733 "Current number of pv entry allocs");
1734 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1735 "Current number of pv entries");
1736 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1737 "Current number of spare pv entries");
1742 * We are in a serious low memory condition. Resort to
1743 * drastic measures to free some pages so we can allocate
1744 * another pv entry chunk.
1746 * Returns NULL if PV entries were reclaimed from the specified pmap.
1748 * We do not, however, unmap 2mpages because subsequent accesses will
1749 * allocate per-page pv entries until repromotion occurs, thereby
1750 * exacerbating the shortage of free pv entries.
1753 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1755 struct pch new_tail;
1756 struct pv_chunk *pc;
1757 struct md_page *pvh;
1760 pt_entry_t *pte, tpte;
1764 struct spglist free;
1766 int bit, field, freed, lvl;
1768 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1769 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
1773 TAILQ_INIT(&new_tail);
1774 mtx_lock(&pv_chunks_mutex);
1775 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) {
1776 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1777 mtx_unlock(&pv_chunks_mutex);
1778 if (pmap != pc->pc_pmap) {
1779 if (pmap != NULL && pmap != locked_pmap)
1782 /* Avoid deadlock and lock recursion. */
1783 if (pmap > locked_pmap) {
1784 RELEASE_PV_LIST_LOCK(lockp);
1786 } else if (pmap != locked_pmap &&
1787 !PMAP_TRYLOCK(pmap)) {
1789 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1790 mtx_lock(&pv_chunks_mutex);
1796 * Destroy every non-wired, 4 KB page mapping in the chunk.
1799 for (field = 0; field < _NPCM; field++) {
1800 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1801 inuse != 0; inuse &= ~(1UL << bit)) {
1802 bit = ffsl(inuse) - 1;
1803 pv = &pc->pc_pventry[field * 64 + bit];
1805 pde = pmap_pde(pmap, va, &lvl);
1808 pte = pmap_l2_to_l3(pde, va);
1809 tpte = pmap_load(pte);
1810 if ((tpte & ATTR_SW_WIRED) != 0)
1812 tpte = pmap_load_clear(pte);
1813 pmap_invalidate_page(pmap, va);
1814 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
1815 if (pmap_page_dirty(tpte))
1817 if ((tpte & ATTR_AF) != 0)
1818 vm_page_aflag_set(m, PGA_REFERENCED);
1819 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1820 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
1822 if (TAILQ_EMPTY(&m->md.pv_list) &&
1823 (m->flags & PG_FICTITIOUS) == 0) {
1824 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
1825 if (TAILQ_EMPTY(&pvh->pv_list)) {
1826 vm_page_aflag_clear(m,
1830 pc->pc_map[field] |= 1UL << bit;
1831 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
1836 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1837 mtx_lock(&pv_chunks_mutex);
1840 /* Every freed mapping is for a 4 KB page. */
1841 pmap_resident_count_dec(pmap, freed);
1842 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
1843 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
1844 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
1845 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1846 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
1847 pc->pc_map[2] == PC_FREE2) {
1848 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1849 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1850 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1851 /* Entire chunk is free; return it. */
1852 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1853 dump_drop_page(m_pc->phys_addr);
1854 mtx_lock(&pv_chunks_mutex);
1857 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1858 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1859 mtx_lock(&pv_chunks_mutex);
1860 /* One freed pv entry in locked_pmap is sufficient. */
1861 if (pmap == locked_pmap)
1864 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
1865 mtx_unlock(&pv_chunks_mutex);
1866 if (pmap != NULL && pmap != locked_pmap)
1868 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
1869 m_pc = SLIST_FIRST(&free);
1870 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
1871 /* Recycle a freed page table page. */
1872 m_pc->wire_count = 1;
1875 vm_page_free_pages_toq(&free, false);
1880 * free the pv_entry back to the free list
1883 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1885 struct pv_chunk *pc;
1886 int idx, field, bit;
1888 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1889 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
1890 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
1891 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
1892 pc = pv_to_chunk(pv);
1893 idx = pv - &pc->pc_pventry[0];
1896 pc->pc_map[field] |= 1ul << bit;
1897 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
1898 pc->pc_map[2] != PC_FREE2) {
1899 /* 98% of the time, pc is already at the head of the list. */
1900 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
1901 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1902 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1906 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1911 free_pv_chunk(struct pv_chunk *pc)
1915 mtx_lock(&pv_chunks_mutex);
1916 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1917 mtx_unlock(&pv_chunks_mutex);
1918 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1919 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1920 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1921 /* entire chunk is free, return it */
1922 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1923 dump_drop_page(m->phys_addr);
1924 vm_page_unwire_noq(m);
1929 * Returns a new PV entry, allocating a new PV chunk from the system when
1930 * needed. If this PV chunk allocation fails and a PV list lock pointer was
1931 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
1934 * The given PV list lock may be released.
1937 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
1941 struct pv_chunk *pc;
1944 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1945 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
1947 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1949 for (field = 0; field < _NPCM; field++) {
1950 if (pc->pc_map[field]) {
1951 bit = ffsl(pc->pc_map[field]) - 1;
1955 if (field < _NPCM) {
1956 pv = &pc->pc_pventry[field * 64 + bit];
1957 pc->pc_map[field] &= ~(1ul << bit);
1958 /* If this was the last item, move it to tail */
1959 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
1960 pc->pc_map[2] == 0) {
1961 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1962 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
1965 PV_STAT(atomic_add_long(&pv_entry_count, 1));
1966 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
1970 /* No free items, allocate another chunk */
1971 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1974 if (lockp == NULL) {
1975 PV_STAT(pc_chunk_tryfail++);
1978 m = reclaim_pv_chunk(pmap, lockp);
1982 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
1983 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
1984 dump_add_page(m->phys_addr);
1985 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
1987 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
1988 pc->pc_map[1] = PC_FREE1;
1989 pc->pc_map[2] = PC_FREE2;
1990 mtx_lock(&pv_chunks_mutex);
1991 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
1992 mtx_unlock(&pv_chunks_mutex);
1993 pv = &pc->pc_pventry[0];
1994 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1995 PV_STAT(atomic_add_long(&pv_entry_count, 1));
1996 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2001 * Ensure that the number of spare PV entries in the specified pmap meets or
2002 * exceeds the given count, "needed".
2004 * The given PV list lock may be released.
2007 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2009 struct pch new_tail;
2010 struct pv_chunk *pc;
2014 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2015 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2018 * Newly allocated PV chunks must be stored in a private list until
2019 * the required number of PV chunks have been allocated. Otherwise,
2020 * reclaim_pv_chunk() could recycle one of these chunks. In
2021 * contrast, these chunks must be added to the pmap upon allocation.
2023 TAILQ_INIT(&new_tail);
2026 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2027 bit_count((bitstr_t *)pc->pc_map, 0,
2028 sizeof(pc->pc_map) * NBBY, &free);
2032 if (avail >= needed)
2035 for (; avail < needed; avail += _NPCPV) {
2036 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2039 m = reclaim_pv_chunk(pmap, lockp);
2043 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2044 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2045 dump_add_page(m->phys_addr);
2046 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2048 pc->pc_map[0] = PC_FREE0;
2049 pc->pc_map[1] = PC_FREE1;
2050 pc->pc_map[2] = PC_FREE2;
2051 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2052 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2053 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2055 if (!TAILQ_EMPTY(&new_tail)) {
2056 mtx_lock(&pv_chunks_mutex);
2057 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2058 mtx_unlock(&pv_chunks_mutex);
2063 * First find and then remove the pv entry for the specified pmap and virtual
2064 * address from the specified pv list. Returns the pv entry if found and NULL
2065 * otherwise. This operation can be performed on pv lists for either 4KB or
2066 * 2MB page mappings.
2068 static __inline pv_entry_t
2069 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2073 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2074 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2075 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2084 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2085 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2086 * entries for each of the 4KB page mappings.
2089 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2090 struct rwlock **lockp)
2092 struct md_page *pvh;
2093 struct pv_chunk *pc;
2095 vm_offset_t va_last;
2099 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2100 KASSERT((pa & L2_OFFSET) == 0,
2101 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2102 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2105 * Transfer the 2mpage's pv entry for this mapping to the first
2106 * page's pv list. Once this transfer begins, the pv list lock
2107 * must not be released until the last pv entry is reinstantiated.
2109 pvh = pa_to_pvh(pa);
2110 va = va & ~L2_OFFSET;
2111 pv = pmap_pvh_remove(pvh, pmap, va);
2112 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2113 m = PHYS_TO_VM_PAGE(pa);
2114 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2116 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2117 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2118 va_last = va + L2_SIZE - PAGE_SIZE;
2120 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2121 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2122 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2123 for (field = 0; field < _NPCM; field++) {
2124 while (pc->pc_map[field]) {
2125 bit = ffsl(pc->pc_map[field]) - 1;
2126 pc->pc_map[field] &= ~(1ul << bit);
2127 pv = &pc->pc_pventry[field * 64 + bit];
2131 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2132 ("pmap_pv_demote_l2: page %p is not managed", m));
2133 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2139 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2140 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2143 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2144 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2145 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2147 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2148 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2152 * First find and then destroy the pv entry for the specified pmap and virtual
2153 * address. This operation can be performed on pv lists for either 4KB or 2MB
2157 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2161 pv = pmap_pvh_remove(pvh, pmap, va);
2162 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2163 free_pv_entry(pmap, pv);
2167 * Conditionally create the PV entry for a 4KB page mapping if the required
2168 * memory can be allocated without resorting to reclamation.
2171 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2172 struct rwlock **lockp)
2176 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2177 /* Pass NULL instead of the lock pointer to disable reclamation. */
2178 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2180 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2181 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2189 * pmap_remove_l2: do the things to unmap a level 2 superpage in a process
2192 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2193 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2195 struct md_page *pvh;
2197 vm_offset_t eva, va;
2200 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2201 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2202 old_l2 = pmap_load_clear(l2);
2203 pmap_invalidate_range(pmap, sva, sva + L2_SIZE);
2204 if (old_l2 & ATTR_SW_WIRED)
2205 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2206 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2207 if (old_l2 & ATTR_SW_MANAGED) {
2208 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2209 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2210 pmap_pvh_free(pvh, pmap, sva);
2211 eva = sva + L2_SIZE;
2212 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2213 va < eva; va += PAGE_SIZE, m++) {
2214 if (pmap_page_dirty(old_l2))
2216 if (old_l2 & ATTR_AF)
2217 vm_page_aflag_set(m, PGA_REFERENCED);
2218 if (TAILQ_EMPTY(&m->md.pv_list) &&
2219 TAILQ_EMPTY(&pvh->pv_list))
2220 vm_page_aflag_clear(m, PGA_WRITEABLE);
2223 KASSERT(pmap != kernel_pmap,
2224 ("Attempting to remove an l2 kernel page"));
2225 ml3 = pmap_remove_pt_page(pmap, sva);
2227 pmap_resident_count_dec(pmap, 1);
2228 KASSERT(ml3->wire_count == NL3PG,
2229 ("pmap_remove_pages: l3 page wire count error"));
2230 ml3->wire_count = 1;
2231 vm_page_unwire_noq(ml3);
2232 pmap_add_delayed_free_list(ml3, free, FALSE);
2234 return (pmap_unuse_pt(pmap, sva, l1e, free));
2238 * pmap_remove_l3: do the things to unmap a page in a process
2241 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2242 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2244 struct md_page *pvh;
2248 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2249 old_l3 = pmap_load_clear(l3);
2250 pmap_invalidate_page(pmap, va);
2251 if (old_l3 & ATTR_SW_WIRED)
2252 pmap->pm_stats.wired_count -= 1;
2253 pmap_resident_count_dec(pmap, 1);
2254 if (old_l3 & ATTR_SW_MANAGED) {
2255 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2256 if (pmap_page_dirty(old_l3))
2258 if (old_l3 & ATTR_AF)
2259 vm_page_aflag_set(m, PGA_REFERENCED);
2260 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2261 pmap_pvh_free(&m->md, pmap, va);
2262 if (TAILQ_EMPTY(&m->md.pv_list) &&
2263 (m->flags & PG_FICTITIOUS) == 0) {
2264 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2265 if (TAILQ_EMPTY(&pvh->pv_list))
2266 vm_page_aflag_clear(m, PGA_WRITEABLE);
2269 return (pmap_unuse_pt(pmap, va, l2e, free));
2273 * Remove the given range of addresses from the specified map.
2275 * It is assumed that the start and end are properly
2276 * rounded to the page size.
2279 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2281 struct rwlock *lock;
2282 vm_offset_t va, va_next;
2283 pd_entry_t *l0, *l1, *l2;
2284 pt_entry_t l3_paddr, *l3;
2285 struct spglist free;
2288 * Perform an unsynchronized read. This is, however, safe.
2290 if (pmap->pm_stats.resident_count == 0)
2298 for (; sva < eva; sva = va_next) {
2300 if (pmap->pm_stats.resident_count == 0)
2303 l0 = pmap_l0(pmap, sva);
2304 if (pmap_load(l0) == 0) {
2305 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2311 l1 = pmap_l0_to_l1(l0, sva);
2312 if (pmap_load(l1) == 0) {
2313 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2320 * Calculate index for next page table.
2322 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2326 l2 = pmap_l1_to_l2(l1, sva);
2330 l3_paddr = pmap_load(l2);
2332 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2333 if (sva + L2_SIZE == va_next && eva >= va_next) {
2334 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2337 } else if (pmap_demote_l2_locked(pmap, l2,
2338 sva &~L2_OFFSET, &lock) == NULL)
2340 l3_paddr = pmap_load(l2);
2344 * Weed out invalid mappings.
2346 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2350 * Limit our scan to either the end of the va represented
2351 * by the current page table page, or to the end of the
2352 * range being removed.
2358 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2361 panic("l3 == NULL");
2362 if (pmap_load(l3) == 0) {
2363 if (va != va_next) {
2364 pmap_invalidate_range(pmap, va, sva);
2371 if (pmap_remove_l3(pmap, l3, sva, l3_paddr, &free,
2378 pmap_invalidate_range(pmap, va, sva);
2383 vm_page_free_pages_toq(&free, false);
2387 * Routine: pmap_remove_all
2389 * Removes this physical page from
2390 * all physical maps in which it resides.
2391 * Reflects back modify bits to the pager.
2394 * Original versions of this routine were very
2395 * inefficient because they iteratively called
2396 * pmap_remove (slow...)
2400 pmap_remove_all(vm_page_t m)
2402 struct md_page *pvh;
2405 struct rwlock *lock;
2406 pd_entry_t *pde, tpde;
2407 pt_entry_t *pte, tpte;
2409 struct spglist free;
2410 int lvl, pvh_gen, md_gen;
2412 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2413 ("pmap_remove_all: page %p is not managed", m));
2415 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2416 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2417 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2420 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2422 if (!PMAP_TRYLOCK(pmap)) {
2423 pvh_gen = pvh->pv_gen;
2427 if (pvh_gen != pvh->pv_gen) {
2434 pte = pmap_pte(pmap, va, &lvl);
2435 KASSERT(pte != NULL,
2436 ("pmap_remove_all: no page table entry found"));
2438 ("pmap_remove_all: invalid pte level %d", lvl));
2440 pmap_demote_l2_locked(pmap, pte, va, &lock);
2443 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2445 if (!PMAP_TRYLOCK(pmap)) {
2446 pvh_gen = pvh->pv_gen;
2447 md_gen = m->md.pv_gen;
2451 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2457 pmap_resident_count_dec(pmap, 1);
2459 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2460 KASSERT(pde != NULL,
2461 ("pmap_remove_all: no page directory entry found"));
2463 ("pmap_remove_all: invalid pde level %d", lvl));
2464 tpde = pmap_load(pde);
2466 pte = pmap_l2_to_l3(pde, pv->pv_va);
2467 tpte = pmap_load(pte);
2468 pmap_load_clear(pte);
2469 pmap_invalidate_page(pmap, pv->pv_va);
2470 if (tpte & ATTR_SW_WIRED)
2471 pmap->pm_stats.wired_count--;
2472 if ((tpte & ATTR_AF) != 0)
2473 vm_page_aflag_set(m, PGA_REFERENCED);
2476 * Update the vm_page_t clean and reference bits.
2478 if (pmap_page_dirty(tpte))
2480 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2481 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2483 free_pv_entry(pmap, pv);
2486 vm_page_aflag_clear(m, PGA_WRITEABLE);
2488 vm_page_free_pages_toq(&free, false);
2492 * Set the physical protection on the
2493 * specified range of this map as requested.
2496 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2498 vm_offset_t va, va_next;
2499 pd_entry_t *l0, *l1, *l2;
2500 pt_entry_t *l3p, l3, nbits;
2502 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
2503 if (prot == VM_PROT_NONE) {
2504 pmap_remove(pmap, sva, eva);
2508 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
2509 (VM_PROT_WRITE | VM_PROT_EXECUTE))
2513 for (; sva < eva; sva = va_next) {
2515 l0 = pmap_l0(pmap, sva);
2516 if (pmap_load(l0) == 0) {
2517 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2523 l1 = pmap_l0_to_l1(l0, sva);
2524 if (pmap_load(l1) == 0) {
2525 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2531 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2535 l2 = pmap_l1_to_l2(l1, sva);
2536 if (pmap_load(l2) == 0)
2539 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
2540 l3p = pmap_demote_l2(pmap, l2, sva);
2544 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
2545 ("pmap_protect: Invalid L2 entry after demotion"));
2551 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2553 l3 = pmap_load(l3p);
2554 if (!pmap_l3_valid(l3))
2558 if ((prot & VM_PROT_WRITE) == 0) {
2559 if ((l3 & ATTR_SW_MANAGED) &&
2560 pmap_page_dirty(l3)) {
2561 vm_page_dirty(PHYS_TO_VM_PAGE(l3 &
2564 nbits |= ATTR_AP(ATTR_AP_RO);
2566 if ((prot & VM_PROT_EXECUTE) == 0)
2569 pmap_set(l3p, nbits);
2570 /* XXX: Use pmap_invalidate_range */
2571 pmap_invalidate_page(pmap, sva);
2578 * Inserts the specified page table page into the specified pmap's collection
2579 * of idle page table pages. Each of a pmap's page table pages is responsible
2580 * for mapping a distinct range of virtual addresses. The pmap's collection is
2581 * ordered by this virtual address range.
2584 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2587 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2588 return (vm_radix_insert(&pmap->pm_root, mpte));
2592 * Removes the page table page mapping the specified virtual address from the
2593 * specified pmap's collection of idle page table pages, and returns it.
2594 * Otherwise, returns NULL if there is no page table page corresponding to the
2595 * specified virtual address.
2597 static __inline vm_page_t
2598 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2601 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2602 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
2606 * Performs a break-before-make update of a pmap entry. This is needed when
2607 * either promoting or demoting pages to ensure the TLB doesn't get into an
2608 * inconsistent state.
2611 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
2612 vm_offset_t va, vm_size_t size)
2616 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2619 * Ensure we don't get switched out with the page table in an
2620 * inconsistent state. We also need to ensure no interrupts fire
2621 * as they may make use of an address we are about to invalidate.
2623 intr = intr_disable();
2626 /* Clear the old mapping */
2627 pmap_load_clear(pte);
2628 pmap_invalidate_range_nopin(pmap, va, va + size);
2630 /* Create the new mapping */
2631 pmap_load_store(pte, newpte);
2637 #if VM_NRESERVLEVEL > 0
2639 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
2640 * replace the many pv entries for the 4KB page mappings by a single pv entry
2641 * for the 2MB page mapping.
2644 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2645 struct rwlock **lockp)
2647 struct md_page *pvh;
2649 vm_offset_t va_last;
2652 KASSERT((pa & L2_OFFSET) == 0,
2653 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
2654 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2657 * Transfer the first page's pv entry for this mapping to the 2mpage's
2658 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
2659 * a transfer avoids the possibility that get_pv_entry() calls
2660 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
2661 * mappings that is being promoted.
2663 m = PHYS_TO_VM_PAGE(pa);
2664 va = va & ~L2_OFFSET;
2665 pv = pmap_pvh_remove(&m->md, pmap, va);
2666 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
2667 pvh = pa_to_pvh(pa);
2668 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2670 /* Free the remaining NPTEPG - 1 pv entries. */
2671 va_last = va + L2_SIZE - PAGE_SIZE;
2675 pmap_pvh_free(&m->md, pmap, va);
2676 } while (va < va_last);
2680 * Tries to promote the 512, contiguous 4KB page mappings that are within a
2681 * single level 2 table entry to a single 2MB page mapping. For promotion
2682 * to occur, two conditions must be met: (1) the 4KB page mappings must map
2683 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
2684 * identical characteristics.
2687 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
2688 struct rwlock **lockp)
2690 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
2694 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2696 sva = va & ~L2_OFFSET;
2697 firstl3 = pmap_l2_to_l3(l2, sva);
2698 newl2 = pmap_load(firstl3);
2700 /* Check the alingment is valid */
2701 if (((newl2 & ~ATTR_MASK) & L2_OFFSET) != 0) {
2702 atomic_add_long(&pmap_l2_p_failures, 1);
2703 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2704 " in pmap %p", va, pmap);
2708 pa = newl2 + L2_SIZE - PAGE_SIZE;
2709 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
2710 oldl3 = pmap_load(l3);
2712 atomic_add_long(&pmap_l2_p_failures, 1);
2713 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2714 " in pmap %p", va, pmap);
2721 * Save the page table page in its current state until the L2
2722 * mapping the superpage is demoted by pmap_demote_l2() or
2723 * destroyed by pmap_remove_l3().
2725 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
2726 KASSERT(mpte >= vm_page_array &&
2727 mpte < &vm_page_array[vm_page_array_size],
2728 ("pmap_promote_l2: page table page is out of range"));
2729 KASSERT(mpte->pindex == pmap_l2_pindex(va),
2730 ("pmap_promote_l2: page table page's pindex is wrong"));
2731 if (pmap_insert_pt_page(pmap, mpte)) {
2732 atomic_add_long(&pmap_l2_p_failures, 1);
2734 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
2739 if ((newl2 & ATTR_SW_MANAGED) != 0)
2740 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
2742 newl2 &= ~ATTR_DESCR_MASK;
2745 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
2747 atomic_add_long(&pmap_l2_promotions, 1);
2748 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
2751 #endif /* VM_NRESERVLEVEL > 0 */
2754 * Insert the given physical page (p) at
2755 * the specified virtual address (v) in the
2756 * target physical map with the protection requested.
2758 * If specified, the page will be wired down, meaning
2759 * that the related pte can not be reclaimed.
2761 * NB: This is the only routine which MAY NOT lazy-evaluate
2762 * or lose information. That is, this routine must actually
2763 * insert this page into the given map NOW.
2766 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2767 u_int flags, int8_t psind __unused)
2769 struct rwlock *lock;
2771 pt_entry_t new_l3, orig_l3;
2772 pt_entry_t *l2, *l3;
2774 vm_paddr_t opa, pa, l1_pa, l2_pa, l3_pa;
2775 vm_page_t mpte, om, l1_m, l2_m, l3_m;
2779 va = trunc_page(va);
2780 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2781 VM_OBJECT_ASSERT_LOCKED(m->object);
2782 pa = VM_PAGE_TO_PHYS(m);
2783 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
2785 if ((prot & VM_PROT_WRITE) == 0)
2786 new_l3 |= ATTR_AP(ATTR_AP_RO);
2787 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
2789 if ((flags & PMAP_ENTER_WIRED) != 0)
2790 new_l3 |= ATTR_SW_WIRED;
2791 if (va < VM_MAXUSER_ADDRESS)
2792 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
2794 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
2801 pde = pmap_pde(pmap, va, &lvl);
2802 if (pde != NULL && lvl == 1) {
2803 l2 = pmap_l1_to_l2(pde, va);
2804 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
2805 (l3 = pmap_demote_l2_locked(pmap, l2, va & ~L2_OFFSET,
2807 l3 = &l3[pmap_l3_index(va)];
2808 if (va < VM_MAXUSER_ADDRESS) {
2809 mpte = PHYS_TO_VM_PAGE(
2810 pmap_load(l2) & ~ATTR_MASK);
2817 if (va < VM_MAXUSER_ADDRESS) {
2818 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
2819 mpte = pmap_alloc_l3(pmap, va, nosleep ? NULL : &lock);
2820 if (mpte == NULL && nosleep) {
2821 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
2825 return (KERN_RESOURCE_SHORTAGE);
2827 pde = pmap_pde(pmap, va, &lvl);
2828 KASSERT(pde != NULL,
2829 ("pmap_enter: Invalid page entry, va: 0x%lx", va));
2831 ("pmap_enter: Invalid level %d", lvl));
2834 * If we get a level 2 pde it must point to a level 3 entry
2835 * otherwise we will need to create the intermediate tables
2841 /* Get the l0 pde to update */
2842 pde = pmap_l0(pmap, va);
2843 KASSERT(pde != NULL, ("..."));
2845 l1_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2846 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2849 panic("pmap_enter: l1 pte_m == NULL");
2850 if ((l1_m->flags & PG_ZERO) == 0)
2851 pmap_zero_page(l1_m);
2853 l1_pa = VM_PAGE_TO_PHYS(l1_m);
2854 pmap_load_store(pde, l1_pa | L0_TABLE);
2857 /* Get the l1 pde to update */
2858 pde = pmap_l1_to_l2(pde, va);
2859 KASSERT(pde != NULL, ("..."));
2861 l2_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2862 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2865 panic("pmap_enter: l2 pte_m == NULL");
2866 if ((l2_m->flags & PG_ZERO) == 0)
2867 pmap_zero_page(l2_m);
2869 l2_pa = VM_PAGE_TO_PHYS(l2_m);
2870 pmap_load_store(pde, l2_pa | L1_TABLE);
2873 /* Get the l2 pde to update */
2874 pde = pmap_l1_to_l2(pde, va);
2875 KASSERT(pde != NULL, ("..."));
2877 l3_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2878 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2881 panic("pmap_enter: l3 pte_m == NULL");
2882 if ((l3_m->flags & PG_ZERO) == 0)
2883 pmap_zero_page(l3_m);
2885 l3_pa = VM_PAGE_TO_PHYS(l3_m);
2886 pmap_load_store(pde, l3_pa | L2_TABLE);
2891 l3 = pmap_l2_to_l3(pde, va);
2895 orig_l3 = pmap_load(l3);
2896 opa = orig_l3 & ~ATTR_MASK;
2899 * Is the specified virtual address already mapped?
2901 if (pmap_l3_valid(orig_l3)) {
2903 * Wiring change, just update stats. We don't worry about
2904 * wiring PT pages as they remain resident as long as there
2905 * are valid mappings in them. Hence, if a user page is wired,
2906 * the PT page will be also.
2908 if ((flags & PMAP_ENTER_WIRED) != 0 &&
2909 (orig_l3 & ATTR_SW_WIRED) == 0)
2910 pmap->pm_stats.wired_count++;
2911 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
2912 (orig_l3 & ATTR_SW_WIRED) != 0)
2913 pmap->pm_stats.wired_count--;
2916 * Remove the extra PT page reference.
2920 KASSERT(mpte->wire_count > 0,
2921 ("pmap_enter: missing reference to page table page,"
2926 * Has the physical page changed?
2930 * No, might be a protection or wiring change.
2932 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
2933 new_l3 |= ATTR_SW_MANAGED;
2934 if ((new_l3 & ATTR_AP(ATTR_AP_RW)) ==
2935 ATTR_AP(ATTR_AP_RW)) {
2936 vm_page_aflag_set(m, PGA_WRITEABLE);
2943 * Increment the counters.
2945 if ((new_l3 & ATTR_SW_WIRED) != 0)
2946 pmap->pm_stats.wired_count++;
2947 pmap_resident_count_inc(pmap, 1);
2950 * Enter on the PV list if part of our managed memory.
2952 if ((m->oflags & VPO_UNMANAGED) == 0) {
2953 new_l3 |= ATTR_SW_MANAGED;
2954 pv = get_pv_entry(pmap, &lock);
2956 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
2957 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2959 if ((new_l3 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
2960 vm_page_aflag_set(m, PGA_WRITEABLE);
2965 * Sync icache if exec permission and attribute VM_MEMATTR_WRITE_BACK
2966 * is set. Do it now, before the mapping is stored and made
2967 * valid for hardware table walk. If done later, then other can
2968 * access this page before caches are properly synced.
2969 * Don't do it for kernel memory which is mapped with exec
2970 * permission even if the memory isn't going to hold executable
2971 * code. The only time when icache sync is needed is after
2972 * kernel module is loaded and the relocation info is processed.
2973 * And it's done in elf_cpu_load_file().
2975 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
2976 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
2977 (opa != pa || (orig_l3 & ATTR_XN)))
2978 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
2981 * Update the L3 entry
2983 if (pmap_l3_valid(orig_l3)) {
2986 pmap_update_entry(pmap, l3, new_l3, va, PAGE_SIZE);
2987 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
2988 om = PHYS_TO_VM_PAGE(opa);
2989 if (pmap_page_dirty(orig_l3))
2991 if ((orig_l3 & ATTR_AF) != 0)
2992 vm_page_aflag_set(om, PGA_REFERENCED);
2993 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
2994 pmap_pvh_free(&om->md, pmap, va);
2995 if ((om->aflags & PGA_WRITEABLE) != 0 &&
2996 TAILQ_EMPTY(&om->md.pv_list) &&
2997 ((om->flags & PG_FICTITIOUS) != 0 ||
2998 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
2999 vm_page_aflag_clear(om, PGA_WRITEABLE);
3001 } else if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3002 /* same PA, different attributes */
3003 pmap_load_store(l3, new_l3);
3004 pmap_invalidate_page(pmap, va);
3005 if (pmap_page_dirty(orig_l3) &&
3006 (orig_l3 & ATTR_SW_MANAGED) != 0)
3011 * This can happens if multiple threads simultaneously
3012 * access not yet mapped page. This bad for performance
3013 * since this can cause full demotion-NOP-promotion
3015 * Another possible reasons are:
3016 * - VM and pmap memory layout are diverged
3017 * - tlb flush is missing somewhere and CPU doesn't see
3020 CTR4(KTR_PMAP, "%s: already mapped page - "
3021 "pmap %p va 0x%#lx pte 0x%lx",
3022 __func__, pmap, va, new_l3);
3026 pmap_load_store(l3, new_l3);
3029 #if VM_NRESERVLEVEL > 0
3030 if (pmap != pmap_kernel() &&
3031 (mpte == NULL || mpte->wire_count == NL3PG) &&
3032 pmap_superpages_enabled() &&
3033 (m->flags & PG_FICTITIOUS) == 0 &&
3034 vm_reserv_level_iffullpop(m) == 0) {
3035 pmap_promote_l2(pmap, pde, va, &lock);
3042 return (KERN_SUCCESS);
3046 * Maps a sequence of resident pages belonging to the same object.
3047 * The sequence begins with the given page m_start. This page is
3048 * mapped at the given virtual address start. Each subsequent page is
3049 * mapped at a virtual address that is offset from start by the same
3050 * amount as the page is offset from m_start within the object. The
3051 * last page in the sequence is the page with the largest offset from
3052 * m_start that can be mapped at a virtual address less than the given
3053 * virtual address end. Not every virtual page between start and end
3054 * is mapped; only those for which a resident page exists with the
3055 * corresponding offset from m_start are mapped.
3058 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3059 vm_page_t m_start, vm_prot_t prot)
3061 struct rwlock *lock;
3064 vm_pindex_t diff, psize;
3066 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3068 psize = atop(end - start);
3073 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3074 va = start + ptoa(diff);
3075 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte, &lock);
3076 m = TAILQ_NEXT(m, listq);
3084 * this code makes some *MAJOR* assumptions:
3085 * 1. Current pmap & pmap exists.
3088 * 4. No page table pages.
3089 * but is *MUCH* faster than pmap_enter...
3093 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3095 struct rwlock *lock;
3099 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3106 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3107 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3109 struct spglist free;
3111 pt_entry_t *l2, *l3, l3_val;
3115 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3116 (m->oflags & VPO_UNMANAGED) != 0,
3117 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3118 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3120 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3122 * In the case that a page table page is not
3123 * resident, we are creating it here.
3125 if (va < VM_MAXUSER_ADDRESS) {
3126 vm_pindex_t l2pindex;
3129 * Calculate pagetable page index
3131 l2pindex = pmap_l2_pindex(va);
3132 if (mpte && (mpte->pindex == l2pindex)) {
3138 pde = pmap_pde(pmap, va, &lvl);
3141 * If the page table page is mapped, we just increment
3142 * the hold count, and activate it. Otherwise, we
3143 * attempt to allocate a page table page. If this
3144 * attempt fails, we don't retry. Instead, we give up.
3147 l2 = pmap_l1_to_l2(pde, va);
3148 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3152 if (lvl == 2 && pmap_load(pde) != 0) {
3154 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3158 * Pass NULL instead of the PV list lock
3159 * pointer, because we don't intend to sleep.
3161 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3166 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3167 l3 = &l3[pmap_l3_index(va)];
3170 pde = pmap_pde(kernel_pmap, va, &lvl);
3171 KASSERT(pde != NULL,
3172 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3175 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3176 l3 = pmap_l2_to_l3(pde, va);
3179 if (pmap_load(l3) != 0) {
3188 * Enter on the PV list if part of our managed memory.
3190 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3191 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3194 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
3195 pmap_invalidate_page(pmap, va);
3196 vm_page_free_pages_toq(&free, false);
3204 * Increment counters
3206 pmap_resident_count_inc(pmap, 1);
3208 pa = VM_PAGE_TO_PHYS(m);
3209 l3_val = pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3210 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3211 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3213 else if (va < VM_MAXUSER_ADDRESS)
3217 * Now validate mapping with RO protection
3219 if ((m->oflags & VPO_UNMANAGED) == 0)
3220 l3_val |= ATTR_SW_MANAGED;
3222 /* Sync icache before the mapping is stored to PTE */
3223 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3224 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
3225 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3227 pmap_load_store(l3, l3_val);
3228 pmap_invalidate_page(pmap, va);
3233 * This code maps large physical mmap regions into the
3234 * processor address space. Note that some shortcuts
3235 * are taken, but the code works.
3238 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3239 vm_pindex_t pindex, vm_size_t size)
3242 VM_OBJECT_ASSERT_WLOCKED(object);
3243 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3244 ("pmap_object_init_pt: non-device object"));
3248 * Clear the wired attribute from the mappings for the specified range of
3249 * addresses in the given pmap. Every valid mapping within that range
3250 * must have the wired attribute set. In contrast, invalid mappings
3251 * cannot have the wired attribute set, so they are ignored.
3253 * The wired attribute of the page table entry is not a hardware feature,
3254 * so there is no need to invalidate any TLB entries.
3257 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3259 vm_offset_t va_next;
3260 pd_entry_t *l0, *l1, *l2;
3264 for (; sva < eva; sva = va_next) {
3265 l0 = pmap_l0(pmap, sva);
3266 if (pmap_load(l0) == 0) {
3267 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3273 l1 = pmap_l0_to_l1(l0, sva);
3274 if (pmap_load(l1) == 0) {
3275 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3281 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3285 l2 = pmap_l1_to_l2(l1, sva);
3286 if (pmap_load(l2) == 0)
3289 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3290 l3 = pmap_demote_l2(pmap, l2, sva);
3294 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3295 ("pmap_unwire: Invalid l2 entry after demotion"));
3299 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3301 if (pmap_load(l3) == 0)
3303 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
3304 panic("pmap_unwire: l3 %#jx is missing "
3305 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
3308 * PG_W must be cleared atomically. Although the pmap
3309 * lock synchronizes access to PG_W, another processor
3310 * could be setting PG_M and/or PG_A concurrently.
3312 atomic_clear_long(l3, ATTR_SW_WIRED);
3313 pmap->pm_stats.wired_count--;
3320 * Copy the range specified by src_addr/len
3321 * from the source map to the range dst_addr/len
3322 * in the destination map.
3324 * This routine is only advisory and need not do anything.
3328 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3329 vm_offset_t src_addr)
3334 * pmap_zero_page zeros the specified hardware page by mapping
3335 * the page into KVM and using bzero to clear its contents.
3338 pmap_zero_page(vm_page_t m)
3340 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3342 pagezero((void *)va);
3346 * pmap_zero_page_area zeros the specified hardware page by mapping
3347 * the page into KVM and using bzero to clear its contents.
3349 * off and size may not cover an area beyond a single hardware page.
3352 pmap_zero_page_area(vm_page_t m, int off, int size)
3354 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3356 if (off == 0 && size == PAGE_SIZE)
3357 pagezero((void *)va);
3359 bzero((char *)va + off, size);
3363 * pmap_copy_page copies the specified (machine independent)
3364 * page by mapping the page into virtual memory and using
3365 * bcopy to copy the page, one machine dependent page at a
3369 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
3371 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
3372 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
3374 pagecopy((void *)src, (void *)dst);
3377 int unmapped_buf_allowed = 1;
3380 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
3381 vm_offset_t b_offset, int xfersize)
3385 vm_paddr_t p_a, p_b;
3386 vm_offset_t a_pg_offset, b_pg_offset;
3389 while (xfersize > 0) {
3390 a_pg_offset = a_offset & PAGE_MASK;
3391 m_a = ma[a_offset >> PAGE_SHIFT];
3392 p_a = m_a->phys_addr;
3393 b_pg_offset = b_offset & PAGE_MASK;
3394 m_b = mb[b_offset >> PAGE_SHIFT];
3395 p_b = m_b->phys_addr;
3396 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
3397 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
3398 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
3399 panic("!DMAP a %lx", p_a);
3401 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
3403 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
3404 panic("!DMAP b %lx", p_b);
3406 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
3408 bcopy(a_cp, b_cp, cnt);
3416 pmap_quick_enter_page(vm_page_t m)
3419 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
3423 pmap_quick_remove_page(vm_offset_t addr)
3428 * Returns true if the pmap's pv is one of the first
3429 * 16 pvs linked to from this page. This count may
3430 * be changed upwards or downwards in the future; it
3431 * is only necessary that true be returned for a small
3432 * subset of pmaps for proper page aging.
3435 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3437 struct md_page *pvh;
3438 struct rwlock *lock;
3443 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3444 ("pmap_page_exists_quick: page %p is not managed", m));
3446 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3448 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3449 if (PV_PMAP(pv) == pmap) {
3457 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
3458 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3459 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3460 if (PV_PMAP(pv) == pmap) {
3474 * pmap_page_wired_mappings:
3476 * Return the number of managed mappings to the given physical page
3480 pmap_page_wired_mappings(vm_page_t m)
3482 struct rwlock *lock;
3483 struct md_page *pvh;
3487 int count, lvl, md_gen, pvh_gen;
3489 if ((m->oflags & VPO_UNMANAGED) != 0)
3491 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3495 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3497 if (!PMAP_TRYLOCK(pmap)) {
3498 md_gen = m->md.pv_gen;
3502 if (md_gen != m->md.pv_gen) {
3507 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3508 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3512 if ((m->flags & PG_FICTITIOUS) == 0) {
3513 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3514 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3516 if (!PMAP_TRYLOCK(pmap)) {
3517 md_gen = m->md.pv_gen;
3518 pvh_gen = pvh->pv_gen;
3522 if (md_gen != m->md.pv_gen ||
3523 pvh_gen != pvh->pv_gen) {
3528 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3530 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3540 * Destroy all managed, non-wired mappings in the given user-space
3541 * pmap. This pmap cannot be active on any processor besides the
3544 * This function cannot be applied to the kernel pmap. Moreover, it
3545 * is not intended for general use. It is only to be used during
3546 * process termination. Consequently, it can be implemented in ways
3547 * that make it faster than pmap_remove(). First, it can more quickly
3548 * destroy mappings by iterating over the pmap's collection of PV
3549 * entries, rather than searching the page table. Second, it doesn't
3550 * have to test and clear the page table entries atomically, because
3551 * no processor is currently accessing the user address space. In
3552 * particular, a page table entry's dirty bit won't change state once
3553 * this function starts.
3556 pmap_remove_pages(pmap_t pmap)
3559 pt_entry_t *pte, tpte;
3560 struct spglist free;
3561 vm_page_t m, ml3, mt;
3563 struct md_page *pvh;
3564 struct pv_chunk *pc, *npc;
3565 struct rwlock *lock;
3567 uint64_t inuse, bitmask;
3568 int allfree, field, freed, idx, lvl;
3575 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
3578 for (field = 0; field < _NPCM; field++) {
3579 inuse = ~pc->pc_map[field] & pc_freemask[field];
3580 while (inuse != 0) {
3581 bit = ffsl(inuse) - 1;
3582 bitmask = 1UL << bit;
3583 idx = field * 64 + bit;
3584 pv = &pc->pc_pventry[idx];
3587 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3588 KASSERT(pde != NULL,
3589 ("Attempting to remove an unmapped page"));
3593 pte = pmap_l1_to_l2(pde, pv->pv_va);
3594 tpte = pmap_load(pte);
3595 KASSERT((tpte & ATTR_DESCR_MASK) ==
3597 ("Attempting to remove an invalid "
3598 "block: %lx", tpte));
3599 tpte = pmap_load(pte);
3602 pte = pmap_l2_to_l3(pde, pv->pv_va);
3603 tpte = pmap_load(pte);
3604 KASSERT((tpte & ATTR_DESCR_MASK) ==
3606 ("Attempting to remove an invalid "
3607 "page: %lx", tpte));
3611 "Invalid page directory level: %d",
3616 * We cannot remove wired pages from a process' mapping at this time
3618 if (tpte & ATTR_SW_WIRED) {
3623 pa = tpte & ~ATTR_MASK;
3625 m = PHYS_TO_VM_PAGE(pa);
3626 KASSERT(m->phys_addr == pa,
3627 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
3628 m, (uintmax_t)m->phys_addr,
3631 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
3632 m < &vm_page_array[vm_page_array_size],
3633 ("pmap_remove_pages: bad pte %#jx",
3636 pmap_load_clear(pte);
3639 * Update the vm_page_t clean/reference bits.
3641 if ((tpte & ATTR_AP_RW_BIT) ==
3642 ATTR_AP(ATTR_AP_RW)) {
3645 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3654 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
3657 pc->pc_map[field] |= bitmask;
3660 pmap_resident_count_dec(pmap,
3661 L2_SIZE / PAGE_SIZE);
3662 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
3663 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
3665 if (TAILQ_EMPTY(&pvh->pv_list)) {
3666 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3667 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
3668 TAILQ_EMPTY(&mt->md.pv_list))
3669 vm_page_aflag_clear(mt, PGA_WRITEABLE);
3671 ml3 = pmap_remove_pt_page(pmap,
3674 pmap_resident_count_dec(pmap,1);
3675 KASSERT(ml3->wire_count == NL3PG,
3676 ("pmap_remove_pages: l3 page wire count error"));
3677 ml3->wire_count = 1;
3678 vm_page_unwire_noq(ml3);
3679 pmap_add_delayed_free_list(ml3,
3684 pmap_resident_count_dec(pmap, 1);
3685 TAILQ_REMOVE(&m->md.pv_list, pv,
3688 if ((m->aflags & PGA_WRITEABLE) != 0 &&
3689 TAILQ_EMPTY(&m->md.pv_list) &&
3690 (m->flags & PG_FICTITIOUS) == 0) {
3692 VM_PAGE_TO_PHYS(m));
3693 if (TAILQ_EMPTY(&pvh->pv_list))
3694 vm_page_aflag_clear(m,
3699 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
3704 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3705 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3706 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3708 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3712 pmap_invalidate_all(pmap);
3716 vm_page_free_pages_toq(&free, false);
3720 * This is used to check if a page has been accessed or modified. As we
3721 * don't have a bit to see if it has been modified we have to assume it
3722 * has been if the page is read/write.
3725 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
3727 struct rwlock *lock;
3729 struct md_page *pvh;
3730 pt_entry_t *pte, mask, value;
3732 int lvl, md_gen, pvh_gen;
3736 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3739 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3741 if (!PMAP_TRYLOCK(pmap)) {
3742 md_gen = m->md.pv_gen;
3746 if (md_gen != m->md.pv_gen) {
3751 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3753 ("pmap_page_test_mappings: Invalid level %d", lvl));
3757 mask |= ATTR_AP_RW_BIT;
3758 value |= ATTR_AP(ATTR_AP_RW);
3761 mask |= ATTR_AF | ATTR_DESCR_MASK;
3762 value |= ATTR_AF | L3_PAGE;
3764 rv = (pmap_load(pte) & mask) == value;
3769 if ((m->flags & PG_FICTITIOUS) == 0) {
3770 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3771 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3773 if (!PMAP_TRYLOCK(pmap)) {
3774 md_gen = m->md.pv_gen;
3775 pvh_gen = pvh->pv_gen;
3779 if (md_gen != m->md.pv_gen ||
3780 pvh_gen != pvh->pv_gen) {
3785 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3787 ("pmap_page_test_mappings: Invalid level %d", lvl));
3791 mask |= ATTR_AP_RW_BIT;
3792 value |= ATTR_AP(ATTR_AP_RW);
3795 mask |= ATTR_AF | ATTR_DESCR_MASK;
3796 value |= ATTR_AF | L2_BLOCK;
3798 rv = (pmap_load(pte) & mask) == value;
3812 * Return whether or not the specified physical page was modified
3813 * in any physical maps.
3816 pmap_is_modified(vm_page_t m)
3819 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3820 ("pmap_is_modified: page %p is not managed", m));
3823 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3824 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
3825 * is clear, no PTEs can have PG_M set.
3827 VM_OBJECT_ASSERT_WLOCKED(m->object);
3828 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3830 return (pmap_page_test_mappings(m, FALSE, TRUE));
3834 * pmap_is_prefaultable:
3836 * Return whether or not the specified virtual address is eligible
3840 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3848 pte = pmap_pte(pmap, addr, &lvl);
3849 if (pte != NULL && pmap_load(pte) != 0) {
3857 * pmap_is_referenced:
3859 * Return whether or not the specified physical page was referenced
3860 * in any physical maps.
3863 pmap_is_referenced(vm_page_t m)
3866 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3867 ("pmap_is_referenced: page %p is not managed", m));
3868 return (pmap_page_test_mappings(m, TRUE, FALSE));
3872 * Clear the write and modified bits in each of the given page's mappings.
3875 pmap_remove_write(vm_page_t m)
3877 struct md_page *pvh;
3879 struct rwlock *lock;
3880 pv_entry_t next_pv, pv;
3881 pt_entry_t oldpte, *pte;
3883 int lvl, md_gen, pvh_gen;
3885 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3886 ("pmap_remove_write: page %p is not managed", m));
3889 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3890 * set by another thread while the object is locked. Thus,
3891 * if PGA_WRITEABLE is clear, no page table entries need updating.
3893 VM_OBJECT_ASSERT_WLOCKED(m->object);
3894 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3896 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3897 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
3898 pa_to_pvh(VM_PAGE_TO_PHYS(m));
3901 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
3903 if (!PMAP_TRYLOCK(pmap)) {
3904 pvh_gen = pvh->pv_gen;
3908 if (pvh_gen != pvh->pv_gen) {
3915 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3916 if ((pmap_load(pte) & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3917 pmap_demote_l2_locked(pmap, pte, va & ~L2_OFFSET,
3919 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
3920 ("inconsistent pv lock %p %p for page %p",
3921 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
3924 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3926 if (!PMAP_TRYLOCK(pmap)) {
3927 pvh_gen = pvh->pv_gen;
3928 md_gen = m->md.pv_gen;
3932 if (pvh_gen != pvh->pv_gen ||
3933 md_gen != m->md.pv_gen) {
3939 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3941 oldpte = pmap_load(pte);
3942 if ((oldpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) {
3943 if (!atomic_cmpset_long(pte, oldpte,
3944 oldpte | ATTR_AP(ATTR_AP_RO)))
3946 if ((oldpte & ATTR_AF) != 0)
3948 pmap_invalidate_page(pmap, pv->pv_va);
3953 vm_page_aflag_clear(m, PGA_WRITEABLE);
3956 static __inline boolean_t
3957 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
3964 * pmap_ts_referenced:
3966 * Return a count of reference bits for a page, clearing those bits.
3967 * It is not necessary for every reference bit to be cleared, but it
3968 * is necessary that 0 only be returned when there are truly no
3969 * reference bits set.
3971 * As an optimization, update the page's dirty field if a modified bit is
3972 * found while counting reference bits. This opportunistic update can be
3973 * performed at low cost and can eliminate the need for some future calls
3974 * to pmap_is_modified(). However, since this function stops after
3975 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
3976 * dirty pages. Those dirty pages will only be detected by a future call
3977 * to pmap_is_modified().
3980 pmap_ts_referenced(vm_page_t m)
3982 struct md_page *pvh;
3985 struct rwlock *lock;
3986 pd_entry_t *pde, tpde;
3987 pt_entry_t *pte, tpte;
3991 int cleared, md_gen, not_cleared, lvl, pvh_gen;
3992 struct spglist free;
3995 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3996 ("pmap_ts_referenced: page %p is not managed", m));
3999 pa = VM_PAGE_TO_PHYS(m);
4000 lock = PHYS_TO_PV_LIST_LOCK(pa);
4001 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4005 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4006 goto small_mappings;
4012 if (!PMAP_TRYLOCK(pmap)) {
4013 pvh_gen = pvh->pv_gen;
4017 if (pvh_gen != pvh->pv_gen) {
4023 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4024 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4026 ("pmap_ts_referenced: invalid pde level %d", lvl));
4027 tpde = pmap_load(pde);
4028 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4029 ("pmap_ts_referenced: found an invalid l1 table"));
4030 pte = pmap_l1_to_l2(pde, pv->pv_va);
4031 tpte = pmap_load(pte);
4032 if (pmap_page_dirty(tpte)) {
4034 * Although "tpte" is mapping a 2MB page, because
4035 * this function is called at a 4KB page granularity,
4036 * we only update the 4KB page under test.
4040 if ((tpte & ATTR_AF) != 0) {
4042 * Since this reference bit is shared by 512 4KB
4043 * pages, it should not be cleared every time it is
4044 * tested. Apply a simple "hash" function on the
4045 * physical page number, the virtual superpage number,
4046 * and the pmap address to select one 4KB page out of
4047 * the 512 on which testing the reference bit will
4048 * result in clearing that reference bit. This
4049 * function is designed to avoid the selection of the
4050 * same 4KB page for every 2MB page mapping.
4052 * On demotion, a mapping that hasn't been referenced
4053 * is simply destroyed. To avoid the possibility of a
4054 * subsequent page fault on a demoted wired mapping,
4055 * always leave its reference bit set. Moreover,
4056 * since the superpage is wired, the current state of
4057 * its reference bit won't affect page replacement.
4059 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4060 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4061 (tpte & ATTR_SW_WIRED) == 0) {
4062 if (safe_to_clear_referenced(pmap, tpte)) {
4064 * TODO: We don't handle the access
4065 * flag at all. We need to be able
4066 * to set it in the exception handler.
4069 "safe_to_clear_referenced\n");
4070 } else if (pmap_demote_l2_locked(pmap, pte,
4071 pv->pv_va, &lock) != NULL) {
4073 va += VM_PAGE_TO_PHYS(m) -
4074 (tpte & ~ATTR_MASK);
4075 l3 = pmap_l2_to_l3(pte, va);
4076 pmap_remove_l3(pmap, l3, va,
4077 pmap_load(pte), NULL, &lock);
4083 * The superpage mapping was removed
4084 * entirely and therefore 'pv' is no
4092 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4093 ("inconsistent pv lock %p %p for page %p",
4094 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4099 /* Rotate the PV list if it has more than one entry. */
4100 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4101 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4102 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4105 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4107 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4109 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4116 if (!PMAP_TRYLOCK(pmap)) {
4117 pvh_gen = pvh->pv_gen;
4118 md_gen = m->md.pv_gen;
4122 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4127 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4128 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4130 ("pmap_ts_referenced: invalid pde level %d", lvl));
4131 tpde = pmap_load(pde);
4132 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4133 ("pmap_ts_referenced: found an invalid l2 table"));
4134 pte = pmap_l2_to_l3(pde, pv->pv_va);
4135 tpte = pmap_load(pte);
4136 if (pmap_page_dirty(tpte))
4138 if ((tpte & ATTR_AF) != 0) {
4139 if (safe_to_clear_referenced(pmap, tpte)) {
4141 * TODO: We don't handle the access flag
4142 * at all. We need to be able to set it in
4143 * the exception handler.
4145 panic("ARM64TODO: safe_to_clear_referenced\n");
4146 } else if ((tpte & ATTR_SW_WIRED) == 0) {
4148 * Wired pages cannot be paged out so
4149 * doing accessed bit emulation for
4150 * them is wasted effort. We do the
4151 * hard work for unwired pages only.
4153 pmap_remove_l3(pmap, pte, pv->pv_va, tpde,
4155 pmap_invalidate_page(pmap, pv->pv_va);
4160 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4161 ("inconsistent pv lock %p %p for page %p",
4162 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4167 /* Rotate the PV list if it has more than one entry. */
4168 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4169 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4170 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4173 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4174 not_cleared < PMAP_TS_REFERENCED_MAX);
4177 vm_page_free_pages_toq(&free, false);
4178 return (cleared + not_cleared);
4182 * Apply the given advice to the specified range of addresses within the
4183 * given pmap. Depending on the advice, clear the referenced and/or
4184 * modified flags in each mapping and set the mapped page's dirty field.
4187 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4192 * Clear the modify bits on the specified physical page.
4195 pmap_clear_modify(vm_page_t m)
4198 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4199 ("pmap_clear_modify: page %p is not managed", m));
4200 VM_OBJECT_ASSERT_WLOCKED(m->object);
4201 KASSERT(!vm_page_xbusied(m),
4202 ("pmap_clear_modify: page %p is exclusive busied", m));
4205 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4206 * If the object containing the page is locked and the page is not
4207 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4209 if ((m->aflags & PGA_WRITEABLE) == 0)
4212 /* ARM64TODO: We lack support for tracking if a page is modified */
4216 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4218 struct pmap_preinit_mapping *ppim;
4219 vm_offset_t va, offset;
4222 int i, lvl, l2_blocks, free_l2_count, start_idx;
4224 if (!vm_initialized) {
4226 * No L3 ptables so map entire L2 blocks where start VA is:
4227 * preinit_map_va + start_idx * L2_SIZE
4228 * There may be duplicate mappings (multiple VA -> same PA) but
4229 * ARM64 dcache is always PIPT so that's acceptable.
4234 /* Calculate how many full L2 blocks are needed for the mapping */
4235 l2_blocks = (roundup2(pa + size, L2_SIZE) - rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
4237 offset = pa & L2_OFFSET;
4239 if (preinit_map_va == 0)
4242 /* Map 2MiB L2 blocks from reserved VA space */
4246 /* Find enough free contiguous VA space */
4247 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
4248 ppim = pmap_preinit_mapping + i;
4249 if (free_l2_count > 0 && ppim->pa != 0) {
4250 /* Not enough space here */
4256 if (ppim->pa == 0) {
4258 if (start_idx == -1)
4261 if (free_l2_count == l2_blocks)
4265 if (free_l2_count != l2_blocks)
4266 panic("%s: too many preinit mappings", __func__);
4268 va = preinit_map_va + (start_idx * L2_SIZE);
4269 for (i = start_idx; i < start_idx + l2_blocks; i++) {
4270 /* Mark entries as allocated */
4271 ppim = pmap_preinit_mapping + i;
4273 ppim->va = va + offset;
4278 pa = rounddown2(pa, L2_SIZE);
4279 for (i = 0; i < l2_blocks; i++) {
4280 pde = pmap_pde(kernel_pmap, va, &lvl);
4281 KASSERT(pde != NULL,
4282 ("pmap_mapbios: Invalid page entry, va: 0x%lx", va));
4283 KASSERT(lvl == 1, ("pmap_mapbios: Invalid level %d", lvl));
4285 /* Insert L2_BLOCK */
4286 l2 = pmap_l1_to_l2(pde, va);
4288 pa | ATTR_DEFAULT | ATTR_XN |
4289 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
4290 pmap_invalidate_range(kernel_pmap, va, va + L2_SIZE);
4296 va = preinit_map_va + (start_idx * L2_SIZE);
4299 /* kva_alloc may be used to map the pages */
4300 offset = pa & PAGE_MASK;
4301 size = round_page(offset + size);
4303 va = kva_alloc(size);
4305 panic("%s: Couldn't allocate KVA", __func__);
4307 pde = pmap_pde(kernel_pmap, va, &lvl);
4308 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
4310 /* L3 table is linked */
4311 va = trunc_page(va);
4312 pa = trunc_page(pa);
4313 pmap_kenter(va, size, pa, CACHED_MEMORY);
4316 return ((void *)(va + offset));
4320 pmap_unmapbios(vm_offset_t va, vm_size_t size)
4322 struct pmap_preinit_mapping *ppim;
4323 vm_offset_t offset, tmpsize, va_trunc;
4326 int i, lvl, l2_blocks, block;
4328 l2_blocks = (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
4329 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
4331 /* Remove preinit mapping */
4333 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
4334 ppim = pmap_preinit_mapping + i;
4335 if (ppim->va == va) {
4336 KASSERT(ppim->size == size, ("pmap_unmapbios: size mismatch"));
4340 offset = block * L2_SIZE;
4341 va_trunc = rounddown2(va, L2_SIZE) + offset;
4343 /* Remove L2_BLOCK */
4344 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
4345 KASSERT(pde != NULL,
4346 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va_trunc));
4347 l2 = pmap_l1_to_l2(pde, va_trunc);
4348 pmap_load_clear(l2);
4349 pmap_invalidate_range(kernel_pmap, va_trunc, va_trunc + L2_SIZE);
4351 if (block == (l2_blocks - 1))
4357 /* Unmap the pages reserved with kva_alloc. */
4358 if (vm_initialized) {
4359 offset = va & PAGE_MASK;
4360 size = round_page(offset + size);
4361 va = trunc_page(va);
4363 pde = pmap_pde(kernel_pmap, va, &lvl);
4364 KASSERT(pde != NULL,
4365 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
4366 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
4368 /* Unmap and invalidate the pages */
4369 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
4370 pmap_kremove(va + tmpsize);
4377 * Sets the memory attribute for the specified page.
4380 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4383 m->md.pv_memattr = ma;
4386 * If "m" is a normal page, update its direct mapping. This update
4387 * can be relied upon to perform any cache operations that are
4388 * required for data coherence.
4390 if ((m->flags & PG_FICTITIOUS) == 0 &&
4391 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
4392 m->md.pv_memattr) != 0)
4393 panic("memory attribute change on the direct map failed");
4397 * Changes the specified virtual address range's memory type to that given by
4398 * the parameter "mode". The specified virtual address range must be
4399 * completely contained within either the direct map or the kernel map. If
4400 * the virtual address range is contained within the kernel map, then the
4401 * memory type for each of the corresponding ranges of the direct map is also
4402 * changed. (The corresponding ranges of the direct map are those ranges that
4403 * map the same physical pages as the specified virtual address range.) These
4404 * changes to the direct map are necessary because Intel describes the
4405 * behavior of their processors as "undefined" if two or more mappings to the
4406 * same physical page have different memory types.
4408 * Returns zero if the change completed successfully, and either EINVAL or
4409 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
4410 * of the virtual address range was not mapped, and ENOMEM is returned if
4411 * there was insufficient memory available to complete the change. In the
4412 * latter case, the memory type may have been changed on some part of the
4413 * virtual address range or the direct map.
4416 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
4420 PMAP_LOCK(kernel_pmap);
4421 error = pmap_change_attr_locked(va, size, mode);
4422 PMAP_UNLOCK(kernel_pmap);
4427 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
4429 vm_offset_t base, offset, tmpva;
4430 pt_entry_t l3, *pte, *newpte;
4433 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
4434 base = trunc_page(va);
4435 offset = va & PAGE_MASK;
4436 size = round_page(offset + size);
4438 if (!VIRT_IN_DMAP(base))
4441 for (tmpva = base; tmpva < base + size; ) {
4442 pte = pmap_pte(kernel_pmap, va, &lvl);
4446 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
4448 * We already have the correct attribute,
4449 * ignore this entry.
4453 panic("Invalid DMAP table level: %d\n", lvl);
4455 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
4458 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
4466 * Split the entry to an level 3 table, then
4467 * set the new attribute.
4471 panic("Invalid DMAP table level: %d\n", lvl);
4473 newpte = pmap_demote_l1(kernel_pmap, pte,
4474 tmpva & ~L1_OFFSET);
4477 pte = pmap_l1_to_l2(pte, tmpva);
4479 newpte = pmap_demote_l2(kernel_pmap, pte,
4480 tmpva & ~L2_OFFSET);
4483 pte = pmap_l2_to_l3(pte, tmpva);
4485 /* Update the entry */
4486 l3 = pmap_load(pte);
4487 l3 &= ~ATTR_IDX_MASK;
4488 l3 |= ATTR_IDX(mode);
4489 if (mode == DEVICE_MEMORY)
4492 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
4496 * If moving to a non-cacheable entry flush
4499 if (mode == VM_MEMATTR_UNCACHEABLE)
4500 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
4512 * Create an L2 table to map all addresses within an L1 mapping.
4515 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
4517 pt_entry_t *l2, newl2, oldl1;
4519 vm_paddr_t l2phys, phys;
4523 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4524 oldl1 = pmap_load(l1);
4525 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
4526 ("pmap_demote_l1: Demoting a non-block entry"));
4527 KASSERT((va & L1_OFFSET) == 0,
4528 ("pmap_demote_l1: Invalid virtual address %#lx", va));
4529 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
4530 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
4533 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
4534 tmpl1 = kva_alloc(PAGE_SIZE);
4539 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
4540 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
4541 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
4542 " in pmap %p", va, pmap);
4546 l2phys = VM_PAGE_TO_PHYS(ml2);
4547 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
4549 /* Address the range points at */
4550 phys = oldl1 & ~ATTR_MASK;
4551 /* The attributed from the old l1 table to be copied */
4552 newl2 = oldl1 & ATTR_MASK;
4554 /* Create the new entries */
4555 for (i = 0; i < Ln_ENTRIES; i++) {
4556 l2[i] = newl2 | phys;
4559 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
4560 ("Invalid l2 page (%lx != %lx)", l2[0],
4561 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
4564 pmap_kenter(tmpl1, PAGE_SIZE,
4565 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY);
4566 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
4569 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
4572 pmap_kremove(tmpl1);
4573 kva_free(tmpl1, PAGE_SIZE);
4580 * Create an L3 table to map all addresses within an L2 mapping.
4583 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
4584 struct rwlock **lockp)
4586 pt_entry_t *l3, newl3, oldl2;
4588 vm_paddr_t l3phys, phys;
4592 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4594 oldl2 = pmap_load(l2);
4595 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
4596 ("pmap_demote_l2: Demoting a non-block entry"));
4597 KASSERT((va & L2_OFFSET) == 0,
4598 ("pmap_demote_l2: Invalid virtual address %#lx", va));
4601 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
4602 tmpl2 = kva_alloc(PAGE_SIZE);
4607 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
4608 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
4609 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4610 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
4612 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
4613 " in pmap %p", va, pmap);
4616 if (va < VM_MAXUSER_ADDRESS)
4617 pmap_resident_count_inc(pmap, 1);
4620 l3phys = VM_PAGE_TO_PHYS(ml3);
4621 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
4623 /* Address the range points at */
4624 phys = oldl2 & ~ATTR_MASK;
4625 /* The attributed from the old l2 table to be copied */
4626 newl3 = (oldl2 & (ATTR_MASK & ~ATTR_DESCR_MASK)) | L3_PAGE;
4629 * If the page table page is new, initialize it.
4631 if (ml3->wire_count == 1) {
4632 for (i = 0; i < Ln_ENTRIES; i++) {
4633 l3[i] = newl3 | phys;
4637 KASSERT(l3[0] == ((oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE),
4638 ("Invalid l3 page (%lx != %lx)", l3[0],
4639 (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE));
4642 * Map the temporary page so we don't lose access to the l2 table.
4645 pmap_kenter(tmpl2, PAGE_SIZE,
4646 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY);
4647 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
4651 * The spare PV entries must be reserved prior to demoting the
4652 * mapping, that is, prior to changing the PDE. Otherwise, the state
4653 * of the L2 and the PV lists will be inconsistent, which can result
4654 * in reclaim_pv_chunk() attempting to remove a PV entry from the
4655 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
4656 * PV entry for the 2MB page mapping that is being demoted.
4658 if ((oldl2 & ATTR_SW_MANAGED) != 0)
4659 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
4661 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
4664 * Demote the PV entry.
4666 if ((oldl2 & ATTR_SW_MANAGED) != 0)
4667 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
4669 atomic_add_long(&pmap_l2_demotions, 1);
4670 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
4671 " in pmap %p %lx", va, pmap, l3[0]);
4675 pmap_kremove(tmpl2);
4676 kva_free(tmpl2, PAGE_SIZE);
4684 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
4686 struct rwlock *lock;
4690 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
4697 * perform the pmap work for mincore
4700 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
4702 pd_entry_t *l1p, l1;
4703 pd_entry_t *l2p, l2;
4704 pt_entry_t *l3p, l3;
4715 l1p = pmap_l1(pmap, addr);
4716 if (l1p == NULL) /* No l1 */
4719 l1 = pmap_load(l1p);
4720 if ((l1 & ATTR_DESCR_MASK) == L1_INVAL)
4723 if ((l1 & ATTR_DESCR_MASK) == L1_BLOCK) {
4724 pa = (l1 & ~ATTR_MASK) | (addr & L1_OFFSET);
4725 managed = (l1 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4726 val = MINCORE_SUPER | MINCORE_INCORE;
4727 if (pmap_page_dirty(l1))
4728 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4729 if ((l1 & ATTR_AF) == ATTR_AF)
4730 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4734 l2p = pmap_l1_to_l2(l1p, addr);
4735 if (l2p == NULL) /* No l2 */
4738 l2 = pmap_load(l2p);
4739 if ((l2 & ATTR_DESCR_MASK) == L2_INVAL)
4742 if ((l2 & ATTR_DESCR_MASK) == L2_BLOCK) {
4743 pa = (l2 & ~ATTR_MASK) | (addr & L2_OFFSET);
4744 managed = (l2 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4745 val = MINCORE_SUPER | MINCORE_INCORE;
4746 if (pmap_page_dirty(l2))
4747 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4748 if ((l2 & ATTR_AF) == ATTR_AF)
4749 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4753 l3p = pmap_l2_to_l3(l2p, addr);
4754 if (l3p == NULL) /* No l3 */
4757 l3 = pmap_load(l2p);
4758 if ((l3 & ATTR_DESCR_MASK) == L3_INVAL)
4761 if ((l3 & ATTR_DESCR_MASK) == L3_PAGE) {
4762 pa = (l3 & ~ATTR_MASK) | (addr & L3_OFFSET);
4763 managed = (l3 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4764 val = MINCORE_INCORE;
4765 if (pmap_page_dirty(l3))
4766 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4767 if ((l3 & ATTR_AF) == ATTR_AF)
4768 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4772 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
4773 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
4774 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
4775 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
4778 PA_UNLOCK_COND(*locked_pa);
4785 pmap_activate(struct thread *td)
4790 pmap = vmspace_pmap(td->td_proc->p_vmspace);
4791 td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0);
4792 __asm __volatile("msr ttbr0_el1, %0" : :
4793 "r"(td->td_proc->p_md.md_l0addr));
4794 pmap_invalidate_all(pmap);
4799 pmap_switch(struct thread *old, struct thread *new)
4801 pcpu_bp_harden bp_harden;
4804 /* Store the new curthread */
4805 PCPU_SET(curthread, new);
4807 /* And the new pcb */
4809 PCPU_SET(curpcb, pcb);
4812 * TODO: We may need to flush the cache here if switching
4813 * to a user process.
4817 old->td_proc->p_md.md_l0addr != new->td_proc->p_md.md_l0addr) {
4819 /* Switch to the new pmap */
4820 "msr ttbr0_el1, %0 \n"
4823 /* Invalidate the TLB */
4828 : : "r"(new->td_proc->p_md.md_l0addr));
4831 * Stop userspace from training the branch predictor against
4832 * other processes. This will call into a CPU specific
4833 * function that clears the branch predictor state.
4835 bp_harden = PCPU_GET(bp_harden);
4836 if (bp_harden != NULL)
4844 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
4847 if (va >= VM_MIN_KERNEL_ADDRESS) {
4848 cpu_icache_sync_range(va, sz);
4853 /* Find the length of data in this page to flush */
4854 offset = va & PAGE_MASK;
4855 len = imin(PAGE_SIZE - offset, sz);
4858 /* Extract the physical address & find it in the DMAP */
4859 pa = pmap_extract(pmap, va);
4861 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
4863 /* Move to the next page */
4866 /* Set the length for the next iteration */
4867 len = imin(PAGE_SIZE, sz);
4873 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
4879 switch (ESR_ELx_EXCEPTION(esr)) {
4880 case EXCP_INSN_ABORT_L:
4881 case EXCP_INSN_ABORT:
4882 case EXCP_DATA_ABORT_L:
4883 case EXCP_DATA_ABORT:
4886 return (KERN_FAILURE);
4889 /* Data and insn aborts use same encoding for FCS field. */
4891 switch (esr & ISS_DATA_DFSC_MASK) {
4892 case ISS_DATA_DFSC_TF_L0:
4893 case ISS_DATA_DFSC_TF_L1:
4894 case ISS_DATA_DFSC_TF_L2:
4895 case ISS_DATA_DFSC_TF_L3:
4896 /* Ask the MMU to check the address */
4897 intr = intr_disable();
4898 if (pmap == kernel_pmap)
4899 par = arm64_address_translate_s1e1r(far);
4901 par = arm64_address_translate_s1e0r(far);
4905 * If the translation was successful the address was invalid
4906 * due to a break-before-make sequence. We can unlock and
4907 * return success to the trap handler.
4909 if (PAR_SUCCESS(par)) {
4911 return (KERN_SUCCESS);
4920 return (KERN_FAILURE);
4924 * Increase the starting virtual address of the given mapping if a
4925 * different alignment might result in more superpage mappings.
4928 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4929 vm_offset_t *addr, vm_size_t size)
4931 vm_offset_t superpage_offset;
4935 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
4936 offset += ptoa(object->pg_color);
4937 superpage_offset = offset & L2_OFFSET;
4938 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
4939 (*addr & L2_OFFSET) == superpage_offset)
4941 if ((*addr & L2_OFFSET) < superpage_offset)
4942 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
4944 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
4948 * Get the kernel virtual address of a set of physical pages. If there are
4949 * physical addresses not covered by the DMAP perform a transient mapping
4950 * that will be removed when calling pmap_unmap_io_transient.
4952 * \param page The pages the caller wishes to obtain the virtual
4953 * address on the kernel memory map.
4954 * \param vaddr On return contains the kernel virtual memory address
4955 * of the pages passed in the page parameter.
4956 * \param count Number of pages passed in.
4957 * \param can_fault TRUE if the thread using the mapped pages can take
4958 * page faults, FALSE otherwise.
4960 * \returns TRUE if the caller must call pmap_unmap_io_transient when
4961 * finished or FALSE otherwise.
4965 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
4966 boolean_t can_fault)
4969 boolean_t needs_mapping;
4973 * Allocate any KVA space that we need, this is done in a separate
4974 * loop to prevent calling vmem_alloc while pinned.
4976 needs_mapping = FALSE;
4977 for (i = 0; i < count; i++) {
4978 paddr = VM_PAGE_TO_PHYS(page[i]);
4979 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
4980 error = vmem_alloc(kernel_arena, PAGE_SIZE,
4981 M_BESTFIT | M_WAITOK, &vaddr[i]);
4982 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
4983 needs_mapping = TRUE;
4985 vaddr[i] = PHYS_TO_DMAP(paddr);
4989 /* Exit early if everything is covered by the DMAP */
4995 for (i = 0; i < count; i++) {
4996 paddr = VM_PAGE_TO_PHYS(page[i]);
4997 if (!PHYS_IN_DMAP(paddr)) {
4999 "pmap_map_io_transient: TODO: Map out of DMAP data");
5003 return (needs_mapping);
5007 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
5008 boolean_t can_fault)
5015 for (i = 0; i < count; i++) {
5016 paddr = VM_PAGE_TO_PHYS(page[i]);
5017 if (!PHYS_IN_DMAP(paddr)) {
5018 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");