2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/msgbuf.h>
120 #include <sys/mutex.h>
121 #include <sys/proc.h>
122 #include <sys/rwlock.h>
124 #include <sys/vmem.h>
125 #include <sys/vmmeter.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/_unrhdr.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/vm_pager.h>
140 #include <vm/vm_phys.h>
141 #include <vm/vm_radix.h>
142 #include <vm/vm_reserv.h>
145 #include <machine/machdep.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
149 #include <arm/include/physmem.h>
151 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
152 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
153 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
154 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
156 #define NUL0E L0_ENTRIES
157 #define NUL1E (NUL0E * NL1PG)
158 #define NUL2E (NUL1E * NL2PG)
160 #if !defined(DIAGNOSTIC)
161 #ifdef __GNUC_GNU_INLINE__
162 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
164 #define PMAP_INLINE extern inline
171 * These are configured by the mair_el1 register. This is set up in locore.S
173 #define DEVICE_MEMORY 0
174 #define UNCACHED_MEMORY 1
175 #define CACHED_MEMORY 2
179 #define PV_STAT(x) do { x ; } while (0)
181 #define PV_STAT(x) do { } while (0)
184 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
185 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
187 #define NPV_LIST_LOCKS MAXCPU
189 #define PHYS_TO_PV_LIST_LOCK(pa) \
190 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
192 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
193 struct rwlock **_lockp = (lockp); \
194 struct rwlock *_new_lock; \
196 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
197 if (_new_lock != *_lockp) { \
198 if (*_lockp != NULL) \
199 rw_wunlock(*_lockp); \
200 *_lockp = _new_lock; \
205 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
206 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
208 #define RELEASE_PV_LIST_LOCK(lockp) do { \
209 struct rwlock **_lockp = (lockp); \
211 if (*_lockp != NULL) { \
212 rw_wunlock(*_lockp); \
217 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
218 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
221 * The presence of this flag indicates that the mapping is writeable.
222 * If the ATTR_AP_RO bit is also set, then the mapping is clean, otherwise it is
223 * dirty. This flag may only be set on managed mappings.
225 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
226 * as a software managed bit.
228 #define ATTR_SW_DBM ATTR_DBM
230 struct pmap kernel_pmap_store;
232 /* Used for mapping ACPI memory before VM is initialized */
233 #define PMAP_PREINIT_MAPPING_COUNT 32
234 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
235 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
236 static int vm_initialized = 0; /* No need to use pre-init maps when set */
239 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
240 * Always map entire L2 block for simplicity.
241 * VA of L2 block = preinit_map_va + i * L2_SIZE
243 static struct pmap_preinit_mapping {
247 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
249 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
250 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
251 vm_offset_t kernel_vm_end = 0;
254 * Data for the pv entry allocation mechanism.
256 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
257 static struct mtx pv_chunks_mutex;
258 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
259 static struct md_page *pv_table;
260 static struct md_page pv_dummy;
262 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
263 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
264 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
266 /* This code assumes all L1 DMAP entries will be used */
267 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
268 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
270 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
271 extern pt_entry_t pagetable_dmap[];
273 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
274 static vm_paddr_t physmap[PHYSMAP_SIZE];
275 static u_int physmap_idx;
277 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
279 static int superpages_enabled = 1;
280 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
281 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
282 "Are large page mappings enabled?");
285 * Internal flags for pmap_enter()'s helper functions.
287 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
288 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
290 static void free_pv_chunk(struct pv_chunk *pc);
291 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
292 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
293 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
294 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
295 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
298 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
299 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
300 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
301 vm_offset_t va, struct rwlock **lockp);
302 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
303 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
304 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
305 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
306 u_int flags, vm_page_t m, struct rwlock **lockp);
307 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
308 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
309 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
310 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
311 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
312 vm_page_t m, struct rwlock **lockp);
314 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
315 struct rwlock **lockp);
317 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
318 struct spglist *free);
319 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
320 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
323 * These load the old table data and store the new value.
324 * They need to be atomic as the System MMU may write to the table at
325 * the same time as the CPU.
327 #define pmap_clear(table) atomic_store_64(table, 0)
328 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
329 #define pmap_load(table) (*table)
330 #define pmap_load_clear(table) atomic_swap_64(table, 0)
331 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
332 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
333 #define pmap_store(table, entry) atomic_store_64(table, entry)
335 /********************/
336 /* Inline functions */
337 /********************/
340 pagecopy(void *s, void *d)
343 memcpy(d, s, PAGE_SIZE);
346 static __inline pd_entry_t *
347 pmap_l0(pmap_t pmap, vm_offset_t va)
350 return (&pmap->pm_l0[pmap_l0_index(va)]);
353 static __inline pd_entry_t *
354 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
358 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
359 return (&l1[pmap_l1_index(va)]);
362 static __inline pd_entry_t *
363 pmap_l1(pmap_t pmap, vm_offset_t va)
367 l0 = pmap_l0(pmap, va);
368 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
371 return (pmap_l0_to_l1(l0, va));
374 static __inline pd_entry_t *
375 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
379 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
380 return (&l2[pmap_l2_index(va)]);
383 static __inline pd_entry_t *
384 pmap_l2(pmap_t pmap, vm_offset_t va)
388 l1 = pmap_l1(pmap, va);
389 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
392 return (pmap_l1_to_l2(l1, va));
395 static __inline pt_entry_t *
396 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
400 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
401 return (&l3[pmap_l3_index(va)]);
405 * Returns the lowest valid pde for a given virtual address.
406 * The next level may or may not point to a valid page or block.
408 static __inline pd_entry_t *
409 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
411 pd_entry_t *l0, *l1, *l2, desc;
413 l0 = pmap_l0(pmap, va);
414 desc = pmap_load(l0) & ATTR_DESCR_MASK;
415 if (desc != L0_TABLE) {
420 l1 = pmap_l0_to_l1(l0, va);
421 desc = pmap_load(l1) & ATTR_DESCR_MASK;
422 if (desc != L1_TABLE) {
427 l2 = pmap_l1_to_l2(l1, va);
428 desc = pmap_load(l2) & ATTR_DESCR_MASK;
429 if (desc != L2_TABLE) {
439 * Returns the lowest valid pte block or table entry for a given virtual
440 * address. If there are no valid entries return NULL and set the level to
441 * the first invalid level.
443 static __inline pt_entry_t *
444 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
446 pd_entry_t *l1, *l2, desc;
449 l1 = pmap_l1(pmap, va);
454 desc = pmap_load(l1) & ATTR_DESCR_MASK;
455 if (desc == L1_BLOCK) {
460 if (desc != L1_TABLE) {
465 l2 = pmap_l1_to_l2(l1, va);
466 desc = pmap_load(l2) & ATTR_DESCR_MASK;
467 if (desc == L2_BLOCK) {
472 if (desc != L2_TABLE) {
478 l3 = pmap_l2_to_l3(l2, va);
479 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
486 pmap_ps_enabled(pmap_t pmap __unused)
489 return (superpages_enabled != 0);
493 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
494 pd_entry_t **l2, pt_entry_t **l3)
496 pd_entry_t *l0p, *l1p, *l2p;
498 if (pmap->pm_l0 == NULL)
501 l0p = pmap_l0(pmap, va);
504 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
507 l1p = pmap_l0_to_l1(l0p, va);
510 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
516 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
519 l2p = pmap_l1_to_l2(l1p, va);
522 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
527 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
530 *l3 = pmap_l2_to_l3(l2p, va);
536 pmap_l3_valid(pt_entry_t l3)
539 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
543 CTASSERT(L1_BLOCK == L2_BLOCK);
546 * Checks if the PTE is dirty.
549 pmap_pte_dirty(pt_entry_t pte)
552 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
553 KASSERT((pte & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) != 0,
554 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
556 return ((pte & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
557 (ATTR_AP(ATTR_AP_RW) | ATTR_SW_DBM));
561 pmap_resident_count_inc(pmap_t pmap, int count)
564 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
565 pmap->pm_stats.resident_count += count;
569 pmap_resident_count_dec(pmap_t pmap, int count)
572 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
573 KASSERT(pmap->pm_stats.resident_count >= count,
574 ("pmap %p resident count underflow %ld %d", pmap,
575 pmap->pm_stats.resident_count, count));
576 pmap->pm_stats.resident_count -= count;
580 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
586 l1 = (pd_entry_t *)l1pt;
587 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
589 /* Check locore has used a table L1 map */
590 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
591 ("Invalid bootstrap L1 table"));
592 /* Find the address of the L2 table */
593 l2 = (pt_entry_t *)init_pt_va;
594 *l2_slot = pmap_l2_index(va);
600 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
602 u_int l1_slot, l2_slot;
605 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
607 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
611 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
612 vm_offset_t freemempos)
616 vm_paddr_t l2_pa, pa;
617 u_int l1_slot, l2_slot, prev_l1_slot;
620 dmap_phys_base = min_pa & ~L1_OFFSET;
626 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
627 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
629 for (i = 0; i < (physmap_idx * 2); i += 2) {
630 pa = physmap[i] & ~L2_OFFSET;
631 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
633 /* Create L2 mappings at the start of the region */
634 if ((pa & L1_OFFSET) != 0) {
635 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
636 if (l1_slot != prev_l1_slot) {
637 prev_l1_slot = l1_slot;
638 l2 = (pt_entry_t *)freemempos;
639 l2_pa = pmap_early_vtophys(kern_l1,
641 freemempos += PAGE_SIZE;
643 pmap_store(&pagetable_dmap[l1_slot],
644 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
646 memset(l2, 0, PAGE_SIZE);
649 ("pmap_bootstrap_dmap: NULL l2 map"));
650 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
651 pa += L2_SIZE, va += L2_SIZE) {
653 * We are on a boundary, stop to
654 * create a level 1 block
656 if ((pa & L1_OFFSET) == 0)
659 l2_slot = pmap_l2_index(va);
660 KASSERT(l2_slot != 0, ("..."));
661 pmap_store(&l2[l2_slot],
662 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
663 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
665 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
669 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
670 (physmap[i + 1] - pa) >= L1_SIZE;
671 pa += L1_SIZE, va += L1_SIZE) {
672 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
673 pmap_store(&pagetable_dmap[l1_slot],
674 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
675 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
678 /* Create L2 mappings at the end of the region */
679 if (pa < physmap[i + 1]) {
680 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
681 if (l1_slot != prev_l1_slot) {
682 prev_l1_slot = l1_slot;
683 l2 = (pt_entry_t *)freemempos;
684 l2_pa = pmap_early_vtophys(kern_l1,
686 freemempos += PAGE_SIZE;
688 pmap_store(&pagetable_dmap[l1_slot],
689 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
691 memset(l2, 0, PAGE_SIZE);
694 ("pmap_bootstrap_dmap: NULL l2 map"));
695 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
696 pa += L2_SIZE, va += L2_SIZE) {
697 l2_slot = pmap_l2_index(va);
698 pmap_store(&l2[l2_slot],
699 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
700 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
704 if (pa > dmap_phys_max) {
716 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
723 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
725 l1 = (pd_entry_t *)l1pt;
726 l1_slot = pmap_l1_index(va);
729 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
730 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
732 pa = pmap_early_vtophys(l1pt, l2pt);
733 pmap_store(&l1[l1_slot],
734 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
738 /* Clean the L2 page table */
739 memset((void *)l2_start, 0, l2pt - l2_start);
745 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
752 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
754 l2 = pmap_l2(kernel_pmap, va);
755 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
756 l2_slot = pmap_l2_index(va);
759 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
760 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
762 pa = pmap_early_vtophys(l1pt, l3pt);
763 pmap_store(&l2[l2_slot],
764 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
768 /* Clean the L2 page table */
769 memset((void *)l3_start, 0, l3pt - l3_start);
775 * Bootstrap the system enough to run with virtual memory.
778 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
781 u_int l1_slot, l2_slot;
783 vm_offset_t va, freemempos;
784 vm_offset_t dpcpu, msgbufpv;
785 vm_paddr_t start_pa, pa, min_pa;
789 kern_delta = KERNBASE - kernstart;
791 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
792 printf("%lx\n", l1pt);
793 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
795 /* Set this early so we can use the pagetable walking functions */
796 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
797 PMAP_LOCK_INIT(kernel_pmap);
799 /* Assume the address we were loaded to is a valid physical address */
800 min_pa = KERNBASE - kern_delta;
802 physmap_idx = arm_physmem_avail(physmap, nitems(physmap));
806 * Find the minimum physical address. physmap is sorted,
807 * but may contain empty ranges.
809 for (i = 0; i < (physmap_idx * 2); i += 2) {
810 if (physmap[i] == physmap[i + 1])
812 if (physmap[i] <= min_pa)
816 freemempos = KERNBASE + kernlen;
817 freemempos = roundup2(freemempos, PAGE_SIZE);
819 /* Create a direct map region early so we can use it for pa -> va */
820 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
823 start_pa = pa = KERNBASE - kern_delta;
826 * Read the page table to find out what is already mapped.
827 * This assumes we have mapped a block of memory from KERNBASE
828 * using a single L1 entry.
830 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
832 /* Sanity check the index, KERNBASE should be the first VA */
833 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
835 /* Find how many pages we have mapped */
836 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
837 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
840 /* Check locore used L2 blocks */
841 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
842 ("Invalid bootstrap L2 table"));
843 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
844 ("Incorrect PA in L2 table"));
850 va = roundup2(va, L1_SIZE);
852 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
853 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
854 /* And the l3 tables for the early devmap */
855 freemempos = pmap_bootstrap_l3(l1pt,
856 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
860 #define alloc_pages(var, np) \
861 (var) = freemempos; \
862 freemempos += (np * PAGE_SIZE); \
863 memset((char *)(var), 0, ((np) * PAGE_SIZE));
865 /* Allocate dynamic per-cpu area. */
866 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
867 dpcpu_init((void *)dpcpu, 0);
869 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
870 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
871 msgbufp = (void *)msgbufpv;
873 /* Reserve some VA space for early BIOS/ACPI mapping */
874 preinit_map_va = roundup2(freemempos, L2_SIZE);
876 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
877 virtual_avail = roundup2(virtual_avail, L1_SIZE);
878 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
879 kernel_vm_end = virtual_avail;
881 pa = pmap_early_vtophys(l1pt, freemempos);
883 arm_physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
889 * Initialize a vm_page's machine-dependent fields.
892 pmap_page_init(vm_page_t m)
895 TAILQ_INIT(&m->md.pv_list);
896 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
900 * Initialize the pmap module.
901 * Called by vm_init, to initialize any structures that the pmap
902 * system needs to map virtual memory.
911 * Are large page mappings enabled?
913 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
914 if (superpages_enabled) {
915 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
916 ("pmap_init: can't assign to pagesizes[1]"));
917 pagesizes[1] = L2_SIZE;
921 * Initialize the pv chunk list mutex.
923 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
926 * Initialize the pool of pv list locks.
928 for (i = 0; i < NPV_LIST_LOCKS; i++)
929 rw_init(&pv_list_locks[i], "pmap pv list");
932 * Calculate the size of the pv head table for superpages.
934 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
937 * Allocate memory for the pv head table for superpages.
939 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
941 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
942 for (i = 0; i < pv_npg; i++)
943 TAILQ_INIT(&pv_table[i].pv_list);
944 TAILQ_INIT(&pv_dummy.pv_list);
949 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
950 "2MB page mapping counters");
952 static u_long pmap_l2_demotions;
953 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
954 &pmap_l2_demotions, 0, "2MB page demotions");
956 static u_long pmap_l2_mappings;
957 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
958 &pmap_l2_mappings, 0, "2MB page mappings");
960 static u_long pmap_l2_p_failures;
961 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
962 &pmap_l2_p_failures, 0, "2MB page promotion failures");
964 static u_long pmap_l2_promotions;
965 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
966 &pmap_l2_promotions, 0, "2MB page promotions");
969 * Invalidate a single TLB entry.
972 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
978 "tlbi vaae1is, %0 \n"
981 : : "r"(va >> PAGE_SHIFT));
986 pmap_invalidate_range_nopin(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
991 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
993 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
1000 static __inline void
1001 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1005 pmap_invalidate_range_nopin(pmap, sva, eva);
1009 static __inline void
1010 pmap_invalidate_all(pmap_t pmap)
1023 * Routine: pmap_extract
1025 * Extract the physical page address associated
1026 * with the given map/virtual_address pair.
1029 pmap_extract(pmap_t pmap, vm_offset_t va)
1031 pt_entry_t *pte, tpte;
1038 * Find the block or page map for this virtual address. pmap_pte
1039 * will return either a valid block/page entry, or NULL.
1041 pte = pmap_pte(pmap, va, &lvl);
1043 tpte = pmap_load(pte);
1044 pa = tpte & ~ATTR_MASK;
1047 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1048 ("pmap_extract: Invalid L1 pte found: %lx",
1049 tpte & ATTR_DESCR_MASK));
1050 pa |= (va & L1_OFFSET);
1053 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1054 ("pmap_extract: Invalid L2 pte found: %lx",
1055 tpte & ATTR_DESCR_MASK));
1056 pa |= (va & L2_OFFSET);
1059 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1060 ("pmap_extract: Invalid L3 pte found: %lx",
1061 tpte & ATTR_DESCR_MASK));
1062 pa |= (va & L3_OFFSET);
1071 * Routine: pmap_extract_and_hold
1073 * Atomically extract and hold the physical page
1074 * with the given pmap and virtual address pair
1075 * if that mapping permits the given protection.
1078 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1080 pt_entry_t *pte, tpte;
1090 pte = pmap_pte(pmap, va, &lvl);
1092 tpte = pmap_load(pte);
1094 KASSERT(lvl > 0 && lvl <= 3,
1095 ("pmap_extract_and_hold: Invalid level %d", lvl));
1096 CTASSERT(L1_BLOCK == L2_BLOCK);
1097 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1098 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1099 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1100 tpte & ATTR_DESCR_MASK));
1101 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1102 ((prot & VM_PROT_WRITE) == 0)) {
1105 off = va & L1_OFFSET;
1108 off = va & L2_OFFSET;
1114 if (vm_page_pa_tryrelock(pmap,
1115 (tpte & ~ATTR_MASK) | off, &pa))
1117 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1127 pmap_kextract(vm_offset_t va)
1129 pt_entry_t *pte, tpte;
1131 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
1132 return (DMAP_TO_PHYS(va));
1133 pte = pmap_l1(kernel_pmap, va);
1138 * A concurrent pmap_update_entry() will clear the entry's valid bit
1139 * but leave the rest of the entry unchanged. Therefore, we treat a
1140 * non-zero entry as being valid, and we ignore the valid bit when
1141 * determining whether the entry maps a block, page, or table.
1143 tpte = pmap_load(pte);
1146 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1147 return ((tpte & ~ATTR_MASK) | (va & L1_OFFSET));
1148 pte = pmap_l1_to_l2(&tpte, va);
1149 tpte = pmap_load(pte);
1152 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1153 return ((tpte & ~ATTR_MASK) | (va & L2_OFFSET));
1154 pte = pmap_l2_to_l3(&tpte, va);
1155 tpte = pmap_load(pte);
1158 return ((tpte & ~ATTR_MASK) | (va & L3_OFFSET));
1161 /***************************************************
1162 * Low level mapping routines.....
1163 ***************************************************/
1166 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1169 pt_entry_t *pte, attr;
1173 KASSERT((pa & L3_OFFSET) == 0,
1174 ("pmap_kenter: Invalid physical address"));
1175 KASSERT((sva & L3_OFFSET) == 0,
1176 ("pmap_kenter: Invalid virtual address"));
1177 KASSERT((size & PAGE_MASK) == 0,
1178 ("pmap_kenter: Mapping is not page-sized"));
1180 attr = ATTR_DEFAULT | ATTR_IDX(mode) | L3_PAGE;
1181 if (mode == DEVICE_MEMORY)
1186 pde = pmap_pde(kernel_pmap, va, &lvl);
1187 KASSERT(pde != NULL,
1188 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1189 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1191 pte = pmap_l2_to_l3(pde, va);
1192 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1198 pmap_invalidate_range(kernel_pmap, sva, va);
1202 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1205 pmap_kenter(sva, size, pa, DEVICE_MEMORY);
1209 * Remove a page from the kernel pagetables.
1212 pmap_kremove(vm_offset_t va)
1217 pte = pmap_pte(kernel_pmap, va, &lvl);
1218 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1219 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1222 pmap_invalidate_page(kernel_pmap, va);
1226 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1232 KASSERT((sva & L3_OFFSET) == 0,
1233 ("pmap_kremove_device: Invalid virtual address"));
1234 KASSERT((size & PAGE_MASK) == 0,
1235 ("pmap_kremove_device: Mapping is not page-sized"));
1239 pte = pmap_pte(kernel_pmap, va, &lvl);
1240 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1242 ("Invalid device pagetable level: %d != 3", lvl));
1248 pmap_invalidate_range(kernel_pmap, sva, va);
1252 * Used to map a range of physical addresses into kernel
1253 * virtual address space.
1255 * The value passed in '*virt' is a suggested virtual address for
1256 * the mapping. Architectures which can support a direct-mapped
1257 * physical to virtual region can return the appropriate address
1258 * within that region, leaving '*virt' unchanged. Other
1259 * architectures should map the pages starting at '*virt' and
1260 * update '*virt' with the first usable address after the mapped
1264 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1266 return PHYS_TO_DMAP(start);
1271 * Add a list of wired pages to the kva
1272 * this routine is only used for temporary
1273 * kernel mappings that do not need to have
1274 * page modification or references recorded.
1275 * Note that old mappings are simply written
1276 * over. The page *must* be wired.
1277 * Note: SMP coherent. Uses a ranged shootdown IPI.
1280 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1283 pt_entry_t *pte, pa;
1289 for (i = 0; i < count; i++) {
1290 pde = pmap_pde(kernel_pmap, va, &lvl);
1291 KASSERT(pde != NULL,
1292 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1294 ("pmap_qenter: Invalid level %d", lvl));
1297 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1298 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1299 if (m->md.pv_memattr == DEVICE_MEMORY)
1301 pte = pmap_l2_to_l3(pde, va);
1302 pmap_load_store(pte, pa);
1306 pmap_invalidate_range(kernel_pmap, sva, va);
1310 * This routine tears out page mappings from the
1311 * kernel -- it is meant only for temporary mappings.
1314 pmap_qremove(vm_offset_t sva, int count)
1320 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1323 while (count-- > 0) {
1324 pte = pmap_pte(kernel_pmap, va, &lvl);
1326 ("Invalid device pagetable level: %d != 3", lvl));
1333 pmap_invalidate_range(kernel_pmap, sva, va);
1336 /***************************************************
1337 * Page table page management routines.....
1338 ***************************************************/
1340 * Schedule the specified unused page table page to be freed. Specifically,
1341 * add the page to the specified list of pages that will be released to the
1342 * physical memory manager after the TLB has been updated.
1344 static __inline void
1345 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1346 boolean_t set_PG_ZERO)
1350 m->flags |= PG_ZERO;
1352 m->flags &= ~PG_ZERO;
1353 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1357 * Decrements a page table page's wire count, which is used to record the
1358 * number of valid page table entries within the page. If the wire count
1359 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1360 * page table page was unmapped and FALSE otherwise.
1362 static inline boolean_t
1363 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1367 if (m->wire_count == 0) {
1368 _pmap_unwire_l3(pmap, va, m, free);
1375 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1378 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1380 * unmap the page table page
1382 if (m->pindex >= (NUL2E + NUL1E)) {
1386 l0 = pmap_l0(pmap, va);
1388 } else if (m->pindex >= NUL2E) {
1392 l1 = pmap_l1(pmap, va);
1398 l2 = pmap_l2(pmap, va);
1401 pmap_resident_count_dec(pmap, 1);
1402 if (m->pindex < NUL2E) {
1403 /* We just released an l3, unhold the matching l2 */
1404 pd_entry_t *l1, tl1;
1407 l1 = pmap_l1(pmap, va);
1408 tl1 = pmap_load(l1);
1409 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1410 pmap_unwire_l3(pmap, va, l2pg, free);
1411 } else if (m->pindex < (NUL2E + NUL1E)) {
1412 /* We just released an l2, unhold the matching l1 */
1413 pd_entry_t *l0, tl0;
1416 l0 = pmap_l0(pmap, va);
1417 tl0 = pmap_load(l0);
1418 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1419 pmap_unwire_l3(pmap, va, l1pg, free);
1421 pmap_invalidate_page(pmap, va);
1424 * Put page on a list so that it is released after
1425 * *ALL* TLB shootdown is done
1427 pmap_add_delayed_free_list(m, free, TRUE);
1431 * After removing a page table entry, this routine is used to
1432 * conditionally free the page, and manage the hold/wire counts.
1435 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1436 struct spglist *free)
1440 if (va >= VM_MAXUSER_ADDRESS)
1442 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1443 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1444 return (pmap_unwire_l3(pmap, va, mpte, free));
1448 pmap_pinit0(pmap_t pmap)
1451 PMAP_LOCK_INIT(pmap);
1452 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1453 pmap->pm_l0 = kernel_pmap->pm_l0;
1454 pmap->pm_root.rt_root = 0;
1458 pmap_pinit(pmap_t pmap)
1464 * allocate the l0 page
1466 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1467 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1470 l0phys = VM_PAGE_TO_PHYS(l0pt);
1471 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1473 if ((l0pt->flags & PG_ZERO) == 0)
1474 pagezero(pmap->pm_l0);
1476 pmap->pm_root.rt_root = 0;
1477 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1483 * This routine is called if the desired page table page does not exist.
1485 * If page table page allocation fails, this routine may sleep before
1486 * returning NULL. It sleeps only if a lock pointer was given.
1488 * Note: If a page allocation fails at page table level two or three,
1489 * one or two pages may be held during the wait, only to be released
1490 * afterwards. This conservative approach is easily argued to avoid
1494 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1496 vm_page_t m, l1pg, l2pg;
1498 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1501 * Allocate a page table page.
1503 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1504 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1505 if (lockp != NULL) {
1506 RELEASE_PV_LIST_LOCK(lockp);
1513 * Indicate the need to retry. While waiting, the page table
1514 * page may have been allocated.
1518 if ((m->flags & PG_ZERO) == 0)
1522 * Because of AArch64's weak memory consistency model, we must have a
1523 * barrier here to ensure that the stores for zeroing "m", whether by
1524 * pmap_zero_page() or an earlier function, are visible before adding
1525 * "m" to the page table. Otherwise, a page table walk by another
1526 * processor's MMU could see the mapping to "m" and a stale, non-zero
1532 * Map the pagetable page into the process address space, if
1533 * it isn't already there.
1536 if (ptepindex >= (NUL2E + NUL1E)) {
1538 vm_pindex_t l0index;
1540 l0index = ptepindex - (NUL2E + NUL1E);
1541 l0 = &pmap->pm_l0[l0index];
1542 pmap_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1543 } else if (ptepindex >= NUL2E) {
1544 vm_pindex_t l0index, l1index;
1545 pd_entry_t *l0, *l1;
1548 l1index = ptepindex - NUL2E;
1549 l0index = l1index >> L0_ENTRIES_SHIFT;
1551 l0 = &pmap->pm_l0[l0index];
1552 tl0 = pmap_load(l0);
1554 /* recurse for allocating page dir */
1555 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1557 vm_page_unwire_noq(m);
1558 vm_page_free_zero(m);
1562 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1566 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1567 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1568 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1570 vm_pindex_t l0index, l1index;
1571 pd_entry_t *l0, *l1, *l2;
1572 pd_entry_t tl0, tl1;
1574 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1575 l0index = l1index >> L0_ENTRIES_SHIFT;
1577 l0 = &pmap->pm_l0[l0index];
1578 tl0 = pmap_load(l0);
1580 /* recurse for allocating page dir */
1581 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1583 vm_page_unwire_noq(m);
1584 vm_page_free_zero(m);
1587 tl0 = pmap_load(l0);
1588 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1589 l1 = &l1[l1index & Ln_ADDR_MASK];
1591 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1592 l1 = &l1[l1index & Ln_ADDR_MASK];
1593 tl1 = pmap_load(l1);
1595 /* recurse for allocating page dir */
1596 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1598 vm_page_unwire_noq(m);
1599 vm_page_free_zero(m);
1603 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1608 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1609 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1610 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1613 pmap_resident_count_inc(pmap, 1);
1619 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1623 vm_pindex_t l2pindex;
1626 l1 = pmap_l1(pmap, va);
1627 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1628 /* Add a reference to the L2 page. */
1629 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1632 /* Allocate a L2 page. */
1633 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1634 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1635 if (l2pg == NULL && lockp != NULL)
1642 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1644 vm_pindex_t ptepindex;
1645 pd_entry_t *pde, tpde;
1653 * Calculate pagetable page index
1655 ptepindex = pmap_l2_pindex(va);
1658 * Get the page directory entry
1660 pde = pmap_pde(pmap, va, &lvl);
1663 * If the page table page is mapped, we just increment the hold count,
1664 * and activate it. If we get a level 2 pde it will point to a level 3
1672 pte = pmap_l0_to_l1(pde, va);
1673 KASSERT(pmap_load(pte) == 0,
1674 ("pmap_alloc_l3: TODO: l0 superpages"));
1679 pte = pmap_l1_to_l2(pde, va);
1680 KASSERT(pmap_load(pte) == 0,
1681 ("pmap_alloc_l3: TODO: l1 superpages"));
1685 tpde = pmap_load(pde);
1687 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1693 panic("pmap_alloc_l3: Invalid level %d", lvl);
1697 * Here if the pte page isn't mapped, or if it has been deallocated.
1699 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1700 if (m == NULL && lockp != NULL)
1706 /***************************************************
1707 * Pmap allocation/deallocation routines.
1708 ***************************************************/
1711 * Release any resources held by the given physical map.
1712 * Called when a pmap initialized by pmap_pinit is being released.
1713 * Should only be called if the map contains no valid mappings.
1716 pmap_release(pmap_t pmap)
1720 KASSERT(pmap->pm_stats.resident_count == 0,
1721 ("pmap_release: pmap resident count %ld != 0",
1722 pmap->pm_stats.resident_count));
1723 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1724 ("pmap_release: pmap has reserved page table page(s)"));
1726 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1728 vm_page_unwire_noq(m);
1729 vm_page_free_zero(m);
1733 kvm_size(SYSCTL_HANDLER_ARGS)
1735 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1737 return sysctl_handle_long(oidp, &ksize, 0, req);
1739 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1740 0, 0, kvm_size, "LU", "Size of KVM");
1743 kvm_free(SYSCTL_HANDLER_ARGS)
1745 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1747 return sysctl_handle_long(oidp, &kfree, 0, req);
1749 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1750 0, 0, kvm_free, "LU", "Amount of KVM free");
1753 * grow the number of kernel page table entries, if needed
1756 pmap_growkernel(vm_offset_t addr)
1760 pd_entry_t *l0, *l1, *l2;
1762 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1764 addr = roundup2(addr, L2_SIZE);
1765 if (addr - 1 >= vm_map_max(kernel_map))
1766 addr = vm_map_max(kernel_map);
1767 while (kernel_vm_end < addr) {
1768 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1769 KASSERT(pmap_load(l0) != 0,
1770 ("pmap_growkernel: No level 0 kernel entry"));
1772 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1773 if (pmap_load(l1) == 0) {
1774 /* We need a new PDP entry */
1775 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1776 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1777 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1779 panic("pmap_growkernel: no memory to grow kernel");
1780 if ((nkpg->flags & PG_ZERO) == 0)
1781 pmap_zero_page(nkpg);
1782 /* See the dmb() in _pmap_alloc_l3(). */
1784 paddr = VM_PAGE_TO_PHYS(nkpg);
1785 pmap_store(l1, paddr | L1_TABLE);
1786 continue; /* try again */
1788 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1789 if (pmap_load(l2) != 0) {
1790 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1791 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1792 kernel_vm_end = vm_map_max(kernel_map);
1798 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1799 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1802 panic("pmap_growkernel: no memory to grow kernel");
1803 if ((nkpg->flags & PG_ZERO) == 0)
1804 pmap_zero_page(nkpg);
1805 /* See the dmb() in _pmap_alloc_l3(). */
1807 paddr = VM_PAGE_TO_PHYS(nkpg);
1808 pmap_store(l2, paddr | L2_TABLE);
1810 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1811 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1812 kernel_vm_end = vm_map_max(kernel_map);
1819 /***************************************************
1820 * page management routines.
1821 ***************************************************/
1823 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1824 CTASSERT(_NPCM == 3);
1825 CTASSERT(_NPCPV == 168);
1827 static __inline struct pv_chunk *
1828 pv_to_chunk(pv_entry_t pv)
1831 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1834 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1836 #define PC_FREE0 0xfffffffffffffffful
1837 #define PC_FREE1 0xfffffffffffffffful
1838 #define PC_FREE2 0x000000fffffffffful
1840 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1844 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1846 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1847 "Current number of pv entry chunks");
1848 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1849 "Current number of pv entry chunks allocated");
1850 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1851 "Current number of pv entry chunks frees");
1852 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1853 "Number of times tried to get a chunk page but failed.");
1855 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1856 static int pv_entry_spare;
1858 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1859 "Current number of pv entry frees");
1860 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1861 "Current number of pv entry allocs");
1862 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1863 "Current number of pv entries");
1864 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1865 "Current number of spare pv entries");
1870 * We are in a serious low memory condition. Resort to
1871 * drastic measures to free some pages so we can allocate
1872 * another pv entry chunk.
1874 * Returns NULL if PV entries were reclaimed from the specified pmap.
1876 * We do not, however, unmap 2mpages because subsequent accesses will
1877 * allocate per-page pv entries until repromotion occurs, thereby
1878 * exacerbating the shortage of free pv entries.
1881 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1883 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
1884 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
1885 struct md_page *pvh;
1887 pmap_t next_pmap, pmap;
1888 pt_entry_t *pte, tpte;
1892 struct spglist free;
1894 int bit, field, freed, lvl;
1895 static int active_reclaims = 0;
1897 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1898 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
1903 bzero(&pc_marker_b, sizeof(pc_marker_b));
1904 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
1905 pc_marker = (struct pv_chunk *)&pc_marker_b;
1906 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
1908 mtx_lock(&pv_chunks_mutex);
1910 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
1911 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
1912 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
1913 SLIST_EMPTY(&free)) {
1914 next_pmap = pc->pc_pmap;
1915 if (next_pmap == NULL) {
1917 * The next chunk is a marker. However, it is
1918 * not our marker, so active_reclaims must be
1919 * > 1. Consequently, the next_chunk code
1920 * will not rotate the pv_chunks list.
1924 mtx_unlock(&pv_chunks_mutex);
1927 * A pv_chunk can only be removed from the pc_lru list
1928 * when both pv_chunks_mutex is owned and the
1929 * corresponding pmap is locked.
1931 if (pmap != next_pmap) {
1932 if (pmap != NULL && pmap != locked_pmap)
1935 /* Avoid deadlock and lock recursion. */
1936 if (pmap > locked_pmap) {
1937 RELEASE_PV_LIST_LOCK(lockp);
1939 mtx_lock(&pv_chunks_mutex);
1941 } else if (pmap != locked_pmap) {
1942 if (PMAP_TRYLOCK(pmap)) {
1943 mtx_lock(&pv_chunks_mutex);
1946 pmap = NULL; /* pmap is not locked */
1947 mtx_lock(&pv_chunks_mutex);
1948 pc = TAILQ_NEXT(pc_marker, pc_lru);
1950 pc->pc_pmap != next_pmap)
1958 * Destroy every non-wired, 4 KB page mapping in the chunk.
1961 for (field = 0; field < _NPCM; field++) {
1962 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1963 inuse != 0; inuse &= ~(1UL << bit)) {
1964 bit = ffsl(inuse) - 1;
1965 pv = &pc->pc_pventry[field * 64 + bit];
1967 pde = pmap_pde(pmap, va, &lvl);
1970 pte = pmap_l2_to_l3(pde, va);
1971 tpte = pmap_load(pte);
1972 if ((tpte & ATTR_SW_WIRED) != 0)
1974 tpte = pmap_load_clear(pte);
1975 pmap_invalidate_page(pmap, va);
1976 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
1977 if (pmap_pte_dirty(tpte))
1979 if ((tpte & ATTR_AF) != 0)
1980 vm_page_aflag_set(m, PGA_REFERENCED);
1981 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1982 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
1984 if (TAILQ_EMPTY(&m->md.pv_list) &&
1985 (m->flags & PG_FICTITIOUS) == 0) {
1986 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
1987 if (TAILQ_EMPTY(&pvh->pv_list)) {
1988 vm_page_aflag_clear(m,
1992 pc->pc_map[field] |= 1UL << bit;
1993 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
1998 mtx_lock(&pv_chunks_mutex);
2001 /* Every freed mapping is for a 4 KB page. */
2002 pmap_resident_count_dec(pmap, freed);
2003 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2004 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2005 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2006 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2007 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2008 pc->pc_map[2] == PC_FREE2) {
2009 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2010 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2011 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2012 /* Entire chunk is free; return it. */
2013 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2014 dump_drop_page(m_pc->phys_addr);
2015 mtx_lock(&pv_chunks_mutex);
2016 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2019 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2020 mtx_lock(&pv_chunks_mutex);
2021 /* One freed pv entry in locked_pmap is sufficient. */
2022 if (pmap == locked_pmap)
2026 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2027 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2028 if (active_reclaims == 1 && pmap != NULL) {
2030 * Rotate the pv chunks list so that we do not
2031 * scan the same pv chunks that could not be
2032 * freed (because they contained a wired
2033 * and/or superpage mapping) on every
2034 * invocation of reclaim_pv_chunk().
2036 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2037 MPASS(pc->pc_pmap != NULL);
2038 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2039 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2043 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2044 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2046 mtx_unlock(&pv_chunks_mutex);
2047 if (pmap != NULL && pmap != locked_pmap)
2049 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2050 m_pc = SLIST_FIRST(&free);
2051 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2052 /* Recycle a freed page table page. */
2053 m_pc->wire_count = 1;
2055 vm_page_free_pages_toq(&free, true);
2060 * free the pv_entry back to the free list
2063 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2065 struct pv_chunk *pc;
2066 int idx, field, bit;
2068 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2069 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2070 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2071 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2072 pc = pv_to_chunk(pv);
2073 idx = pv - &pc->pc_pventry[0];
2076 pc->pc_map[field] |= 1ul << bit;
2077 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2078 pc->pc_map[2] != PC_FREE2) {
2079 /* 98% of the time, pc is already at the head of the list. */
2080 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2081 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2082 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2086 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2091 free_pv_chunk(struct pv_chunk *pc)
2095 mtx_lock(&pv_chunks_mutex);
2096 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2097 mtx_unlock(&pv_chunks_mutex);
2098 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2099 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2100 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2101 /* entire chunk is free, return it */
2102 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2103 dump_drop_page(m->phys_addr);
2104 vm_page_unwire_noq(m);
2109 * Returns a new PV entry, allocating a new PV chunk from the system when
2110 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2111 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2114 * The given PV list lock may be released.
2117 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2121 struct pv_chunk *pc;
2124 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2125 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2127 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2129 for (field = 0; field < _NPCM; field++) {
2130 if (pc->pc_map[field]) {
2131 bit = ffsl(pc->pc_map[field]) - 1;
2135 if (field < _NPCM) {
2136 pv = &pc->pc_pventry[field * 64 + bit];
2137 pc->pc_map[field] &= ~(1ul << bit);
2138 /* If this was the last item, move it to tail */
2139 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2140 pc->pc_map[2] == 0) {
2141 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2142 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2145 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2146 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2150 /* No free items, allocate another chunk */
2151 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2154 if (lockp == NULL) {
2155 PV_STAT(pc_chunk_tryfail++);
2158 m = reclaim_pv_chunk(pmap, lockp);
2162 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2163 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2164 dump_add_page(m->phys_addr);
2165 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2167 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2168 pc->pc_map[1] = PC_FREE1;
2169 pc->pc_map[2] = PC_FREE2;
2170 mtx_lock(&pv_chunks_mutex);
2171 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2172 mtx_unlock(&pv_chunks_mutex);
2173 pv = &pc->pc_pventry[0];
2174 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2175 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2176 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2181 * Ensure that the number of spare PV entries in the specified pmap meets or
2182 * exceeds the given count, "needed".
2184 * The given PV list lock may be released.
2187 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2189 struct pch new_tail;
2190 struct pv_chunk *pc;
2195 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2196 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2199 * Newly allocated PV chunks must be stored in a private list until
2200 * the required number of PV chunks have been allocated. Otherwise,
2201 * reclaim_pv_chunk() could recycle one of these chunks. In
2202 * contrast, these chunks must be added to the pmap upon allocation.
2204 TAILQ_INIT(&new_tail);
2207 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2208 bit_count((bitstr_t *)pc->pc_map, 0,
2209 sizeof(pc->pc_map) * NBBY, &free);
2213 if (avail >= needed)
2216 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2217 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2220 m = reclaim_pv_chunk(pmap, lockp);
2225 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2226 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2227 dump_add_page(m->phys_addr);
2228 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2230 pc->pc_map[0] = PC_FREE0;
2231 pc->pc_map[1] = PC_FREE1;
2232 pc->pc_map[2] = PC_FREE2;
2233 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2234 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2235 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2238 * The reclaim might have freed a chunk from the current pmap.
2239 * If that chunk contained available entries, we need to
2240 * re-count the number of available entries.
2245 if (!TAILQ_EMPTY(&new_tail)) {
2246 mtx_lock(&pv_chunks_mutex);
2247 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2248 mtx_unlock(&pv_chunks_mutex);
2253 * First find and then remove the pv entry for the specified pmap and virtual
2254 * address from the specified pv list. Returns the pv entry if found and NULL
2255 * otherwise. This operation can be performed on pv lists for either 4KB or
2256 * 2MB page mappings.
2258 static __inline pv_entry_t
2259 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2263 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2264 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2265 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2274 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2275 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2276 * entries for each of the 4KB page mappings.
2279 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2280 struct rwlock **lockp)
2282 struct md_page *pvh;
2283 struct pv_chunk *pc;
2285 vm_offset_t va_last;
2289 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2290 KASSERT((va & L2_OFFSET) == 0,
2291 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
2292 KASSERT((pa & L2_OFFSET) == 0,
2293 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2294 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2297 * Transfer the 2mpage's pv entry for this mapping to the first
2298 * page's pv list. Once this transfer begins, the pv list lock
2299 * must not be released until the last pv entry is reinstantiated.
2301 pvh = pa_to_pvh(pa);
2302 pv = pmap_pvh_remove(pvh, pmap, va);
2303 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2304 m = PHYS_TO_VM_PAGE(pa);
2305 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2307 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2308 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2309 va_last = va + L2_SIZE - PAGE_SIZE;
2311 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2312 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2313 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2314 for (field = 0; field < _NPCM; field++) {
2315 while (pc->pc_map[field]) {
2316 bit = ffsl(pc->pc_map[field]) - 1;
2317 pc->pc_map[field] &= ~(1ul << bit);
2318 pv = &pc->pc_pventry[field * 64 + bit];
2322 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2323 ("pmap_pv_demote_l2: page %p is not managed", m));
2324 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2330 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2331 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2334 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2335 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2336 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2338 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2339 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2343 * First find and then destroy the pv entry for the specified pmap and virtual
2344 * address. This operation can be performed on pv lists for either 4KB or 2MB
2348 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2352 pv = pmap_pvh_remove(pvh, pmap, va);
2353 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2354 free_pv_entry(pmap, pv);
2358 * Conditionally create the PV entry for a 4KB page mapping if the required
2359 * memory can be allocated without resorting to reclamation.
2362 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2363 struct rwlock **lockp)
2367 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2368 /* Pass NULL instead of the lock pointer to disable reclamation. */
2369 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2371 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2372 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2380 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2381 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2382 * false if the PV entry cannot be allocated without resorting to reclamation.
2385 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2386 struct rwlock **lockp)
2388 struct md_page *pvh;
2392 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2393 /* Pass NULL instead of the lock pointer to disable reclamation. */
2394 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2395 NULL : lockp)) == NULL)
2398 pa = l2e & ~ATTR_MASK;
2399 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2400 pvh = pa_to_pvh(pa);
2401 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2407 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2409 pt_entry_t newl2, oldl2;
2413 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2414 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2415 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2417 ml3 = pmap_remove_pt_page(pmap, va);
2419 panic("pmap_remove_kernel_l2: Missing pt page");
2421 ml3pa = VM_PAGE_TO_PHYS(ml3);
2422 newl2 = ml3pa | L2_TABLE;
2425 * If this page table page was unmapped by a promotion, then it
2426 * contains valid mappings. Zero it to invalidate those mappings.
2428 if (ml3->valid != 0)
2429 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2432 * Demote the mapping. The caller must have already invalidated the
2433 * mapping (i.e., the "break" in break-before-make).
2435 oldl2 = pmap_load_store(l2, newl2);
2436 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
2437 __func__, l2, oldl2));
2441 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
2444 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2445 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2447 struct md_page *pvh;
2449 vm_offset_t eva, va;
2452 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2453 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2454 old_l2 = pmap_load_clear(l2);
2455 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2456 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2459 * Since a promotion must break the 4KB page mappings before making
2460 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2462 pmap_invalidate_page(pmap, sva);
2464 if (old_l2 & ATTR_SW_WIRED)
2465 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2466 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2467 if (old_l2 & ATTR_SW_MANAGED) {
2468 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2469 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2470 pmap_pvh_free(pvh, pmap, sva);
2471 eva = sva + L2_SIZE;
2472 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2473 va < eva; va += PAGE_SIZE, m++) {
2474 if (pmap_pte_dirty(old_l2))
2476 if (old_l2 & ATTR_AF)
2477 vm_page_aflag_set(m, PGA_REFERENCED);
2478 if (TAILQ_EMPTY(&m->md.pv_list) &&
2479 TAILQ_EMPTY(&pvh->pv_list))
2480 vm_page_aflag_clear(m, PGA_WRITEABLE);
2483 if (pmap == kernel_pmap) {
2484 pmap_remove_kernel_l2(pmap, l2, sva);
2486 ml3 = pmap_remove_pt_page(pmap, sva);
2488 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
2489 ("pmap_remove_l2: l3 page not promoted"));
2490 pmap_resident_count_dec(pmap, 1);
2491 KASSERT(ml3->wire_count == NL3PG,
2492 ("pmap_remove_l2: l3 page wire count error"));
2493 ml3->wire_count = 0;
2494 pmap_add_delayed_free_list(ml3, free, FALSE);
2497 return (pmap_unuse_pt(pmap, sva, l1e, free));
2501 * pmap_remove_l3: do the things to unmap a page in a process
2504 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2505 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2507 struct md_page *pvh;
2511 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2512 old_l3 = pmap_load_clear(l3);
2513 pmap_invalidate_page(pmap, va);
2514 if (old_l3 & ATTR_SW_WIRED)
2515 pmap->pm_stats.wired_count -= 1;
2516 pmap_resident_count_dec(pmap, 1);
2517 if (old_l3 & ATTR_SW_MANAGED) {
2518 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2519 if (pmap_pte_dirty(old_l3))
2521 if (old_l3 & ATTR_AF)
2522 vm_page_aflag_set(m, PGA_REFERENCED);
2523 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2524 pmap_pvh_free(&m->md, pmap, va);
2525 if (TAILQ_EMPTY(&m->md.pv_list) &&
2526 (m->flags & PG_FICTITIOUS) == 0) {
2527 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2528 if (TAILQ_EMPTY(&pvh->pv_list))
2529 vm_page_aflag_clear(m, PGA_WRITEABLE);
2532 return (pmap_unuse_pt(pmap, va, l2e, free));
2536 * Remove the specified range of addresses from the L3 page table that is
2537 * identified by the given L2 entry.
2540 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
2541 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
2543 struct md_page *pvh;
2544 struct rwlock *new_lock;
2545 pt_entry_t *l3, old_l3;
2549 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2550 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
2551 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
2553 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
2554 if (!pmap_l3_valid(pmap_load(l3))) {
2556 pmap_invalidate_range(pmap, va, sva);
2561 old_l3 = pmap_load_clear(l3);
2562 if ((old_l3 & ATTR_SW_WIRED) != 0)
2563 pmap->pm_stats.wired_count--;
2564 pmap_resident_count_dec(pmap, 1);
2565 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
2566 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2567 if (pmap_pte_dirty(old_l3))
2569 if ((old_l3 & ATTR_AF) != 0)
2570 vm_page_aflag_set(m, PGA_REFERENCED);
2571 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
2572 if (new_lock != *lockp) {
2573 if (*lockp != NULL) {
2575 * Pending TLB invalidations must be
2576 * performed before the PV list lock is
2577 * released. Otherwise, a concurrent
2578 * pmap_remove_all() on a physical page
2579 * could return while a stale TLB entry
2580 * still provides access to that page.
2583 pmap_invalidate_range(pmap, va,
2592 pmap_pvh_free(&m->md, pmap, sva);
2593 if (TAILQ_EMPTY(&m->md.pv_list) &&
2594 (m->flags & PG_FICTITIOUS) == 0) {
2595 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2596 if (TAILQ_EMPTY(&pvh->pv_list))
2597 vm_page_aflag_clear(m, PGA_WRITEABLE);
2602 if (pmap_unuse_pt(pmap, sva, l2e, free)) {
2608 pmap_invalidate_range(pmap, va, sva);
2612 * Remove the given range of addresses from the specified map.
2614 * It is assumed that the start and end are properly
2615 * rounded to the page size.
2618 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2620 struct rwlock *lock;
2621 vm_offset_t va_next;
2622 pd_entry_t *l0, *l1, *l2;
2623 pt_entry_t l3_paddr;
2624 struct spglist free;
2627 * Perform an unsynchronized read. This is, however, safe.
2629 if (pmap->pm_stats.resident_count == 0)
2637 for (; sva < eva; sva = va_next) {
2639 if (pmap->pm_stats.resident_count == 0)
2642 l0 = pmap_l0(pmap, sva);
2643 if (pmap_load(l0) == 0) {
2644 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2650 l1 = pmap_l0_to_l1(l0, sva);
2651 if (pmap_load(l1) == 0) {
2652 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2659 * Calculate index for next page table.
2661 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2665 l2 = pmap_l1_to_l2(l1, sva);
2669 l3_paddr = pmap_load(l2);
2671 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2672 if (sva + L2_SIZE == va_next && eva >= va_next) {
2673 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2676 } else if (pmap_demote_l2_locked(pmap, l2, sva,
2679 l3_paddr = pmap_load(l2);
2683 * Weed out invalid mappings.
2685 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2689 * Limit our scan to either the end of the va represented
2690 * by the current page table page, or to the end of the
2691 * range being removed.
2696 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
2702 vm_page_free_pages_toq(&free, true);
2706 * Routine: pmap_remove_all
2708 * Removes this physical page from
2709 * all physical maps in which it resides.
2710 * Reflects back modify bits to the pager.
2713 * Original versions of this routine were very
2714 * inefficient because they iteratively called
2715 * pmap_remove (slow...)
2719 pmap_remove_all(vm_page_t m)
2721 struct md_page *pvh;
2724 struct rwlock *lock;
2725 pd_entry_t *pde, tpde;
2726 pt_entry_t *pte, tpte;
2728 struct spglist free;
2729 int lvl, pvh_gen, md_gen;
2731 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2732 ("pmap_remove_all: page %p is not managed", m));
2734 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2735 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2736 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2739 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2741 if (!PMAP_TRYLOCK(pmap)) {
2742 pvh_gen = pvh->pv_gen;
2746 if (pvh_gen != pvh->pv_gen) {
2753 pte = pmap_pte(pmap, va, &lvl);
2754 KASSERT(pte != NULL,
2755 ("pmap_remove_all: no page table entry found"));
2757 ("pmap_remove_all: invalid pte level %d", lvl));
2759 pmap_demote_l2_locked(pmap, pte, va, &lock);
2762 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2764 if (!PMAP_TRYLOCK(pmap)) {
2765 pvh_gen = pvh->pv_gen;
2766 md_gen = m->md.pv_gen;
2770 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2776 pmap_resident_count_dec(pmap, 1);
2778 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2779 KASSERT(pde != NULL,
2780 ("pmap_remove_all: no page directory entry found"));
2782 ("pmap_remove_all: invalid pde level %d", lvl));
2783 tpde = pmap_load(pde);
2785 pte = pmap_l2_to_l3(pde, pv->pv_va);
2786 tpte = pmap_load_clear(pte);
2787 pmap_invalidate_page(pmap, pv->pv_va);
2788 if (tpte & ATTR_SW_WIRED)
2789 pmap->pm_stats.wired_count--;
2790 if ((tpte & ATTR_AF) != 0)
2791 vm_page_aflag_set(m, PGA_REFERENCED);
2794 * Update the vm_page_t clean and reference bits.
2796 if (pmap_pte_dirty(tpte))
2798 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2799 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2801 free_pv_entry(pmap, pv);
2804 vm_page_aflag_clear(m, PGA_WRITEABLE);
2806 vm_page_free_pages_toq(&free, true);
2810 * pmap_protect_l2: do the things to protect a 2MB page in a pmap
2813 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
2819 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2820 KASSERT((sva & L2_OFFSET) == 0,
2821 ("pmap_protect_l2: sva is not 2mpage aligned"));
2822 old_l2 = pmap_load(l2);
2823 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2824 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
2827 * Return if the L2 entry already has the desired access restrictions
2831 if ((old_l2 & mask) == nbits)
2835 * When a dirty read/write superpage mapping is write protected,
2836 * update the dirty field of each of the superpage's constituent 4KB
2839 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
2840 (nbits & ATTR_AP(ATTR_AP_RO)) != 0 && pmap_pte_dirty(old_l2)) {
2841 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2842 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
2846 if (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
2850 * Since a promotion must break the 4KB page mappings before making
2851 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2853 pmap_invalidate_page(pmap, sva);
2857 * Set the physical protection on the
2858 * specified range of this map as requested.
2861 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2863 vm_offset_t va, va_next;
2864 pd_entry_t *l0, *l1, *l2;
2865 pt_entry_t *l3p, l3, mask, nbits;
2867 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
2868 if (prot == VM_PROT_NONE) {
2869 pmap_remove(pmap, sva, eva);
2874 if ((prot & VM_PROT_WRITE) == 0) {
2875 mask |= ATTR_AP_RW_BIT | ATTR_SW_DBM;
2876 nbits |= ATTR_AP(ATTR_AP_RO);
2878 if ((prot & VM_PROT_EXECUTE) == 0) {
2886 for (; sva < eva; sva = va_next) {
2888 l0 = pmap_l0(pmap, sva);
2889 if (pmap_load(l0) == 0) {
2890 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2896 l1 = pmap_l0_to_l1(l0, sva);
2897 if (pmap_load(l1) == 0) {
2898 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2904 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2908 l2 = pmap_l1_to_l2(l1, sva);
2909 if (pmap_load(l2) == 0)
2912 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
2913 if (sva + L2_SIZE == va_next && eva >= va_next) {
2914 pmap_protect_l2(pmap, l2, sva, mask, nbits);
2916 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
2919 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
2920 ("pmap_protect: Invalid L2 entry after demotion"));
2926 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2928 l3 = pmap_load(l3p);
2931 * Go to the next L3 entry if the current one is
2932 * invalid or already has the desired access
2933 * restrictions in place. (The latter case occurs
2934 * frequently. For example, in a "buildworld"
2935 * workload, almost 1 out of 4 L3 entries already
2936 * have the desired restrictions.)
2938 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
2939 if (va != va_next) {
2940 pmap_invalidate_range(pmap, va, sva);
2947 * When a dirty read/write mapping is write protected,
2948 * update the page's dirty field.
2950 if ((l3 & ATTR_SW_MANAGED) != 0 &&
2951 (nbits & ATTR_AP(ATTR_AP_RO)) != 0 &&
2953 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK));
2955 if (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) | nbits))
2961 pmap_invalidate_range(pmap, va, sva);
2967 * Inserts the specified page table page into the specified pmap's collection
2968 * of idle page table pages. Each of a pmap's page table pages is responsible
2969 * for mapping a distinct range of virtual addresses. The pmap's collection is
2970 * ordered by this virtual address range.
2972 * If "promoted" is false, then the page table page "mpte" must be zero filled.
2975 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
2978 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2979 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
2980 return (vm_radix_insert(&pmap->pm_root, mpte));
2984 * Removes the page table page mapping the specified virtual address from the
2985 * specified pmap's collection of idle page table pages, and returns it.
2986 * Otherwise, returns NULL if there is no page table page corresponding to the
2987 * specified virtual address.
2989 static __inline vm_page_t
2990 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2993 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2994 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
2998 * Performs a break-before-make update of a pmap entry. This is needed when
2999 * either promoting or demoting pages to ensure the TLB doesn't get into an
3000 * inconsistent state.
3003 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
3004 vm_offset_t va, vm_size_t size)
3008 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3011 * Ensure we don't get switched out with the page table in an
3012 * inconsistent state. We also need to ensure no interrupts fire
3013 * as they may make use of an address we are about to invalidate.
3015 intr = intr_disable();
3019 * Clear the old mapping's valid bit, but leave the rest of the entry
3020 * unchanged, so that a lockless, concurrent pmap_kextract() can still
3021 * lookup the physical address.
3023 pmap_clear_bits(pte, ATTR_DESCR_VALID);
3024 pmap_invalidate_range_nopin(pmap, va, va + size);
3026 /* Create the new mapping */
3027 pmap_store(pte, newpte);
3034 #if VM_NRESERVLEVEL > 0
3036 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3037 * replace the many pv entries for the 4KB page mappings by a single pv entry
3038 * for the 2MB page mapping.
3041 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3042 struct rwlock **lockp)
3044 struct md_page *pvh;
3046 vm_offset_t va_last;
3049 KASSERT((pa & L2_OFFSET) == 0,
3050 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
3051 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3054 * Transfer the first page's pv entry for this mapping to the 2mpage's
3055 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3056 * a transfer avoids the possibility that get_pv_entry() calls
3057 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3058 * mappings that is being promoted.
3060 m = PHYS_TO_VM_PAGE(pa);
3061 va = va & ~L2_OFFSET;
3062 pv = pmap_pvh_remove(&m->md, pmap, va);
3063 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
3064 pvh = pa_to_pvh(pa);
3065 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3067 /* Free the remaining NPTEPG - 1 pv entries. */
3068 va_last = va + L2_SIZE - PAGE_SIZE;
3072 pmap_pvh_free(&m->md, pmap, va);
3073 } while (va < va_last);
3077 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3078 * single level 2 table entry to a single 2MB page mapping. For promotion
3079 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3080 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3081 * identical characteristics.
3084 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
3085 struct rwlock **lockp)
3087 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
3091 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3093 sva = va & ~L2_OFFSET;
3094 firstl3 = pmap_l2_to_l3(l2, sva);
3095 newl2 = pmap_load(firstl3);
3098 if (((newl2 & (~ATTR_MASK | ATTR_AF)) & L2_OFFSET) != ATTR_AF) {
3099 atomic_add_long(&pmap_l2_p_failures, 1);
3100 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3101 " in pmap %p", va, pmap);
3105 if ((newl2 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
3106 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM)) {
3107 if (!atomic_fcmpset_64(l2, &newl2, newl2 & ~ATTR_SW_DBM))
3109 newl2 &= ~ATTR_SW_DBM;
3112 pa = newl2 + L2_SIZE - PAGE_SIZE;
3113 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
3114 oldl3 = pmap_load(l3);
3116 if ((oldl3 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
3117 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM)) {
3118 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
3121 oldl3 &= ~ATTR_SW_DBM;
3124 atomic_add_long(&pmap_l2_p_failures, 1);
3125 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3126 " in pmap %p", va, pmap);
3133 * Save the page table page in its current state until the L2
3134 * mapping the superpage is demoted by pmap_demote_l2() or
3135 * destroyed by pmap_remove_l3().
3137 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3138 KASSERT(mpte >= vm_page_array &&
3139 mpte < &vm_page_array[vm_page_array_size],
3140 ("pmap_promote_l2: page table page is out of range"));
3141 KASSERT(mpte->pindex == pmap_l2_pindex(va),
3142 ("pmap_promote_l2: page table page's pindex is wrong"));
3143 if (pmap_insert_pt_page(pmap, mpte, true)) {
3144 atomic_add_long(&pmap_l2_p_failures, 1);
3146 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
3151 if ((newl2 & ATTR_SW_MANAGED) != 0)
3152 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
3154 newl2 &= ~ATTR_DESCR_MASK;
3157 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
3159 atomic_add_long(&pmap_l2_promotions, 1);
3160 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
3163 #endif /* VM_NRESERVLEVEL > 0 */
3166 * Insert the given physical page (p) at
3167 * the specified virtual address (v) in the
3168 * target physical map with the protection requested.
3170 * If specified, the page will be wired down, meaning
3171 * that the related pte can not be reclaimed.
3173 * NB: This is the only routine which MAY NOT lazy-evaluate
3174 * or lose information. That is, this routine must actually
3175 * insert this page into the given map NOW.
3178 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3179 u_int flags, int8_t psind)
3181 struct rwlock *lock;
3183 pt_entry_t new_l3, orig_l3;
3184 pt_entry_t *l2, *l3;
3191 va = trunc_page(va);
3192 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3193 VM_OBJECT_ASSERT_LOCKED(m->object);
3194 pa = VM_PAGE_TO_PHYS(m);
3195 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3197 if ((prot & VM_PROT_WRITE) == 0)
3198 new_l3 |= ATTR_AP(ATTR_AP_RO);
3199 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3201 if ((flags & PMAP_ENTER_WIRED) != 0)
3202 new_l3 |= ATTR_SW_WIRED;
3203 if (va < VM_MAXUSER_ADDRESS)
3204 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3205 if ((m->oflags & VPO_UNMANAGED) == 0) {
3206 new_l3 |= ATTR_SW_MANAGED;
3207 if ((prot & VM_PROT_WRITE) != 0) {
3208 new_l3 |= ATTR_SW_DBM;
3209 if ((flags & VM_PROT_WRITE) == 0)
3210 new_l3 |= ATTR_AP(ATTR_AP_RO);
3214 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3219 /* Assert the required virtual and physical alignment. */
3220 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3221 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3222 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3229 * In the case that a page table page is not
3230 * resident, we are creating it here.
3233 pde = pmap_pde(pmap, va, &lvl);
3234 if (pde != NULL && lvl == 2) {
3235 l3 = pmap_l2_to_l3(pde, va);
3236 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3237 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3241 } else if (pde != NULL && lvl == 1) {
3242 l2 = pmap_l1_to_l2(pde, va);
3243 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3244 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
3245 l3 = &l3[pmap_l3_index(va)];
3246 if (va < VM_MAXUSER_ADDRESS) {
3247 mpte = PHYS_TO_VM_PAGE(
3248 pmap_load(l2) & ~ATTR_MASK);
3253 /* We need to allocate an L3 table. */
3255 if (va < VM_MAXUSER_ADDRESS) {
3256 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
3259 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
3260 * to handle the possibility that a superpage mapping for "va"
3261 * was created while we slept.
3263 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
3264 nosleep ? NULL : &lock);
3265 if (mpte == NULL && nosleep) {
3266 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3267 rv = KERN_RESOURCE_SHORTAGE;
3272 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
3275 orig_l3 = pmap_load(l3);
3276 opa = orig_l3 & ~ATTR_MASK;
3280 * Is the specified virtual address already mapped?
3282 if (pmap_l3_valid(orig_l3)) {
3284 * Wiring change, just update stats. We don't worry about
3285 * wiring PT pages as they remain resident as long as there
3286 * are valid mappings in them. Hence, if a user page is wired,
3287 * the PT page will be also.
3289 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3290 (orig_l3 & ATTR_SW_WIRED) == 0)
3291 pmap->pm_stats.wired_count++;
3292 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3293 (orig_l3 & ATTR_SW_WIRED) != 0)
3294 pmap->pm_stats.wired_count--;
3297 * Remove the extra PT page reference.
3301 KASSERT(mpte->wire_count > 0,
3302 ("pmap_enter: missing reference to page table page,"
3307 * Has the physical page changed?
3311 * No, might be a protection or wiring change.
3313 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3314 (new_l3 & ATTR_SW_DBM) != 0)
3315 vm_page_aflag_set(m, PGA_WRITEABLE);
3320 * The physical page has changed. Temporarily invalidate
3323 orig_l3 = pmap_load_clear(l3);
3324 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
3325 ("pmap_enter: unexpected pa update for %#lx", va));
3326 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3327 om = PHYS_TO_VM_PAGE(opa);
3330 * The pmap lock is sufficient to synchronize with
3331 * concurrent calls to pmap_page_test_mappings() and
3332 * pmap_ts_referenced().
3334 if (pmap_pte_dirty(orig_l3))
3336 if ((orig_l3 & ATTR_AF) != 0)
3337 vm_page_aflag_set(om, PGA_REFERENCED);
3338 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3339 pv = pmap_pvh_remove(&om->md, pmap, va);
3340 if ((m->oflags & VPO_UNMANAGED) != 0)
3341 free_pv_entry(pmap, pv);
3342 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3343 TAILQ_EMPTY(&om->md.pv_list) &&
3344 ((om->flags & PG_FICTITIOUS) != 0 ||
3345 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3346 vm_page_aflag_clear(om, PGA_WRITEABLE);
3348 pmap_invalidate_page(pmap, va);
3352 * Increment the counters.
3354 if ((new_l3 & ATTR_SW_WIRED) != 0)
3355 pmap->pm_stats.wired_count++;
3356 pmap_resident_count_inc(pmap, 1);
3359 * Enter on the PV list if part of our managed memory.
3361 if ((m->oflags & VPO_UNMANAGED) == 0) {
3363 pv = get_pv_entry(pmap, &lock);
3366 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3367 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3369 if ((new_l3 & ATTR_SW_DBM) != 0)
3370 vm_page_aflag_set(m, PGA_WRITEABLE);
3375 * Sync icache if exec permission and attribute VM_MEMATTR_WRITE_BACK
3376 * is set. Do it now, before the mapping is stored and made
3377 * valid for hardware table walk. If done later, then other can
3378 * access this page before caches are properly synced.
3379 * Don't do it for kernel memory which is mapped with exec
3380 * permission even if the memory isn't going to hold executable
3381 * code. The only time when icache sync is needed is after
3382 * kernel module is loaded and the relocation info is processed.
3383 * And it's done in elf_cpu_load_file().
3385 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3386 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3387 (opa != pa || (orig_l3 & ATTR_XN)))
3388 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3391 * Update the L3 entry
3393 if (pmap_l3_valid(orig_l3)) {
3394 KASSERT(opa == pa, ("pmap_enter: invalid update"));
3395 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3396 /* same PA, different attributes */
3397 /* XXXMJ need to reload orig_l3 for hardware DBM. */
3398 pmap_load_store(l3, new_l3);
3399 pmap_invalidate_page(pmap, va);
3400 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3401 pmap_pte_dirty(orig_l3))
3406 * This can happens if multiple threads simultaneously
3407 * access not yet mapped page. This bad for performance
3408 * since this can cause full demotion-NOP-promotion
3410 * Another possible reasons are:
3411 * - VM and pmap memory layout are diverged
3412 * - tlb flush is missing somewhere and CPU doesn't see
3415 CTR4(KTR_PMAP, "%s: already mapped page - "
3416 "pmap %p va 0x%#lx pte 0x%lx",
3417 __func__, pmap, va, new_l3);
3421 pmap_store(l3, new_l3);
3425 #if VM_NRESERVLEVEL > 0
3426 if ((mpte == NULL || mpte->wire_count == NL3PG) &&
3427 pmap_ps_enabled(pmap) &&
3428 (m->flags & PG_FICTITIOUS) == 0 &&
3429 vm_reserv_level_iffullpop(m) == 0) {
3430 pmap_promote_l2(pmap, pde, va, &lock);
3443 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
3444 * if successful. Returns false if (1) a page table page cannot be allocated
3445 * without sleeping, (2) a mapping already exists at the specified virtual
3446 * address, or (3) a PV entry cannot be allocated without reclaiming another
3450 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3451 struct rwlock **lockp)
3455 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3457 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
3458 ATTR_IDX(m->md.pv_memattr) | ATTR_AP(ATTR_AP_RO) | L2_BLOCK);
3459 if ((m->oflags & VPO_UNMANAGED) == 0) {
3460 new_l2 |= ATTR_SW_MANAGED;
3463 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3465 if (va < VM_MAXUSER_ADDRESS)
3466 new_l2 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3467 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
3468 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
3473 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
3474 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
3475 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
3476 * a mapping already exists at the specified virtual address. Returns
3477 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
3478 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
3479 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3481 * The parameter "m" is only used when creating a managed, writeable mapping.
3484 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
3485 vm_page_t m, struct rwlock **lockp)
3487 struct spglist free;
3488 pd_entry_t *l2, old_l2;
3491 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3493 if ((l2pg = pmap_alloc_l2(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
3494 NULL : lockp)) == NULL) {
3495 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
3497 return (KERN_RESOURCE_SHORTAGE);
3500 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
3501 l2 = &l2[pmap_l2_index(va)];
3502 if ((old_l2 = pmap_load(l2)) != 0) {
3503 KASSERT(l2pg->wire_count > 1,
3504 ("pmap_enter_l2: l2pg's wire count is too low"));
3505 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3508 "pmap_enter_l2: failure for va %#lx in pmap %p",
3510 return (KERN_FAILURE);
3513 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
3514 (void)pmap_remove_l2(pmap, l2, va,
3515 pmap_load(pmap_l1(pmap, va)), &free, lockp);
3517 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
3519 vm_page_free_pages_toq(&free, true);
3520 if (va >= VM_MAXUSER_ADDRESS) {
3522 * Both pmap_remove_l2() and pmap_remove_l3_range()
3523 * will leave the kernel page table page zero filled.
3524 * Nonetheless, the TLB could have an intermediate
3525 * entry for the kernel page table page.
3527 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3528 if (pmap_insert_pt_page(pmap, mt, false))
3529 panic("pmap_enter_l2: trie insert failed");
3531 pmap_invalidate_page(pmap, va);
3533 KASSERT(pmap_load(l2) == 0,
3534 ("pmap_enter_l2: non-zero L2 entry %p", l2));
3537 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
3539 * Abort this mapping if its PV entry could not be created.
3541 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
3543 if (pmap_unwire_l3(pmap, va, l2pg, &free)) {
3545 * Although "va" is not mapped, the TLB could
3546 * nonetheless have intermediate entries that
3547 * refer to the freed page table pages.
3548 * Invalidate those entries.
3550 * XXX redundant invalidation (See
3551 * _pmap_unwire_l3().)
3553 pmap_invalidate_page(pmap, va);
3554 vm_page_free_pages_toq(&free, true);
3557 "pmap_enter_l2: failure for va %#lx in pmap %p",
3559 return (KERN_RESOURCE_SHORTAGE);
3561 if ((new_l2 & ATTR_SW_DBM) != 0)
3562 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3563 vm_page_aflag_set(mt, PGA_WRITEABLE);
3567 * Increment counters.
3569 if ((new_l2 & ATTR_SW_WIRED) != 0)
3570 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
3571 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
3574 * Map the superpage.
3576 pmap_store(l2, new_l2);
3579 atomic_add_long(&pmap_l2_mappings, 1);
3580 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
3583 return (KERN_SUCCESS);
3587 * Maps a sequence of resident pages belonging to the same object.
3588 * The sequence begins with the given page m_start. This page is
3589 * mapped at the given virtual address start. Each subsequent page is
3590 * mapped at a virtual address that is offset from start by the same
3591 * amount as the page is offset from m_start within the object. The
3592 * last page in the sequence is the page with the largest offset from
3593 * m_start that can be mapped at a virtual address less than the given
3594 * virtual address end. Not every virtual page between start and end
3595 * is mapped; only those for which a resident page exists with the
3596 * corresponding offset from m_start are mapped.
3599 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3600 vm_page_t m_start, vm_prot_t prot)
3602 struct rwlock *lock;
3605 vm_pindex_t diff, psize;
3607 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3609 psize = atop(end - start);
3614 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3615 va = start + ptoa(diff);
3616 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
3617 m->psind == 1 && pmap_ps_enabled(pmap) &&
3618 pmap_enter_2mpage(pmap, va, m, prot, &lock))
3619 m = &m[L2_SIZE / PAGE_SIZE - 1];
3621 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
3623 m = TAILQ_NEXT(m, listq);
3631 * this code makes some *MAJOR* assumptions:
3632 * 1. Current pmap & pmap exists.
3635 * 4. No page table pages.
3636 * but is *MUCH* faster than pmap_enter...
3640 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3642 struct rwlock *lock;
3646 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3653 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3654 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3656 struct spglist free;
3658 pt_entry_t *l2, *l3, l3_val;
3662 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3663 (m->oflags & VPO_UNMANAGED) != 0,
3664 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3665 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3667 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3669 * In the case that a page table page is not
3670 * resident, we are creating it here.
3672 if (va < VM_MAXUSER_ADDRESS) {
3673 vm_pindex_t l2pindex;
3676 * Calculate pagetable page index
3678 l2pindex = pmap_l2_pindex(va);
3679 if (mpte && (mpte->pindex == l2pindex)) {
3685 pde = pmap_pde(pmap, va, &lvl);
3688 * If the page table page is mapped, we just increment
3689 * the hold count, and activate it. Otherwise, we
3690 * attempt to allocate a page table page. If this
3691 * attempt fails, we don't retry. Instead, we give up.
3694 l2 = pmap_l1_to_l2(pde, va);
3695 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3699 if (lvl == 2 && pmap_load(pde) != 0) {
3701 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3705 * Pass NULL instead of the PV list lock
3706 * pointer, because we don't intend to sleep.
3708 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3713 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3714 l3 = &l3[pmap_l3_index(va)];
3717 pde = pmap_pde(kernel_pmap, va, &lvl);
3718 KASSERT(pde != NULL,
3719 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3722 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3723 l3 = pmap_l2_to_l3(pde, va);
3727 * Abort if a mapping already exists.
3729 if (pmap_load(l3) != 0) {
3738 * Enter on the PV list if part of our managed memory.
3740 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3741 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3744 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
3745 pmap_invalidate_page(pmap, va);
3746 vm_page_free_pages_toq(&free, true);
3754 * Increment counters
3756 pmap_resident_count_inc(pmap, 1);
3758 pa = VM_PAGE_TO_PHYS(m);
3759 l3_val = pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3760 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3761 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3763 else if (va < VM_MAXUSER_ADDRESS)
3767 * Now validate mapping with RO protection
3769 if ((m->oflags & VPO_UNMANAGED) == 0) {
3770 l3_val |= ATTR_SW_MANAGED;
3774 /* Sync icache before the mapping is stored to PTE */
3775 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3776 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
3777 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3779 pmap_store(l3, l3_val);
3786 * This code maps large physical mmap regions into the
3787 * processor address space. Note that some shortcuts
3788 * are taken, but the code works.
3791 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3792 vm_pindex_t pindex, vm_size_t size)
3795 VM_OBJECT_ASSERT_WLOCKED(object);
3796 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3797 ("pmap_object_init_pt: non-device object"));
3801 * Clear the wired attribute from the mappings for the specified range of
3802 * addresses in the given pmap. Every valid mapping within that range
3803 * must have the wired attribute set. In contrast, invalid mappings
3804 * cannot have the wired attribute set, so they are ignored.
3806 * The wired attribute of the page table entry is not a hardware feature,
3807 * so there is no need to invalidate any TLB entries.
3810 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3812 vm_offset_t va_next;
3813 pd_entry_t *l0, *l1, *l2;
3817 for (; sva < eva; sva = va_next) {
3818 l0 = pmap_l0(pmap, sva);
3819 if (pmap_load(l0) == 0) {
3820 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3826 l1 = pmap_l0_to_l1(l0, sva);
3827 if (pmap_load(l1) == 0) {
3828 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3834 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3838 l2 = pmap_l1_to_l2(l1, sva);
3839 if (pmap_load(l2) == 0)
3842 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3843 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
3844 panic("pmap_unwire: l2 %#jx is missing "
3845 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
3848 * Are we unwiring the entire large page? If not,
3849 * demote the mapping and fall through.
3851 if (sva + L2_SIZE == va_next && eva >= va_next) {
3852 pmap_clear_bits(l2, ATTR_SW_WIRED);
3853 pmap->pm_stats.wired_count -= L2_SIZE /
3856 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3857 panic("pmap_unwire: demotion failed");
3859 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3860 ("pmap_unwire: Invalid l2 entry after demotion"));
3864 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3866 if (pmap_load(l3) == 0)
3868 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
3869 panic("pmap_unwire: l3 %#jx is missing "
3870 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
3873 * ATTR_SW_WIRED must be cleared atomically. Although
3874 * the pmap lock synchronizes access to ATTR_SW_WIRED,
3875 * the System MMU may write to the entry concurrently.
3877 pmap_clear_bits(l3, ATTR_SW_WIRED);
3878 pmap->pm_stats.wired_count--;
3885 * Copy the range specified by src_addr/len
3886 * from the source map to the range dst_addr/len
3887 * in the destination map.
3889 * This routine is only advisory and need not do anything.
3891 * Because the executable mappings created by this routine are copied,
3892 * it should not have to flush the instruction cache.
3895 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3896 vm_offset_t src_addr)
3898 struct rwlock *lock;
3899 struct spglist free;
3900 pd_entry_t *l0, *l1, *l2, srcptepaddr;
3901 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
3902 vm_offset_t addr, end_addr, va_next;
3903 vm_page_t dst_l2pg, dstmpte, srcmpte;
3905 if (dst_addr != src_addr)
3907 end_addr = src_addr + len;
3909 if (dst_pmap < src_pmap) {
3910 PMAP_LOCK(dst_pmap);
3911 PMAP_LOCK(src_pmap);
3913 PMAP_LOCK(src_pmap);
3914 PMAP_LOCK(dst_pmap);
3916 for (addr = src_addr; addr < end_addr; addr = va_next) {
3917 l0 = pmap_l0(src_pmap, addr);
3918 if (pmap_load(l0) == 0) {
3919 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
3924 l1 = pmap_l0_to_l1(l0, addr);
3925 if (pmap_load(l1) == 0) {
3926 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
3931 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
3934 l2 = pmap_l1_to_l2(l1, addr);
3935 srcptepaddr = pmap_load(l2);
3936 if (srcptepaddr == 0)
3938 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
3939 if ((addr & L2_OFFSET) != 0 ||
3940 addr + L2_SIZE > end_addr)
3942 dst_l2pg = pmap_alloc_l2(dst_pmap, addr, NULL);
3943 if (dst_l2pg == NULL)
3946 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_l2pg));
3947 l2 = &l2[pmap_l2_index(addr)];
3948 if (pmap_load(l2) == 0 &&
3949 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
3950 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
3951 PMAP_ENTER_NORECLAIM, &lock))) {
3952 mask = ATTR_AF | ATTR_SW_WIRED;
3954 if ((srcptepaddr & ATTR_SW_DBM) != 0)
3955 nbits |= ATTR_AP_RW_BIT;
3956 pmap_store(l2, (srcptepaddr & ~mask) | nbits);
3957 pmap_resident_count_inc(dst_pmap, L2_SIZE /
3959 atomic_add_long(&pmap_l2_mappings, 1);
3961 dst_l2pg->wire_count--;
3964 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
3965 ("pmap_copy: invalid L2 entry"));
3966 srcptepaddr &= ~ATTR_MASK;
3967 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
3968 KASSERT(srcmpte->wire_count > 0,
3969 ("pmap_copy: source page table page is unused"));
3970 if (va_next > end_addr)
3972 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
3973 src_pte = &src_pte[pmap_l3_index(addr)];
3975 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
3976 ptetemp = pmap_load(src_pte);
3979 * We only virtual copy managed pages.
3981 if ((ptetemp & ATTR_SW_MANAGED) == 0)
3984 if (dstmpte != NULL) {
3985 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
3986 ("dstmpte pindex/addr mismatch"));
3987 dstmpte->wire_count++;
3988 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
3991 dst_pte = (pt_entry_t *)
3992 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
3993 dst_pte = &dst_pte[pmap_l3_index(addr)];
3994 if (pmap_load(dst_pte) == 0 &&
3995 pmap_try_insert_pv_entry(dst_pmap, addr,
3996 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
3998 * Clear the wired, modified, and accessed
3999 * (referenced) bits during the copy.
4001 mask = ATTR_AF | ATTR_SW_WIRED;
4003 if ((ptetemp & ATTR_SW_DBM) != 0)
4004 nbits |= ATTR_AP_RW_BIT;
4005 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
4006 pmap_resident_count_inc(dst_pmap, 1);
4009 if (pmap_unwire_l3(dst_pmap, addr, dstmpte,
4012 * Although "addr" is not mapped,
4013 * the TLB could nonetheless have
4014 * intermediate entries that refer
4015 * to the freed page table pages.
4016 * Invalidate those entries.
4018 * XXX redundant invalidation
4020 pmap_invalidate_page(dst_pmap, addr);
4021 vm_page_free_pages_toq(&free, true);
4025 /* Have we copied all of the valid mappings? */
4026 if (dstmpte->wire_count >= srcmpte->wire_count)
4032 * XXX This barrier may not be needed because the destination pmap is
4039 PMAP_UNLOCK(src_pmap);
4040 PMAP_UNLOCK(dst_pmap);
4044 * pmap_zero_page zeros the specified hardware page by mapping
4045 * the page into KVM and using bzero to clear its contents.
4048 pmap_zero_page(vm_page_t m)
4050 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4052 pagezero((void *)va);
4056 * pmap_zero_page_area zeros the specified hardware page by mapping
4057 * the page into KVM and using bzero to clear its contents.
4059 * off and size may not cover an area beyond a single hardware page.
4062 pmap_zero_page_area(vm_page_t m, int off, int size)
4064 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4066 if (off == 0 && size == PAGE_SIZE)
4067 pagezero((void *)va);
4069 bzero((char *)va + off, size);
4073 * pmap_copy_page copies the specified (machine independent)
4074 * page by mapping the page into virtual memory and using
4075 * bcopy to copy the page, one machine dependent page at a
4079 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4081 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4082 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4084 pagecopy((void *)src, (void *)dst);
4087 int unmapped_buf_allowed = 1;
4090 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4091 vm_offset_t b_offset, int xfersize)
4095 vm_paddr_t p_a, p_b;
4096 vm_offset_t a_pg_offset, b_pg_offset;
4099 while (xfersize > 0) {
4100 a_pg_offset = a_offset & PAGE_MASK;
4101 m_a = ma[a_offset >> PAGE_SHIFT];
4102 p_a = m_a->phys_addr;
4103 b_pg_offset = b_offset & PAGE_MASK;
4104 m_b = mb[b_offset >> PAGE_SHIFT];
4105 p_b = m_b->phys_addr;
4106 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4107 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4108 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
4109 panic("!DMAP a %lx", p_a);
4111 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
4113 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
4114 panic("!DMAP b %lx", p_b);
4116 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
4118 bcopy(a_cp, b_cp, cnt);
4126 pmap_quick_enter_page(vm_page_t m)
4129 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
4133 pmap_quick_remove_page(vm_offset_t addr)
4138 * Returns true if the pmap's pv is one of the first
4139 * 16 pvs linked to from this page. This count may
4140 * be changed upwards or downwards in the future; it
4141 * is only necessary that true be returned for a small
4142 * subset of pmaps for proper page aging.
4145 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4147 struct md_page *pvh;
4148 struct rwlock *lock;
4153 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4154 ("pmap_page_exists_quick: page %p is not managed", m));
4156 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4158 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4159 if (PV_PMAP(pv) == pmap) {
4167 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4168 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4169 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4170 if (PV_PMAP(pv) == pmap) {
4184 * pmap_page_wired_mappings:
4186 * Return the number of managed mappings to the given physical page
4190 pmap_page_wired_mappings(vm_page_t m)
4192 struct rwlock *lock;
4193 struct md_page *pvh;
4197 int count, lvl, md_gen, pvh_gen;
4199 if ((m->oflags & VPO_UNMANAGED) != 0)
4201 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4205 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4207 if (!PMAP_TRYLOCK(pmap)) {
4208 md_gen = m->md.pv_gen;
4212 if (md_gen != m->md.pv_gen) {
4217 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4218 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4222 if ((m->flags & PG_FICTITIOUS) == 0) {
4223 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4224 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4226 if (!PMAP_TRYLOCK(pmap)) {
4227 md_gen = m->md.pv_gen;
4228 pvh_gen = pvh->pv_gen;
4232 if (md_gen != m->md.pv_gen ||
4233 pvh_gen != pvh->pv_gen) {
4238 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4240 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4250 * Destroy all managed, non-wired mappings in the given user-space
4251 * pmap. This pmap cannot be active on any processor besides the
4254 * This function cannot be applied to the kernel pmap. Moreover, it
4255 * is not intended for general use. It is only to be used during
4256 * process termination. Consequently, it can be implemented in ways
4257 * that make it faster than pmap_remove(). First, it can more quickly
4258 * destroy mappings by iterating over the pmap's collection of PV
4259 * entries, rather than searching the page table. Second, it doesn't
4260 * have to test and clear the page table entries atomically, because
4261 * no processor is currently accessing the user address space. In
4262 * particular, a page table entry's dirty bit won't change state once
4263 * this function starts.
4266 pmap_remove_pages(pmap_t pmap)
4269 pt_entry_t *pte, tpte;
4270 struct spglist free;
4271 vm_page_t m, ml3, mt;
4273 struct md_page *pvh;
4274 struct pv_chunk *pc, *npc;
4275 struct rwlock *lock;
4277 uint64_t inuse, bitmask;
4278 int allfree, field, freed, idx, lvl;
4285 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4288 for (field = 0; field < _NPCM; field++) {
4289 inuse = ~pc->pc_map[field] & pc_freemask[field];
4290 while (inuse != 0) {
4291 bit = ffsl(inuse) - 1;
4292 bitmask = 1UL << bit;
4293 idx = field * 64 + bit;
4294 pv = &pc->pc_pventry[idx];
4297 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4298 KASSERT(pde != NULL,
4299 ("Attempting to remove an unmapped page"));
4303 pte = pmap_l1_to_l2(pde, pv->pv_va);
4304 tpte = pmap_load(pte);
4305 KASSERT((tpte & ATTR_DESCR_MASK) ==
4307 ("Attempting to remove an invalid "
4308 "block: %lx", tpte));
4309 tpte = pmap_load(pte);
4312 pte = pmap_l2_to_l3(pde, pv->pv_va);
4313 tpte = pmap_load(pte);
4314 KASSERT((tpte & ATTR_DESCR_MASK) ==
4316 ("Attempting to remove an invalid "
4317 "page: %lx", tpte));
4321 "Invalid page directory level: %d",
4326 * We cannot remove wired pages from a process' mapping at this time
4328 if (tpte & ATTR_SW_WIRED) {
4333 pa = tpte & ~ATTR_MASK;
4335 m = PHYS_TO_VM_PAGE(pa);
4336 KASSERT(m->phys_addr == pa,
4337 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4338 m, (uintmax_t)m->phys_addr,
4341 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4342 m < &vm_page_array[vm_page_array_size],
4343 ("pmap_remove_pages: bad pte %#jx",
4347 * Because this pmap is not active on other
4348 * processors, the dirty bit cannot have
4349 * changed state since we last loaded pte.
4354 * Update the vm_page_t clean/reference bits.
4356 if (pmap_pte_dirty(tpte)) {
4359 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4368 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4371 pc->pc_map[field] |= bitmask;
4374 pmap_resident_count_dec(pmap,
4375 L2_SIZE / PAGE_SIZE);
4376 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
4377 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
4379 if (TAILQ_EMPTY(&pvh->pv_list)) {
4380 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4381 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
4382 TAILQ_EMPTY(&mt->md.pv_list))
4383 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4385 ml3 = pmap_remove_pt_page(pmap,
4388 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
4389 ("pmap_remove_pages: l3 page not promoted"));
4390 pmap_resident_count_dec(pmap,1);
4391 KASSERT(ml3->wire_count == NL3PG,
4392 ("pmap_remove_pages: l3 page wire count error"));
4393 ml3->wire_count = 0;
4394 pmap_add_delayed_free_list(ml3,
4399 pmap_resident_count_dec(pmap, 1);
4400 TAILQ_REMOVE(&m->md.pv_list, pv,
4403 if ((m->aflags & PGA_WRITEABLE) != 0 &&
4404 TAILQ_EMPTY(&m->md.pv_list) &&
4405 (m->flags & PG_FICTITIOUS) == 0) {
4407 VM_PAGE_TO_PHYS(m));
4408 if (TAILQ_EMPTY(&pvh->pv_list))
4409 vm_page_aflag_clear(m,
4414 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
4419 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4420 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4421 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4423 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4427 pmap_invalidate_all(pmap);
4431 vm_page_free_pages_toq(&free, true);
4435 * This is used to check if a page has been accessed or modified. As we
4436 * don't have a bit to see if it has been modified we have to assume it
4437 * has been if the page is read/write.
4440 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
4442 struct rwlock *lock;
4444 struct md_page *pvh;
4445 pt_entry_t *pte, mask, value;
4447 int lvl, md_gen, pvh_gen;
4451 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4454 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4456 if (!PMAP_TRYLOCK(pmap)) {
4457 md_gen = m->md.pv_gen;
4461 if (md_gen != m->md.pv_gen) {
4466 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4468 ("pmap_page_test_mappings: Invalid level %d", lvl));
4472 mask |= ATTR_AP_RW_BIT;
4473 value |= ATTR_AP(ATTR_AP_RW);
4476 mask |= ATTR_AF | ATTR_DESCR_MASK;
4477 value |= ATTR_AF | L3_PAGE;
4479 rv = (pmap_load(pte) & mask) == value;
4484 if ((m->flags & PG_FICTITIOUS) == 0) {
4485 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4486 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4488 if (!PMAP_TRYLOCK(pmap)) {
4489 md_gen = m->md.pv_gen;
4490 pvh_gen = pvh->pv_gen;
4494 if (md_gen != m->md.pv_gen ||
4495 pvh_gen != pvh->pv_gen) {
4500 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4502 ("pmap_page_test_mappings: Invalid level %d", lvl));
4506 mask |= ATTR_AP_RW_BIT;
4507 value |= ATTR_AP(ATTR_AP_RW);
4510 mask |= ATTR_AF | ATTR_DESCR_MASK;
4511 value |= ATTR_AF | L2_BLOCK;
4513 rv = (pmap_load(pte) & mask) == value;
4527 * Return whether or not the specified physical page was modified
4528 * in any physical maps.
4531 pmap_is_modified(vm_page_t m)
4534 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4535 ("pmap_is_modified: page %p is not managed", m));
4538 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4539 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4540 * is clear, no PTEs can have PG_M set.
4542 VM_OBJECT_ASSERT_WLOCKED(m->object);
4543 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4545 return (pmap_page_test_mappings(m, FALSE, TRUE));
4549 * pmap_is_prefaultable:
4551 * Return whether or not the specified virtual address is eligible
4555 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4563 pte = pmap_pte(pmap, addr, &lvl);
4564 if (pte != NULL && pmap_load(pte) != 0) {
4572 * pmap_is_referenced:
4574 * Return whether or not the specified physical page was referenced
4575 * in any physical maps.
4578 pmap_is_referenced(vm_page_t m)
4581 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4582 ("pmap_is_referenced: page %p is not managed", m));
4583 return (pmap_page_test_mappings(m, TRUE, FALSE));
4587 * Clear the write and modified bits in each of the given page's mappings.
4590 pmap_remove_write(vm_page_t m)
4592 struct md_page *pvh;
4594 struct rwlock *lock;
4595 pv_entry_t next_pv, pv;
4596 pt_entry_t oldpte, *pte;
4598 int lvl, md_gen, pvh_gen;
4600 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4601 ("pmap_remove_write: page %p is not managed", m));
4604 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4605 * set by another thread while the object is locked. Thus,
4606 * if PGA_WRITEABLE is clear, no page table entries need updating.
4608 VM_OBJECT_ASSERT_WLOCKED(m->object);
4609 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4611 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4612 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4613 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4616 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4618 if (!PMAP_TRYLOCK(pmap)) {
4619 pvh_gen = pvh->pv_gen;
4623 if (pvh_gen != pvh->pv_gen) {
4630 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4631 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
4632 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
4633 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4634 ("inconsistent pv lock %p %p for page %p",
4635 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4638 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4640 if (!PMAP_TRYLOCK(pmap)) {
4641 pvh_gen = pvh->pv_gen;
4642 md_gen = m->md.pv_gen;
4646 if (pvh_gen != pvh->pv_gen ||
4647 md_gen != m->md.pv_gen) {
4653 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4654 oldpte = pmap_load(pte);
4656 if ((oldpte & ATTR_SW_DBM) != 0) {
4657 if (!atomic_fcmpset_long(pte, &oldpte,
4658 (oldpte | ATTR_AP_RW_BIT) & ~ATTR_SW_DBM))
4660 if ((oldpte & ATTR_AP_RW_BIT) ==
4661 ATTR_AP(ATTR_AP_RW))
4663 pmap_invalidate_page(pmap, pv->pv_va);
4668 vm_page_aflag_clear(m, PGA_WRITEABLE);
4672 * pmap_ts_referenced:
4674 * Return a count of reference bits for a page, clearing those bits.
4675 * It is not necessary for every reference bit to be cleared, but it
4676 * is necessary that 0 only be returned when there are truly no
4677 * reference bits set.
4679 * As an optimization, update the page's dirty field if a modified bit is
4680 * found while counting reference bits. This opportunistic update can be
4681 * performed at low cost and can eliminate the need for some future calls
4682 * to pmap_is_modified(). However, since this function stops after
4683 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4684 * dirty pages. Those dirty pages will only be detected by a future call
4685 * to pmap_is_modified().
4688 pmap_ts_referenced(vm_page_t m)
4690 struct md_page *pvh;
4693 struct rwlock *lock;
4694 pd_entry_t *pde, tpde;
4695 pt_entry_t *pte, tpte;
4698 int cleared, lvl, md_gen, not_cleared, pvh_gen;
4699 struct spglist free;
4701 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4702 ("pmap_ts_referenced: page %p is not managed", m));
4705 pa = VM_PAGE_TO_PHYS(m);
4706 lock = PHYS_TO_PV_LIST_LOCK(pa);
4707 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4711 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4712 goto small_mappings;
4718 if (!PMAP_TRYLOCK(pmap)) {
4719 pvh_gen = pvh->pv_gen;
4723 if (pvh_gen != pvh->pv_gen) {
4729 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4730 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4732 ("pmap_ts_referenced: invalid pde level %d", lvl));
4733 tpde = pmap_load(pde);
4734 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4735 ("pmap_ts_referenced: found an invalid l1 table"));
4736 pte = pmap_l1_to_l2(pde, pv->pv_va);
4737 tpte = pmap_load(pte);
4738 if (pmap_pte_dirty(tpte)) {
4740 * Although "tpte" is mapping a 2MB page, because
4741 * this function is called at a 4KB page granularity,
4742 * we only update the 4KB page under test.
4747 if ((tpte & ATTR_AF) != 0) {
4749 * Since this reference bit is shared by 512 4KB pages,
4750 * it should not be cleared every time it is tested.
4751 * Apply a simple "hash" function on the physical page
4752 * number, the virtual superpage number, and the pmap
4753 * address to select one 4KB page out of the 512 on
4754 * which testing the reference bit will result in
4755 * clearing that reference bit. This function is
4756 * designed to avoid the selection of the same 4KB page
4757 * for every 2MB page mapping.
4759 * On demotion, a mapping that hasn't been referenced
4760 * is simply destroyed. To avoid the possibility of a
4761 * subsequent page fault on a demoted wired mapping,
4762 * always leave its reference bit set. Moreover,
4763 * since the superpage is wired, the current state of
4764 * its reference bit won't affect page replacement.
4766 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4767 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4768 (tpte & ATTR_SW_WIRED) == 0) {
4769 pmap_clear_bits(pte, ATTR_AF);
4770 pmap_invalidate_page(pmap, pv->pv_va);
4776 /* Rotate the PV list if it has more than one entry. */
4777 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4778 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4779 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4782 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4784 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4786 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4793 if (!PMAP_TRYLOCK(pmap)) {
4794 pvh_gen = pvh->pv_gen;
4795 md_gen = m->md.pv_gen;
4799 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4804 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4805 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4807 ("pmap_ts_referenced: invalid pde level %d", lvl));
4808 tpde = pmap_load(pde);
4809 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4810 ("pmap_ts_referenced: found an invalid l2 table"));
4811 pte = pmap_l2_to_l3(pde, pv->pv_va);
4812 tpte = pmap_load(pte);
4813 if (pmap_pte_dirty(tpte))
4815 if ((tpte & ATTR_AF) != 0) {
4816 if ((tpte & ATTR_SW_WIRED) == 0) {
4817 pmap_clear_bits(pte, ATTR_AF);
4818 pmap_invalidate_page(pmap, pv->pv_va);
4824 /* Rotate the PV list if it has more than one entry. */
4825 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4826 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4827 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4830 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4831 not_cleared < PMAP_TS_REFERENCED_MAX);
4834 vm_page_free_pages_toq(&free, true);
4835 return (cleared + not_cleared);
4839 * Apply the given advice to the specified range of addresses within the
4840 * given pmap. Depending on the advice, clear the referenced and/or
4841 * modified flags in each mapping and set the mapped page's dirty field.
4844 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4846 struct rwlock *lock;
4847 vm_offset_t va, va_next;
4849 pd_entry_t *l0, *l1, *l2, oldl2;
4850 pt_entry_t *l3, oldl3;
4852 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4856 for (; sva < eva; sva = va_next) {
4857 l0 = pmap_l0(pmap, sva);
4858 if (pmap_load(l0) == 0) {
4859 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
4864 l1 = pmap_l0_to_l1(l0, sva);
4865 if (pmap_load(l1) == 0) {
4866 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
4871 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
4874 l2 = pmap_l1_to_l2(l1, sva);
4875 oldl2 = pmap_load(l2);
4878 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
4879 if ((oldl2 & ATTR_SW_MANAGED) == 0)
4882 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
4887 * The 2MB page mapping was destroyed.
4893 * Unless the page mappings are wired, remove the
4894 * mapping to a single page so that a subsequent
4895 * access may repromote. Choosing the last page
4896 * within the address range [sva, min(va_next, eva))
4897 * generally results in more repromotions. Since the
4898 * underlying page table page is fully populated, this
4899 * removal never frees a page table page.
4901 if ((oldl2 & ATTR_SW_WIRED) == 0) {
4907 ("pmap_advise: no address gap"));
4908 l3 = pmap_l2_to_l3(l2, va);
4909 KASSERT(pmap_load(l3) != 0,
4910 ("pmap_advise: invalid PTE"));
4911 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
4917 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
4918 ("pmap_advise: invalid L2 entry after demotion"));
4922 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
4924 oldl3 = pmap_load(l3);
4925 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
4926 (ATTR_SW_MANAGED | L3_PAGE))
4928 else if (pmap_pte_dirty(oldl3)) {
4929 if (advice == MADV_DONTNEED) {
4931 * Future calls to pmap_is_modified()
4932 * can be avoided by making the page
4935 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK);
4938 while (!atomic_fcmpset_long(l3, &oldl3,
4939 (oldl3 & ~ATTR_AF) | ATTR_AP(ATTR_AP_RO)))
4941 } else if ((oldl3 & ATTR_AF) != 0)
4942 pmap_clear_bits(l3, ATTR_AF);
4949 if (va != va_next) {
4950 pmap_invalidate_range(pmap, va, sva);
4955 pmap_invalidate_range(pmap, va, sva);
4961 * Clear the modify bits on the specified physical page.
4964 pmap_clear_modify(vm_page_t m)
4966 struct md_page *pvh;
4967 struct rwlock *lock;
4969 pv_entry_t next_pv, pv;
4970 pd_entry_t *l2, oldl2;
4971 pt_entry_t *l3, oldl3;
4973 int md_gen, pvh_gen;
4975 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4976 ("pmap_clear_modify: page %p is not managed", m));
4977 VM_OBJECT_ASSERT_WLOCKED(m->object);
4978 KASSERT(!vm_page_xbusied(m),
4979 ("pmap_clear_modify: page %p is exclusive busied", m));
4982 * If the page is not PGA_WRITEABLE, then no PTEs can have ATTR_SW_DBM
4983 * set. If the object containing the page is locked and the page is not
4984 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4986 if ((m->aflags & PGA_WRITEABLE) == 0)
4988 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4989 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4990 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4993 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4995 if (!PMAP_TRYLOCK(pmap)) {
4996 pvh_gen = pvh->pv_gen;
5000 if (pvh_gen != pvh->pv_gen) {
5006 l2 = pmap_l2(pmap, va);
5007 oldl2 = pmap_load(l2);
5008 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */
5009 if ((oldl2 & ATTR_SW_DBM) != 0 &&
5010 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
5011 (oldl2 & ATTR_SW_WIRED) == 0) {
5013 * Write protect the mapping to a single page so that
5014 * a subsequent write access may repromote.
5016 va += VM_PAGE_TO_PHYS(m) - (oldl2 & ~ATTR_MASK);
5017 l3 = pmap_l2_to_l3(l2, va);
5018 oldl3 = pmap_load(l3);
5019 while (!atomic_fcmpset_long(l3, &oldl3,
5020 (oldl3 & ~ATTR_SW_DBM) | ATTR_AP(ATTR_AP_RO)))
5023 pmap_invalidate_page(pmap, va);
5027 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5029 if (!PMAP_TRYLOCK(pmap)) {
5030 md_gen = m->md.pv_gen;
5031 pvh_gen = pvh->pv_gen;
5035 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5040 l2 = pmap_l2(pmap, pv->pv_va);
5041 l3 = pmap_l2_to_l3(l2, pv->pv_va);
5042 oldl3 = pmap_load(l3);
5043 if (pmap_l3_valid(oldl3) &&
5044 (oldl3 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM) {
5045 pmap_set_bits(l3, ATTR_AP(ATTR_AP_RO));
5046 pmap_invalidate_page(pmap, pv->pv_va);
5054 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5056 struct pmap_preinit_mapping *ppim;
5057 vm_offset_t va, offset;
5060 int i, lvl, l2_blocks, free_l2_count, start_idx;
5062 if (!vm_initialized) {
5064 * No L3 ptables so map entire L2 blocks where start VA is:
5065 * preinit_map_va + start_idx * L2_SIZE
5066 * There may be duplicate mappings (multiple VA -> same PA) but
5067 * ARM64 dcache is always PIPT so that's acceptable.
5072 /* Calculate how many L2 blocks are needed for the mapping */
5073 l2_blocks = (roundup2(pa + size, L2_SIZE) -
5074 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
5076 offset = pa & L2_OFFSET;
5078 if (preinit_map_va == 0)
5081 /* Map 2MiB L2 blocks from reserved VA space */
5085 /* Find enough free contiguous VA space */
5086 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5087 ppim = pmap_preinit_mapping + i;
5088 if (free_l2_count > 0 && ppim->pa != 0) {
5089 /* Not enough space here */
5095 if (ppim->pa == 0) {
5097 if (start_idx == -1)
5100 if (free_l2_count == l2_blocks)
5104 if (free_l2_count != l2_blocks)
5105 panic("%s: too many preinit mappings", __func__);
5107 va = preinit_map_va + (start_idx * L2_SIZE);
5108 for (i = start_idx; i < start_idx + l2_blocks; i++) {
5109 /* Mark entries as allocated */
5110 ppim = pmap_preinit_mapping + i;
5112 ppim->va = va + offset;
5117 pa = rounddown2(pa, L2_SIZE);
5118 for (i = 0; i < l2_blocks; i++) {
5119 pde = pmap_pde(kernel_pmap, va, &lvl);
5120 KASSERT(pde != NULL,
5121 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
5124 ("pmap_mapbios: Invalid level %d", lvl));
5126 /* Insert L2_BLOCK */
5127 l2 = pmap_l1_to_l2(pde, va);
5129 pa | ATTR_DEFAULT | ATTR_XN |
5130 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
5135 pmap_invalidate_all(kernel_pmap);
5137 va = preinit_map_va + (start_idx * L2_SIZE);
5140 /* kva_alloc may be used to map the pages */
5141 offset = pa & PAGE_MASK;
5142 size = round_page(offset + size);
5144 va = kva_alloc(size);
5146 panic("%s: Couldn't allocate KVA", __func__);
5148 pde = pmap_pde(kernel_pmap, va, &lvl);
5149 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
5151 /* L3 table is linked */
5152 va = trunc_page(va);
5153 pa = trunc_page(pa);
5154 pmap_kenter(va, size, pa, CACHED_MEMORY);
5157 return ((void *)(va + offset));
5161 pmap_unmapbios(vm_offset_t va, vm_size_t size)
5163 struct pmap_preinit_mapping *ppim;
5164 vm_offset_t offset, tmpsize, va_trunc;
5167 int i, lvl, l2_blocks, block;
5171 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
5172 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
5174 /* Remove preinit mapping */
5175 preinit_map = false;
5177 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5178 ppim = pmap_preinit_mapping + i;
5179 if (ppim->va == va) {
5180 KASSERT(ppim->size == size,
5181 ("pmap_unmapbios: size mismatch"));
5186 offset = block * L2_SIZE;
5187 va_trunc = rounddown2(va, L2_SIZE) + offset;
5189 /* Remove L2_BLOCK */
5190 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
5191 KASSERT(pde != NULL,
5192 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
5194 l2 = pmap_l1_to_l2(pde, va_trunc);
5197 if (block == (l2_blocks - 1))
5203 pmap_invalidate_all(kernel_pmap);
5207 /* Unmap the pages reserved with kva_alloc. */
5208 if (vm_initialized) {
5209 offset = va & PAGE_MASK;
5210 size = round_page(offset + size);
5211 va = trunc_page(va);
5213 pde = pmap_pde(kernel_pmap, va, &lvl);
5214 KASSERT(pde != NULL,
5215 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
5216 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
5218 /* Unmap and invalidate the pages */
5219 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5220 pmap_kremove(va + tmpsize);
5227 * Sets the memory attribute for the specified page.
5230 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5233 m->md.pv_memattr = ma;
5236 * If "m" is a normal page, update its direct mapping. This update
5237 * can be relied upon to perform any cache operations that are
5238 * required for data coherence.
5240 if ((m->flags & PG_FICTITIOUS) == 0 &&
5241 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
5242 m->md.pv_memattr) != 0)
5243 panic("memory attribute change on the direct map failed");
5247 * Changes the specified virtual address range's memory type to that given by
5248 * the parameter "mode". The specified virtual address range must be
5249 * completely contained within either the direct map or the kernel map. If
5250 * the virtual address range is contained within the kernel map, then the
5251 * memory type for each of the corresponding ranges of the direct map is also
5252 * changed. (The corresponding ranges of the direct map are those ranges that
5253 * map the same physical pages as the specified virtual address range.) These
5254 * changes to the direct map are necessary because Intel describes the
5255 * behavior of their processors as "undefined" if two or more mappings to the
5256 * same physical page have different memory types.
5258 * Returns zero if the change completed successfully, and either EINVAL or
5259 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5260 * of the virtual address range was not mapped, and ENOMEM is returned if
5261 * there was insufficient memory available to complete the change. In the
5262 * latter case, the memory type may have been changed on some part of the
5263 * virtual address range or the direct map.
5266 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5270 PMAP_LOCK(kernel_pmap);
5271 error = pmap_change_attr_locked(va, size, mode);
5272 PMAP_UNLOCK(kernel_pmap);
5277 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
5279 vm_offset_t base, offset, tmpva;
5280 pt_entry_t l3, *pte, *newpte;
5283 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
5284 base = trunc_page(va);
5285 offset = va & PAGE_MASK;
5286 size = round_page(offset + size);
5288 if (!VIRT_IN_DMAP(base))
5291 for (tmpva = base; tmpva < base + size; ) {
5292 pte = pmap_pte(kernel_pmap, tmpva, &lvl);
5296 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
5298 * We already have the correct attribute,
5299 * ignore this entry.
5303 panic("Invalid DMAP table level: %d\n", lvl);
5305 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
5308 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
5316 * Split the entry to an level 3 table, then
5317 * set the new attribute.
5321 panic("Invalid DMAP table level: %d\n", lvl);
5323 newpte = pmap_demote_l1(kernel_pmap, pte,
5324 tmpva & ~L1_OFFSET);
5327 pte = pmap_l1_to_l2(pte, tmpva);
5329 newpte = pmap_demote_l2(kernel_pmap, pte,
5333 pte = pmap_l2_to_l3(pte, tmpva);
5335 /* Update the entry */
5336 l3 = pmap_load(pte);
5337 l3 &= ~ATTR_IDX_MASK;
5338 l3 |= ATTR_IDX(mode);
5339 if (mode == DEVICE_MEMORY)
5342 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
5346 * If moving to a non-cacheable entry flush
5349 if (mode == VM_MEMATTR_UNCACHEABLE)
5350 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
5362 * Create an L2 table to map all addresses within an L1 mapping.
5365 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
5367 pt_entry_t *l2, newl2, oldl1;
5369 vm_paddr_t l2phys, phys;
5373 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5374 oldl1 = pmap_load(l1);
5375 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
5376 ("pmap_demote_l1: Demoting a non-block entry"));
5377 KASSERT((va & L1_OFFSET) == 0,
5378 ("pmap_demote_l1: Invalid virtual address %#lx", va));
5379 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
5380 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
5383 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
5384 tmpl1 = kva_alloc(PAGE_SIZE);
5389 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
5390 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
5391 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
5392 " in pmap %p", va, pmap);
5396 l2phys = VM_PAGE_TO_PHYS(ml2);
5397 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
5399 /* Address the range points at */
5400 phys = oldl1 & ~ATTR_MASK;
5401 /* The attributed from the old l1 table to be copied */
5402 newl2 = oldl1 & ATTR_MASK;
5404 /* Create the new entries */
5405 for (i = 0; i < Ln_ENTRIES; i++) {
5406 l2[i] = newl2 | phys;
5409 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
5410 ("Invalid l2 page (%lx != %lx)", l2[0],
5411 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
5414 pmap_kenter(tmpl1, PAGE_SIZE,
5415 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY);
5416 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
5419 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
5422 pmap_kremove(tmpl1);
5423 kva_free(tmpl1, PAGE_SIZE);
5430 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
5434 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
5441 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
5442 struct rwlock **lockp)
5444 struct spglist free;
5447 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
5449 vm_page_free_pages_toq(&free, true);
5453 * Create an L3 table to map all addresses within an L2 mapping.
5456 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
5457 struct rwlock **lockp)
5459 pt_entry_t *l3, newl3, oldl2;
5464 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5466 oldl2 = pmap_load(l2);
5467 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
5468 ("pmap_demote_l2: Demoting a non-block entry"));
5472 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
5473 tmpl2 = kva_alloc(PAGE_SIZE);
5479 * Invalidate the 2MB page mapping and return "failure" if the
5480 * mapping was never accessed.
5482 if ((oldl2 & ATTR_AF) == 0) {
5483 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5484 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
5485 pmap_demote_l2_abort(pmap, va, l2, lockp);
5486 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
5491 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
5492 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5493 ("pmap_demote_l2: page table page for a wired mapping"
5497 * If the page table page is missing and the mapping
5498 * is for a kernel address, the mapping must belong to
5499 * the direct map. Page table pages are preallocated
5500 * for every other part of the kernel address space,
5501 * so the direct map region is the only part of the
5502 * kernel address space that must be handled here.
5504 KASSERT(va < VM_MAXUSER_ADDRESS || VIRT_IN_DMAP(va),
5505 ("pmap_demote_l2: No saved mpte for va %#lx", va));
5508 * If the 2MB page mapping belongs to the direct map
5509 * region of the kernel's address space, then the page
5510 * allocation request specifies the highest possible
5511 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5512 * priority is normal.
5514 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
5515 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5516 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5519 * If the allocation of the new page table page fails,
5520 * invalidate the 2MB page mapping and return "failure".
5523 pmap_demote_l2_abort(pmap, va, l2, lockp);
5524 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
5525 " in pmap %p", va, pmap);
5529 if (va < VM_MAXUSER_ADDRESS) {
5530 ml3->wire_count = NL3PG;
5531 pmap_resident_count_inc(pmap, 1);
5534 l3phys = VM_PAGE_TO_PHYS(ml3);
5535 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
5536 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
5537 KASSERT((oldl2 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) !=
5538 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM),
5539 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
5542 * If the page table page is not leftover from an earlier promotion,
5543 * or the mapping attributes have changed, (re)initialize the L3 table.
5545 * When pmap_update_entry() clears the old L2 mapping, it (indirectly)
5546 * performs a dsb(). That dsb() ensures that the stores for filling
5547 * "l3" are visible before "l3" is added to the page table.
5549 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK))
5550 pmap_fill_l3(l3, newl3);
5553 * Map the temporary page so we don't lose access to the l2 table.
5556 pmap_kenter(tmpl2, PAGE_SIZE,
5557 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY);
5558 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
5562 * The spare PV entries must be reserved prior to demoting the
5563 * mapping, that is, prior to changing the PDE. Otherwise, the state
5564 * of the L2 and the PV lists will be inconsistent, which can result
5565 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5566 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
5567 * PV entry for the 2MB page mapping that is being demoted.
5569 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5570 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
5573 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
5574 * the 2MB page mapping.
5576 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
5579 * Demote the PV entry.
5581 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5582 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
5584 atomic_add_long(&pmap_l2_demotions, 1);
5585 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
5586 " in pmap %p %lx", va, pmap, l3[0]);
5590 pmap_kremove(tmpl2);
5591 kva_free(tmpl2, PAGE_SIZE);
5599 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
5601 struct rwlock *lock;
5605 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
5612 * perform the pmap work for mincore
5615 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5617 pt_entry_t *pte, tpte;
5618 vm_paddr_t mask, pa;
5625 pte = pmap_pte(pmap, addr, &lvl);
5627 tpte = pmap_load(pte);
5640 panic("pmap_mincore: invalid level %d", lvl);
5643 managed = (tpte & ATTR_SW_MANAGED) != 0;
5644 val = MINCORE_INCORE;
5646 val |= MINCORE_SUPER;
5647 if ((managed && pmap_pte_dirty(tpte)) || (!managed &&
5648 (tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)))
5649 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5650 if ((tpte & ATTR_AF) == ATTR_AF)
5651 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5653 pa = (tpte & ~ATTR_MASK) | (addr & mask);
5657 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5658 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
5659 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5660 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5663 PA_UNLOCK_COND(*locked_pa);
5670 pmap_activate(struct thread *td)
5675 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5676 td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0);
5678 "msr ttbr0_el1, %0 \n"
5680 : : "r"(td->td_proc->p_md.md_l0addr));
5681 pmap_invalidate_all(pmap);
5686 pmap_switch(struct thread *old, struct thread *new)
5688 pcpu_bp_harden bp_harden;
5691 /* Store the new curthread */
5692 PCPU_SET(curthread, new);
5694 /* And the new pcb */
5696 PCPU_SET(curpcb, pcb);
5699 * TODO: We may need to flush the cache here if switching
5700 * to a user process.
5704 old->td_proc->p_md.md_l0addr != new->td_proc->p_md.md_l0addr) {
5706 /* Switch to the new pmap */
5707 "msr ttbr0_el1, %0 \n"
5710 /* Invalidate the TLB */
5715 : : "r"(new->td_proc->p_md.md_l0addr));
5718 * Stop userspace from training the branch predictor against
5719 * other processes. This will call into a CPU specific
5720 * function that clears the branch predictor state.
5722 bp_harden = PCPU_GET(bp_harden);
5723 if (bp_harden != NULL)
5731 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
5734 if (va >= VM_MIN_KERNEL_ADDRESS) {
5735 cpu_icache_sync_range(va, sz);
5740 /* Find the length of data in this page to flush */
5741 offset = va & PAGE_MASK;
5742 len = imin(PAGE_SIZE - offset, sz);
5745 /* Extract the physical address & find it in the DMAP */
5746 pa = pmap_extract(pmap, va);
5748 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
5750 /* Move to the next page */
5753 /* Set the length for the next iteration */
5754 len = imin(PAGE_SIZE, sz);
5760 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
5762 pt_entry_t pte, *ptep;
5769 ec = ESR_ELx_EXCEPTION(esr);
5771 case EXCP_INSN_ABORT_L:
5772 case EXCP_INSN_ABORT:
5773 case EXCP_DATA_ABORT_L:
5774 case EXCP_DATA_ABORT:
5780 /* Data and insn aborts use same encoding for FSC field. */
5781 switch (esr & ISS_DATA_DFSC_MASK) {
5782 case ISS_DATA_DFSC_AFF_L1:
5783 case ISS_DATA_DFSC_AFF_L2:
5784 case ISS_DATA_DFSC_AFF_L3:
5786 ptep = pmap_pte(pmap, far, &lvl);
5788 pmap_set_bits(ptep, ATTR_AF);
5791 * XXXMJ as an optimization we could mark the entry
5792 * dirty if this is a write fault.
5797 case ISS_DATA_DFSC_PF_L1:
5798 case ISS_DATA_DFSC_PF_L2:
5799 case ISS_DATA_DFSC_PF_L3:
5800 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
5801 (esr & ISS_DATA_WnR) == 0)
5804 ptep = pmap_pte(pmap, far, &lvl);
5806 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
5807 if ((pte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RO)) {
5808 pmap_clear_bits(ptep, ATTR_AP_RW_BIT);
5809 pmap_invalidate_page(pmap, far);
5815 case ISS_DATA_DFSC_TF_L0:
5816 case ISS_DATA_DFSC_TF_L1:
5817 case ISS_DATA_DFSC_TF_L2:
5818 case ISS_DATA_DFSC_TF_L3:
5820 /* Ask the MMU to check the address */
5821 intr = intr_disable();
5822 if (pmap == kernel_pmap)
5823 par = arm64_address_translate_s1e1r(far);
5825 par = arm64_address_translate_s1e0r(far);
5830 * If the translation was successful the address was invalid
5831 * due to a break-before-make sequence. We can unlock and
5832 * return success to the trap handler.
5834 if (PAR_SUCCESS(par))
5843 * Increase the starting virtual address of the given mapping if a
5844 * different alignment might result in more superpage mappings.
5847 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5848 vm_offset_t *addr, vm_size_t size)
5850 vm_offset_t superpage_offset;
5854 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5855 offset += ptoa(object->pg_color);
5856 superpage_offset = offset & L2_OFFSET;
5857 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
5858 (*addr & L2_OFFSET) == superpage_offset)
5860 if ((*addr & L2_OFFSET) < superpage_offset)
5861 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
5863 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
5867 * Get the kernel virtual address of a set of physical pages. If there are
5868 * physical addresses not covered by the DMAP perform a transient mapping
5869 * that will be removed when calling pmap_unmap_io_transient.
5871 * \param page The pages the caller wishes to obtain the virtual
5872 * address on the kernel memory map.
5873 * \param vaddr On return contains the kernel virtual memory address
5874 * of the pages passed in the page parameter.
5875 * \param count Number of pages passed in.
5876 * \param can_fault TRUE if the thread using the mapped pages can take
5877 * page faults, FALSE otherwise.
5879 * \returns TRUE if the caller must call pmap_unmap_io_transient when
5880 * finished or FALSE otherwise.
5884 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
5885 boolean_t can_fault)
5888 boolean_t needs_mapping;
5892 * Allocate any KVA space that we need, this is done in a separate
5893 * loop to prevent calling vmem_alloc while pinned.
5895 needs_mapping = FALSE;
5896 for (i = 0; i < count; i++) {
5897 paddr = VM_PAGE_TO_PHYS(page[i]);
5898 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
5899 error = vmem_alloc(kernel_arena, PAGE_SIZE,
5900 M_BESTFIT | M_WAITOK, &vaddr[i]);
5901 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
5902 needs_mapping = TRUE;
5904 vaddr[i] = PHYS_TO_DMAP(paddr);
5908 /* Exit early if everything is covered by the DMAP */
5914 for (i = 0; i < count; i++) {
5915 paddr = VM_PAGE_TO_PHYS(page[i]);
5916 if (!PHYS_IN_DMAP(paddr)) {
5918 "pmap_map_io_transient: TODO: Map out of DMAP data");
5922 return (needs_mapping);
5926 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
5927 boolean_t can_fault)
5934 for (i = 0; i < count; i++) {
5935 paddr = VM_PAGE_TO_PHYS(page[i]);
5936 if (!PHYS_IN_DMAP(paddr)) {
5937 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
5943 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
5946 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);