2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/msgbuf.h>
120 #include <sys/mutex.h>
121 #include <sys/proc.h>
122 #include <sys/rwlock.h>
124 #include <sys/vmem.h>
125 #include <sys/vmmeter.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/_unrhdr.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/vm_pager.h>
140 #include <vm/vm_phys.h>
141 #include <vm/vm_radix.h>
142 #include <vm/vm_reserv.h>
145 #include <machine/machdep.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
149 #include <arm/include/physmem.h>
151 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
152 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
153 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
154 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
156 #define NUL0E L0_ENTRIES
157 #define NUL1E (NUL0E * NL1PG)
158 #define NUL2E (NUL1E * NL2PG)
160 #if !defined(DIAGNOSTIC)
161 #ifdef __GNUC_GNU_INLINE__
162 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
164 #define PMAP_INLINE extern inline
171 * These are configured by the mair_el1 register. This is set up in locore.S
173 #define DEVICE_MEMORY 0
174 #define UNCACHED_MEMORY 1
175 #define CACHED_MEMORY 2
179 #define PV_STAT(x) do { x ; } while (0)
181 #define PV_STAT(x) do { } while (0)
184 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
185 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
187 #define NPV_LIST_LOCKS MAXCPU
189 #define PHYS_TO_PV_LIST_LOCK(pa) \
190 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
192 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
193 struct rwlock **_lockp = (lockp); \
194 struct rwlock *_new_lock; \
196 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
197 if (_new_lock != *_lockp) { \
198 if (*_lockp != NULL) \
199 rw_wunlock(*_lockp); \
200 *_lockp = _new_lock; \
205 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
206 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
208 #define RELEASE_PV_LIST_LOCK(lockp) do { \
209 struct rwlock **_lockp = (lockp); \
211 if (*_lockp != NULL) { \
212 rw_wunlock(*_lockp); \
217 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
218 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
220 struct pmap kernel_pmap_store;
222 /* Used for mapping ACPI memory before VM is initialized */
223 #define PMAP_PREINIT_MAPPING_COUNT 32
224 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
225 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
226 static int vm_initialized = 0; /* No need to use pre-init maps when set */
229 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
230 * Always map entire L2 block for simplicity.
231 * VA of L2 block = preinit_map_va + i * L2_SIZE
233 static struct pmap_preinit_mapping {
237 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
239 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
240 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
241 vm_offset_t kernel_vm_end = 0;
244 * Data for the pv entry allocation mechanism.
246 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
247 static struct mtx pv_chunks_mutex;
248 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
249 static struct md_page *pv_table;
250 static struct md_page pv_dummy;
252 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
253 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
254 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
256 /* This code assumes all L1 DMAP entries will be used */
257 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
258 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
260 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
261 extern pt_entry_t pagetable_dmap[];
263 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
264 static vm_paddr_t physmap[PHYSMAP_SIZE];
265 static u_int physmap_idx;
267 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
269 static int superpages_enabled = 1;
270 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
271 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
272 "Are large page mappings enabled?");
275 * Internal flags for pmap_enter()'s helper functions.
277 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
278 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
280 static void free_pv_chunk(struct pv_chunk *pc);
281 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
282 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
283 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
284 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
285 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
288 static int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode);
289 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
290 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
291 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
292 vm_offset_t va, struct rwlock **lockp);
293 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
294 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
295 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
296 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
297 u_int flags, vm_page_t m, struct rwlock **lockp);
298 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
299 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
300 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
301 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
302 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
303 vm_page_t m, struct rwlock **lockp);
305 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
306 struct rwlock **lockp);
308 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
309 struct spglist *free);
310 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
311 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
314 * These load the old table data and store the new value.
315 * They need to be atomic as the System MMU may write to the table at
316 * the same time as the CPU.
318 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
319 #define pmap_set(table, mask) atomic_set_64(table, mask)
320 #define pmap_load_clear(table) atomic_swap_64(table, 0)
321 #define pmap_load(table) (*table)
323 /********************/
324 /* Inline functions */
325 /********************/
328 pagecopy(void *s, void *d)
331 memcpy(d, s, PAGE_SIZE);
334 static __inline pd_entry_t *
335 pmap_l0(pmap_t pmap, vm_offset_t va)
338 return (&pmap->pm_l0[pmap_l0_index(va)]);
341 static __inline pd_entry_t *
342 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
346 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
347 return (&l1[pmap_l1_index(va)]);
350 static __inline pd_entry_t *
351 pmap_l1(pmap_t pmap, vm_offset_t va)
355 l0 = pmap_l0(pmap, va);
356 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
359 return (pmap_l0_to_l1(l0, va));
362 static __inline pd_entry_t *
363 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
367 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
368 return (&l2[pmap_l2_index(va)]);
371 static __inline pd_entry_t *
372 pmap_l2(pmap_t pmap, vm_offset_t va)
376 l1 = pmap_l1(pmap, va);
377 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
380 return (pmap_l1_to_l2(l1, va));
383 static __inline pt_entry_t *
384 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
388 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
389 return (&l3[pmap_l3_index(va)]);
393 * Returns the lowest valid pde for a given virtual address.
394 * The next level may or may not point to a valid page or block.
396 static __inline pd_entry_t *
397 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
399 pd_entry_t *l0, *l1, *l2, desc;
401 l0 = pmap_l0(pmap, va);
402 desc = pmap_load(l0) & ATTR_DESCR_MASK;
403 if (desc != L0_TABLE) {
408 l1 = pmap_l0_to_l1(l0, va);
409 desc = pmap_load(l1) & ATTR_DESCR_MASK;
410 if (desc != L1_TABLE) {
415 l2 = pmap_l1_to_l2(l1, va);
416 desc = pmap_load(l2) & ATTR_DESCR_MASK;
417 if (desc != L2_TABLE) {
427 * Returns the lowest valid pte block or table entry for a given virtual
428 * address. If there are no valid entries return NULL and set the level to
429 * the first invalid level.
431 static __inline pt_entry_t *
432 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
434 pd_entry_t *l1, *l2, desc;
437 l1 = pmap_l1(pmap, va);
442 desc = pmap_load(l1) & ATTR_DESCR_MASK;
443 if (desc == L1_BLOCK) {
448 if (desc != L1_TABLE) {
453 l2 = pmap_l1_to_l2(l1, va);
454 desc = pmap_load(l2) & ATTR_DESCR_MASK;
455 if (desc == L2_BLOCK) {
460 if (desc != L2_TABLE) {
466 l3 = pmap_l2_to_l3(l2, va);
467 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
474 pmap_ps_enabled(pmap_t pmap __unused)
477 return (superpages_enabled != 0);
481 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
482 pd_entry_t **l2, pt_entry_t **l3)
484 pd_entry_t *l0p, *l1p, *l2p;
486 if (pmap->pm_l0 == NULL)
489 l0p = pmap_l0(pmap, va);
492 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
495 l1p = pmap_l0_to_l1(l0p, va);
498 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
504 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
507 l2p = pmap_l1_to_l2(l1p, va);
510 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
515 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
518 *l3 = pmap_l2_to_l3(l2p, va);
524 pmap_l3_valid(pt_entry_t l3)
527 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
531 CTASSERT(L1_BLOCK == L2_BLOCK);
534 * Checks if the page is dirty. We currently lack proper tracking of this on
535 * arm64 so for now assume is a page mapped as rw was accessed it is.
538 pmap_page_dirty(pt_entry_t pte)
541 return ((pte & (ATTR_AF | ATTR_AP_RW_BIT)) ==
542 (ATTR_AF | ATTR_AP(ATTR_AP_RW)));
546 pmap_resident_count_inc(pmap_t pmap, int count)
549 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
550 pmap->pm_stats.resident_count += count;
554 pmap_resident_count_dec(pmap_t pmap, int count)
557 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
558 KASSERT(pmap->pm_stats.resident_count >= count,
559 ("pmap %p resident count underflow %ld %d", pmap,
560 pmap->pm_stats.resident_count, count));
561 pmap->pm_stats.resident_count -= count;
565 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
571 l1 = (pd_entry_t *)l1pt;
572 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
574 /* Check locore has used a table L1 map */
575 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
576 ("Invalid bootstrap L1 table"));
577 /* Find the address of the L2 table */
578 l2 = (pt_entry_t *)init_pt_va;
579 *l2_slot = pmap_l2_index(va);
585 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
587 u_int l1_slot, l2_slot;
590 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
592 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
596 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
597 vm_offset_t freemempos)
601 vm_paddr_t l2_pa, pa;
602 u_int l1_slot, l2_slot, prev_l1_slot;
605 dmap_phys_base = min_pa & ~L1_OFFSET;
611 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
612 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
614 for (i = 0; i < (physmap_idx * 2); i += 2) {
615 pa = physmap[i] & ~L2_OFFSET;
616 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
618 /* Create L2 mappings at the start of the region */
619 if ((pa & L1_OFFSET) != 0) {
620 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
621 if (l1_slot != prev_l1_slot) {
622 prev_l1_slot = l1_slot;
623 l2 = (pt_entry_t *)freemempos;
624 l2_pa = pmap_early_vtophys(kern_l1,
626 freemempos += PAGE_SIZE;
628 pmap_load_store(&pagetable_dmap[l1_slot],
629 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
631 memset(l2, 0, PAGE_SIZE);
634 ("pmap_bootstrap_dmap: NULL l2 map"));
635 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
636 pa += L2_SIZE, va += L2_SIZE) {
638 * We are on a boundary, stop to
639 * create a level 1 block
641 if ((pa & L1_OFFSET) == 0)
644 l2_slot = pmap_l2_index(va);
645 KASSERT(l2_slot != 0, ("..."));
646 pmap_load_store(&l2[l2_slot],
647 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
648 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
650 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
654 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
655 (physmap[i + 1] - pa) >= L1_SIZE;
656 pa += L1_SIZE, va += L1_SIZE) {
657 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
658 pmap_load_store(&pagetable_dmap[l1_slot],
659 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
660 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
663 /* Create L2 mappings at the end of the region */
664 if (pa < physmap[i + 1]) {
665 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
666 if (l1_slot != prev_l1_slot) {
667 prev_l1_slot = l1_slot;
668 l2 = (pt_entry_t *)freemempos;
669 l2_pa = pmap_early_vtophys(kern_l1,
671 freemempos += PAGE_SIZE;
673 pmap_load_store(&pagetable_dmap[l1_slot],
674 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
676 memset(l2, 0, PAGE_SIZE);
679 ("pmap_bootstrap_dmap: NULL l2 map"));
680 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
681 pa += L2_SIZE, va += L2_SIZE) {
682 l2_slot = pmap_l2_index(va);
683 pmap_load_store(&l2[l2_slot],
684 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
685 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
689 if (pa > dmap_phys_max) {
701 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
708 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
710 l1 = (pd_entry_t *)l1pt;
711 l1_slot = pmap_l1_index(va);
714 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
715 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
717 pa = pmap_early_vtophys(l1pt, l2pt);
718 pmap_load_store(&l1[l1_slot],
719 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
723 /* Clean the L2 page table */
724 memset((void *)l2_start, 0, l2pt - l2_start);
730 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
737 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
739 l2 = pmap_l2(kernel_pmap, va);
740 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
741 l2_slot = pmap_l2_index(va);
744 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
745 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
747 pa = pmap_early_vtophys(l1pt, l3pt);
748 pmap_load_store(&l2[l2_slot],
749 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
753 /* Clean the L2 page table */
754 memset((void *)l3_start, 0, l3pt - l3_start);
760 * Bootstrap the system enough to run with virtual memory.
763 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
766 u_int l1_slot, l2_slot;
769 vm_offset_t va, freemempos;
770 vm_offset_t dpcpu, msgbufpv;
771 vm_paddr_t start_pa, pa, min_pa;
774 kern_delta = KERNBASE - kernstart;
776 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
777 printf("%lx\n", l1pt);
778 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
780 /* Set this early so we can use the pagetable walking functions */
781 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
782 PMAP_LOCK_INIT(kernel_pmap);
784 /* Assume the address we were loaded to is a valid physical address */
785 min_pa = KERNBASE - kern_delta;
787 physmap_idx = arm_physmem_avail(physmap, nitems(physmap));
791 * Find the minimum physical address. physmap is sorted,
792 * but may contain empty ranges.
794 for (i = 0; i < (physmap_idx * 2); i += 2) {
795 if (physmap[i] == physmap[i + 1])
797 if (physmap[i] <= min_pa)
801 freemempos = KERNBASE + kernlen;
802 freemempos = roundup2(freemempos, PAGE_SIZE);
804 /* Create a direct map region early so we can use it for pa -> va */
805 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
808 start_pa = pa = KERNBASE - kern_delta;
811 * Read the page table to find out what is already mapped.
812 * This assumes we have mapped a block of memory from KERNBASE
813 * using a single L1 entry.
815 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
817 /* Sanity check the index, KERNBASE should be the first VA */
818 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
820 /* Find how many pages we have mapped */
821 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
822 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
825 /* Check locore used L2 blocks */
826 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
827 ("Invalid bootstrap L2 table"));
828 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
829 ("Incorrect PA in L2 table"));
835 va = roundup2(va, L1_SIZE);
837 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
838 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
839 /* And the l3 tables for the early devmap */
840 freemempos = pmap_bootstrap_l3(l1pt,
841 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
845 #define alloc_pages(var, np) \
846 (var) = freemempos; \
847 freemempos += (np * PAGE_SIZE); \
848 memset((char *)(var), 0, ((np) * PAGE_SIZE));
850 /* Allocate dynamic per-cpu area. */
851 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
852 dpcpu_init((void *)dpcpu, 0);
854 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
855 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
856 msgbufp = (void *)msgbufpv;
858 /* Reserve some VA space for early BIOS/ACPI mapping */
859 preinit_map_va = roundup2(freemempos, L2_SIZE);
861 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
862 virtual_avail = roundup2(virtual_avail, L1_SIZE);
863 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
864 kernel_vm_end = virtual_avail;
866 pa = pmap_early_vtophys(l1pt, freemempos);
868 arm_physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
874 * Initialize a vm_page's machine-dependent fields.
877 pmap_page_init(vm_page_t m)
880 TAILQ_INIT(&m->md.pv_list);
881 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
885 * Initialize the pmap module.
886 * Called by vm_init, to initialize any structures that the pmap
887 * system needs to map virtual memory.
896 * Are large page mappings enabled?
898 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
899 if (superpages_enabled) {
900 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
901 ("pmap_init: can't assign to pagesizes[1]"));
902 pagesizes[1] = L2_SIZE;
906 * Initialize the pv chunk list mutex.
908 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
911 * Initialize the pool of pv list locks.
913 for (i = 0; i < NPV_LIST_LOCKS; i++)
914 rw_init(&pv_list_locks[i], "pmap pv list");
917 * Calculate the size of the pv head table for superpages.
919 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
922 * Allocate memory for the pv head table for superpages.
924 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
926 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
928 for (i = 0; i < pv_npg; i++)
929 TAILQ_INIT(&pv_table[i].pv_list);
930 TAILQ_INIT(&pv_dummy.pv_list);
935 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
936 "2MB page mapping counters");
938 static u_long pmap_l2_demotions;
939 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
940 &pmap_l2_demotions, 0, "2MB page demotions");
942 static u_long pmap_l2_mappings;
943 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
944 &pmap_l2_mappings, 0, "2MB page mappings");
946 static u_long pmap_l2_p_failures;
947 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
948 &pmap_l2_p_failures, 0, "2MB page promotion failures");
950 static u_long pmap_l2_promotions;
951 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
952 &pmap_l2_promotions, 0, "2MB page promotions");
955 * Invalidate a single TLB entry.
958 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
964 "tlbi vaae1is, %0 \n"
967 : : "r"(va >> PAGE_SHIFT));
972 pmap_invalidate_range_nopin(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
977 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
979 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
987 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
991 pmap_invalidate_range_nopin(pmap, sva, eva);
996 pmap_invalidate_all(pmap_t pmap)
1009 * Routine: pmap_extract
1011 * Extract the physical page address associated
1012 * with the given map/virtual_address pair.
1015 pmap_extract(pmap_t pmap, vm_offset_t va)
1017 pt_entry_t *pte, tpte;
1024 * Find the block or page map for this virtual address. pmap_pte
1025 * will return either a valid block/page entry, or NULL.
1027 pte = pmap_pte(pmap, va, &lvl);
1029 tpte = pmap_load(pte);
1030 pa = tpte & ~ATTR_MASK;
1033 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1034 ("pmap_extract: Invalid L1 pte found: %lx",
1035 tpte & ATTR_DESCR_MASK));
1036 pa |= (va & L1_OFFSET);
1039 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1040 ("pmap_extract: Invalid L2 pte found: %lx",
1041 tpte & ATTR_DESCR_MASK));
1042 pa |= (va & L2_OFFSET);
1045 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1046 ("pmap_extract: Invalid L3 pte found: %lx",
1047 tpte & ATTR_DESCR_MASK));
1048 pa |= (va & L3_OFFSET);
1057 * Routine: pmap_extract_and_hold
1059 * Atomically extract and hold the physical page
1060 * with the given pmap and virtual address pair
1061 * if that mapping permits the given protection.
1064 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1066 pt_entry_t *pte, tpte;
1076 pte = pmap_pte(pmap, va, &lvl);
1078 tpte = pmap_load(pte);
1080 KASSERT(lvl > 0 && lvl <= 3,
1081 ("pmap_extract_and_hold: Invalid level %d", lvl));
1082 CTASSERT(L1_BLOCK == L2_BLOCK);
1083 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1084 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1085 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1086 tpte & ATTR_DESCR_MASK));
1087 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1088 ((prot & VM_PROT_WRITE) == 0)) {
1091 off = va & L1_OFFSET;
1094 off = va & L2_OFFSET;
1100 if (vm_page_pa_tryrelock(pmap,
1101 (tpte & ~ATTR_MASK) | off, &pa))
1103 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1113 pmap_kextract(vm_offset_t va)
1115 pt_entry_t *pte, tpte;
1119 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1120 pa = DMAP_TO_PHYS(va);
1123 pte = pmap_pte(kernel_pmap, va, &lvl);
1125 tpte = pmap_load(pte);
1126 pa = tpte & ~ATTR_MASK;
1129 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1130 ("pmap_kextract: Invalid L1 pte found: %lx",
1131 tpte & ATTR_DESCR_MASK));
1132 pa |= (va & L1_OFFSET);
1135 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1136 ("pmap_kextract: Invalid L2 pte found: %lx",
1137 tpte & ATTR_DESCR_MASK));
1138 pa |= (va & L2_OFFSET);
1141 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1142 ("pmap_kextract: Invalid L3 pte found: %lx",
1143 tpte & ATTR_DESCR_MASK));
1144 pa |= (va & L3_OFFSET);
1152 /***************************************************
1153 * Low level mapping routines.....
1154 ***************************************************/
1157 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1160 pt_entry_t *pte, attr;
1164 KASSERT((pa & L3_OFFSET) == 0,
1165 ("pmap_kenter: Invalid physical address"));
1166 KASSERT((sva & L3_OFFSET) == 0,
1167 ("pmap_kenter: Invalid virtual address"));
1168 KASSERT((size & PAGE_MASK) == 0,
1169 ("pmap_kenter: Mapping is not page-sized"));
1171 attr = ATTR_DEFAULT | ATTR_IDX(mode) | L3_PAGE;
1172 if (mode == DEVICE_MEMORY)
1177 pde = pmap_pde(kernel_pmap, va, &lvl);
1178 KASSERT(pde != NULL,
1179 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1180 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1182 pte = pmap_l2_to_l3(pde, va);
1183 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1189 pmap_invalidate_range(kernel_pmap, sva, va);
1193 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1196 pmap_kenter(sva, size, pa, DEVICE_MEMORY);
1200 * Remove a page from the kernel pagetables.
1203 pmap_kremove(vm_offset_t va)
1208 pte = pmap_pte(kernel_pmap, va, &lvl);
1209 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1210 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1212 pmap_load_clear(pte);
1213 pmap_invalidate_page(kernel_pmap, va);
1217 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1223 KASSERT((sva & L3_OFFSET) == 0,
1224 ("pmap_kremove_device: Invalid virtual address"));
1225 KASSERT((size & PAGE_MASK) == 0,
1226 ("pmap_kremove_device: Mapping is not page-sized"));
1230 pte = pmap_pte(kernel_pmap, va, &lvl);
1231 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1233 ("Invalid device pagetable level: %d != 3", lvl));
1234 pmap_load_clear(pte);
1239 pmap_invalidate_range(kernel_pmap, sva, va);
1243 * Used to map a range of physical addresses into kernel
1244 * virtual address space.
1246 * The value passed in '*virt' is a suggested virtual address for
1247 * the mapping. Architectures which can support a direct-mapped
1248 * physical to virtual region can return the appropriate address
1249 * within that region, leaving '*virt' unchanged. Other
1250 * architectures should map the pages starting at '*virt' and
1251 * update '*virt' with the first usable address after the mapped
1255 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1257 return PHYS_TO_DMAP(start);
1262 * Add a list of wired pages to the kva
1263 * this routine is only used for temporary
1264 * kernel mappings that do not need to have
1265 * page modification or references recorded.
1266 * Note that old mappings are simply written
1267 * over. The page *must* be wired.
1268 * Note: SMP coherent. Uses a ranged shootdown IPI.
1271 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1274 pt_entry_t *pte, pa;
1280 for (i = 0; i < count; i++) {
1281 pde = pmap_pde(kernel_pmap, va, &lvl);
1282 KASSERT(pde != NULL,
1283 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1285 ("pmap_qenter: Invalid level %d", lvl));
1288 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1289 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1290 if (m->md.pv_memattr == DEVICE_MEMORY)
1292 pte = pmap_l2_to_l3(pde, va);
1293 pmap_load_store(pte, pa);
1297 pmap_invalidate_range(kernel_pmap, sva, va);
1301 * This routine tears out page mappings from the
1302 * kernel -- it is meant only for temporary mappings.
1305 pmap_qremove(vm_offset_t sva, int count)
1311 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1314 while (count-- > 0) {
1315 pte = pmap_pte(kernel_pmap, va, &lvl);
1317 ("Invalid device pagetable level: %d != 3", lvl));
1319 pmap_load_clear(pte);
1324 pmap_invalidate_range(kernel_pmap, sva, va);
1327 /***************************************************
1328 * Page table page management routines.....
1329 ***************************************************/
1331 * Schedule the specified unused page table page to be freed. Specifically,
1332 * add the page to the specified list of pages that will be released to the
1333 * physical memory manager after the TLB has been updated.
1335 static __inline void
1336 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1337 boolean_t set_PG_ZERO)
1341 m->flags |= PG_ZERO;
1343 m->flags &= ~PG_ZERO;
1344 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1348 * Decrements a page table page's wire count, which is used to record the
1349 * number of valid page table entries within the page. If the wire count
1350 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1351 * page table page was unmapped and FALSE otherwise.
1353 static inline boolean_t
1354 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1358 if (m->wire_count == 0) {
1359 _pmap_unwire_l3(pmap, va, m, free);
1366 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1369 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1371 * unmap the page table page
1373 if (m->pindex >= (NUL2E + NUL1E)) {
1377 l0 = pmap_l0(pmap, va);
1378 pmap_load_clear(l0);
1379 } else if (m->pindex >= NUL2E) {
1383 l1 = pmap_l1(pmap, va);
1384 pmap_load_clear(l1);
1389 l2 = pmap_l2(pmap, va);
1390 pmap_load_clear(l2);
1392 pmap_resident_count_dec(pmap, 1);
1393 if (m->pindex < NUL2E) {
1394 /* We just released an l3, unhold the matching l2 */
1395 pd_entry_t *l1, tl1;
1398 l1 = pmap_l1(pmap, va);
1399 tl1 = pmap_load(l1);
1400 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1401 pmap_unwire_l3(pmap, va, l2pg, free);
1402 } else if (m->pindex < (NUL2E + NUL1E)) {
1403 /* We just released an l2, unhold the matching l1 */
1404 pd_entry_t *l0, tl0;
1407 l0 = pmap_l0(pmap, va);
1408 tl0 = pmap_load(l0);
1409 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1410 pmap_unwire_l3(pmap, va, l1pg, free);
1412 pmap_invalidate_page(pmap, va);
1417 * Put page on a list so that it is released after
1418 * *ALL* TLB shootdown is done
1420 pmap_add_delayed_free_list(m, free, TRUE);
1424 * After removing a page table entry, this routine is used to
1425 * conditionally free the page, and manage the hold/wire counts.
1428 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1429 struct spglist *free)
1433 if (va >= VM_MAXUSER_ADDRESS)
1435 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1436 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1437 return (pmap_unwire_l3(pmap, va, mpte, free));
1441 pmap_pinit0(pmap_t pmap)
1444 PMAP_LOCK_INIT(pmap);
1445 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1446 pmap->pm_l0 = kernel_pmap->pm_l0;
1447 pmap->pm_root.rt_root = 0;
1451 pmap_pinit(pmap_t pmap)
1457 * allocate the l0 page
1459 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1460 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1463 l0phys = VM_PAGE_TO_PHYS(l0pt);
1464 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1466 if ((l0pt->flags & PG_ZERO) == 0)
1467 pagezero(pmap->pm_l0);
1469 pmap->pm_root.rt_root = 0;
1470 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1476 * This routine is called if the desired page table page does not exist.
1478 * If page table page allocation fails, this routine may sleep before
1479 * returning NULL. It sleeps only if a lock pointer was given.
1481 * Note: If a page allocation fails at page table level two or three,
1482 * one or two pages may be held during the wait, only to be released
1483 * afterwards. This conservative approach is easily argued to avoid
1487 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1489 vm_page_t m, l1pg, l2pg;
1491 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1494 * Allocate a page table page.
1496 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1497 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1498 if (lockp != NULL) {
1499 RELEASE_PV_LIST_LOCK(lockp);
1506 * Indicate the need to retry. While waiting, the page table
1507 * page may have been allocated.
1511 if ((m->flags & PG_ZERO) == 0)
1515 * Map the pagetable page into the process address space, if
1516 * it isn't already there.
1519 if (ptepindex >= (NUL2E + NUL1E)) {
1521 vm_pindex_t l0index;
1523 l0index = ptepindex - (NUL2E + NUL1E);
1524 l0 = &pmap->pm_l0[l0index];
1525 pmap_load_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1526 } else if (ptepindex >= NUL2E) {
1527 vm_pindex_t l0index, l1index;
1528 pd_entry_t *l0, *l1;
1531 l1index = ptepindex - NUL2E;
1532 l0index = l1index >> L0_ENTRIES_SHIFT;
1534 l0 = &pmap->pm_l0[l0index];
1535 tl0 = pmap_load(l0);
1537 /* recurse for allocating page dir */
1538 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1540 vm_page_unwire_noq(m);
1541 vm_page_free_zero(m);
1545 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1549 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1550 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1551 pmap_load_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1553 vm_pindex_t l0index, l1index;
1554 pd_entry_t *l0, *l1, *l2;
1555 pd_entry_t tl0, tl1;
1557 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1558 l0index = l1index >> L0_ENTRIES_SHIFT;
1560 l0 = &pmap->pm_l0[l0index];
1561 tl0 = pmap_load(l0);
1563 /* recurse for allocating page dir */
1564 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1566 vm_page_unwire_noq(m);
1567 vm_page_free_zero(m);
1570 tl0 = pmap_load(l0);
1571 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1572 l1 = &l1[l1index & Ln_ADDR_MASK];
1574 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1575 l1 = &l1[l1index & Ln_ADDR_MASK];
1576 tl1 = pmap_load(l1);
1578 /* recurse for allocating page dir */
1579 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1581 vm_page_unwire_noq(m);
1582 vm_page_free_zero(m);
1586 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1591 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1592 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1593 pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1596 pmap_resident_count_inc(pmap, 1);
1602 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1606 vm_pindex_t l2pindex;
1609 l1 = pmap_l1(pmap, va);
1610 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1611 /* Add a reference to the L2 page. */
1612 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1615 /* Allocate a L2 page. */
1616 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1617 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1618 if (l2pg == NULL && lockp != NULL)
1625 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1627 vm_pindex_t ptepindex;
1628 pd_entry_t *pde, tpde;
1636 * Calculate pagetable page index
1638 ptepindex = pmap_l2_pindex(va);
1641 * Get the page directory entry
1643 pde = pmap_pde(pmap, va, &lvl);
1646 * If the page table page is mapped, we just increment the hold count,
1647 * and activate it. If we get a level 2 pde it will point to a level 3
1655 pte = pmap_l0_to_l1(pde, va);
1656 KASSERT(pmap_load(pte) == 0,
1657 ("pmap_alloc_l3: TODO: l0 superpages"));
1662 pte = pmap_l1_to_l2(pde, va);
1663 KASSERT(pmap_load(pte) == 0,
1664 ("pmap_alloc_l3: TODO: l1 superpages"));
1668 tpde = pmap_load(pde);
1670 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1676 panic("pmap_alloc_l3: Invalid level %d", lvl);
1680 * Here if the pte page isn't mapped, or if it has been deallocated.
1682 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1683 if (m == NULL && lockp != NULL)
1689 /***************************************************
1690 * Pmap allocation/deallocation routines.
1691 ***************************************************/
1694 * Release any resources held by the given physical map.
1695 * Called when a pmap initialized by pmap_pinit is being released.
1696 * Should only be called if the map contains no valid mappings.
1699 pmap_release(pmap_t pmap)
1703 KASSERT(pmap->pm_stats.resident_count == 0,
1704 ("pmap_release: pmap resident count %ld != 0",
1705 pmap->pm_stats.resident_count));
1706 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1707 ("pmap_release: pmap has reserved page table page(s)"));
1709 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1711 vm_page_unwire_noq(m);
1712 vm_page_free_zero(m);
1716 kvm_size(SYSCTL_HANDLER_ARGS)
1718 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1720 return sysctl_handle_long(oidp, &ksize, 0, req);
1722 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1723 0, 0, kvm_size, "LU", "Size of KVM");
1726 kvm_free(SYSCTL_HANDLER_ARGS)
1728 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1730 return sysctl_handle_long(oidp, &kfree, 0, req);
1732 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1733 0, 0, kvm_free, "LU", "Amount of KVM free");
1736 * grow the number of kernel page table entries, if needed
1739 pmap_growkernel(vm_offset_t addr)
1743 pd_entry_t *l0, *l1, *l2;
1745 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1747 addr = roundup2(addr, L2_SIZE);
1748 if (addr - 1 >= kernel_map->max_offset)
1749 addr = kernel_map->max_offset;
1750 while (kernel_vm_end < addr) {
1751 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1752 KASSERT(pmap_load(l0) != 0,
1753 ("pmap_growkernel: No level 0 kernel entry"));
1755 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1756 if (pmap_load(l1) == 0) {
1757 /* We need a new PDP entry */
1758 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1759 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1760 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1762 panic("pmap_growkernel: no memory to grow kernel");
1763 if ((nkpg->flags & PG_ZERO) == 0)
1764 pmap_zero_page(nkpg);
1765 paddr = VM_PAGE_TO_PHYS(nkpg);
1766 pmap_load_store(l1, paddr | L1_TABLE);
1767 continue; /* try again */
1769 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1770 if ((pmap_load(l2) & ATTR_AF) != 0) {
1771 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1772 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1773 kernel_vm_end = kernel_map->max_offset;
1779 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1780 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1783 panic("pmap_growkernel: no memory to grow kernel");
1784 if ((nkpg->flags & PG_ZERO) == 0)
1785 pmap_zero_page(nkpg);
1786 paddr = VM_PAGE_TO_PHYS(nkpg);
1787 pmap_load_store(l2, paddr | L2_TABLE);
1788 pmap_invalidate_page(kernel_pmap, kernel_vm_end);
1790 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1791 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1792 kernel_vm_end = kernel_map->max_offset;
1799 /***************************************************
1800 * page management routines.
1801 ***************************************************/
1803 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1804 CTASSERT(_NPCM == 3);
1805 CTASSERT(_NPCPV == 168);
1807 static __inline struct pv_chunk *
1808 pv_to_chunk(pv_entry_t pv)
1811 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1814 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1816 #define PC_FREE0 0xfffffffffffffffful
1817 #define PC_FREE1 0xfffffffffffffffful
1818 #define PC_FREE2 0x000000fffffffffful
1820 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1824 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1826 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1827 "Current number of pv entry chunks");
1828 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1829 "Current number of pv entry chunks allocated");
1830 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1831 "Current number of pv entry chunks frees");
1832 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1833 "Number of times tried to get a chunk page but failed.");
1835 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1836 static int pv_entry_spare;
1838 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1839 "Current number of pv entry frees");
1840 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1841 "Current number of pv entry allocs");
1842 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1843 "Current number of pv entries");
1844 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1845 "Current number of spare pv entries");
1850 * We are in a serious low memory condition. Resort to
1851 * drastic measures to free some pages so we can allocate
1852 * another pv entry chunk.
1854 * Returns NULL if PV entries were reclaimed from the specified pmap.
1856 * We do not, however, unmap 2mpages because subsequent accesses will
1857 * allocate per-page pv entries until repromotion occurs, thereby
1858 * exacerbating the shortage of free pv entries.
1861 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1863 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
1864 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
1865 struct md_page *pvh;
1867 pmap_t next_pmap, pmap;
1868 pt_entry_t *pte, tpte;
1872 struct spglist free;
1874 int bit, field, freed, lvl;
1875 static int active_reclaims = 0;
1877 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1878 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
1883 bzero(&pc_marker_b, sizeof(pc_marker_b));
1884 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
1885 pc_marker = (struct pv_chunk *)&pc_marker_b;
1886 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
1888 mtx_lock(&pv_chunks_mutex);
1890 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
1891 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
1892 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
1893 SLIST_EMPTY(&free)) {
1894 next_pmap = pc->pc_pmap;
1895 if (next_pmap == NULL) {
1897 * The next chunk is a marker. However, it is
1898 * not our marker, so active_reclaims must be
1899 * > 1. Consequently, the next_chunk code
1900 * will not rotate the pv_chunks list.
1904 mtx_unlock(&pv_chunks_mutex);
1907 * A pv_chunk can only be removed from the pc_lru list
1908 * when both pv_chunks_mutex is owned and the
1909 * corresponding pmap is locked.
1911 if (pmap != next_pmap) {
1912 if (pmap != NULL && pmap != locked_pmap)
1915 /* Avoid deadlock and lock recursion. */
1916 if (pmap > locked_pmap) {
1917 RELEASE_PV_LIST_LOCK(lockp);
1919 mtx_lock(&pv_chunks_mutex);
1921 } else if (pmap != locked_pmap) {
1922 if (PMAP_TRYLOCK(pmap)) {
1923 mtx_lock(&pv_chunks_mutex);
1926 pmap = NULL; /* pmap is not locked */
1927 mtx_lock(&pv_chunks_mutex);
1928 pc = TAILQ_NEXT(pc_marker, pc_lru);
1930 pc->pc_pmap != next_pmap)
1938 * Destroy every non-wired, 4 KB page mapping in the chunk.
1941 for (field = 0; field < _NPCM; field++) {
1942 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1943 inuse != 0; inuse &= ~(1UL << bit)) {
1944 bit = ffsl(inuse) - 1;
1945 pv = &pc->pc_pventry[field * 64 + bit];
1947 pde = pmap_pde(pmap, va, &lvl);
1950 pte = pmap_l2_to_l3(pde, va);
1951 tpte = pmap_load(pte);
1952 if ((tpte & ATTR_SW_WIRED) != 0)
1954 tpte = pmap_load_clear(pte);
1955 pmap_invalidate_page(pmap, va);
1956 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
1957 if (pmap_page_dirty(tpte))
1959 if ((tpte & ATTR_AF) != 0)
1960 vm_page_aflag_set(m, PGA_REFERENCED);
1961 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1962 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
1964 if (TAILQ_EMPTY(&m->md.pv_list) &&
1965 (m->flags & PG_FICTITIOUS) == 0) {
1966 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
1967 if (TAILQ_EMPTY(&pvh->pv_list)) {
1968 vm_page_aflag_clear(m,
1972 pc->pc_map[field] |= 1UL << bit;
1973 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
1978 mtx_lock(&pv_chunks_mutex);
1981 /* Every freed mapping is for a 4 KB page. */
1982 pmap_resident_count_dec(pmap, freed);
1983 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
1984 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
1985 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
1986 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1987 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
1988 pc->pc_map[2] == PC_FREE2) {
1989 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1990 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1991 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1992 /* Entire chunk is free; return it. */
1993 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1994 dump_drop_page(m_pc->phys_addr);
1995 mtx_lock(&pv_chunks_mutex);
1996 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1999 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2000 mtx_lock(&pv_chunks_mutex);
2001 /* One freed pv entry in locked_pmap is sufficient. */
2002 if (pmap == locked_pmap)
2006 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2007 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2008 if (active_reclaims == 1 && pmap != NULL) {
2010 * Rotate the pv chunks list so that we do not
2011 * scan the same pv chunks that could not be
2012 * freed (because they contained a wired
2013 * and/or superpage mapping) on every
2014 * invocation of reclaim_pv_chunk().
2016 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2017 MPASS(pc->pc_pmap != NULL);
2018 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2019 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2023 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2024 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2026 mtx_unlock(&pv_chunks_mutex);
2027 if (pmap != NULL && pmap != locked_pmap)
2029 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2030 m_pc = SLIST_FIRST(&free);
2031 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2032 /* Recycle a freed page table page. */
2033 m_pc->wire_count = 1;
2036 vm_page_free_pages_toq(&free, false);
2041 * free the pv_entry back to the free list
2044 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2046 struct pv_chunk *pc;
2047 int idx, field, bit;
2049 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2050 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2051 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2052 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2053 pc = pv_to_chunk(pv);
2054 idx = pv - &pc->pc_pventry[0];
2057 pc->pc_map[field] |= 1ul << bit;
2058 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2059 pc->pc_map[2] != PC_FREE2) {
2060 /* 98% of the time, pc is already at the head of the list. */
2061 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2062 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2063 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2067 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2072 free_pv_chunk(struct pv_chunk *pc)
2076 mtx_lock(&pv_chunks_mutex);
2077 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2078 mtx_unlock(&pv_chunks_mutex);
2079 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2080 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2081 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2082 /* entire chunk is free, return it */
2083 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2084 dump_drop_page(m->phys_addr);
2085 vm_page_unwire_noq(m);
2090 * Returns a new PV entry, allocating a new PV chunk from the system when
2091 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2092 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2095 * The given PV list lock may be released.
2098 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2102 struct pv_chunk *pc;
2105 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2106 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2108 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2110 for (field = 0; field < _NPCM; field++) {
2111 if (pc->pc_map[field]) {
2112 bit = ffsl(pc->pc_map[field]) - 1;
2116 if (field < _NPCM) {
2117 pv = &pc->pc_pventry[field * 64 + bit];
2118 pc->pc_map[field] &= ~(1ul << bit);
2119 /* If this was the last item, move it to tail */
2120 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2121 pc->pc_map[2] == 0) {
2122 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2123 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2126 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2127 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2131 /* No free items, allocate another chunk */
2132 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2135 if (lockp == NULL) {
2136 PV_STAT(pc_chunk_tryfail++);
2139 m = reclaim_pv_chunk(pmap, lockp);
2143 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2144 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2145 dump_add_page(m->phys_addr);
2146 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2148 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2149 pc->pc_map[1] = PC_FREE1;
2150 pc->pc_map[2] = PC_FREE2;
2151 mtx_lock(&pv_chunks_mutex);
2152 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2153 mtx_unlock(&pv_chunks_mutex);
2154 pv = &pc->pc_pventry[0];
2155 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2156 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2157 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2162 * Ensure that the number of spare PV entries in the specified pmap meets or
2163 * exceeds the given count, "needed".
2165 * The given PV list lock may be released.
2168 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2170 struct pch new_tail;
2171 struct pv_chunk *pc;
2176 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2177 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2180 * Newly allocated PV chunks must be stored in a private list until
2181 * the required number of PV chunks have been allocated. Otherwise,
2182 * reclaim_pv_chunk() could recycle one of these chunks. In
2183 * contrast, these chunks must be added to the pmap upon allocation.
2185 TAILQ_INIT(&new_tail);
2188 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2189 bit_count((bitstr_t *)pc->pc_map, 0,
2190 sizeof(pc->pc_map) * NBBY, &free);
2194 if (avail >= needed)
2197 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2198 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2201 m = reclaim_pv_chunk(pmap, lockp);
2206 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2207 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2208 dump_add_page(m->phys_addr);
2209 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2211 pc->pc_map[0] = PC_FREE0;
2212 pc->pc_map[1] = PC_FREE1;
2213 pc->pc_map[2] = PC_FREE2;
2214 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2215 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2216 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2219 * The reclaim might have freed a chunk from the current pmap.
2220 * If that chunk contained available entries, we need to
2221 * re-count the number of available entries.
2226 if (!TAILQ_EMPTY(&new_tail)) {
2227 mtx_lock(&pv_chunks_mutex);
2228 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2229 mtx_unlock(&pv_chunks_mutex);
2234 * First find and then remove the pv entry for the specified pmap and virtual
2235 * address from the specified pv list. Returns the pv entry if found and NULL
2236 * otherwise. This operation can be performed on pv lists for either 4KB or
2237 * 2MB page mappings.
2239 static __inline pv_entry_t
2240 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2244 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2245 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2246 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2255 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2256 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2257 * entries for each of the 4KB page mappings.
2260 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2261 struct rwlock **lockp)
2263 struct md_page *pvh;
2264 struct pv_chunk *pc;
2266 vm_offset_t va_last;
2270 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2271 KASSERT((pa & L2_OFFSET) == 0,
2272 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2273 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2276 * Transfer the 2mpage's pv entry for this mapping to the first
2277 * page's pv list. Once this transfer begins, the pv list lock
2278 * must not be released until the last pv entry is reinstantiated.
2280 pvh = pa_to_pvh(pa);
2281 va = va & ~L2_OFFSET;
2282 pv = pmap_pvh_remove(pvh, pmap, va);
2283 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2284 m = PHYS_TO_VM_PAGE(pa);
2285 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2287 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2288 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2289 va_last = va + L2_SIZE - PAGE_SIZE;
2291 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2292 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2293 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2294 for (field = 0; field < _NPCM; field++) {
2295 while (pc->pc_map[field]) {
2296 bit = ffsl(pc->pc_map[field]) - 1;
2297 pc->pc_map[field] &= ~(1ul << bit);
2298 pv = &pc->pc_pventry[field * 64 + bit];
2302 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2303 ("pmap_pv_demote_l2: page %p is not managed", m));
2304 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2310 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2311 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2314 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2315 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2316 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2318 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2319 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2323 * First find and then destroy the pv entry for the specified pmap and virtual
2324 * address. This operation can be performed on pv lists for either 4KB or 2MB
2328 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2332 pv = pmap_pvh_remove(pvh, pmap, va);
2333 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2334 free_pv_entry(pmap, pv);
2338 * Conditionally create the PV entry for a 4KB page mapping if the required
2339 * memory can be allocated without resorting to reclamation.
2342 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2343 struct rwlock **lockp)
2347 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2348 /* Pass NULL instead of the lock pointer to disable reclamation. */
2349 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2351 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2352 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2360 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2361 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2362 * false if the PV entry cannot be allocated without resorting to reclamation.
2365 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2366 struct rwlock **lockp)
2368 struct md_page *pvh;
2372 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2373 /* Pass NULL instead of the lock pointer to disable reclamation. */
2374 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2375 NULL : lockp)) == NULL)
2378 pa = l2e & ~ATTR_MASK;
2379 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2380 pvh = pa_to_pvh(pa);
2381 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2387 * pmap_remove_l2: do the things to unmap a level 2 superpage in a process
2390 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2391 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2393 struct md_page *pvh;
2395 vm_offset_t eva, va;
2398 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2399 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2400 old_l2 = pmap_load_clear(l2);
2401 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2402 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2403 pmap_invalidate_range(pmap, sva, sva + L2_SIZE);
2404 if (old_l2 & ATTR_SW_WIRED)
2405 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2406 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2407 if (old_l2 & ATTR_SW_MANAGED) {
2408 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2409 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2410 pmap_pvh_free(pvh, pmap, sva);
2411 eva = sva + L2_SIZE;
2412 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2413 va < eva; va += PAGE_SIZE, m++) {
2414 if (pmap_page_dirty(old_l2))
2416 if (old_l2 & ATTR_AF)
2417 vm_page_aflag_set(m, PGA_REFERENCED);
2418 if (TAILQ_EMPTY(&m->md.pv_list) &&
2419 TAILQ_EMPTY(&pvh->pv_list))
2420 vm_page_aflag_clear(m, PGA_WRITEABLE);
2423 KASSERT(pmap != kernel_pmap,
2424 ("Attempting to remove an l2 kernel page"));
2425 ml3 = pmap_remove_pt_page(pmap, sva);
2427 pmap_resident_count_dec(pmap, 1);
2428 KASSERT(ml3->wire_count == NL3PG,
2429 ("pmap_remove_l2: l3 page wire count error"));
2430 ml3->wire_count = 1;
2431 vm_page_unwire_noq(ml3);
2432 pmap_add_delayed_free_list(ml3, free, FALSE);
2434 return (pmap_unuse_pt(pmap, sva, l1e, free));
2438 * pmap_remove_l3: do the things to unmap a page in a process
2441 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2442 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2444 struct md_page *pvh;
2448 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2449 old_l3 = pmap_load_clear(l3);
2450 pmap_invalidate_page(pmap, va);
2451 if (old_l3 & ATTR_SW_WIRED)
2452 pmap->pm_stats.wired_count -= 1;
2453 pmap_resident_count_dec(pmap, 1);
2454 if (old_l3 & ATTR_SW_MANAGED) {
2455 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2456 if (pmap_page_dirty(old_l3))
2458 if (old_l3 & ATTR_AF)
2459 vm_page_aflag_set(m, PGA_REFERENCED);
2460 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2461 pmap_pvh_free(&m->md, pmap, va);
2462 if (TAILQ_EMPTY(&m->md.pv_list) &&
2463 (m->flags & PG_FICTITIOUS) == 0) {
2464 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2465 if (TAILQ_EMPTY(&pvh->pv_list))
2466 vm_page_aflag_clear(m, PGA_WRITEABLE);
2469 return (pmap_unuse_pt(pmap, va, l2e, free));
2473 * Remove the given range of addresses from the specified map.
2475 * It is assumed that the start and end are properly
2476 * rounded to the page size.
2479 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2481 struct rwlock *lock;
2482 vm_offset_t va, va_next;
2483 pd_entry_t *l0, *l1, *l2;
2484 pt_entry_t l3_paddr, *l3;
2485 struct spglist free;
2488 * Perform an unsynchronized read. This is, however, safe.
2490 if (pmap->pm_stats.resident_count == 0)
2498 for (; sva < eva; sva = va_next) {
2500 if (pmap->pm_stats.resident_count == 0)
2503 l0 = pmap_l0(pmap, sva);
2504 if (pmap_load(l0) == 0) {
2505 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2511 l1 = pmap_l0_to_l1(l0, sva);
2512 if (pmap_load(l1) == 0) {
2513 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2520 * Calculate index for next page table.
2522 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2526 l2 = pmap_l1_to_l2(l1, sva);
2530 l3_paddr = pmap_load(l2);
2532 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2533 if (sva + L2_SIZE == va_next && eva >= va_next) {
2534 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2537 } else if (pmap_demote_l2_locked(pmap, l2,
2538 sva &~L2_OFFSET, &lock) == NULL)
2540 l3_paddr = pmap_load(l2);
2544 * Weed out invalid mappings.
2546 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2550 * Limit our scan to either the end of the va represented
2551 * by the current page table page, or to the end of the
2552 * range being removed.
2558 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2561 panic("l3 == NULL");
2562 if (pmap_load(l3) == 0) {
2563 if (va != va_next) {
2564 pmap_invalidate_range(pmap, va, sva);
2571 if (pmap_remove_l3(pmap, l3, sva, l3_paddr, &free,
2578 pmap_invalidate_range(pmap, va, sva);
2583 vm_page_free_pages_toq(&free, false);
2587 * Routine: pmap_remove_all
2589 * Removes this physical page from
2590 * all physical maps in which it resides.
2591 * Reflects back modify bits to the pager.
2594 * Original versions of this routine were very
2595 * inefficient because they iteratively called
2596 * pmap_remove (slow...)
2600 pmap_remove_all(vm_page_t m)
2602 struct md_page *pvh;
2605 struct rwlock *lock;
2606 pd_entry_t *pde, tpde;
2607 pt_entry_t *pte, tpte;
2609 struct spglist free;
2610 int lvl, pvh_gen, md_gen;
2612 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2613 ("pmap_remove_all: page %p is not managed", m));
2615 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2616 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2617 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2620 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2622 if (!PMAP_TRYLOCK(pmap)) {
2623 pvh_gen = pvh->pv_gen;
2627 if (pvh_gen != pvh->pv_gen) {
2634 pte = pmap_pte(pmap, va, &lvl);
2635 KASSERT(pte != NULL,
2636 ("pmap_remove_all: no page table entry found"));
2638 ("pmap_remove_all: invalid pte level %d", lvl));
2640 pmap_demote_l2_locked(pmap, pte, va, &lock);
2643 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2645 if (!PMAP_TRYLOCK(pmap)) {
2646 pvh_gen = pvh->pv_gen;
2647 md_gen = m->md.pv_gen;
2651 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2657 pmap_resident_count_dec(pmap, 1);
2659 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2660 KASSERT(pde != NULL,
2661 ("pmap_remove_all: no page directory entry found"));
2663 ("pmap_remove_all: invalid pde level %d", lvl));
2664 tpde = pmap_load(pde);
2666 pte = pmap_l2_to_l3(pde, pv->pv_va);
2667 tpte = pmap_load(pte);
2668 pmap_load_clear(pte);
2669 pmap_invalidate_page(pmap, pv->pv_va);
2670 if (tpte & ATTR_SW_WIRED)
2671 pmap->pm_stats.wired_count--;
2672 if ((tpte & ATTR_AF) != 0)
2673 vm_page_aflag_set(m, PGA_REFERENCED);
2676 * Update the vm_page_t clean and reference bits.
2678 if (pmap_page_dirty(tpte))
2680 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2681 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2683 free_pv_entry(pmap, pv);
2686 vm_page_aflag_clear(m, PGA_WRITEABLE);
2688 vm_page_free_pages_toq(&free, false);
2692 * Set the physical protection on the
2693 * specified range of this map as requested.
2696 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2698 vm_offset_t va, va_next;
2699 pd_entry_t *l0, *l1, *l2;
2700 pt_entry_t *l3p, l3, nbits;
2702 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
2703 if (prot == VM_PROT_NONE) {
2704 pmap_remove(pmap, sva, eva);
2708 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
2709 (VM_PROT_WRITE | VM_PROT_EXECUTE))
2713 for (; sva < eva; sva = va_next) {
2715 l0 = pmap_l0(pmap, sva);
2716 if (pmap_load(l0) == 0) {
2717 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2723 l1 = pmap_l0_to_l1(l0, sva);
2724 if (pmap_load(l1) == 0) {
2725 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2731 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2735 l2 = pmap_l1_to_l2(l1, sva);
2736 if (pmap_load(l2) == 0)
2739 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
2740 l3p = pmap_demote_l2(pmap, l2, sva);
2744 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
2745 ("pmap_protect: Invalid L2 entry after demotion"));
2751 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2753 l3 = pmap_load(l3p);
2754 if (!pmap_l3_valid(l3))
2758 if ((prot & VM_PROT_WRITE) == 0) {
2759 if ((l3 & ATTR_SW_MANAGED) &&
2760 pmap_page_dirty(l3)) {
2761 vm_page_dirty(PHYS_TO_VM_PAGE(l3 &
2764 nbits |= ATTR_AP(ATTR_AP_RO);
2766 if ((prot & VM_PROT_EXECUTE) == 0)
2769 pmap_set(l3p, nbits);
2770 /* XXX: Use pmap_invalidate_range */
2771 pmap_invalidate_page(pmap, sva);
2778 * Inserts the specified page table page into the specified pmap's collection
2779 * of idle page table pages. Each of a pmap's page table pages is responsible
2780 * for mapping a distinct range of virtual addresses. The pmap's collection is
2781 * ordered by this virtual address range.
2784 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2787 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2788 return (vm_radix_insert(&pmap->pm_root, mpte));
2792 * Removes the page table page mapping the specified virtual address from the
2793 * specified pmap's collection of idle page table pages, and returns it.
2794 * Otherwise, returns NULL if there is no page table page corresponding to the
2795 * specified virtual address.
2797 static __inline vm_page_t
2798 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2801 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2802 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
2806 * Performs a break-before-make update of a pmap entry. This is needed when
2807 * either promoting or demoting pages to ensure the TLB doesn't get into an
2808 * inconsistent state.
2811 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
2812 vm_offset_t va, vm_size_t size)
2816 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2819 * Ensure we don't get switched out with the page table in an
2820 * inconsistent state. We also need to ensure no interrupts fire
2821 * as they may make use of an address we are about to invalidate.
2823 intr = intr_disable();
2826 /* Clear the old mapping */
2827 pmap_load_clear(pte);
2828 pmap_invalidate_range_nopin(pmap, va, va + size);
2830 /* Create the new mapping */
2831 pmap_load_store(pte, newpte);
2837 #if VM_NRESERVLEVEL > 0
2839 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
2840 * replace the many pv entries for the 4KB page mappings by a single pv entry
2841 * for the 2MB page mapping.
2844 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2845 struct rwlock **lockp)
2847 struct md_page *pvh;
2849 vm_offset_t va_last;
2852 KASSERT((pa & L2_OFFSET) == 0,
2853 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
2854 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2857 * Transfer the first page's pv entry for this mapping to the 2mpage's
2858 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
2859 * a transfer avoids the possibility that get_pv_entry() calls
2860 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
2861 * mappings that is being promoted.
2863 m = PHYS_TO_VM_PAGE(pa);
2864 va = va & ~L2_OFFSET;
2865 pv = pmap_pvh_remove(&m->md, pmap, va);
2866 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
2867 pvh = pa_to_pvh(pa);
2868 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2870 /* Free the remaining NPTEPG - 1 pv entries. */
2871 va_last = va + L2_SIZE - PAGE_SIZE;
2875 pmap_pvh_free(&m->md, pmap, va);
2876 } while (va < va_last);
2880 * Tries to promote the 512, contiguous 4KB page mappings that are within a
2881 * single level 2 table entry to a single 2MB page mapping. For promotion
2882 * to occur, two conditions must be met: (1) the 4KB page mappings must map
2883 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
2884 * identical characteristics.
2887 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
2888 struct rwlock **lockp)
2890 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
2894 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2896 sva = va & ~L2_OFFSET;
2897 firstl3 = pmap_l2_to_l3(l2, sva);
2898 newl2 = pmap_load(firstl3);
2900 /* Check the alingment is valid */
2901 if (((newl2 & ~ATTR_MASK) & L2_OFFSET) != 0) {
2902 atomic_add_long(&pmap_l2_p_failures, 1);
2903 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2904 " in pmap %p", va, pmap);
2908 pa = newl2 + L2_SIZE - PAGE_SIZE;
2909 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
2910 oldl3 = pmap_load(l3);
2912 atomic_add_long(&pmap_l2_p_failures, 1);
2913 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2914 " in pmap %p", va, pmap);
2921 * Save the page table page in its current state until the L2
2922 * mapping the superpage is demoted by pmap_demote_l2() or
2923 * destroyed by pmap_remove_l3().
2925 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
2926 KASSERT(mpte >= vm_page_array &&
2927 mpte < &vm_page_array[vm_page_array_size],
2928 ("pmap_promote_l2: page table page is out of range"));
2929 KASSERT(mpte->pindex == pmap_l2_pindex(va),
2930 ("pmap_promote_l2: page table page's pindex is wrong"));
2931 if (pmap_insert_pt_page(pmap, mpte)) {
2932 atomic_add_long(&pmap_l2_p_failures, 1);
2934 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
2939 if ((newl2 & ATTR_SW_MANAGED) != 0)
2940 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
2942 newl2 &= ~ATTR_DESCR_MASK;
2945 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
2947 atomic_add_long(&pmap_l2_promotions, 1);
2948 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
2951 #endif /* VM_NRESERVLEVEL > 0 */
2954 * Insert the given physical page (p) at
2955 * the specified virtual address (v) in the
2956 * target physical map with the protection requested.
2958 * If specified, the page will be wired down, meaning
2959 * that the related pte can not be reclaimed.
2961 * NB: This is the only routine which MAY NOT lazy-evaluate
2962 * or lose information. That is, this routine must actually
2963 * insert this page into the given map NOW.
2966 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2967 u_int flags, int8_t psind)
2969 struct rwlock *lock;
2971 pt_entry_t new_l3, orig_l3;
2972 pt_entry_t *l2, *l3;
2974 vm_paddr_t opa, pa, l1_pa, l2_pa, l3_pa;
2975 vm_page_t mpte, om, l1_m, l2_m, l3_m;
2979 va = trunc_page(va);
2980 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2981 VM_OBJECT_ASSERT_LOCKED(m->object);
2982 pa = VM_PAGE_TO_PHYS(m);
2983 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
2985 if ((prot & VM_PROT_WRITE) == 0)
2986 new_l3 |= ATTR_AP(ATTR_AP_RO);
2987 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
2989 if ((flags & PMAP_ENTER_WIRED) != 0)
2990 new_l3 |= ATTR_SW_WIRED;
2991 if (va < VM_MAXUSER_ADDRESS)
2992 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
2993 if ((m->oflags & VPO_UNMANAGED) == 0)
2994 new_l3 |= ATTR_SW_MANAGED;
2996 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3002 /* Assert the required virtual and physical alignment. */
3003 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3004 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3005 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3010 pde = pmap_pde(pmap, va, &lvl);
3011 if (pde != NULL && lvl == 1) {
3012 l2 = pmap_l1_to_l2(pde, va);
3013 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3014 (l3 = pmap_demote_l2_locked(pmap, l2, va & ~L2_OFFSET,
3016 l3 = &l3[pmap_l3_index(va)];
3017 if (va < VM_MAXUSER_ADDRESS) {
3018 mpte = PHYS_TO_VM_PAGE(
3019 pmap_load(l2) & ~ATTR_MASK);
3026 if (va < VM_MAXUSER_ADDRESS) {
3027 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
3028 mpte = pmap_alloc_l3(pmap, va, nosleep ? NULL : &lock);
3029 if (mpte == NULL && nosleep) {
3030 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3034 return (KERN_RESOURCE_SHORTAGE);
3036 pde = pmap_pde(pmap, va, &lvl);
3037 KASSERT(pde != NULL,
3038 ("pmap_enter: Invalid page entry, va: 0x%lx", va));
3040 ("pmap_enter: Invalid level %d", lvl));
3043 * If we get a level 2 pde it must point to a level 3 entry
3044 * otherwise we will need to create the intermediate tables
3050 /* Get the l0 pde to update */
3051 pde = pmap_l0(pmap, va);
3052 KASSERT(pde != NULL, ("..."));
3054 l1_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3055 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3058 panic("pmap_enter: l1 pte_m == NULL");
3059 if ((l1_m->flags & PG_ZERO) == 0)
3060 pmap_zero_page(l1_m);
3062 l1_pa = VM_PAGE_TO_PHYS(l1_m);
3063 pmap_load_store(pde, l1_pa | L0_TABLE);
3066 /* Get the l1 pde to update */
3067 pde = pmap_l1_to_l2(pde, va);
3068 KASSERT(pde != NULL, ("..."));
3070 l2_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3071 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3074 panic("pmap_enter: l2 pte_m == NULL");
3075 if ((l2_m->flags & PG_ZERO) == 0)
3076 pmap_zero_page(l2_m);
3078 l2_pa = VM_PAGE_TO_PHYS(l2_m);
3079 pmap_load_store(pde, l2_pa | L1_TABLE);
3082 /* Get the l2 pde to update */
3083 pde = pmap_l1_to_l2(pde, va);
3084 KASSERT(pde != NULL, ("..."));
3086 l3_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3087 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3090 panic("pmap_enter: l3 pte_m == NULL");
3091 if ((l3_m->flags & PG_ZERO) == 0)
3092 pmap_zero_page(l3_m);
3094 l3_pa = VM_PAGE_TO_PHYS(l3_m);
3095 pmap_load_store(pde, l3_pa | L2_TABLE);
3100 l3 = pmap_l2_to_l3(pde, va);
3103 orig_l3 = pmap_load(l3);
3104 opa = orig_l3 & ~ATTR_MASK;
3108 * Is the specified virtual address already mapped?
3110 if (pmap_l3_valid(orig_l3)) {
3112 * Wiring change, just update stats. We don't worry about
3113 * wiring PT pages as they remain resident as long as there
3114 * are valid mappings in them. Hence, if a user page is wired,
3115 * the PT page will be also.
3117 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3118 (orig_l3 & ATTR_SW_WIRED) == 0)
3119 pmap->pm_stats.wired_count++;
3120 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3121 (orig_l3 & ATTR_SW_WIRED) != 0)
3122 pmap->pm_stats.wired_count--;
3125 * Remove the extra PT page reference.
3129 KASSERT(mpte->wire_count > 0,
3130 ("pmap_enter: missing reference to page table page,"
3135 * Has the physical page changed?
3139 * No, might be a protection or wiring change.
3141 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3142 if ((new_l3 & ATTR_AP(ATTR_AP_RW)) ==
3143 ATTR_AP(ATTR_AP_RW)) {
3144 vm_page_aflag_set(m, PGA_WRITEABLE);
3151 * The physical page has changed.
3153 (void)pmap_load_clear(l3);
3154 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
3155 ("pmap_enter: unexpected pa update for %#lx", va));
3156 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3157 om = PHYS_TO_VM_PAGE(opa);
3160 * The pmap lock is sufficient to synchronize with
3161 * concurrent calls to pmap_page_test_mappings() and
3162 * pmap_ts_referenced().
3164 if (pmap_page_dirty(orig_l3))
3166 if ((orig_l3 & ATTR_AF) != 0)
3167 vm_page_aflag_set(om, PGA_REFERENCED);
3168 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3169 pv = pmap_pvh_remove(&om->md, pmap, va);
3170 if ((m->oflags & VPO_UNMANAGED) != 0)
3171 free_pv_entry(pmap, pv);
3172 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3173 TAILQ_EMPTY(&om->md.pv_list) &&
3174 ((om->flags & PG_FICTITIOUS) != 0 ||
3175 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3176 vm_page_aflag_clear(om, PGA_WRITEABLE);
3178 pmap_invalidate_page(pmap, va);
3182 * Increment the counters.
3184 if ((new_l3 & ATTR_SW_WIRED) != 0)
3185 pmap->pm_stats.wired_count++;
3186 pmap_resident_count_inc(pmap, 1);
3189 * Enter on the PV list if part of our managed memory.
3191 if ((m->oflags & VPO_UNMANAGED) == 0) {
3193 pv = get_pv_entry(pmap, &lock);
3196 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3197 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3199 if ((new_l3 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3200 vm_page_aflag_set(m, PGA_WRITEABLE);
3205 * Sync icache if exec permission and attribute VM_MEMATTR_WRITE_BACK
3206 * is set. Do it now, before the mapping is stored and made
3207 * valid for hardware table walk. If done later, then other can
3208 * access this page before caches are properly synced.
3209 * Don't do it for kernel memory which is mapped with exec
3210 * permission even if the memory isn't going to hold executable
3211 * code. The only time when icache sync is needed is after
3212 * kernel module is loaded and the relocation info is processed.
3213 * And it's done in elf_cpu_load_file().
3215 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3216 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3217 (opa != pa || (orig_l3 & ATTR_XN)))
3218 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3221 * Update the L3 entry
3223 if (pmap_l3_valid(orig_l3)) {
3224 KASSERT(opa == pa, ("pmap_enter: invalid update"));
3225 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3226 /* same PA, different attributes */
3227 pmap_load_store(l3, new_l3);
3228 pmap_invalidate_page(pmap, va);
3229 if (pmap_page_dirty(orig_l3) &&
3230 (orig_l3 & ATTR_SW_MANAGED) != 0)
3235 * This can happens if multiple threads simultaneously
3236 * access not yet mapped page. This bad for performance
3237 * since this can cause full demotion-NOP-promotion
3239 * Another possible reasons are:
3240 * - VM and pmap memory layout are diverged
3241 * - tlb flush is missing somewhere and CPU doesn't see
3244 CTR4(KTR_PMAP, "%s: already mapped page - "
3245 "pmap %p va 0x%#lx pte 0x%lx",
3246 __func__, pmap, va, new_l3);
3250 pmap_load_store(l3, new_l3);
3253 #if VM_NRESERVLEVEL > 0
3254 if (pmap != pmap_kernel() &&
3255 (mpte == NULL || mpte->wire_count == NL3PG) &&
3256 pmap_ps_enabled(pmap) &&
3257 (m->flags & PG_FICTITIOUS) == 0 &&
3258 vm_reserv_level_iffullpop(m) == 0) {
3259 pmap_promote_l2(pmap, pde, va, &lock);
3272 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
3273 * if successful. Returns false if (1) a page table page cannot be allocated
3274 * without sleeping, (2) a mapping already exists at the specified virtual
3275 * address, or (3) a PV entry cannot be allocated without reclaiming another
3279 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3280 struct rwlock **lockp)
3284 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3286 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
3287 ATTR_IDX(m->md.pv_memattr) | ATTR_AP(ATTR_AP_RO) | L2_BLOCK);
3288 if ((m->oflags & VPO_UNMANAGED) == 0)
3289 new_l2 |= ATTR_SW_MANAGED;
3290 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3292 if (va < VM_MAXUSER_ADDRESS)
3293 new_l2 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3294 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
3295 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
3300 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
3301 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
3302 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
3303 * a mapping already exists at the specified virtual address. Returns
3304 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
3305 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
3306 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3308 * The parameter "m" is only used when creating a managed, writeable mapping.
3311 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
3312 vm_page_t m, struct rwlock **lockp)
3314 struct spglist free;
3315 pd_entry_t *l2, *l3, old_l2;
3319 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3321 if ((l2pg = pmap_alloc_l2(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
3322 NULL : lockp)) == NULL) {
3323 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
3325 return (KERN_RESOURCE_SHORTAGE);
3328 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
3329 l2 = &l2[pmap_l2_index(va)];
3330 if ((old_l2 = pmap_load(l2)) != 0) {
3331 KASSERT(l2pg->wire_count > 1,
3332 ("pmap_enter_l2: l2pg's wire count is too low"));
3333 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3336 "pmap_enter_l2: failure for va %#lx in pmap %p",
3338 return (KERN_FAILURE);
3341 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
3342 (void)pmap_remove_l2(pmap, l2, va,
3343 pmap_load(pmap_l1(pmap, va)), &free, lockp);
3345 for (sva = va; sva < va + L2_SIZE; sva += PAGE_SIZE) {
3346 l3 = pmap_l2_to_l3(l2, sva);
3347 if (pmap_l3_valid(pmap_load(l3)) &&
3348 pmap_remove_l3(pmap, l3, sva, old_l2, &free,
3352 vm_page_free_pages_toq(&free, true);
3353 if (va >= VM_MAXUSER_ADDRESS) {
3354 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3355 if (pmap_insert_pt_page(pmap, mt)) {
3357 * XXX Currently, this can't happen bacuse
3358 * we do not perform pmap_enter(psind == 1)
3359 * on the kernel pmap.
3361 panic("pmap_enter_l2: trie insert failed");
3364 KASSERT(pmap_load(l2) == 0,
3365 ("pmap_enter_l2: non-zero L2 entry %p", l2));
3368 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
3370 * Abort this mapping if its PV entry could not be created.
3372 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
3374 if (pmap_unwire_l3(pmap, va, l2pg, &free)) {
3376 * Although "va" is not mapped, paging-structure
3377 * caches could nonetheless have entries that
3378 * refer to the freed page table pages.
3379 * Invalidate those entries.
3381 pmap_invalidate_page(pmap, va);
3382 vm_page_free_pages_toq(&free, true);
3385 "pmap_enter_l2: failure for va %#lx in pmap %p",
3387 return (KERN_RESOURCE_SHORTAGE);
3389 if ((new_l2 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3390 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3391 vm_page_aflag_set(mt, PGA_WRITEABLE);
3395 * Increment counters.
3397 if ((new_l2 & ATTR_SW_WIRED) != 0)
3398 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
3399 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
3402 * Map the superpage.
3404 (void)pmap_load_store(l2, new_l2);
3406 atomic_add_long(&pmap_l2_mappings, 1);
3407 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
3410 return (KERN_SUCCESS);
3414 * Maps a sequence of resident pages belonging to the same object.
3415 * The sequence begins with the given page m_start. This page is
3416 * mapped at the given virtual address start. Each subsequent page is
3417 * mapped at a virtual address that is offset from start by the same
3418 * amount as the page is offset from m_start within the object. The
3419 * last page in the sequence is the page with the largest offset from
3420 * m_start that can be mapped at a virtual address less than the given
3421 * virtual address end. Not every virtual page between start and end
3422 * is mapped; only those for which a resident page exists with the
3423 * corresponding offset from m_start are mapped.
3426 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3427 vm_page_t m_start, vm_prot_t prot)
3429 struct rwlock *lock;
3432 vm_pindex_t diff, psize;
3434 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3436 psize = atop(end - start);
3441 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3442 va = start + ptoa(diff);
3443 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
3444 m->psind == 1 && pmap_ps_enabled(pmap) &&
3445 pmap_enter_2mpage(pmap, va, m, prot, &lock))
3446 m = &m[L2_SIZE / PAGE_SIZE - 1];
3448 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
3450 m = TAILQ_NEXT(m, listq);
3458 * this code makes some *MAJOR* assumptions:
3459 * 1. Current pmap & pmap exists.
3462 * 4. No page table pages.
3463 * but is *MUCH* faster than pmap_enter...
3467 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3469 struct rwlock *lock;
3473 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3480 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3481 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3483 struct spglist free;
3485 pt_entry_t *l2, *l3, l3_val;
3489 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3490 (m->oflags & VPO_UNMANAGED) != 0,
3491 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3492 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3494 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3496 * In the case that a page table page is not
3497 * resident, we are creating it here.
3499 if (va < VM_MAXUSER_ADDRESS) {
3500 vm_pindex_t l2pindex;
3503 * Calculate pagetable page index
3505 l2pindex = pmap_l2_pindex(va);
3506 if (mpte && (mpte->pindex == l2pindex)) {
3512 pde = pmap_pde(pmap, va, &lvl);
3515 * If the page table page is mapped, we just increment
3516 * the hold count, and activate it. Otherwise, we
3517 * attempt to allocate a page table page. If this
3518 * attempt fails, we don't retry. Instead, we give up.
3521 l2 = pmap_l1_to_l2(pde, va);
3522 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3526 if (lvl == 2 && pmap_load(pde) != 0) {
3528 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3532 * Pass NULL instead of the PV list lock
3533 * pointer, because we don't intend to sleep.
3535 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3540 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3541 l3 = &l3[pmap_l3_index(va)];
3544 pde = pmap_pde(kernel_pmap, va, &lvl);
3545 KASSERT(pde != NULL,
3546 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3549 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3550 l3 = pmap_l2_to_l3(pde, va);
3553 if (pmap_load(l3) != 0) {
3562 * Enter on the PV list if part of our managed memory.
3564 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3565 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3568 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
3569 pmap_invalidate_page(pmap, va);
3570 vm_page_free_pages_toq(&free, false);
3578 * Increment counters
3580 pmap_resident_count_inc(pmap, 1);
3582 pa = VM_PAGE_TO_PHYS(m);
3583 l3_val = pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3584 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3585 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3587 else if (va < VM_MAXUSER_ADDRESS)
3591 * Now validate mapping with RO protection
3593 if ((m->oflags & VPO_UNMANAGED) == 0)
3594 l3_val |= ATTR_SW_MANAGED;
3596 /* Sync icache before the mapping is stored to PTE */
3597 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3598 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
3599 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3601 pmap_load_store(l3, l3_val);
3602 pmap_invalidate_page(pmap, va);
3607 * This code maps large physical mmap regions into the
3608 * processor address space. Note that some shortcuts
3609 * are taken, but the code works.
3612 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3613 vm_pindex_t pindex, vm_size_t size)
3616 VM_OBJECT_ASSERT_WLOCKED(object);
3617 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3618 ("pmap_object_init_pt: non-device object"));
3622 * Clear the wired attribute from the mappings for the specified range of
3623 * addresses in the given pmap. Every valid mapping within that range
3624 * must have the wired attribute set. In contrast, invalid mappings
3625 * cannot have the wired attribute set, so they are ignored.
3627 * The wired attribute of the page table entry is not a hardware feature,
3628 * so there is no need to invalidate any TLB entries.
3631 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3633 vm_offset_t va_next;
3634 pd_entry_t *l0, *l1, *l2;
3638 for (; sva < eva; sva = va_next) {
3639 l0 = pmap_l0(pmap, sva);
3640 if (pmap_load(l0) == 0) {
3641 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3647 l1 = pmap_l0_to_l1(l0, sva);
3648 if (pmap_load(l1) == 0) {
3649 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3655 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3659 l2 = pmap_l1_to_l2(l1, sva);
3660 if (pmap_load(l2) == 0)
3663 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3664 l3 = pmap_demote_l2(pmap, l2, sva);
3668 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3669 ("pmap_unwire: Invalid l2 entry after demotion"));
3673 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3675 if (pmap_load(l3) == 0)
3677 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
3678 panic("pmap_unwire: l3 %#jx is missing "
3679 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
3682 * PG_W must be cleared atomically. Although the pmap
3683 * lock synchronizes access to PG_W, another processor
3684 * could be setting PG_M and/or PG_A concurrently.
3686 atomic_clear_long(l3, ATTR_SW_WIRED);
3687 pmap->pm_stats.wired_count--;
3694 * Copy the range specified by src_addr/len
3695 * from the source map to the range dst_addr/len
3696 * in the destination map.
3698 * This routine is only advisory and need not do anything.
3702 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3703 vm_offset_t src_addr)
3708 * pmap_zero_page zeros the specified hardware page by mapping
3709 * the page into KVM and using bzero to clear its contents.
3712 pmap_zero_page(vm_page_t m)
3714 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3716 pagezero((void *)va);
3720 * pmap_zero_page_area zeros the specified hardware page by mapping
3721 * the page into KVM and using bzero to clear its contents.
3723 * off and size may not cover an area beyond a single hardware page.
3726 pmap_zero_page_area(vm_page_t m, int off, int size)
3728 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3730 if (off == 0 && size == PAGE_SIZE)
3731 pagezero((void *)va);
3733 bzero((char *)va + off, size);
3737 * pmap_copy_page copies the specified (machine independent)
3738 * page by mapping the page into virtual memory and using
3739 * bcopy to copy the page, one machine dependent page at a
3743 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
3745 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
3746 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
3748 pagecopy((void *)src, (void *)dst);
3751 int unmapped_buf_allowed = 1;
3754 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
3755 vm_offset_t b_offset, int xfersize)
3759 vm_paddr_t p_a, p_b;
3760 vm_offset_t a_pg_offset, b_pg_offset;
3763 while (xfersize > 0) {
3764 a_pg_offset = a_offset & PAGE_MASK;
3765 m_a = ma[a_offset >> PAGE_SHIFT];
3766 p_a = m_a->phys_addr;
3767 b_pg_offset = b_offset & PAGE_MASK;
3768 m_b = mb[b_offset >> PAGE_SHIFT];
3769 p_b = m_b->phys_addr;
3770 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
3771 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
3772 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
3773 panic("!DMAP a %lx", p_a);
3775 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
3777 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
3778 panic("!DMAP b %lx", p_b);
3780 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
3782 bcopy(a_cp, b_cp, cnt);
3790 pmap_quick_enter_page(vm_page_t m)
3793 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
3797 pmap_quick_remove_page(vm_offset_t addr)
3802 * Returns true if the pmap's pv is one of the first
3803 * 16 pvs linked to from this page. This count may
3804 * be changed upwards or downwards in the future; it
3805 * is only necessary that true be returned for a small
3806 * subset of pmaps for proper page aging.
3809 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3811 struct md_page *pvh;
3812 struct rwlock *lock;
3817 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3818 ("pmap_page_exists_quick: page %p is not managed", m));
3820 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3822 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3823 if (PV_PMAP(pv) == pmap) {
3831 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
3832 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3833 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3834 if (PV_PMAP(pv) == pmap) {
3848 * pmap_page_wired_mappings:
3850 * Return the number of managed mappings to the given physical page
3854 pmap_page_wired_mappings(vm_page_t m)
3856 struct rwlock *lock;
3857 struct md_page *pvh;
3861 int count, lvl, md_gen, pvh_gen;
3863 if ((m->oflags & VPO_UNMANAGED) != 0)
3865 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3869 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3871 if (!PMAP_TRYLOCK(pmap)) {
3872 md_gen = m->md.pv_gen;
3876 if (md_gen != m->md.pv_gen) {
3881 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3882 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3886 if ((m->flags & PG_FICTITIOUS) == 0) {
3887 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3888 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3890 if (!PMAP_TRYLOCK(pmap)) {
3891 md_gen = m->md.pv_gen;
3892 pvh_gen = pvh->pv_gen;
3896 if (md_gen != m->md.pv_gen ||
3897 pvh_gen != pvh->pv_gen) {
3902 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3904 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3914 * Destroy all managed, non-wired mappings in the given user-space
3915 * pmap. This pmap cannot be active on any processor besides the
3918 * This function cannot be applied to the kernel pmap. Moreover, it
3919 * is not intended for general use. It is only to be used during
3920 * process termination. Consequently, it can be implemented in ways
3921 * that make it faster than pmap_remove(). First, it can more quickly
3922 * destroy mappings by iterating over the pmap's collection of PV
3923 * entries, rather than searching the page table. Second, it doesn't
3924 * have to test and clear the page table entries atomically, because
3925 * no processor is currently accessing the user address space. In
3926 * particular, a page table entry's dirty bit won't change state once
3927 * this function starts.
3930 pmap_remove_pages(pmap_t pmap)
3933 pt_entry_t *pte, tpte;
3934 struct spglist free;
3935 vm_page_t m, ml3, mt;
3937 struct md_page *pvh;
3938 struct pv_chunk *pc, *npc;
3939 struct rwlock *lock;
3941 uint64_t inuse, bitmask;
3942 int allfree, field, freed, idx, lvl;
3949 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
3952 for (field = 0; field < _NPCM; field++) {
3953 inuse = ~pc->pc_map[field] & pc_freemask[field];
3954 while (inuse != 0) {
3955 bit = ffsl(inuse) - 1;
3956 bitmask = 1UL << bit;
3957 idx = field * 64 + bit;
3958 pv = &pc->pc_pventry[idx];
3961 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3962 KASSERT(pde != NULL,
3963 ("Attempting to remove an unmapped page"));
3967 pte = pmap_l1_to_l2(pde, pv->pv_va);
3968 tpte = pmap_load(pte);
3969 KASSERT((tpte & ATTR_DESCR_MASK) ==
3971 ("Attempting to remove an invalid "
3972 "block: %lx", tpte));
3973 tpte = pmap_load(pte);
3976 pte = pmap_l2_to_l3(pde, pv->pv_va);
3977 tpte = pmap_load(pte);
3978 KASSERT((tpte & ATTR_DESCR_MASK) ==
3980 ("Attempting to remove an invalid "
3981 "page: %lx", tpte));
3985 "Invalid page directory level: %d",
3990 * We cannot remove wired pages from a process' mapping at this time
3992 if (tpte & ATTR_SW_WIRED) {
3997 pa = tpte & ~ATTR_MASK;
3999 m = PHYS_TO_VM_PAGE(pa);
4000 KASSERT(m->phys_addr == pa,
4001 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4002 m, (uintmax_t)m->phys_addr,
4005 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4006 m < &vm_page_array[vm_page_array_size],
4007 ("pmap_remove_pages: bad pte %#jx",
4010 pmap_load_clear(pte);
4013 * Update the vm_page_t clean/reference bits.
4015 if ((tpte & ATTR_AP_RW_BIT) ==
4016 ATTR_AP(ATTR_AP_RW)) {
4019 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4028 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4031 pc->pc_map[field] |= bitmask;
4034 pmap_resident_count_dec(pmap,
4035 L2_SIZE / PAGE_SIZE);
4036 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
4037 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
4039 if (TAILQ_EMPTY(&pvh->pv_list)) {
4040 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4041 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
4042 TAILQ_EMPTY(&mt->md.pv_list))
4043 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4045 ml3 = pmap_remove_pt_page(pmap,
4048 pmap_resident_count_dec(pmap,1);
4049 KASSERT(ml3->wire_count == NL3PG,
4050 ("pmap_remove_pages: l3 page wire count error"));
4051 ml3->wire_count = 1;
4052 vm_page_unwire_noq(ml3);
4053 pmap_add_delayed_free_list(ml3,
4058 pmap_resident_count_dec(pmap, 1);
4059 TAILQ_REMOVE(&m->md.pv_list, pv,
4062 if ((m->aflags & PGA_WRITEABLE) != 0 &&
4063 TAILQ_EMPTY(&m->md.pv_list) &&
4064 (m->flags & PG_FICTITIOUS) == 0) {
4066 VM_PAGE_TO_PHYS(m));
4067 if (TAILQ_EMPTY(&pvh->pv_list))
4068 vm_page_aflag_clear(m,
4073 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
4078 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4079 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4080 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4082 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4086 pmap_invalidate_all(pmap);
4090 vm_page_free_pages_toq(&free, false);
4094 * This is used to check if a page has been accessed or modified. As we
4095 * don't have a bit to see if it has been modified we have to assume it
4096 * has been if the page is read/write.
4099 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
4101 struct rwlock *lock;
4103 struct md_page *pvh;
4104 pt_entry_t *pte, mask, value;
4106 int lvl, md_gen, pvh_gen;
4110 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4113 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4115 if (!PMAP_TRYLOCK(pmap)) {
4116 md_gen = m->md.pv_gen;
4120 if (md_gen != m->md.pv_gen) {
4125 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4127 ("pmap_page_test_mappings: Invalid level %d", lvl));
4131 mask |= ATTR_AP_RW_BIT;
4132 value |= ATTR_AP(ATTR_AP_RW);
4135 mask |= ATTR_AF | ATTR_DESCR_MASK;
4136 value |= ATTR_AF | L3_PAGE;
4138 rv = (pmap_load(pte) & mask) == value;
4143 if ((m->flags & PG_FICTITIOUS) == 0) {
4144 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4145 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4147 if (!PMAP_TRYLOCK(pmap)) {
4148 md_gen = m->md.pv_gen;
4149 pvh_gen = pvh->pv_gen;
4153 if (md_gen != m->md.pv_gen ||
4154 pvh_gen != pvh->pv_gen) {
4159 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4161 ("pmap_page_test_mappings: Invalid level %d", lvl));
4165 mask |= ATTR_AP_RW_BIT;
4166 value |= ATTR_AP(ATTR_AP_RW);
4169 mask |= ATTR_AF | ATTR_DESCR_MASK;
4170 value |= ATTR_AF | L2_BLOCK;
4172 rv = (pmap_load(pte) & mask) == value;
4186 * Return whether or not the specified physical page was modified
4187 * in any physical maps.
4190 pmap_is_modified(vm_page_t m)
4193 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4194 ("pmap_is_modified: page %p is not managed", m));
4197 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4198 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4199 * is clear, no PTEs can have PG_M set.
4201 VM_OBJECT_ASSERT_WLOCKED(m->object);
4202 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4204 return (pmap_page_test_mappings(m, FALSE, TRUE));
4208 * pmap_is_prefaultable:
4210 * Return whether or not the specified virtual address is eligible
4214 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4222 pte = pmap_pte(pmap, addr, &lvl);
4223 if (pte != NULL && pmap_load(pte) != 0) {
4231 * pmap_is_referenced:
4233 * Return whether or not the specified physical page was referenced
4234 * in any physical maps.
4237 pmap_is_referenced(vm_page_t m)
4240 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4241 ("pmap_is_referenced: page %p is not managed", m));
4242 return (pmap_page_test_mappings(m, TRUE, FALSE));
4246 * Clear the write and modified bits in each of the given page's mappings.
4249 pmap_remove_write(vm_page_t m)
4251 struct md_page *pvh;
4253 struct rwlock *lock;
4254 pv_entry_t next_pv, pv;
4255 pt_entry_t oldpte, *pte;
4257 int lvl, md_gen, pvh_gen;
4259 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4260 ("pmap_remove_write: page %p is not managed", m));
4263 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4264 * set by another thread while the object is locked. Thus,
4265 * if PGA_WRITEABLE is clear, no page table entries need updating.
4267 VM_OBJECT_ASSERT_WLOCKED(m->object);
4268 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4270 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4271 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4272 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4275 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4277 if (!PMAP_TRYLOCK(pmap)) {
4278 pvh_gen = pvh->pv_gen;
4282 if (pvh_gen != pvh->pv_gen) {
4289 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4290 if ((pmap_load(pte) & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
4291 pmap_demote_l2_locked(pmap, pte, va & ~L2_OFFSET,
4293 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4294 ("inconsistent pv lock %p %p for page %p",
4295 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4298 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4300 if (!PMAP_TRYLOCK(pmap)) {
4301 pvh_gen = pvh->pv_gen;
4302 md_gen = m->md.pv_gen;
4306 if (pvh_gen != pvh->pv_gen ||
4307 md_gen != m->md.pv_gen) {
4313 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4315 oldpte = pmap_load(pte);
4316 if ((oldpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) {
4317 if (!atomic_cmpset_long(pte, oldpte,
4318 oldpte | ATTR_AP(ATTR_AP_RO)))
4320 if ((oldpte & ATTR_AF) != 0)
4322 pmap_invalidate_page(pmap, pv->pv_va);
4327 vm_page_aflag_clear(m, PGA_WRITEABLE);
4330 static __inline boolean_t
4331 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
4338 * pmap_ts_referenced:
4340 * Return a count of reference bits for a page, clearing those bits.
4341 * It is not necessary for every reference bit to be cleared, but it
4342 * is necessary that 0 only be returned when there are truly no
4343 * reference bits set.
4345 * As an optimization, update the page's dirty field if a modified bit is
4346 * found while counting reference bits. This opportunistic update can be
4347 * performed at low cost and can eliminate the need for some future calls
4348 * to pmap_is_modified(). However, since this function stops after
4349 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4350 * dirty pages. Those dirty pages will only be detected by a future call
4351 * to pmap_is_modified().
4354 pmap_ts_referenced(vm_page_t m)
4356 struct md_page *pvh;
4359 struct rwlock *lock;
4360 pd_entry_t *pde, tpde;
4361 pt_entry_t *pte, tpte;
4365 int cleared, md_gen, not_cleared, lvl, pvh_gen;
4366 struct spglist free;
4369 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4370 ("pmap_ts_referenced: page %p is not managed", m));
4373 pa = VM_PAGE_TO_PHYS(m);
4374 lock = PHYS_TO_PV_LIST_LOCK(pa);
4375 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4379 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4380 goto small_mappings;
4386 if (!PMAP_TRYLOCK(pmap)) {
4387 pvh_gen = pvh->pv_gen;
4391 if (pvh_gen != pvh->pv_gen) {
4397 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4398 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4400 ("pmap_ts_referenced: invalid pde level %d", lvl));
4401 tpde = pmap_load(pde);
4402 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4403 ("pmap_ts_referenced: found an invalid l1 table"));
4404 pte = pmap_l1_to_l2(pde, pv->pv_va);
4405 tpte = pmap_load(pte);
4406 if (pmap_page_dirty(tpte)) {
4408 * Although "tpte" is mapping a 2MB page, because
4409 * this function is called at a 4KB page granularity,
4410 * we only update the 4KB page under test.
4414 if ((tpte & ATTR_AF) != 0) {
4416 * Since this reference bit is shared by 512 4KB
4417 * pages, it should not be cleared every time it is
4418 * tested. Apply a simple "hash" function on the
4419 * physical page number, the virtual superpage number,
4420 * and the pmap address to select one 4KB page out of
4421 * the 512 on which testing the reference bit will
4422 * result in clearing that reference bit. This
4423 * function is designed to avoid the selection of the
4424 * same 4KB page for every 2MB page mapping.
4426 * On demotion, a mapping that hasn't been referenced
4427 * is simply destroyed. To avoid the possibility of a
4428 * subsequent page fault on a demoted wired mapping,
4429 * always leave its reference bit set. Moreover,
4430 * since the superpage is wired, the current state of
4431 * its reference bit won't affect page replacement.
4433 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4434 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4435 (tpte & ATTR_SW_WIRED) == 0) {
4436 if (safe_to_clear_referenced(pmap, tpte)) {
4438 * TODO: We don't handle the access
4439 * flag at all. We need to be able
4440 * to set it in the exception handler.
4443 "safe_to_clear_referenced\n");
4444 } else if (pmap_demote_l2_locked(pmap, pte,
4445 pv->pv_va, &lock) != NULL) {
4447 va += VM_PAGE_TO_PHYS(m) -
4448 (tpte & ~ATTR_MASK);
4449 l3 = pmap_l2_to_l3(pte, va);
4450 pmap_remove_l3(pmap, l3, va,
4451 pmap_load(pte), NULL, &lock);
4457 * The superpage mapping was removed
4458 * entirely and therefore 'pv' is no
4466 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4467 ("inconsistent pv lock %p %p for page %p",
4468 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4473 /* Rotate the PV list if it has more than one entry. */
4474 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4475 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4476 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4479 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4481 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4483 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4490 if (!PMAP_TRYLOCK(pmap)) {
4491 pvh_gen = pvh->pv_gen;
4492 md_gen = m->md.pv_gen;
4496 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4501 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4502 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4504 ("pmap_ts_referenced: invalid pde level %d", lvl));
4505 tpde = pmap_load(pde);
4506 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4507 ("pmap_ts_referenced: found an invalid l2 table"));
4508 pte = pmap_l2_to_l3(pde, pv->pv_va);
4509 tpte = pmap_load(pte);
4510 if (pmap_page_dirty(tpte))
4512 if ((tpte & ATTR_AF) != 0) {
4513 if (safe_to_clear_referenced(pmap, tpte)) {
4515 * TODO: We don't handle the access flag
4516 * at all. We need to be able to set it in
4517 * the exception handler.
4519 panic("ARM64TODO: safe_to_clear_referenced\n");
4520 } else if ((tpte & ATTR_SW_WIRED) == 0) {
4522 * Wired pages cannot be paged out so
4523 * doing accessed bit emulation for
4524 * them is wasted effort. We do the
4525 * hard work for unwired pages only.
4527 pmap_remove_l3(pmap, pte, pv->pv_va, tpde,
4529 pmap_invalidate_page(pmap, pv->pv_va);
4534 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4535 ("inconsistent pv lock %p %p for page %p",
4536 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4541 /* Rotate the PV list if it has more than one entry. */
4542 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4543 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4544 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4547 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4548 not_cleared < PMAP_TS_REFERENCED_MAX);
4551 vm_page_free_pages_toq(&free, false);
4552 return (cleared + not_cleared);
4556 * Apply the given advice to the specified range of addresses within the
4557 * given pmap. Depending on the advice, clear the referenced and/or
4558 * modified flags in each mapping and set the mapped page's dirty field.
4561 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4566 * Clear the modify bits on the specified physical page.
4569 pmap_clear_modify(vm_page_t m)
4572 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4573 ("pmap_clear_modify: page %p is not managed", m));
4574 VM_OBJECT_ASSERT_WLOCKED(m->object);
4575 KASSERT(!vm_page_xbusied(m),
4576 ("pmap_clear_modify: page %p is exclusive busied", m));
4579 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4580 * If the object containing the page is locked and the page is not
4581 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4583 if ((m->aflags & PGA_WRITEABLE) == 0)
4586 /* ARM64TODO: We lack support for tracking if a page is modified */
4590 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4592 struct pmap_preinit_mapping *ppim;
4593 vm_offset_t va, offset;
4596 int i, lvl, l2_blocks, free_l2_count, start_idx;
4598 if (!vm_initialized) {
4600 * No L3 ptables so map entire L2 blocks where start VA is:
4601 * preinit_map_va + start_idx * L2_SIZE
4602 * There may be duplicate mappings (multiple VA -> same PA) but
4603 * ARM64 dcache is always PIPT so that's acceptable.
4608 /* Calculate how many full L2 blocks are needed for the mapping */
4609 l2_blocks = (roundup2(pa + size, L2_SIZE) - rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
4611 offset = pa & L2_OFFSET;
4613 if (preinit_map_va == 0)
4616 /* Map 2MiB L2 blocks from reserved VA space */
4620 /* Find enough free contiguous VA space */
4621 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
4622 ppim = pmap_preinit_mapping + i;
4623 if (free_l2_count > 0 && ppim->pa != 0) {
4624 /* Not enough space here */
4630 if (ppim->pa == 0) {
4632 if (start_idx == -1)
4635 if (free_l2_count == l2_blocks)
4639 if (free_l2_count != l2_blocks)
4640 panic("%s: too many preinit mappings", __func__);
4642 va = preinit_map_va + (start_idx * L2_SIZE);
4643 for (i = start_idx; i < start_idx + l2_blocks; i++) {
4644 /* Mark entries as allocated */
4645 ppim = pmap_preinit_mapping + i;
4647 ppim->va = va + offset;
4652 pa = rounddown2(pa, L2_SIZE);
4653 for (i = 0; i < l2_blocks; i++) {
4654 pde = pmap_pde(kernel_pmap, va, &lvl);
4655 KASSERT(pde != NULL,
4656 ("pmap_mapbios: Invalid page entry, va: 0x%lx", va));
4657 KASSERT(lvl == 1, ("pmap_mapbios: Invalid level %d", lvl));
4659 /* Insert L2_BLOCK */
4660 l2 = pmap_l1_to_l2(pde, va);
4662 pa | ATTR_DEFAULT | ATTR_XN |
4663 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
4664 pmap_invalidate_range(kernel_pmap, va, va + L2_SIZE);
4670 va = preinit_map_va + (start_idx * L2_SIZE);
4673 /* kva_alloc may be used to map the pages */
4674 offset = pa & PAGE_MASK;
4675 size = round_page(offset + size);
4677 va = kva_alloc(size);
4679 panic("%s: Couldn't allocate KVA", __func__);
4681 pde = pmap_pde(kernel_pmap, va, &lvl);
4682 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
4684 /* L3 table is linked */
4685 va = trunc_page(va);
4686 pa = trunc_page(pa);
4687 pmap_kenter(va, size, pa, CACHED_MEMORY);
4690 return ((void *)(va + offset));
4694 pmap_unmapbios(vm_offset_t va, vm_size_t size)
4696 struct pmap_preinit_mapping *ppim;
4697 vm_offset_t offset, tmpsize, va_trunc;
4700 int i, lvl, l2_blocks, block;
4702 l2_blocks = (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
4703 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
4705 /* Remove preinit mapping */
4707 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
4708 ppim = pmap_preinit_mapping + i;
4709 if (ppim->va == va) {
4710 KASSERT(ppim->size == size, ("pmap_unmapbios: size mismatch"));
4714 offset = block * L2_SIZE;
4715 va_trunc = rounddown2(va, L2_SIZE) + offset;
4717 /* Remove L2_BLOCK */
4718 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
4719 KASSERT(pde != NULL,
4720 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va_trunc));
4721 l2 = pmap_l1_to_l2(pde, va_trunc);
4722 pmap_load_clear(l2);
4723 pmap_invalidate_range(kernel_pmap, va_trunc, va_trunc + L2_SIZE);
4725 if (block == (l2_blocks - 1))
4731 /* Unmap the pages reserved with kva_alloc. */
4732 if (vm_initialized) {
4733 offset = va & PAGE_MASK;
4734 size = round_page(offset + size);
4735 va = trunc_page(va);
4737 pde = pmap_pde(kernel_pmap, va, &lvl);
4738 KASSERT(pde != NULL,
4739 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
4740 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
4742 /* Unmap and invalidate the pages */
4743 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
4744 pmap_kremove(va + tmpsize);
4751 * Sets the memory attribute for the specified page.
4754 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4757 m->md.pv_memattr = ma;
4760 * If "m" is a normal page, update its direct mapping. This update
4761 * can be relied upon to perform any cache operations that are
4762 * required for data coherence.
4764 if ((m->flags & PG_FICTITIOUS) == 0 &&
4765 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
4766 m->md.pv_memattr) != 0)
4767 panic("memory attribute change on the direct map failed");
4771 * Changes the specified virtual address range's memory type to that given by
4772 * the parameter "mode". The specified virtual address range must be
4773 * completely contained within either the direct map or the kernel map. If
4774 * the virtual address range is contained within the kernel map, then the
4775 * memory type for each of the corresponding ranges of the direct map is also
4776 * changed. (The corresponding ranges of the direct map are those ranges that
4777 * map the same physical pages as the specified virtual address range.) These
4778 * changes to the direct map are necessary because Intel describes the
4779 * behavior of their processors as "undefined" if two or more mappings to the
4780 * same physical page have different memory types.
4782 * Returns zero if the change completed successfully, and either EINVAL or
4783 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
4784 * of the virtual address range was not mapped, and ENOMEM is returned if
4785 * there was insufficient memory available to complete the change. In the
4786 * latter case, the memory type may have been changed on some part of the
4787 * virtual address range or the direct map.
4790 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
4794 PMAP_LOCK(kernel_pmap);
4795 error = pmap_change_attr_locked(va, size, mode);
4796 PMAP_UNLOCK(kernel_pmap);
4801 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
4803 vm_offset_t base, offset, tmpva;
4804 pt_entry_t l3, *pte, *newpte;
4807 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
4808 base = trunc_page(va);
4809 offset = va & PAGE_MASK;
4810 size = round_page(offset + size);
4812 if (!VIRT_IN_DMAP(base))
4815 for (tmpva = base; tmpva < base + size; ) {
4816 pte = pmap_pte(kernel_pmap, va, &lvl);
4820 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
4822 * We already have the correct attribute,
4823 * ignore this entry.
4827 panic("Invalid DMAP table level: %d\n", lvl);
4829 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
4832 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
4840 * Split the entry to an level 3 table, then
4841 * set the new attribute.
4845 panic("Invalid DMAP table level: %d\n", lvl);
4847 newpte = pmap_demote_l1(kernel_pmap, pte,
4848 tmpva & ~L1_OFFSET);
4851 pte = pmap_l1_to_l2(pte, tmpva);
4853 newpte = pmap_demote_l2(kernel_pmap, pte,
4854 tmpva & ~L2_OFFSET);
4857 pte = pmap_l2_to_l3(pte, tmpva);
4859 /* Update the entry */
4860 l3 = pmap_load(pte);
4861 l3 &= ~ATTR_IDX_MASK;
4862 l3 |= ATTR_IDX(mode);
4863 if (mode == DEVICE_MEMORY)
4866 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
4870 * If moving to a non-cacheable entry flush
4873 if (mode == VM_MEMATTR_UNCACHEABLE)
4874 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
4886 * Create an L2 table to map all addresses within an L1 mapping.
4889 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
4891 pt_entry_t *l2, newl2, oldl1;
4893 vm_paddr_t l2phys, phys;
4897 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4898 oldl1 = pmap_load(l1);
4899 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
4900 ("pmap_demote_l1: Demoting a non-block entry"));
4901 KASSERT((va & L1_OFFSET) == 0,
4902 ("pmap_demote_l1: Invalid virtual address %#lx", va));
4903 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
4904 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
4907 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
4908 tmpl1 = kva_alloc(PAGE_SIZE);
4913 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
4914 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
4915 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
4916 " in pmap %p", va, pmap);
4920 l2phys = VM_PAGE_TO_PHYS(ml2);
4921 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
4923 /* Address the range points at */
4924 phys = oldl1 & ~ATTR_MASK;
4925 /* The attributed from the old l1 table to be copied */
4926 newl2 = oldl1 & ATTR_MASK;
4928 /* Create the new entries */
4929 for (i = 0; i < Ln_ENTRIES; i++) {
4930 l2[i] = newl2 | phys;
4933 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
4934 ("Invalid l2 page (%lx != %lx)", l2[0],
4935 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
4938 pmap_kenter(tmpl1, PAGE_SIZE,
4939 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY);
4940 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
4943 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
4946 pmap_kremove(tmpl1);
4947 kva_free(tmpl1, PAGE_SIZE);
4954 * Create an L3 table to map all addresses within an L2 mapping.
4957 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
4958 struct rwlock **lockp)
4960 pt_entry_t *l3, newl3, oldl2;
4962 vm_paddr_t l3phys, phys;
4966 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4968 oldl2 = pmap_load(l2);
4969 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
4970 ("pmap_demote_l2: Demoting a non-block entry"));
4971 KASSERT((va & L2_OFFSET) == 0,
4972 ("pmap_demote_l2: Invalid virtual address %#lx", va));
4975 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
4976 tmpl2 = kva_alloc(PAGE_SIZE);
4981 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
4982 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
4983 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4984 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
4986 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
4987 " in pmap %p", va, pmap);
4990 if (va < VM_MAXUSER_ADDRESS)
4991 pmap_resident_count_inc(pmap, 1);
4994 l3phys = VM_PAGE_TO_PHYS(ml3);
4995 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
4997 /* Address the range points at */
4998 phys = oldl2 & ~ATTR_MASK;
4999 /* The attributed from the old l2 table to be copied */
5000 newl3 = (oldl2 & (ATTR_MASK & ~ATTR_DESCR_MASK)) | L3_PAGE;
5003 * If the page table page is new, initialize it.
5005 if (ml3->wire_count == 1) {
5006 ml3->wire_count = NL3PG;
5007 for (i = 0; i < Ln_ENTRIES; i++) {
5008 l3[i] = newl3 | phys;
5012 KASSERT(l3[0] == ((oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE),
5013 ("Invalid l3 page (%lx != %lx)", l3[0],
5014 (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE));
5017 * Map the temporary page so we don't lose access to the l2 table.
5020 pmap_kenter(tmpl2, PAGE_SIZE,
5021 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY);
5022 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
5026 * The spare PV entries must be reserved prior to demoting the
5027 * mapping, that is, prior to changing the PDE. Otherwise, the state
5028 * of the L2 and the PV lists will be inconsistent, which can result
5029 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5030 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
5031 * PV entry for the 2MB page mapping that is being demoted.
5033 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5034 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
5036 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
5039 * Demote the PV entry.
5041 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5042 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
5044 atomic_add_long(&pmap_l2_demotions, 1);
5045 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
5046 " in pmap %p %lx", va, pmap, l3[0]);
5050 pmap_kremove(tmpl2);
5051 kva_free(tmpl2, PAGE_SIZE);
5059 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
5061 struct rwlock *lock;
5065 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
5072 * perform the pmap work for mincore
5075 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5077 pt_entry_t *pte, tpte;
5078 vm_paddr_t mask, pa;
5085 pte = pmap_pte(pmap, addr, &lvl);
5087 tpte = pmap_load(pte);
5100 panic("pmap_mincore: invalid level %d", lvl);
5103 val = MINCORE_INCORE;
5105 val |= MINCORE_SUPER;
5106 if (pmap_page_dirty(tpte))
5107 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5108 if ((tpte & ATTR_AF) == ATTR_AF)
5109 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5111 managed = (tpte & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
5112 pa = (tpte & ~ATTR_MASK) | (addr & mask);
5116 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5117 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
5118 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5119 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5122 PA_UNLOCK_COND(*locked_pa);
5129 pmap_activate(struct thread *td)
5134 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5135 td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0);
5136 __asm __volatile("msr ttbr0_el1, %0" : :
5137 "r"(td->td_proc->p_md.md_l0addr));
5138 pmap_invalidate_all(pmap);
5143 pmap_switch(struct thread *old, struct thread *new)
5145 pcpu_bp_harden bp_harden;
5148 /* Store the new curthread */
5149 PCPU_SET(curthread, new);
5151 /* And the new pcb */
5153 PCPU_SET(curpcb, pcb);
5156 * TODO: We may need to flush the cache here if switching
5157 * to a user process.
5161 old->td_proc->p_md.md_l0addr != new->td_proc->p_md.md_l0addr) {
5163 /* Switch to the new pmap */
5164 "msr ttbr0_el1, %0 \n"
5167 /* Invalidate the TLB */
5172 : : "r"(new->td_proc->p_md.md_l0addr));
5175 * Stop userspace from training the branch predictor against
5176 * other processes. This will call into a CPU specific
5177 * function that clears the branch predictor state.
5179 bp_harden = PCPU_GET(bp_harden);
5180 if (bp_harden != NULL)
5188 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
5191 if (va >= VM_MIN_KERNEL_ADDRESS) {
5192 cpu_icache_sync_range(va, sz);
5197 /* Find the length of data in this page to flush */
5198 offset = va & PAGE_MASK;
5199 len = imin(PAGE_SIZE - offset, sz);
5202 /* Extract the physical address & find it in the DMAP */
5203 pa = pmap_extract(pmap, va);
5205 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
5207 /* Move to the next page */
5210 /* Set the length for the next iteration */
5211 len = imin(PAGE_SIZE, sz);
5217 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
5223 switch (ESR_ELx_EXCEPTION(esr)) {
5224 case EXCP_INSN_ABORT_L:
5225 case EXCP_INSN_ABORT:
5226 case EXCP_DATA_ABORT_L:
5227 case EXCP_DATA_ABORT:
5230 return (KERN_FAILURE);
5233 /* Data and insn aborts use same encoding for FCS field. */
5234 switch (esr & ISS_DATA_DFSC_MASK) {
5235 case ISS_DATA_DFSC_TF_L0:
5236 case ISS_DATA_DFSC_TF_L1:
5237 case ISS_DATA_DFSC_TF_L2:
5238 case ISS_DATA_DFSC_TF_L3:
5240 /* Ask the MMU to check the address */
5241 intr = intr_disable();
5242 if (pmap == kernel_pmap)
5243 par = arm64_address_translate_s1e1r(far);
5245 par = arm64_address_translate_s1e0r(far);
5250 * If the translation was successful the address was invalid
5251 * due to a break-before-make sequence. We can unlock and
5252 * return success to the trap handler.
5254 if (PAR_SUCCESS(par))
5255 return (KERN_SUCCESS);
5262 return (KERN_FAILURE);
5266 * Increase the starting virtual address of the given mapping if a
5267 * different alignment might result in more superpage mappings.
5270 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5271 vm_offset_t *addr, vm_size_t size)
5273 vm_offset_t superpage_offset;
5277 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5278 offset += ptoa(object->pg_color);
5279 superpage_offset = offset & L2_OFFSET;
5280 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
5281 (*addr & L2_OFFSET) == superpage_offset)
5283 if ((*addr & L2_OFFSET) < superpage_offset)
5284 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
5286 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
5290 * Get the kernel virtual address of a set of physical pages. If there are
5291 * physical addresses not covered by the DMAP perform a transient mapping
5292 * that will be removed when calling pmap_unmap_io_transient.
5294 * \param page The pages the caller wishes to obtain the virtual
5295 * address on the kernel memory map.
5296 * \param vaddr On return contains the kernel virtual memory address
5297 * of the pages passed in the page parameter.
5298 * \param count Number of pages passed in.
5299 * \param can_fault TRUE if the thread using the mapped pages can take
5300 * page faults, FALSE otherwise.
5302 * \returns TRUE if the caller must call pmap_unmap_io_transient when
5303 * finished or FALSE otherwise.
5307 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
5308 boolean_t can_fault)
5311 boolean_t needs_mapping;
5315 * Allocate any KVA space that we need, this is done in a separate
5316 * loop to prevent calling vmem_alloc while pinned.
5318 needs_mapping = FALSE;
5319 for (i = 0; i < count; i++) {
5320 paddr = VM_PAGE_TO_PHYS(page[i]);
5321 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
5322 error = vmem_alloc(kernel_arena, PAGE_SIZE,
5323 M_BESTFIT | M_WAITOK, &vaddr[i]);
5324 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
5325 needs_mapping = TRUE;
5327 vaddr[i] = PHYS_TO_DMAP(paddr);
5331 /* Exit early if everything is covered by the DMAP */
5337 for (i = 0; i < count; i++) {
5338 paddr = VM_PAGE_TO_PHYS(page[i]);
5339 if (!PHYS_IN_DMAP(paddr)) {
5341 "pmap_map_io_transient: TODO: Map out of DMAP data");
5345 return (needs_mapping);
5349 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
5350 boolean_t can_fault)
5357 for (i = 0; i < count; i++) {
5358 paddr = VM_PAGE_TO_PHYS(page[i]);
5359 if (!PHYS_IN_DMAP(paddr)) {
5360 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
5366 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
5369 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);