2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/msgbuf.h>
120 #include <sys/mutex.h>
121 #include <sys/proc.h>
122 #include <sys/rwlock.h>
124 #include <sys/vmem.h>
125 #include <sys/vmmeter.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/_unrhdr.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/vm_pager.h>
140 #include <vm/vm_phys.h>
141 #include <vm/vm_radix.h>
142 #include <vm/vm_reserv.h>
145 #include <machine/machdep.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
149 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
150 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
151 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
152 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
154 #define NUL0E L0_ENTRIES
155 #define NUL1E (NUL0E * NL1PG)
156 #define NUL2E (NUL1E * NL2PG)
158 #if !defined(DIAGNOSTIC)
159 #ifdef __GNUC_GNU_INLINE__
160 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
162 #define PMAP_INLINE extern inline
169 * These are configured by the mair_el1 register. This is set up in locore.S
171 #define DEVICE_MEMORY 0
172 #define UNCACHED_MEMORY 1
173 #define CACHED_MEMORY 2
177 #define PV_STAT(x) do { x ; } while (0)
179 #define PV_STAT(x) do { } while (0)
182 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
183 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
185 #define NPV_LIST_LOCKS MAXCPU
187 #define PHYS_TO_PV_LIST_LOCK(pa) \
188 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
190 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
191 struct rwlock **_lockp = (lockp); \
192 struct rwlock *_new_lock; \
194 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
195 if (_new_lock != *_lockp) { \
196 if (*_lockp != NULL) \
197 rw_wunlock(*_lockp); \
198 *_lockp = _new_lock; \
203 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
204 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
206 #define RELEASE_PV_LIST_LOCK(lockp) do { \
207 struct rwlock **_lockp = (lockp); \
209 if (*_lockp != NULL) { \
210 rw_wunlock(*_lockp); \
215 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
216 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
218 struct pmap kernel_pmap_store;
220 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
221 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
222 vm_offset_t kernel_vm_end = 0;
225 * Data for the pv entry allocation mechanism.
226 * Updates to pv_invl_gen are protected by the pv_list_locks[]
227 * elements, but reads are not.
229 static struct md_page *pv_table;
230 static struct md_page pv_dummy;
232 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
233 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
234 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
236 /* This code assumes all L1 DMAP entries will be used */
237 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
238 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
240 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
241 extern pt_entry_t pagetable_dmap[];
243 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
245 static int superpages_enabled = 1;
246 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
247 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
248 "Are large page mappings enabled?");
251 * Data for the pv entry allocation mechanism
253 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
254 static struct mtx pv_chunks_mutex;
255 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
257 static void free_pv_chunk(struct pv_chunk *pc);
258 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
259 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
260 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
261 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
262 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
265 static int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode);
266 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
267 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
268 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
269 vm_offset_t va, struct rwlock **lockp);
270 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
271 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
272 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
273 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
274 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
275 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
276 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
277 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
278 vm_page_t m, struct rwlock **lockp);
280 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
281 struct rwlock **lockp);
283 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
284 struct spglist *free);
285 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
286 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
289 * These load the old table data and store the new value.
290 * They need to be atomic as the System MMU may write to the table at
291 * the same time as the CPU.
293 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
294 #define pmap_set(table, mask) atomic_set_64(table, mask)
295 #define pmap_load_clear(table) atomic_swap_64(table, 0)
296 #define pmap_load(table) (*table)
298 /********************/
299 /* Inline functions */
300 /********************/
303 pagecopy(void *s, void *d)
306 memcpy(d, s, PAGE_SIZE);
309 static __inline pd_entry_t *
310 pmap_l0(pmap_t pmap, vm_offset_t va)
313 return (&pmap->pm_l0[pmap_l0_index(va)]);
316 static __inline pd_entry_t *
317 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
321 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
322 return (&l1[pmap_l1_index(va)]);
325 static __inline pd_entry_t *
326 pmap_l1(pmap_t pmap, vm_offset_t va)
330 l0 = pmap_l0(pmap, va);
331 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
334 return (pmap_l0_to_l1(l0, va));
337 static __inline pd_entry_t *
338 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
342 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
343 return (&l2[pmap_l2_index(va)]);
346 static __inline pd_entry_t *
347 pmap_l2(pmap_t pmap, vm_offset_t va)
351 l1 = pmap_l1(pmap, va);
352 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
355 return (pmap_l1_to_l2(l1, va));
358 static __inline pt_entry_t *
359 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
363 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
364 return (&l3[pmap_l3_index(va)]);
368 * Returns the lowest valid pde for a given virtual address.
369 * The next level may or may not point to a valid page or block.
371 static __inline pd_entry_t *
372 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
374 pd_entry_t *l0, *l1, *l2, desc;
376 l0 = pmap_l0(pmap, va);
377 desc = pmap_load(l0) & ATTR_DESCR_MASK;
378 if (desc != L0_TABLE) {
383 l1 = pmap_l0_to_l1(l0, va);
384 desc = pmap_load(l1) & ATTR_DESCR_MASK;
385 if (desc != L1_TABLE) {
390 l2 = pmap_l1_to_l2(l1, va);
391 desc = pmap_load(l2) & ATTR_DESCR_MASK;
392 if (desc != L2_TABLE) {
402 * Returns the lowest valid pte block or table entry for a given virtual
403 * address. If there are no valid entries return NULL and set the level to
404 * the first invalid level.
406 static __inline pt_entry_t *
407 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
409 pd_entry_t *l1, *l2, desc;
412 l1 = pmap_l1(pmap, va);
417 desc = pmap_load(l1) & ATTR_DESCR_MASK;
418 if (desc == L1_BLOCK) {
423 if (desc != L1_TABLE) {
428 l2 = pmap_l1_to_l2(l1, va);
429 desc = pmap_load(l2) & ATTR_DESCR_MASK;
430 if (desc == L2_BLOCK) {
435 if (desc != L2_TABLE) {
441 l3 = pmap_l2_to_l3(l2, va);
442 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
449 pmap_superpages_enabled(void)
452 return (superpages_enabled != 0);
456 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
457 pd_entry_t **l2, pt_entry_t **l3)
459 pd_entry_t *l0p, *l1p, *l2p;
461 if (pmap->pm_l0 == NULL)
464 l0p = pmap_l0(pmap, va);
467 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
470 l1p = pmap_l0_to_l1(l0p, va);
473 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
479 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
482 l2p = pmap_l1_to_l2(l1p, va);
485 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
490 *l3 = pmap_l2_to_l3(l2p, va);
496 pmap_l3_valid(pt_entry_t l3)
499 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
503 CTASSERT(L1_BLOCK == L2_BLOCK);
506 * Checks if the page is dirty. We currently lack proper tracking of this on
507 * arm64 so for now assume is a page mapped as rw was accessed it is.
510 pmap_page_dirty(pt_entry_t pte)
513 return ((pte & (ATTR_AF | ATTR_AP_RW_BIT)) ==
514 (ATTR_AF | ATTR_AP(ATTR_AP_RW)));
518 pmap_resident_count_inc(pmap_t pmap, int count)
521 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
522 pmap->pm_stats.resident_count += count;
526 pmap_resident_count_dec(pmap_t pmap, int count)
529 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
530 KASSERT(pmap->pm_stats.resident_count >= count,
531 ("pmap %p resident count underflow %ld %d", pmap,
532 pmap->pm_stats.resident_count, count));
533 pmap->pm_stats.resident_count -= count;
537 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
543 l1 = (pd_entry_t *)l1pt;
544 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
546 /* Check locore has used a table L1 map */
547 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
548 ("Invalid bootstrap L1 table"));
549 /* Find the address of the L2 table */
550 l2 = (pt_entry_t *)init_pt_va;
551 *l2_slot = pmap_l2_index(va);
557 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
559 u_int l1_slot, l2_slot;
562 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
564 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
568 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa, vm_paddr_t max_pa)
574 pa = dmap_phys_base = min_pa & ~L1_OFFSET;
575 va = DMAP_MIN_ADDRESS;
576 for (; va < DMAP_MAX_ADDRESS && pa < max_pa;
577 pa += L1_SIZE, va += L1_SIZE, l1_slot++) {
578 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
580 pmap_load_store(&pagetable_dmap[l1_slot],
581 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
582 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
585 /* Set the upper limit of the DMAP region */
593 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
600 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
602 l1 = (pd_entry_t *)l1pt;
603 l1_slot = pmap_l1_index(va);
606 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
607 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
609 pa = pmap_early_vtophys(l1pt, l2pt);
610 pmap_load_store(&l1[l1_slot],
611 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
615 /* Clean the L2 page table */
616 memset((void *)l2_start, 0, l2pt - l2_start);
622 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
629 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
631 l2 = pmap_l2(kernel_pmap, va);
632 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
633 l2_slot = pmap_l2_index(va);
636 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
637 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
639 pa = pmap_early_vtophys(l1pt, l3pt);
640 pmap_load_store(&l2[l2_slot],
641 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
645 /* Clean the L2 page table */
646 memset((void *)l3_start, 0, l3pt - l3_start);
652 * Bootstrap the system enough to run with virtual memory.
655 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
658 u_int l1_slot, l2_slot, avail_slot, map_slot, used_map_slot;
661 vm_offset_t va, freemempos;
662 vm_offset_t dpcpu, msgbufpv;
663 vm_paddr_t pa, max_pa, min_pa;
666 kern_delta = KERNBASE - kernstart;
669 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
670 printf("%lx\n", l1pt);
671 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
673 /* Set this early so we can use the pagetable walking functions */
674 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
675 PMAP_LOCK_INIT(kernel_pmap);
677 /* Assume the address we were loaded to is a valid physical address */
678 min_pa = max_pa = KERNBASE - kern_delta;
681 * Find the minimum physical address. physmap is sorted,
682 * but may contain empty ranges.
684 for (i = 0; i < (physmap_idx * 2); i += 2) {
685 if (physmap[i] == physmap[i + 1])
687 if (physmap[i] <= min_pa)
689 if (physmap[i + 1] > max_pa)
690 max_pa = physmap[i + 1];
693 /* Create a direct map region early so we can use it for pa -> va */
694 pmap_bootstrap_dmap(l1pt, min_pa, max_pa);
697 pa = KERNBASE - kern_delta;
700 * Start to initialise phys_avail by copying from physmap
701 * up to the physical address KERNBASE points at.
703 map_slot = avail_slot = 0;
704 for (; map_slot < (physmap_idx * 2) &&
705 avail_slot < (PHYS_AVAIL_SIZE - 2); map_slot += 2) {
706 if (physmap[map_slot] == physmap[map_slot + 1])
709 if (physmap[map_slot] <= pa &&
710 physmap[map_slot + 1] > pa)
713 phys_avail[avail_slot] = physmap[map_slot];
714 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
715 physmem += (phys_avail[avail_slot + 1] -
716 phys_avail[avail_slot]) >> PAGE_SHIFT;
720 /* Add the memory before the kernel */
721 if (physmap[avail_slot] < pa && avail_slot < (PHYS_AVAIL_SIZE - 2)) {
722 phys_avail[avail_slot] = physmap[map_slot];
723 phys_avail[avail_slot + 1] = pa;
724 physmem += (phys_avail[avail_slot + 1] -
725 phys_avail[avail_slot]) >> PAGE_SHIFT;
728 used_map_slot = map_slot;
731 * Read the page table to find out what is already mapped.
732 * This assumes we have mapped a block of memory from KERNBASE
733 * using a single L1 entry.
735 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
737 /* Sanity check the index, KERNBASE should be the first VA */
738 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
740 /* Find how many pages we have mapped */
741 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
742 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
745 /* Check locore used L2 blocks */
746 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
747 ("Invalid bootstrap L2 table"));
748 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
749 ("Incorrect PA in L2 table"));
755 va = roundup2(va, L1_SIZE);
757 freemempos = KERNBASE + kernlen;
758 freemempos = roundup2(freemempos, PAGE_SIZE);
759 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
760 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
761 /* And the l3 tables for the early devmap */
762 freemempos = pmap_bootstrap_l3(l1pt,
763 VM_MAX_KERNEL_ADDRESS - L2_SIZE, freemempos);
767 #define alloc_pages(var, np) \
768 (var) = freemempos; \
769 freemempos += (np * PAGE_SIZE); \
770 memset((char *)(var), 0, ((np) * PAGE_SIZE));
772 /* Allocate dynamic per-cpu area. */
773 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
774 dpcpu_init((void *)dpcpu, 0);
776 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
777 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
778 msgbufp = (void *)msgbufpv;
780 virtual_avail = roundup2(freemempos, L1_SIZE);
781 virtual_end = VM_MAX_KERNEL_ADDRESS - L2_SIZE;
782 kernel_vm_end = virtual_avail;
784 pa = pmap_early_vtophys(l1pt, freemempos);
786 /* Finish initialising physmap */
787 map_slot = used_map_slot;
788 for (; avail_slot < (PHYS_AVAIL_SIZE - 2) &&
789 map_slot < (physmap_idx * 2); map_slot += 2) {
790 if (physmap[map_slot] == physmap[map_slot + 1])
793 /* Have we used the current range? */
794 if (physmap[map_slot + 1] <= pa)
797 /* Do we need to split the entry? */
798 if (physmap[map_slot] < pa) {
799 phys_avail[avail_slot] = pa;
800 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
802 phys_avail[avail_slot] = physmap[map_slot];
803 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
805 physmem += (phys_avail[avail_slot + 1] -
806 phys_avail[avail_slot]) >> PAGE_SHIFT;
810 phys_avail[avail_slot] = 0;
811 phys_avail[avail_slot + 1] = 0;
814 * Maxmem isn't the "maximum memory", it's one larger than the
815 * highest page of the physical address space. It should be
816 * called something like "Maxphyspage".
818 Maxmem = atop(phys_avail[avail_slot - 1]);
824 * Initialize a vm_page's machine-dependent fields.
827 pmap_page_init(vm_page_t m)
830 TAILQ_INIT(&m->md.pv_list);
831 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
835 * Initialize the pmap module.
836 * Called by vm_init, to initialize any structures that the pmap
837 * system needs to map virtual memory.
846 * Are large page mappings enabled?
848 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
851 * Initialize the pv chunk list mutex.
853 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
856 * Initialize the pool of pv list locks.
858 for (i = 0; i < NPV_LIST_LOCKS; i++)
859 rw_init(&pv_list_locks[i], "pmap pv list");
862 * Calculate the size of the pv head table for superpages.
864 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
867 * Allocate memory for the pv head table for superpages.
869 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
871 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
873 for (i = 0; i < pv_npg; i++)
874 TAILQ_INIT(&pv_table[i].pv_list);
875 TAILQ_INIT(&pv_dummy.pv_list);
878 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
879 "2MB page mapping counters");
881 static u_long pmap_l2_demotions;
882 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
883 &pmap_l2_demotions, 0, "2MB page demotions");
885 static u_long pmap_l2_p_failures;
886 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
887 &pmap_l2_p_failures, 0, "2MB page promotion failures");
889 static u_long pmap_l2_promotions;
890 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
891 &pmap_l2_promotions, 0, "2MB page promotions");
894 * Invalidate a single TLB entry.
897 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
903 "tlbi vaae1is, %0 \n"
906 : : "r"(va >> PAGE_SHIFT));
911 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
917 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
919 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
928 pmap_invalidate_all(pmap_t pmap)
941 * Routine: pmap_extract
943 * Extract the physical page address associated
944 * with the given map/virtual_address pair.
947 pmap_extract(pmap_t pmap, vm_offset_t va)
949 pt_entry_t *pte, tpte;
956 * Find the block or page map for this virtual address. pmap_pte
957 * will return either a valid block/page entry, or NULL.
959 pte = pmap_pte(pmap, va, &lvl);
961 tpte = pmap_load(pte);
962 pa = tpte & ~ATTR_MASK;
965 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
966 ("pmap_extract: Invalid L1 pte found: %lx",
967 tpte & ATTR_DESCR_MASK));
968 pa |= (va & L1_OFFSET);
971 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
972 ("pmap_extract: Invalid L2 pte found: %lx",
973 tpte & ATTR_DESCR_MASK));
974 pa |= (va & L2_OFFSET);
977 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
978 ("pmap_extract: Invalid L3 pte found: %lx",
979 tpte & ATTR_DESCR_MASK));
980 pa |= (va & L3_OFFSET);
989 * Routine: pmap_extract_and_hold
991 * Atomically extract and hold the physical page
992 * with the given pmap and virtual address pair
993 * if that mapping permits the given protection.
996 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
998 pt_entry_t *pte, tpte;
1008 pte = pmap_pte(pmap, va, &lvl);
1010 tpte = pmap_load(pte);
1012 KASSERT(lvl > 0 && lvl <= 3,
1013 ("pmap_extract_and_hold: Invalid level %d", lvl));
1014 CTASSERT(L1_BLOCK == L2_BLOCK);
1015 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1016 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1017 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1018 tpte & ATTR_DESCR_MASK));
1019 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1020 ((prot & VM_PROT_WRITE) == 0)) {
1023 off = va & L1_OFFSET;
1026 off = va & L2_OFFSET;
1032 if (vm_page_pa_tryrelock(pmap,
1033 (tpte & ~ATTR_MASK) | off, &pa))
1035 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1045 pmap_kextract(vm_offset_t va)
1047 pt_entry_t *pte, tpte;
1051 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1052 pa = DMAP_TO_PHYS(va);
1055 pte = pmap_pte(kernel_pmap, va, &lvl);
1057 tpte = pmap_load(pte);
1058 pa = tpte & ~ATTR_MASK;
1061 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1062 ("pmap_kextract: Invalid L1 pte found: %lx",
1063 tpte & ATTR_DESCR_MASK));
1064 pa |= (va & L1_OFFSET);
1067 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1068 ("pmap_kextract: Invalid L2 pte found: %lx",
1069 tpte & ATTR_DESCR_MASK));
1070 pa |= (va & L2_OFFSET);
1073 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1074 ("pmap_kextract: Invalid L3 pte found: %lx",
1075 tpte & ATTR_DESCR_MASK));
1076 pa |= (va & L3_OFFSET);
1084 /***************************************************
1085 * Low level mapping routines.....
1086 ***************************************************/
1089 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1092 pt_entry_t *pte, attr;
1096 KASSERT((pa & L3_OFFSET) == 0,
1097 ("pmap_kenter: Invalid physical address"));
1098 KASSERT((sva & L3_OFFSET) == 0,
1099 ("pmap_kenter: Invalid virtual address"));
1100 KASSERT((size & PAGE_MASK) == 0,
1101 ("pmap_kenter: Mapping is not page-sized"));
1103 attr = ATTR_DEFAULT | ATTR_IDX(mode) | L3_PAGE;
1104 if (mode == DEVICE_MEMORY)
1109 pde = pmap_pde(kernel_pmap, va, &lvl);
1110 KASSERT(pde != NULL,
1111 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1112 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1114 pte = pmap_l2_to_l3(pde, va);
1115 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1121 pmap_invalidate_range(kernel_pmap, sva, va);
1125 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1128 pmap_kenter(sva, size, pa, DEVICE_MEMORY);
1132 * Remove a page from the kernel pagetables.
1135 pmap_kremove(vm_offset_t va)
1140 pte = pmap_pte(kernel_pmap, va, &lvl);
1141 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1142 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1144 pmap_load_clear(pte);
1145 pmap_invalidate_page(kernel_pmap, va);
1149 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1155 KASSERT((sva & L3_OFFSET) == 0,
1156 ("pmap_kremove_device: Invalid virtual address"));
1157 KASSERT((size & PAGE_MASK) == 0,
1158 ("pmap_kremove_device: Mapping is not page-sized"));
1162 pte = pmap_pte(kernel_pmap, va, &lvl);
1163 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1165 ("Invalid device pagetable level: %d != 3", lvl));
1166 pmap_load_clear(pte);
1171 pmap_invalidate_range(kernel_pmap, sva, va);
1175 * Used to map a range of physical addresses into kernel
1176 * virtual address space.
1178 * The value passed in '*virt' is a suggested virtual address for
1179 * the mapping. Architectures which can support a direct-mapped
1180 * physical to virtual region can return the appropriate address
1181 * within that region, leaving '*virt' unchanged. Other
1182 * architectures should map the pages starting at '*virt' and
1183 * update '*virt' with the first usable address after the mapped
1187 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1189 return PHYS_TO_DMAP(start);
1194 * Add a list of wired pages to the kva
1195 * this routine is only used for temporary
1196 * kernel mappings that do not need to have
1197 * page modification or references recorded.
1198 * Note that old mappings are simply written
1199 * over. The page *must* be wired.
1200 * Note: SMP coherent. Uses a ranged shootdown IPI.
1203 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1206 pt_entry_t *pte, pa;
1212 for (i = 0; i < count; i++) {
1213 pde = pmap_pde(kernel_pmap, va, &lvl);
1214 KASSERT(pde != NULL,
1215 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1217 ("pmap_qenter: Invalid level %d", lvl));
1220 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1221 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1222 if (m->md.pv_memattr == DEVICE_MEMORY)
1224 pte = pmap_l2_to_l3(pde, va);
1225 pmap_load_store(pte, pa);
1229 pmap_invalidate_range(kernel_pmap, sva, va);
1233 * This routine tears out page mappings from the
1234 * kernel -- it is meant only for temporary mappings.
1237 pmap_qremove(vm_offset_t sva, int count)
1243 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1246 while (count-- > 0) {
1247 pte = pmap_pte(kernel_pmap, va, &lvl);
1249 ("Invalid device pagetable level: %d != 3", lvl));
1251 pmap_load_clear(pte);
1256 pmap_invalidate_range(kernel_pmap, sva, va);
1259 /***************************************************
1260 * Page table page management routines.....
1261 ***************************************************/
1262 static __inline void
1263 pmap_free_zero_pages(struct spglist *free)
1267 while ((m = SLIST_FIRST(free)) != NULL) {
1268 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1269 /* Preserve the page's PG_ZERO setting. */
1270 vm_page_free_toq(m);
1275 * Schedule the specified unused page table page to be freed. Specifically,
1276 * add the page to the specified list of pages that will be released to the
1277 * physical memory manager after the TLB has been updated.
1279 static __inline void
1280 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1281 boolean_t set_PG_ZERO)
1285 m->flags |= PG_ZERO;
1287 m->flags &= ~PG_ZERO;
1288 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1292 * Decrements a page table page's wire count, which is used to record the
1293 * number of valid page table entries within the page. If the wire count
1294 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1295 * page table page was unmapped and FALSE otherwise.
1297 static inline boolean_t
1298 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1302 if (m->wire_count == 0) {
1303 _pmap_unwire_l3(pmap, va, m, free);
1310 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1313 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1315 * unmap the page table page
1317 if (m->pindex >= (NUL2E + NUL1E)) {
1321 l0 = pmap_l0(pmap, va);
1322 pmap_load_clear(l0);
1323 } else if (m->pindex >= NUL2E) {
1327 l1 = pmap_l1(pmap, va);
1328 pmap_load_clear(l1);
1333 l2 = pmap_l2(pmap, va);
1334 pmap_load_clear(l2);
1336 pmap_resident_count_dec(pmap, 1);
1337 if (m->pindex < NUL2E) {
1338 /* We just released an l3, unhold the matching l2 */
1339 pd_entry_t *l1, tl1;
1342 l1 = pmap_l1(pmap, va);
1343 tl1 = pmap_load(l1);
1344 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1345 pmap_unwire_l3(pmap, va, l2pg, free);
1346 } else if (m->pindex < (NUL2E + NUL1E)) {
1347 /* We just released an l2, unhold the matching l1 */
1348 pd_entry_t *l0, tl0;
1351 l0 = pmap_l0(pmap, va);
1352 tl0 = pmap_load(l0);
1353 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1354 pmap_unwire_l3(pmap, va, l1pg, free);
1356 pmap_invalidate_page(pmap, va);
1359 * This is a release store so that the ordinary store unmapping
1360 * the page table page is globally performed before TLB shoot-
1363 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
1366 * Put page on a list so that it is released after
1367 * *ALL* TLB shootdown is done
1369 pmap_add_delayed_free_list(m, free, TRUE);
1373 * After removing a page table entry, this routine is used to
1374 * conditionally free the page, and manage the hold/wire counts.
1377 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1378 struct spglist *free)
1382 if (va >= VM_MAXUSER_ADDRESS)
1384 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1385 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1386 return (pmap_unwire_l3(pmap, va, mpte, free));
1390 pmap_pinit0(pmap_t pmap)
1393 PMAP_LOCK_INIT(pmap);
1394 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1395 pmap->pm_l0 = kernel_pmap->pm_l0;
1396 pmap->pm_root.rt_root = 0;
1400 pmap_pinit(pmap_t pmap)
1406 * allocate the l0 page
1408 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1409 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1412 l0phys = VM_PAGE_TO_PHYS(l0pt);
1413 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1415 if ((l0pt->flags & PG_ZERO) == 0)
1416 pagezero(pmap->pm_l0);
1418 pmap->pm_root.rt_root = 0;
1419 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1425 * This routine is called if the desired page table page does not exist.
1427 * If page table page allocation fails, this routine may sleep before
1428 * returning NULL. It sleeps only if a lock pointer was given.
1430 * Note: If a page allocation fails at page table level two or three,
1431 * one or two pages may be held during the wait, only to be released
1432 * afterwards. This conservative approach is easily argued to avoid
1436 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1438 vm_page_t m, l1pg, l2pg;
1440 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1443 * Allocate a page table page.
1445 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1446 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1447 if (lockp != NULL) {
1448 RELEASE_PV_LIST_LOCK(lockp);
1455 * Indicate the need to retry. While waiting, the page table
1456 * page may have been allocated.
1460 if ((m->flags & PG_ZERO) == 0)
1464 * Map the pagetable page into the process address space, if
1465 * it isn't already there.
1468 if (ptepindex >= (NUL2E + NUL1E)) {
1470 vm_pindex_t l0index;
1472 l0index = ptepindex - (NUL2E + NUL1E);
1473 l0 = &pmap->pm_l0[l0index];
1474 pmap_load_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1475 } else if (ptepindex >= NUL2E) {
1476 vm_pindex_t l0index, l1index;
1477 pd_entry_t *l0, *l1;
1480 l1index = ptepindex - NUL2E;
1481 l0index = l1index >> L0_ENTRIES_SHIFT;
1483 l0 = &pmap->pm_l0[l0index];
1484 tl0 = pmap_load(l0);
1486 /* recurse for allocating page dir */
1487 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1490 /* XXX: release mem barrier? */
1491 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1492 vm_page_free_zero(m);
1496 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1500 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1501 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1502 pmap_load_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1504 vm_pindex_t l0index, l1index;
1505 pd_entry_t *l0, *l1, *l2;
1506 pd_entry_t tl0, tl1;
1508 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1509 l0index = l1index >> L0_ENTRIES_SHIFT;
1511 l0 = &pmap->pm_l0[l0index];
1512 tl0 = pmap_load(l0);
1514 /* recurse for allocating page dir */
1515 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1518 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1519 vm_page_free_zero(m);
1522 tl0 = pmap_load(l0);
1523 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1524 l1 = &l1[l1index & Ln_ADDR_MASK];
1526 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1527 l1 = &l1[l1index & Ln_ADDR_MASK];
1528 tl1 = pmap_load(l1);
1530 /* recurse for allocating page dir */
1531 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1534 /* XXX: release mem barrier? */
1535 atomic_subtract_int(
1536 &vm_cnt.v_wire_count, 1);
1537 vm_page_free_zero(m);
1541 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1546 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1547 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1548 pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1551 pmap_resident_count_inc(pmap, 1);
1557 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1559 vm_pindex_t ptepindex;
1560 pd_entry_t *pde, tpde;
1568 * Calculate pagetable page index
1570 ptepindex = pmap_l2_pindex(va);
1573 * Get the page directory entry
1575 pde = pmap_pde(pmap, va, &lvl);
1578 * If the page table page is mapped, we just increment the hold count,
1579 * and activate it. If we get a level 2 pde it will point to a level 3
1587 pte = pmap_l0_to_l1(pde, va);
1588 KASSERT(pmap_load(pte) == 0,
1589 ("pmap_alloc_l3: TODO: l0 superpages"));
1594 pte = pmap_l1_to_l2(pde, va);
1595 KASSERT(pmap_load(pte) == 0,
1596 ("pmap_alloc_l3: TODO: l1 superpages"));
1600 tpde = pmap_load(pde);
1602 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1608 panic("pmap_alloc_l3: Invalid level %d", lvl);
1612 * Here if the pte page isn't mapped, or if it has been deallocated.
1614 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1615 if (m == NULL && lockp != NULL)
1622 /***************************************************
1623 * Pmap allocation/deallocation routines.
1624 ***************************************************/
1627 * Release any resources held by the given physical map.
1628 * Called when a pmap initialized by pmap_pinit is being released.
1629 * Should only be called if the map contains no valid mappings.
1632 pmap_release(pmap_t pmap)
1636 KASSERT(pmap->pm_stats.resident_count == 0,
1637 ("pmap_release: pmap resident count %ld != 0",
1638 pmap->pm_stats.resident_count));
1639 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1640 ("pmap_release: pmap has reserved page table page(s)"));
1642 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1645 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1646 vm_page_free_zero(m);
1650 kvm_size(SYSCTL_HANDLER_ARGS)
1652 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1654 return sysctl_handle_long(oidp, &ksize, 0, req);
1656 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1657 0, 0, kvm_size, "LU", "Size of KVM");
1660 kvm_free(SYSCTL_HANDLER_ARGS)
1662 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1664 return sysctl_handle_long(oidp, &kfree, 0, req);
1666 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1667 0, 0, kvm_free, "LU", "Amount of KVM free");
1670 * grow the number of kernel page table entries, if needed
1673 pmap_growkernel(vm_offset_t addr)
1677 pd_entry_t *l0, *l1, *l2;
1679 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1681 addr = roundup2(addr, L2_SIZE);
1682 if (addr - 1 >= kernel_map->max_offset)
1683 addr = kernel_map->max_offset;
1684 while (kernel_vm_end < addr) {
1685 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1686 KASSERT(pmap_load(l0) != 0,
1687 ("pmap_growkernel: No level 0 kernel entry"));
1689 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1690 if (pmap_load(l1) == 0) {
1691 /* We need a new PDP entry */
1692 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1693 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1694 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1696 panic("pmap_growkernel: no memory to grow kernel");
1697 if ((nkpg->flags & PG_ZERO) == 0)
1698 pmap_zero_page(nkpg);
1699 paddr = VM_PAGE_TO_PHYS(nkpg);
1700 pmap_load_store(l1, paddr | L1_TABLE);
1701 continue; /* try again */
1703 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1704 if ((pmap_load(l2) & ATTR_AF) != 0) {
1705 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1706 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1707 kernel_vm_end = kernel_map->max_offset;
1713 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1714 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1717 panic("pmap_growkernel: no memory to grow kernel");
1718 if ((nkpg->flags & PG_ZERO) == 0)
1719 pmap_zero_page(nkpg);
1720 paddr = VM_PAGE_TO_PHYS(nkpg);
1721 pmap_load_store(l2, paddr | L2_TABLE);
1722 pmap_invalidate_page(kernel_pmap, kernel_vm_end);
1724 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1725 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1726 kernel_vm_end = kernel_map->max_offset;
1733 /***************************************************
1734 * page management routines.
1735 ***************************************************/
1737 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1738 CTASSERT(_NPCM == 3);
1739 CTASSERT(_NPCPV == 168);
1741 static __inline struct pv_chunk *
1742 pv_to_chunk(pv_entry_t pv)
1745 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1748 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1750 #define PC_FREE0 0xfffffffffffffffful
1751 #define PC_FREE1 0xfffffffffffffffful
1752 #define PC_FREE2 0x000000fffffffffful
1754 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1758 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1760 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1761 "Current number of pv entry chunks");
1762 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1763 "Current number of pv entry chunks allocated");
1764 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1765 "Current number of pv entry chunks frees");
1766 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1767 "Number of times tried to get a chunk page but failed.");
1769 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1770 static int pv_entry_spare;
1772 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1773 "Current number of pv entry frees");
1774 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1775 "Current number of pv entry allocs");
1776 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1777 "Current number of pv entries");
1778 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1779 "Current number of spare pv entries");
1784 * We are in a serious low memory condition. Resort to
1785 * drastic measures to free some pages so we can allocate
1786 * another pv entry chunk.
1788 * Returns NULL if PV entries were reclaimed from the specified pmap.
1790 * We do not, however, unmap 2mpages because subsequent accesses will
1791 * allocate per-page pv entries until repromotion occurs, thereby
1792 * exacerbating the shortage of free pv entries.
1795 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1797 struct pch new_tail;
1798 struct pv_chunk *pc;
1799 struct md_page *pvh;
1802 pt_entry_t *pte, tpte;
1806 struct spglist free;
1808 int bit, field, freed, lvl;
1810 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1811 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
1815 TAILQ_INIT(&new_tail);
1816 mtx_lock(&pv_chunks_mutex);
1817 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) {
1818 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1819 mtx_unlock(&pv_chunks_mutex);
1820 if (pmap != pc->pc_pmap) {
1821 if (pmap != NULL && pmap != locked_pmap)
1824 /* Avoid deadlock and lock recursion. */
1825 if (pmap > locked_pmap) {
1826 RELEASE_PV_LIST_LOCK(lockp);
1828 } else if (pmap != locked_pmap &&
1829 !PMAP_TRYLOCK(pmap)) {
1831 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1832 mtx_lock(&pv_chunks_mutex);
1838 * Destroy every non-wired, 4 KB page mapping in the chunk.
1841 for (field = 0; field < _NPCM; field++) {
1842 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1843 inuse != 0; inuse &= ~(1UL << bit)) {
1844 bit = ffsl(inuse) - 1;
1845 pv = &pc->pc_pventry[field * 64 + bit];
1847 pde = pmap_pde(pmap, va, &lvl);
1850 pte = pmap_l2_to_l3(pde, va);
1851 tpte = pmap_load(pte);
1852 if ((tpte & ATTR_SW_WIRED) != 0)
1854 tpte = pmap_load_clear(pte);
1855 pmap_invalidate_page(pmap, va);
1856 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
1857 if (pmap_page_dirty(tpte))
1859 if ((tpte & ATTR_AF) != 0)
1860 vm_page_aflag_set(m, PGA_REFERENCED);
1861 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1862 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
1864 if (TAILQ_EMPTY(&m->md.pv_list) &&
1865 (m->flags & PG_FICTITIOUS) == 0) {
1866 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
1867 if (TAILQ_EMPTY(&pvh->pv_list)) {
1868 vm_page_aflag_clear(m,
1872 pc->pc_map[field] |= 1UL << bit;
1873 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
1878 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1879 mtx_lock(&pv_chunks_mutex);
1882 /* Every freed mapping is for a 4 KB page. */
1883 pmap_resident_count_dec(pmap, freed);
1884 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
1885 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
1886 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
1887 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1888 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
1889 pc->pc_map[2] == PC_FREE2) {
1890 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1891 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1892 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1893 /* Entire chunk is free; return it. */
1894 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1895 dump_drop_page(m_pc->phys_addr);
1896 mtx_lock(&pv_chunks_mutex);
1899 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1900 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1901 mtx_lock(&pv_chunks_mutex);
1902 /* One freed pv entry in locked_pmap is sufficient. */
1903 if (pmap == locked_pmap)
1906 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
1907 mtx_unlock(&pv_chunks_mutex);
1908 if (pmap != NULL && pmap != locked_pmap)
1910 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
1911 m_pc = SLIST_FIRST(&free);
1912 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
1913 /* Recycle a freed page table page. */
1914 m_pc->wire_count = 1;
1915 atomic_add_int(&vm_cnt.v_wire_count, 1);
1917 pmap_free_zero_pages(&free);
1922 * free the pv_entry back to the free list
1925 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1927 struct pv_chunk *pc;
1928 int idx, field, bit;
1930 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1931 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
1932 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
1933 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
1934 pc = pv_to_chunk(pv);
1935 idx = pv - &pc->pc_pventry[0];
1938 pc->pc_map[field] |= 1ul << bit;
1939 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
1940 pc->pc_map[2] != PC_FREE2) {
1941 /* 98% of the time, pc is already at the head of the list. */
1942 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
1943 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1944 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1948 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1953 free_pv_chunk(struct pv_chunk *pc)
1957 mtx_lock(&pv_chunks_mutex);
1958 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1959 mtx_unlock(&pv_chunks_mutex);
1960 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1961 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1962 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1963 /* entire chunk is free, return it */
1964 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1965 dump_drop_page(m->phys_addr);
1966 vm_page_unwire(m, PQ_NONE);
1971 * Returns a new PV entry, allocating a new PV chunk from the system when
1972 * needed. If this PV chunk allocation fails and a PV list lock pointer was
1973 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
1976 * The given PV list lock may be released.
1979 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
1983 struct pv_chunk *pc;
1986 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1987 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
1989 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1991 for (field = 0; field < _NPCM; field++) {
1992 if (pc->pc_map[field]) {
1993 bit = ffsl(pc->pc_map[field]) - 1;
1997 if (field < _NPCM) {
1998 pv = &pc->pc_pventry[field * 64 + bit];
1999 pc->pc_map[field] &= ~(1ul << bit);
2000 /* If this was the last item, move it to tail */
2001 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2002 pc->pc_map[2] == 0) {
2003 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2004 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2007 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2008 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2012 /* No free items, allocate another chunk */
2013 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2016 if (lockp == NULL) {
2017 PV_STAT(pc_chunk_tryfail++);
2020 m = reclaim_pv_chunk(pmap, lockp);
2024 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2025 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2026 dump_add_page(m->phys_addr);
2027 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2029 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2030 pc->pc_map[1] = PC_FREE1;
2031 pc->pc_map[2] = PC_FREE2;
2032 mtx_lock(&pv_chunks_mutex);
2033 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2034 mtx_unlock(&pv_chunks_mutex);
2035 pv = &pc->pc_pventry[0];
2036 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2037 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2038 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2043 * Ensure that the number of spare PV entries in the specified pmap meets or
2044 * exceeds the given count, "needed".
2046 * The given PV list lock may be released.
2049 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2051 struct pch new_tail;
2052 struct pv_chunk *pc;
2056 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2057 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2060 * Newly allocated PV chunks must be stored in a private list until
2061 * the required number of PV chunks have been allocated. Otherwise,
2062 * reclaim_pv_chunk() could recycle one of these chunks. In
2063 * contrast, these chunks must be added to the pmap upon allocation.
2065 TAILQ_INIT(&new_tail);
2068 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2069 bit_count((bitstr_t *)pc->pc_map, 0,
2070 sizeof(pc->pc_map) * NBBY, &free);
2074 if (avail >= needed)
2077 for (; avail < needed; avail += _NPCPV) {
2078 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2081 m = reclaim_pv_chunk(pmap, lockp);
2085 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2086 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2087 dump_add_page(m->phys_addr);
2088 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2090 pc->pc_map[0] = PC_FREE0;
2091 pc->pc_map[1] = PC_FREE1;
2092 pc->pc_map[2] = PC_FREE2;
2093 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2094 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2095 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2097 if (!TAILQ_EMPTY(&new_tail)) {
2098 mtx_lock(&pv_chunks_mutex);
2099 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2100 mtx_unlock(&pv_chunks_mutex);
2105 * First find and then remove the pv entry for the specified pmap and virtual
2106 * address from the specified pv list. Returns the pv entry if found and NULL
2107 * otherwise. This operation can be performed on pv lists for either 4KB or
2108 * 2MB page mappings.
2110 static __inline pv_entry_t
2111 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2115 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2116 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2117 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2126 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2127 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2128 * entries for each of the 4KB page mappings.
2131 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2132 struct rwlock **lockp)
2134 struct md_page *pvh;
2135 struct pv_chunk *pc;
2137 vm_offset_t va_last;
2141 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2142 KASSERT((pa & L2_OFFSET) == 0,
2143 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2144 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2147 * Transfer the 2mpage's pv entry for this mapping to the first
2148 * page's pv list. Once this transfer begins, the pv list lock
2149 * must not be released until the last pv entry is reinstantiated.
2151 pvh = pa_to_pvh(pa);
2152 va = va & ~L2_OFFSET;
2153 pv = pmap_pvh_remove(pvh, pmap, va);
2154 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2155 m = PHYS_TO_VM_PAGE(pa);
2156 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2158 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2159 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2160 va_last = va + L2_SIZE - PAGE_SIZE;
2162 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2163 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2164 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2165 for (field = 0; field < _NPCM; field++) {
2166 while (pc->pc_map[field]) {
2167 bit = ffsl(pc->pc_map[field]) - 1;
2168 pc->pc_map[field] &= ~(1ul << bit);
2169 pv = &pc->pc_pventry[field * 64 + bit];
2173 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2174 ("pmap_pv_demote_l2: page %p is not managed", m));
2175 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2181 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2182 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2185 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2186 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2187 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2189 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2190 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2194 * First find and then destroy the pv entry for the specified pmap and virtual
2195 * address. This operation can be performed on pv lists for either 4KB or 2MB
2199 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2203 pv = pmap_pvh_remove(pvh, pmap, va);
2204 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2205 free_pv_entry(pmap, pv);
2209 * Conditionally create the PV entry for a 4KB page mapping if the required
2210 * memory can be allocated without resorting to reclamation.
2213 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2214 struct rwlock **lockp)
2218 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2219 /* Pass NULL instead of the lock pointer to disable reclamation. */
2220 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2222 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2223 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2231 * pmap_remove_l2: do the things to unmap a level 2 superpage in a process
2234 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2235 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2237 struct md_page *pvh;
2239 vm_offset_t eva, va;
2242 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2243 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2244 old_l2 = pmap_load_clear(l2);
2245 pmap_invalidate_range(pmap, sva, sva + L2_SIZE);
2246 if (old_l2 & ATTR_SW_WIRED)
2247 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2248 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2249 if (old_l2 & ATTR_SW_MANAGED) {
2250 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2251 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2252 pmap_pvh_free(pvh, pmap, sva);
2253 eva = sva + L2_SIZE;
2254 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2255 va < eva; va += PAGE_SIZE, m++) {
2256 if (pmap_page_dirty(old_l2))
2258 if (old_l2 & ATTR_AF)
2259 vm_page_aflag_set(m, PGA_REFERENCED);
2260 if (TAILQ_EMPTY(&m->md.pv_list) &&
2261 TAILQ_EMPTY(&pvh->pv_list))
2262 vm_page_aflag_clear(m, PGA_WRITEABLE);
2265 KASSERT(pmap != kernel_pmap,
2266 ("Attempting to remove an l2 kernel page"));
2267 ml3 = pmap_remove_pt_page(pmap, sva);
2269 pmap_resident_count_dec(pmap, 1);
2270 KASSERT(ml3->wire_count == NL3PG,
2271 ("pmap_remove_pages: l3 page wire count error"));
2272 ml3->wire_count = 0;
2273 pmap_add_delayed_free_list(ml3, free, FALSE);
2274 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2276 return (pmap_unuse_pt(pmap, sva, l1e, free));
2280 * pmap_remove_l3: do the things to unmap a page in a process
2283 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2284 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2286 struct md_page *pvh;
2290 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2291 old_l3 = pmap_load_clear(l3);
2292 pmap_invalidate_page(pmap, va);
2293 if (old_l3 & ATTR_SW_WIRED)
2294 pmap->pm_stats.wired_count -= 1;
2295 pmap_resident_count_dec(pmap, 1);
2296 if (old_l3 & ATTR_SW_MANAGED) {
2297 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2298 if (pmap_page_dirty(old_l3))
2300 if (old_l3 & ATTR_AF)
2301 vm_page_aflag_set(m, PGA_REFERENCED);
2302 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2303 pmap_pvh_free(&m->md, pmap, va);
2304 if (TAILQ_EMPTY(&m->md.pv_list) &&
2305 (m->flags & PG_FICTITIOUS) == 0) {
2306 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2307 if (TAILQ_EMPTY(&pvh->pv_list))
2308 vm_page_aflag_clear(m, PGA_WRITEABLE);
2311 return (pmap_unuse_pt(pmap, va, l2e, free));
2315 * Remove the given range of addresses from the specified map.
2317 * It is assumed that the start and end are properly
2318 * rounded to the page size.
2321 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2323 struct rwlock *lock;
2324 vm_offset_t va, va_next;
2325 pd_entry_t *l0, *l1, *l2;
2326 pt_entry_t l3_paddr, *l3;
2327 struct spglist free;
2330 * Perform an unsynchronized read. This is, however, safe.
2332 if (pmap->pm_stats.resident_count == 0)
2340 for (; sva < eva; sva = va_next) {
2342 if (pmap->pm_stats.resident_count == 0)
2345 l0 = pmap_l0(pmap, sva);
2346 if (pmap_load(l0) == 0) {
2347 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2353 l1 = pmap_l0_to_l1(l0, sva);
2354 if (pmap_load(l1) == 0) {
2355 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2362 * Calculate index for next page table.
2364 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2368 l2 = pmap_l1_to_l2(l1, sva);
2372 l3_paddr = pmap_load(l2);
2374 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2375 if (sva + L2_SIZE == va_next && eva >= va_next) {
2376 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2379 } else if (pmap_demote_l2_locked(pmap, l2,
2380 sva &~L2_OFFSET, &lock) == NULL)
2382 l3_paddr = pmap_load(l2);
2386 * Weed out invalid mappings.
2388 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2392 * Limit our scan to either the end of the va represented
2393 * by the current page table page, or to the end of the
2394 * range being removed.
2400 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2403 panic("l3 == NULL");
2404 if (pmap_load(l3) == 0) {
2405 if (va != va_next) {
2406 pmap_invalidate_range(pmap, va, sva);
2413 if (pmap_remove_l3(pmap, l3, sva, l3_paddr, &free,
2420 pmap_invalidate_range(pmap, va, sva);
2425 pmap_free_zero_pages(&free);
2429 * Routine: pmap_remove_all
2431 * Removes this physical page from
2432 * all physical maps in which it resides.
2433 * Reflects back modify bits to the pager.
2436 * Original versions of this routine were very
2437 * inefficient because they iteratively called
2438 * pmap_remove (slow...)
2442 pmap_remove_all(vm_page_t m)
2444 struct md_page *pvh;
2447 struct rwlock *lock;
2448 pd_entry_t *pde, tpde;
2449 pt_entry_t *pte, tpte;
2451 struct spglist free;
2452 int lvl, pvh_gen, md_gen;
2454 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2455 ("pmap_remove_all: page %p is not managed", m));
2457 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2458 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2459 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2462 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2464 if (!PMAP_TRYLOCK(pmap)) {
2465 pvh_gen = pvh->pv_gen;
2469 if (pvh_gen != pvh->pv_gen) {
2476 pte = pmap_pte(pmap, va, &lvl);
2477 KASSERT(pte != NULL,
2478 ("pmap_remove_all: no page table entry found"));
2480 ("pmap_remove_all: invalid pte level %d", lvl));
2482 pmap_demote_l2_locked(pmap, pte, va, &lock);
2485 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2487 if (!PMAP_TRYLOCK(pmap)) {
2488 pvh_gen = pvh->pv_gen;
2489 md_gen = m->md.pv_gen;
2493 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2499 pmap_resident_count_dec(pmap, 1);
2501 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2502 KASSERT(pde != NULL,
2503 ("pmap_remove_all: no page directory entry found"));
2505 ("pmap_remove_all: invalid pde level %d", lvl));
2506 tpde = pmap_load(pde);
2508 pte = pmap_l2_to_l3(pde, pv->pv_va);
2509 tpte = pmap_load(pte);
2510 pmap_load_clear(pte);
2511 pmap_invalidate_page(pmap, pv->pv_va);
2512 if (tpte & ATTR_SW_WIRED)
2513 pmap->pm_stats.wired_count--;
2514 if ((tpte & ATTR_AF) != 0)
2515 vm_page_aflag_set(m, PGA_REFERENCED);
2518 * Update the vm_page_t clean and reference bits.
2520 if (pmap_page_dirty(tpte))
2522 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2523 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2525 free_pv_entry(pmap, pv);
2528 vm_page_aflag_clear(m, PGA_WRITEABLE);
2530 pmap_free_zero_pages(&free);
2534 * Set the physical protection on the
2535 * specified range of this map as requested.
2538 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2540 vm_offset_t va, va_next;
2541 pd_entry_t *l0, *l1, *l2;
2542 pt_entry_t *l3p, l3, nbits;
2544 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
2545 if (prot == VM_PROT_NONE) {
2546 pmap_remove(pmap, sva, eva);
2550 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
2551 (VM_PROT_WRITE | VM_PROT_EXECUTE))
2555 for (; sva < eva; sva = va_next) {
2557 l0 = pmap_l0(pmap, sva);
2558 if (pmap_load(l0) == 0) {
2559 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2565 l1 = pmap_l0_to_l1(l0, sva);
2566 if (pmap_load(l1) == 0) {
2567 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2573 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2577 l2 = pmap_l1_to_l2(l1, sva);
2578 if (pmap_load(l2) == 0)
2581 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
2582 l3p = pmap_demote_l2(pmap, l2, sva);
2586 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
2587 ("pmap_protect: Invalid L2 entry after demotion"));
2593 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2595 l3 = pmap_load(l3p);
2596 if (!pmap_l3_valid(l3))
2600 if ((prot & VM_PROT_WRITE) == 0) {
2601 if ((l3 & ATTR_SW_MANAGED) &&
2602 pmap_page_dirty(l3)) {
2603 vm_page_dirty(PHYS_TO_VM_PAGE(l3 &
2606 nbits |= ATTR_AP(ATTR_AP_RO);
2608 if ((prot & VM_PROT_EXECUTE) == 0)
2611 pmap_set(l3p, nbits);
2612 /* XXX: Use pmap_invalidate_range */
2613 pmap_invalidate_page(pmap, sva);
2620 * Inserts the specified page table page into the specified pmap's collection
2621 * of idle page table pages. Each of a pmap's page table pages is responsible
2622 * for mapping a distinct range of virtual addresses. The pmap's collection is
2623 * ordered by this virtual address range.
2626 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2629 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2630 return (vm_radix_insert(&pmap->pm_root, mpte));
2634 * Removes the page table page mapping the specified virtual address from the
2635 * specified pmap's collection of idle page table pages, and returns it.
2636 * Otherwise, returns NULL if there is no page table page corresponding to the
2637 * specified virtual address.
2639 static __inline vm_page_t
2640 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2643 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2644 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
2648 * Performs a break-before-make update of a pmap entry. This is needed when
2649 * either promoting or demoting pages to ensure the TLB doesn't get into an
2650 * inconsistent state.
2653 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
2654 vm_offset_t va, vm_size_t size)
2658 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2661 * Ensure we don't get switched out with the page table in an
2662 * inconsistent state. We also need to ensure no interrupts fire
2663 * as they may make use of an address we are about to invalidate.
2665 intr = intr_disable();
2668 /* Clear the old mapping */
2669 pmap_load_clear(pte);
2670 pmap_invalidate_range(pmap, va, va + size);
2672 /* Create the new mapping */
2673 pmap_load_store(pte, newpte);
2679 #if VM_NRESERVLEVEL > 0
2681 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
2682 * replace the many pv entries for the 4KB page mappings by a single pv entry
2683 * for the 2MB page mapping.
2686 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2687 struct rwlock **lockp)
2689 struct md_page *pvh;
2691 vm_offset_t va_last;
2694 KASSERT((pa & L2_OFFSET) == 0,
2695 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
2696 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2699 * Transfer the first page's pv entry for this mapping to the 2mpage's
2700 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
2701 * a transfer avoids the possibility that get_pv_entry() calls
2702 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
2703 * mappings that is being promoted.
2705 m = PHYS_TO_VM_PAGE(pa);
2706 va = va & ~L2_OFFSET;
2707 pv = pmap_pvh_remove(&m->md, pmap, va);
2708 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
2709 pvh = pa_to_pvh(pa);
2710 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2712 /* Free the remaining NPTEPG - 1 pv entries. */
2713 va_last = va + L2_SIZE - PAGE_SIZE;
2717 pmap_pvh_free(&m->md, pmap, va);
2718 } while (va < va_last);
2722 * Tries to promote the 512, contiguous 4KB page mappings that are within a
2723 * single level 2 table entry to a single 2MB page mapping. For promotion
2724 * to occur, two conditions must be met: (1) the 4KB page mappings must map
2725 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
2726 * identical characteristics.
2729 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
2730 struct rwlock **lockp)
2732 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
2736 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2738 sva = va & ~L2_OFFSET;
2739 firstl3 = pmap_l2_to_l3(l2, sva);
2740 newl2 = pmap_load(firstl3);
2742 /* Check the alingment is valid */
2743 if (((newl2 & ~ATTR_MASK) & L2_OFFSET) != 0) {
2744 atomic_add_long(&pmap_l2_p_failures, 1);
2745 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2746 " in pmap %p", va, pmap);
2750 pa = newl2 + L2_SIZE - PAGE_SIZE;
2751 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
2752 oldl3 = pmap_load(l3);
2754 atomic_add_long(&pmap_l2_p_failures, 1);
2755 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2756 " in pmap %p", va, pmap);
2763 * Save the page table page in its current state until the L2
2764 * mapping the superpage is demoted by pmap_demote_l2() or
2765 * destroyed by pmap_remove_l3().
2767 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
2768 KASSERT(mpte >= vm_page_array &&
2769 mpte < &vm_page_array[vm_page_array_size],
2770 ("pmap_promote_l2: page table page is out of range"));
2771 KASSERT(mpte->pindex == pmap_l2_pindex(va),
2772 ("pmap_promote_l2: page table page's pindex is wrong"));
2773 if (pmap_insert_pt_page(pmap, mpte)) {
2774 atomic_add_long(&pmap_l2_p_failures, 1);
2776 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
2781 if ((newl2 & ATTR_SW_MANAGED) != 0)
2782 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
2784 newl2 &= ~ATTR_DESCR_MASK;
2787 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
2789 atomic_add_long(&pmap_l2_promotions, 1);
2790 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
2793 #endif /* VM_NRESERVLEVEL > 0 */
2796 * Insert the given physical page (p) at
2797 * the specified virtual address (v) in the
2798 * target physical map with the protection requested.
2800 * If specified, the page will be wired down, meaning
2801 * that the related pte can not be reclaimed.
2803 * NB: This is the only routine which MAY NOT lazy-evaluate
2804 * or lose information. That is, this routine must actually
2805 * insert this page into the given map NOW.
2808 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2809 u_int flags, int8_t psind __unused)
2811 struct rwlock *lock;
2813 pt_entry_t new_l3, orig_l3;
2814 pt_entry_t *l2, *l3;
2816 vm_paddr_t opa, pa, l1_pa, l2_pa, l3_pa;
2817 vm_page_t mpte, om, l1_m, l2_m, l3_m;
2821 va = trunc_page(va);
2822 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2823 VM_OBJECT_ASSERT_LOCKED(m->object);
2824 pa = VM_PAGE_TO_PHYS(m);
2825 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
2827 if ((prot & VM_PROT_WRITE) == 0)
2828 new_l3 |= ATTR_AP(ATTR_AP_RO);
2829 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
2831 if ((flags & PMAP_ENTER_WIRED) != 0)
2832 new_l3 |= ATTR_SW_WIRED;
2833 if (va < VM_MAXUSER_ADDRESS)
2834 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
2836 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
2843 pde = pmap_pde(pmap, va, &lvl);
2844 if (pde != NULL && lvl == 1) {
2845 l2 = pmap_l1_to_l2(pde, va);
2846 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
2847 (l3 = pmap_demote_l2_locked(pmap, l2, va & ~L2_OFFSET,
2849 l3 = &l3[pmap_l3_index(va)];
2850 if (va < VM_MAXUSER_ADDRESS) {
2851 mpte = PHYS_TO_VM_PAGE(
2852 pmap_load(l2) & ~ATTR_MASK);
2859 if (va < VM_MAXUSER_ADDRESS) {
2860 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
2861 mpte = pmap_alloc_l3(pmap, va, nosleep ? NULL : &lock);
2862 if (mpte == NULL && nosleep) {
2863 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
2867 return (KERN_RESOURCE_SHORTAGE);
2869 pde = pmap_pde(pmap, va, &lvl);
2870 KASSERT(pde != NULL,
2871 ("pmap_enter: Invalid page entry, va: 0x%lx", va));
2873 ("pmap_enter: Invalid level %d", lvl));
2875 l3 = pmap_l2_to_l3(pde, va);
2878 * If we get a level 2 pde it must point to a level 3 entry
2879 * otherwise we will need to create the intermediate tables
2885 /* Get the l0 pde to update */
2886 pde = pmap_l0(pmap, va);
2887 KASSERT(pde != NULL, ("..."));
2889 l1_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2890 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2893 panic("pmap_enter: l1 pte_m == NULL");
2894 if ((l1_m->flags & PG_ZERO) == 0)
2895 pmap_zero_page(l1_m);
2897 l1_pa = VM_PAGE_TO_PHYS(l1_m);
2898 pmap_load_store(pde, l1_pa | L0_TABLE);
2901 /* Get the l1 pde to update */
2902 pde = pmap_l1_to_l2(pde, va);
2903 KASSERT(pde != NULL, ("..."));
2905 l2_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2906 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2909 panic("pmap_enter: l2 pte_m == NULL");
2910 if ((l2_m->flags & PG_ZERO) == 0)
2911 pmap_zero_page(l2_m);
2913 l2_pa = VM_PAGE_TO_PHYS(l2_m);
2914 pmap_load_store(pde, l2_pa | L1_TABLE);
2917 /* Get the l2 pde to update */
2918 pde = pmap_l1_to_l2(pde, va);
2920 l3_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2921 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2924 panic("pmap_enter: l3 pte_m == NULL");
2925 if ((l3_m->flags & PG_ZERO) == 0)
2926 pmap_zero_page(l3_m);
2928 l3_pa = VM_PAGE_TO_PHYS(l3_m);
2929 pmap_load_store(pde, l3_pa | L2_TABLE);
2933 l3 = pmap_l2_to_l3(pde, va);
2934 pmap_invalidate_page(pmap, va);
2939 orig_l3 = pmap_load(l3);
2940 opa = orig_l3 & ~ATTR_MASK;
2943 * Is the specified virtual address already mapped?
2945 if (pmap_l3_valid(orig_l3)) {
2947 * Wiring change, just update stats. We don't worry about
2948 * wiring PT pages as they remain resident as long as there
2949 * are valid mappings in them. Hence, if a user page is wired,
2950 * the PT page will be also.
2952 if ((flags & PMAP_ENTER_WIRED) != 0 &&
2953 (orig_l3 & ATTR_SW_WIRED) == 0)
2954 pmap->pm_stats.wired_count++;
2955 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
2956 (orig_l3 & ATTR_SW_WIRED) != 0)
2957 pmap->pm_stats.wired_count--;
2960 * Remove the extra PT page reference.
2964 KASSERT(mpte->wire_count > 0,
2965 ("pmap_enter: missing reference to page table page,"
2970 * Has the physical page changed?
2974 * No, might be a protection or wiring change.
2976 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
2977 new_l3 |= ATTR_SW_MANAGED;
2978 if ((new_l3 & ATTR_AP(ATTR_AP_RW)) ==
2979 ATTR_AP(ATTR_AP_RW)) {
2980 vm_page_aflag_set(m, PGA_WRITEABLE);
2987 * Increment the counters.
2989 if ((new_l3 & ATTR_SW_WIRED) != 0)
2990 pmap->pm_stats.wired_count++;
2991 pmap_resident_count_inc(pmap, 1);
2994 * Enter on the PV list if part of our managed memory.
2996 if ((m->oflags & VPO_UNMANAGED) == 0) {
2997 new_l3 |= ATTR_SW_MANAGED;
2998 pv = get_pv_entry(pmap, &lock);
3000 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3001 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3003 if ((new_l3 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3004 vm_page_aflag_set(m, PGA_WRITEABLE);
3008 * Update the L3 entry.
3012 orig_l3 = pmap_load(l3);
3013 opa = orig_l3 & ~ATTR_MASK;
3016 pmap_update_entry(pmap, l3, new_l3, va, PAGE_SIZE);
3017 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3018 om = PHYS_TO_VM_PAGE(opa);
3019 if (pmap_page_dirty(orig_l3))
3021 if ((orig_l3 & ATTR_AF) != 0)
3022 vm_page_aflag_set(om, PGA_REFERENCED);
3023 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3024 pmap_pvh_free(&om->md, pmap, va);
3025 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3026 TAILQ_EMPTY(&om->md.pv_list) &&
3027 ((om->flags & PG_FICTITIOUS) != 0 ||
3028 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3029 vm_page_aflag_clear(om, PGA_WRITEABLE);
3032 pmap_load_store(l3, new_l3);
3033 pmap_invalidate_page(pmap, va);
3034 if (pmap_page_dirty(orig_l3) &&
3035 (orig_l3 & ATTR_SW_MANAGED) != 0)
3039 pmap_load_store(l3, new_l3);
3042 pmap_invalidate_page(pmap, va);
3044 if (pmap != pmap_kernel()) {
3045 if (pmap == &curproc->p_vmspace->vm_pmap &&
3046 (prot & VM_PROT_EXECUTE) != 0)
3047 cpu_icache_sync_range(va, PAGE_SIZE);
3049 #if VM_NRESERVLEVEL > 0
3050 if ((mpte == NULL || mpte->wire_count == NL3PG) &&
3051 pmap_superpages_enabled() &&
3052 (m->flags & PG_FICTITIOUS) == 0 &&
3053 vm_reserv_level_iffullpop(m) == 0) {
3054 pmap_promote_l2(pmap, pde, va, &lock);
3062 return (KERN_SUCCESS);
3066 * Maps a sequence of resident pages belonging to the same object.
3067 * The sequence begins with the given page m_start. This page is
3068 * mapped at the given virtual address start. Each subsequent page is
3069 * mapped at a virtual address that is offset from start by the same
3070 * amount as the page is offset from m_start within the object. The
3071 * last page in the sequence is the page with the largest offset from
3072 * m_start that can be mapped at a virtual address less than the given
3073 * virtual address end. Not every virtual page between start and end
3074 * is mapped; only those for which a resident page exists with the
3075 * corresponding offset from m_start are mapped.
3078 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3079 vm_page_t m_start, vm_prot_t prot)
3081 struct rwlock *lock;
3084 vm_pindex_t diff, psize;
3086 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3088 psize = atop(end - start);
3093 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3094 va = start + ptoa(diff);
3095 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte, &lock);
3096 m = TAILQ_NEXT(m, listq);
3104 * this code makes some *MAJOR* assumptions:
3105 * 1. Current pmap & pmap exists.
3108 * 4. No page table pages.
3109 * but is *MUCH* faster than pmap_enter...
3113 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3115 struct rwlock *lock;
3119 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3126 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3127 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3129 struct spglist free;
3131 pt_entry_t *l2, *l3;
3135 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3136 (m->oflags & VPO_UNMANAGED) != 0,
3137 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3138 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3140 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3142 * In the case that a page table page is not
3143 * resident, we are creating it here.
3145 if (va < VM_MAXUSER_ADDRESS) {
3146 vm_pindex_t l2pindex;
3149 * Calculate pagetable page index
3151 l2pindex = pmap_l2_pindex(va);
3152 if (mpte && (mpte->pindex == l2pindex)) {
3158 pde = pmap_pde(pmap, va, &lvl);
3161 * If the page table page is mapped, we just increment
3162 * the hold count, and activate it. Otherwise, we
3163 * attempt to allocate a page table page. If this
3164 * attempt fails, we don't retry. Instead, we give up.
3167 l2 = pmap_l1_to_l2(pde, va);
3168 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3172 if (lvl == 2 && pmap_load(pde) != 0) {
3174 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3178 * Pass NULL instead of the PV list lock
3179 * pointer, because we don't intend to sleep.
3181 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3186 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3187 l3 = &l3[pmap_l3_index(va)];
3190 pde = pmap_pde(kernel_pmap, va, &lvl);
3191 KASSERT(pde != NULL,
3192 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3195 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3196 l3 = pmap_l2_to_l3(pde, va);
3199 if (pmap_load(l3) != 0) {
3208 * Enter on the PV list if part of our managed memory.
3210 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3211 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3214 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
3215 pmap_invalidate_page(pmap, va);
3216 pmap_free_zero_pages(&free);
3224 * Increment counters
3226 pmap_resident_count_inc(pmap, 1);
3228 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3229 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3230 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3232 else if (va < VM_MAXUSER_ADDRESS)
3236 * Now validate mapping with RO protection
3238 if ((m->oflags & VPO_UNMANAGED) == 0)
3239 pa |= ATTR_SW_MANAGED;
3240 pmap_load_store(l3, pa);
3241 pmap_invalidate_page(pmap, va);
3246 * This code maps large physical mmap regions into the
3247 * processor address space. Note that some shortcuts
3248 * are taken, but the code works.
3251 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3252 vm_pindex_t pindex, vm_size_t size)
3255 VM_OBJECT_ASSERT_WLOCKED(object);
3256 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3257 ("pmap_object_init_pt: non-device object"));
3261 * Clear the wired attribute from the mappings for the specified range of
3262 * addresses in the given pmap. Every valid mapping within that range
3263 * must have the wired attribute set. In contrast, invalid mappings
3264 * cannot have the wired attribute set, so they are ignored.
3266 * The wired attribute of the page table entry is not a hardware feature,
3267 * so there is no need to invalidate any TLB entries.
3270 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3272 vm_offset_t va_next;
3273 pd_entry_t *l0, *l1, *l2;
3277 for (; sva < eva; sva = va_next) {
3278 l0 = pmap_l0(pmap, sva);
3279 if (pmap_load(l0) == 0) {
3280 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3286 l1 = pmap_l0_to_l1(l0, sva);
3287 if (pmap_load(l1) == 0) {
3288 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3294 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3298 l2 = pmap_l1_to_l2(l1, sva);
3299 if (pmap_load(l2) == 0)
3302 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3303 l3 = pmap_demote_l2(pmap, l2, sva);
3307 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3308 ("pmap_unwire: Invalid l2 entry after demotion"));
3312 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3314 if (pmap_load(l3) == 0)
3316 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
3317 panic("pmap_unwire: l3 %#jx is missing "
3318 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
3321 * PG_W must be cleared atomically. Although the pmap
3322 * lock synchronizes access to PG_W, another processor
3323 * could be setting PG_M and/or PG_A concurrently.
3325 atomic_clear_long(l3, ATTR_SW_WIRED);
3326 pmap->pm_stats.wired_count--;
3333 * Copy the range specified by src_addr/len
3334 * from the source map to the range dst_addr/len
3335 * in the destination map.
3337 * This routine is only advisory and need not do anything.
3341 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3342 vm_offset_t src_addr)
3347 * pmap_zero_page zeros the specified hardware page by mapping
3348 * the page into KVM and using bzero to clear its contents.
3351 pmap_zero_page(vm_page_t m)
3353 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3355 pagezero((void *)va);
3359 * pmap_zero_page_area zeros the specified hardware page by mapping
3360 * the page into KVM and using bzero to clear its contents.
3362 * off and size may not cover an area beyond a single hardware page.
3365 pmap_zero_page_area(vm_page_t m, int off, int size)
3367 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3369 if (off == 0 && size == PAGE_SIZE)
3370 pagezero((void *)va);
3372 bzero((char *)va + off, size);
3376 * pmap_copy_page copies the specified (machine independent)
3377 * page by mapping the page into virtual memory and using
3378 * bcopy to copy the page, one machine dependent page at a
3382 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
3384 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
3385 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
3387 pagecopy((void *)src, (void *)dst);
3390 int unmapped_buf_allowed = 1;
3393 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
3394 vm_offset_t b_offset, int xfersize)
3398 vm_paddr_t p_a, p_b;
3399 vm_offset_t a_pg_offset, b_pg_offset;
3402 while (xfersize > 0) {
3403 a_pg_offset = a_offset & PAGE_MASK;
3404 m_a = ma[a_offset >> PAGE_SHIFT];
3405 p_a = m_a->phys_addr;
3406 b_pg_offset = b_offset & PAGE_MASK;
3407 m_b = mb[b_offset >> PAGE_SHIFT];
3408 p_b = m_b->phys_addr;
3409 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
3410 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
3411 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
3412 panic("!DMAP a %lx", p_a);
3414 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
3416 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
3417 panic("!DMAP b %lx", p_b);
3419 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
3421 bcopy(a_cp, b_cp, cnt);
3429 pmap_quick_enter_page(vm_page_t m)
3432 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
3436 pmap_quick_remove_page(vm_offset_t addr)
3441 * Returns true if the pmap's pv is one of the first
3442 * 16 pvs linked to from this page. This count may
3443 * be changed upwards or downwards in the future; it
3444 * is only necessary that true be returned for a small
3445 * subset of pmaps for proper page aging.
3448 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3450 struct md_page *pvh;
3451 struct rwlock *lock;
3456 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3457 ("pmap_page_exists_quick: page %p is not managed", m));
3459 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3461 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3462 if (PV_PMAP(pv) == pmap) {
3470 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
3471 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3472 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3473 if (PV_PMAP(pv) == pmap) {
3487 * pmap_page_wired_mappings:
3489 * Return the number of managed mappings to the given physical page
3493 pmap_page_wired_mappings(vm_page_t m)
3495 struct rwlock *lock;
3496 struct md_page *pvh;
3500 int count, lvl, md_gen, pvh_gen;
3502 if ((m->oflags & VPO_UNMANAGED) != 0)
3504 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3508 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3510 if (!PMAP_TRYLOCK(pmap)) {
3511 md_gen = m->md.pv_gen;
3515 if (md_gen != m->md.pv_gen) {
3520 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3521 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3525 if ((m->flags & PG_FICTITIOUS) == 0) {
3526 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3527 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3529 if (!PMAP_TRYLOCK(pmap)) {
3530 md_gen = m->md.pv_gen;
3531 pvh_gen = pvh->pv_gen;
3535 if (md_gen != m->md.pv_gen ||
3536 pvh_gen != pvh->pv_gen) {
3541 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3543 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3553 * Destroy all managed, non-wired mappings in the given user-space
3554 * pmap. This pmap cannot be active on any processor besides the
3557 * This function cannot be applied to the kernel pmap. Moreover, it
3558 * is not intended for general use. It is only to be used during
3559 * process termination. Consequently, it can be implemented in ways
3560 * that make it faster than pmap_remove(). First, it can more quickly
3561 * destroy mappings by iterating over the pmap's collection of PV
3562 * entries, rather than searching the page table. Second, it doesn't
3563 * have to test and clear the page table entries atomically, because
3564 * no processor is currently accessing the user address space. In
3565 * particular, a page table entry's dirty bit won't change state once
3566 * this function starts.
3569 pmap_remove_pages(pmap_t pmap)
3572 pt_entry_t *pte, tpte;
3573 struct spglist free;
3574 vm_page_t m, ml3, mt;
3576 struct md_page *pvh;
3577 struct pv_chunk *pc, *npc;
3578 struct rwlock *lock;
3580 uint64_t inuse, bitmask;
3581 int allfree, field, freed, idx, lvl;
3588 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
3591 for (field = 0; field < _NPCM; field++) {
3592 inuse = ~pc->pc_map[field] & pc_freemask[field];
3593 while (inuse != 0) {
3594 bit = ffsl(inuse) - 1;
3595 bitmask = 1UL << bit;
3596 idx = field * 64 + bit;
3597 pv = &pc->pc_pventry[idx];
3600 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3601 KASSERT(pde != NULL,
3602 ("Attempting to remove an unmapped page"));
3606 pte = pmap_l1_to_l2(pde, pv->pv_va);
3607 tpte = pmap_load(pte);
3608 KASSERT((tpte & ATTR_DESCR_MASK) ==
3610 ("Attempting to remove an invalid "
3611 "block: %lx", tpte));
3612 tpte = pmap_load(pte);
3615 pte = pmap_l2_to_l3(pde, pv->pv_va);
3616 tpte = pmap_load(pte);
3617 KASSERT((tpte & ATTR_DESCR_MASK) ==
3619 ("Attempting to remove an invalid "
3620 "page: %lx", tpte));
3624 "Invalid page directory level: %d",
3629 * We cannot remove wired pages from a process' mapping at this time
3631 if (tpte & ATTR_SW_WIRED) {
3636 pa = tpte & ~ATTR_MASK;
3638 m = PHYS_TO_VM_PAGE(pa);
3639 KASSERT(m->phys_addr == pa,
3640 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
3641 m, (uintmax_t)m->phys_addr,
3644 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
3645 m < &vm_page_array[vm_page_array_size],
3646 ("pmap_remove_pages: bad pte %#jx",
3649 pmap_load_clear(pte);
3652 * Update the vm_page_t clean/reference bits.
3654 if ((tpte & ATTR_AP_RW_BIT) ==
3655 ATTR_AP(ATTR_AP_RW)) {
3658 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3667 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
3670 pc->pc_map[field] |= bitmask;
3673 pmap_resident_count_dec(pmap,
3674 L2_SIZE / PAGE_SIZE);
3675 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
3676 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
3678 if (TAILQ_EMPTY(&pvh->pv_list)) {
3679 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3680 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
3681 TAILQ_EMPTY(&mt->md.pv_list))
3682 vm_page_aflag_clear(mt, PGA_WRITEABLE);
3684 ml3 = pmap_remove_pt_page(pmap,
3687 pmap_resident_count_dec(pmap,1);
3688 KASSERT(ml3->wire_count == NL3PG,
3689 ("pmap_remove_pages: l3 page wire count error"));
3690 ml3->wire_count = 0;
3691 pmap_add_delayed_free_list(ml3,
3693 atomic_subtract_int(
3694 &vm_cnt.v_wire_count, 1);
3698 pmap_resident_count_dec(pmap, 1);
3699 TAILQ_REMOVE(&m->md.pv_list, pv,
3702 if ((m->aflags & PGA_WRITEABLE) != 0 &&
3703 TAILQ_EMPTY(&m->md.pv_list) &&
3704 (m->flags & PG_FICTITIOUS) == 0) {
3706 VM_PAGE_TO_PHYS(m));
3707 if (TAILQ_EMPTY(&pvh->pv_list))
3708 vm_page_aflag_clear(m,
3713 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
3718 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3719 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3720 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3722 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3726 pmap_invalidate_all(pmap);
3730 pmap_free_zero_pages(&free);
3734 * This is used to check if a page has been accessed or modified. As we
3735 * don't have a bit to see if it has been modified we have to assume it
3736 * has been if the page is read/write.
3739 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
3741 struct rwlock *lock;
3743 struct md_page *pvh;
3744 pt_entry_t *pte, mask, value;
3746 int lvl, md_gen, pvh_gen;
3750 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3753 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3755 if (!PMAP_TRYLOCK(pmap)) {
3756 md_gen = m->md.pv_gen;
3760 if (md_gen != m->md.pv_gen) {
3765 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3767 ("pmap_page_test_mappings: Invalid level %d", lvl));
3771 mask |= ATTR_AP_RW_BIT;
3772 value |= ATTR_AP(ATTR_AP_RW);
3775 mask |= ATTR_AF | ATTR_DESCR_MASK;
3776 value |= ATTR_AF | L3_PAGE;
3778 rv = (pmap_load(pte) & mask) == value;
3783 if ((m->flags & PG_FICTITIOUS) == 0) {
3784 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3785 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3787 if (!PMAP_TRYLOCK(pmap)) {
3788 md_gen = m->md.pv_gen;
3789 pvh_gen = pvh->pv_gen;
3793 if (md_gen != m->md.pv_gen ||
3794 pvh_gen != pvh->pv_gen) {
3799 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3801 ("pmap_page_test_mappings: Invalid level %d", lvl));
3805 mask |= ATTR_AP_RW_BIT;
3806 value |= ATTR_AP(ATTR_AP_RW);
3809 mask |= ATTR_AF | ATTR_DESCR_MASK;
3810 value |= ATTR_AF | L2_BLOCK;
3812 rv = (pmap_load(pte) & mask) == value;
3826 * Return whether or not the specified physical page was modified
3827 * in any physical maps.
3830 pmap_is_modified(vm_page_t m)
3833 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3834 ("pmap_is_modified: page %p is not managed", m));
3837 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3838 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
3839 * is clear, no PTEs can have PG_M set.
3841 VM_OBJECT_ASSERT_WLOCKED(m->object);
3842 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3844 return (pmap_page_test_mappings(m, FALSE, TRUE));
3848 * pmap_is_prefaultable:
3850 * Return whether or not the specified virtual address is eligible
3854 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3862 pte = pmap_pte(pmap, addr, &lvl);
3863 if (pte != NULL && pmap_load(pte) != 0) {
3871 * pmap_is_referenced:
3873 * Return whether or not the specified physical page was referenced
3874 * in any physical maps.
3877 pmap_is_referenced(vm_page_t m)
3880 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3881 ("pmap_is_referenced: page %p is not managed", m));
3882 return (pmap_page_test_mappings(m, TRUE, FALSE));
3886 * Clear the write and modified bits in each of the given page's mappings.
3889 pmap_remove_write(vm_page_t m)
3891 struct md_page *pvh;
3893 struct rwlock *lock;
3894 pv_entry_t next_pv, pv;
3895 pt_entry_t oldpte, *pte;
3897 int lvl, md_gen, pvh_gen;
3899 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3900 ("pmap_remove_write: page %p is not managed", m));
3903 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3904 * set by another thread while the object is locked. Thus,
3905 * if PGA_WRITEABLE is clear, no page table entries need updating.
3907 VM_OBJECT_ASSERT_WLOCKED(m->object);
3908 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3910 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3911 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
3912 pa_to_pvh(VM_PAGE_TO_PHYS(m));
3915 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
3917 if (!PMAP_TRYLOCK(pmap)) {
3918 pvh_gen = pvh->pv_gen;
3922 if (pvh_gen != pvh->pv_gen) {
3929 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3930 if ((pmap_load(pte) & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3931 pmap_demote_l2_locked(pmap, pte, va & ~L2_OFFSET,
3933 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
3934 ("inconsistent pv lock %p %p for page %p",
3935 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
3938 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3940 if (!PMAP_TRYLOCK(pmap)) {
3941 pvh_gen = pvh->pv_gen;
3942 md_gen = m->md.pv_gen;
3946 if (pvh_gen != pvh->pv_gen ||
3947 md_gen != m->md.pv_gen) {
3953 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3955 oldpte = pmap_load(pte);
3956 if ((oldpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) {
3957 if (!atomic_cmpset_long(pte, oldpte,
3958 oldpte | ATTR_AP(ATTR_AP_RO)))
3960 if ((oldpte & ATTR_AF) != 0)
3962 pmap_invalidate_page(pmap, pv->pv_va);
3967 vm_page_aflag_clear(m, PGA_WRITEABLE);
3970 static __inline boolean_t
3971 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
3978 * pmap_ts_referenced:
3980 * Return a count of reference bits for a page, clearing those bits.
3981 * It is not necessary for every reference bit to be cleared, but it
3982 * is necessary that 0 only be returned when there are truly no
3983 * reference bits set.
3985 * As an optimization, update the page's dirty field if a modified bit is
3986 * found while counting reference bits. This opportunistic update can be
3987 * performed at low cost and can eliminate the need for some future calls
3988 * to pmap_is_modified(). However, since this function stops after
3989 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
3990 * dirty pages. Those dirty pages will only be detected by a future call
3991 * to pmap_is_modified().
3994 pmap_ts_referenced(vm_page_t m)
3996 struct md_page *pvh;
3999 struct rwlock *lock;
4000 pd_entry_t *pde, tpde;
4001 pt_entry_t *pte, tpte;
4005 int cleared, md_gen, not_cleared, lvl, pvh_gen;
4006 struct spglist free;
4009 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4010 ("pmap_ts_referenced: page %p is not managed", m));
4013 pa = VM_PAGE_TO_PHYS(m);
4014 lock = PHYS_TO_PV_LIST_LOCK(pa);
4015 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4019 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4020 goto small_mappings;
4026 if (!PMAP_TRYLOCK(pmap)) {
4027 pvh_gen = pvh->pv_gen;
4031 if (pvh_gen != pvh->pv_gen) {
4037 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4038 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4040 ("pmap_ts_referenced: invalid pde level %d", lvl));
4041 tpde = pmap_load(pde);
4042 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4043 ("pmap_ts_referenced: found an invalid l1 table"));
4044 pte = pmap_l1_to_l2(pde, pv->pv_va);
4045 tpte = pmap_load(pte);
4046 if (pmap_page_dirty(tpte)) {
4048 * Although "tpte" is mapping a 2MB page, because
4049 * this function is called at a 4KB page granularity,
4050 * we only update the 4KB page under test.
4054 if ((tpte & ATTR_AF) != 0) {
4056 * Since this reference bit is shared by 512 4KB
4057 * pages, it should not be cleared every time it is
4058 * tested. Apply a simple "hash" function on the
4059 * physical page number, the virtual superpage number,
4060 * and the pmap address to select one 4KB page out of
4061 * the 512 on which testing the reference bit will
4062 * result in clearing that reference bit. This
4063 * function is designed to avoid the selection of the
4064 * same 4KB page for every 2MB page mapping.
4066 * On demotion, a mapping that hasn't been referenced
4067 * is simply destroyed. To avoid the possibility of a
4068 * subsequent page fault on a demoted wired mapping,
4069 * always leave its reference bit set. Moreover,
4070 * since the superpage is wired, the current state of
4071 * its reference bit won't affect page replacement.
4073 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4074 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4075 (tpte & ATTR_SW_WIRED) == 0) {
4076 if (safe_to_clear_referenced(pmap, tpte)) {
4078 * TODO: We don't handle the access
4079 * flag at all. We need to be able
4080 * to set it in the exception handler.
4083 "safe_to_clear_referenced\n");
4084 } else if (pmap_demote_l2_locked(pmap, pte,
4085 pv->pv_va, &lock) != NULL) {
4087 va += VM_PAGE_TO_PHYS(m) -
4088 (tpte & ~ATTR_MASK);
4089 l3 = pmap_l2_to_l3(pte, va);
4090 pmap_remove_l3(pmap, l3, va,
4091 pmap_load(pte), NULL, &lock);
4097 * The superpage mapping was removed
4098 * entirely and therefore 'pv' is no
4106 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4107 ("inconsistent pv lock %p %p for page %p",
4108 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4113 /* Rotate the PV list if it has more than one entry. */
4114 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4115 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4116 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4119 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4121 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4123 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4130 if (!PMAP_TRYLOCK(pmap)) {
4131 pvh_gen = pvh->pv_gen;
4132 md_gen = m->md.pv_gen;
4136 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4141 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4142 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4144 ("pmap_ts_referenced: invalid pde level %d", lvl));
4145 tpde = pmap_load(pde);
4146 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4147 ("pmap_ts_referenced: found an invalid l2 table"));
4148 pte = pmap_l2_to_l3(pde, pv->pv_va);
4149 tpte = pmap_load(pte);
4150 if (pmap_page_dirty(tpte))
4152 if ((tpte & ATTR_AF) != 0) {
4153 if (safe_to_clear_referenced(pmap, tpte)) {
4155 * TODO: We don't handle the access flag
4156 * at all. We need to be able to set it in
4157 * the exception handler.
4159 panic("ARM64TODO: safe_to_clear_referenced\n");
4160 } else if ((tpte & ATTR_SW_WIRED) == 0) {
4162 * Wired pages cannot be paged out so
4163 * doing accessed bit emulation for
4164 * them is wasted effort. We do the
4165 * hard work for unwired pages only.
4167 pmap_remove_l3(pmap, pte, pv->pv_va, tpde,
4169 pmap_invalidate_page(pmap, pv->pv_va);
4174 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4175 ("inconsistent pv lock %p %p for page %p",
4176 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4181 /* Rotate the PV list if it has more than one entry. */
4182 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4183 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4184 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4187 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4188 not_cleared < PMAP_TS_REFERENCED_MAX);
4191 pmap_free_zero_pages(&free);
4192 return (cleared + not_cleared);
4196 * Apply the given advice to the specified range of addresses within the
4197 * given pmap. Depending on the advice, clear the referenced and/or
4198 * modified flags in each mapping and set the mapped page's dirty field.
4201 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4206 * Clear the modify bits on the specified physical page.
4209 pmap_clear_modify(vm_page_t m)
4212 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4213 ("pmap_clear_modify: page %p is not managed", m));
4214 VM_OBJECT_ASSERT_WLOCKED(m->object);
4215 KASSERT(!vm_page_xbusied(m),
4216 ("pmap_clear_modify: page %p is exclusive busied", m));
4219 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4220 * If the object containing the page is locked and the page is not
4221 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4223 if ((m->aflags & PGA_WRITEABLE) == 0)
4226 /* ARM64TODO: We lack support for tracking if a page is modified */
4230 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4233 return ((void *)PHYS_TO_DMAP(pa));
4237 pmap_unmapbios(vm_paddr_t pa, vm_size_t size)
4242 * Sets the memory attribute for the specified page.
4245 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4248 m->md.pv_memattr = ma;
4251 * If "m" is a normal page, update its direct mapping. This update
4252 * can be relied upon to perform any cache operations that are
4253 * required for data coherence.
4255 if ((m->flags & PG_FICTITIOUS) == 0 &&
4256 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
4257 m->md.pv_memattr) != 0)
4258 panic("memory attribute change on the direct map failed");
4262 * Changes the specified virtual address range's memory type to that given by
4263 * the parameter "mode". The specified virtual address range must be
4264 * completely contained within either the direct map or the kernel map. If
4265 * the virtual address range is contained within the kernel map, then the
4266 * memory type for each of the corresponding ranges of the direct map is also
4267 * changed. (The corresponding ranges of the direct map are those ranges that
4268 * map the same physical pages as the specified virtual address range.) These
4269 * changes to the direct map are necessary because Intel describes the
4270 * behavior of their processors as "undefined" if two or more mappings to the
4271 * same physical page have different memory types.
4273 * Returns zero if the change completed successfully, and either EINVAL or
4274 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
4275 * of the virtual address range was not mapped, and ENOMEM is returned if
4276 * there was insufficient memory available to complete the change. In the
4277 * latter case, the memory type may have been changed on some part of the
4278 * virtual address range or the direct map.
4281 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
4285 PMAP_LOCK(kernel_pmap);
4286 error = pmap_change_attr_locked(va, size, mode);
4287 PMAP_UNLOCK(kernel_pmap);
4292 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
4294 vm_offset_t base, offset, tmpva;
4295 pt_entry_t l3, *pte, *newpte;
4298 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
4299 base = trunc_page(va);
4300 offset = va & PAGE_MASK;
4301 size = round_page(offset + size);
4303 if (!VIRT_IN_DMAP(base))
4306 for (tmpva = base; tmpva < base + size; ) {
4307 pte = pmap_pte(kernel_pmap, va, &lvl);
4311 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
4313 * We already have the correct attribute,
4314 * ignore this entry.
4318 panic("Invalid DMAP table level: %d\n", lvl);
4320 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
4323 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
4331 * Split the entry to an level 3 table, then
4332 * set the new attribute.
4336 panic("Invalid DMAP table level: %d\n", lvl);
4338 newpte = pmap_demote_l1(kernel_pmap, pte,
4339 tmpva & ~L1_OFFSET);
4342 pte = pmap_l1_to_l2(pte, tmpva);
4344 newpte = pmap_demote_l2(kernel_pmap, pte,
4345 tmpva & ~L2_OFFSET);
4348 pte = pmap_l2_to_l3(pte, tmpva);
4350 /* Update the entry */
4351 l3 = pmap_load(pte);
4352 l3 &= ~ATTR_IDX_MASK;
4353 l3 |= ATTR_IDX(mode);
4354 if (mode == DEVICE_MEMORY)
4357 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
4361 * If moving to a non-cacheable entry flush
4364 if (mode == VM_MEMATTR_UNCACHEABLE)
4365 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
4377 * Create an L2 table to map all addresses within an L1 mapping.
4380 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
4382 pt_entry_t *l2, newl2, oldl1;
4384 vm_paddr_t l2phys, phys;
4388 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4389 oldl1 = pmap_load(l1);
4390 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
4391 ("pmap_demote_l1: Demoting a non-block entry"));
4392 KASSERT((va & L1_OFFSET) == 0,
4393 ("pmap_demote_l1: Invalid virtual address %#lx", va));
4394 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
4395 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
4398 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
4399 tmpl1 = kva_alloc(PAGE_SIZE);
4404 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
4405 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
4406 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
4407 " in pmap %p", va, pmap);
4411 l2phys = VM_PAGE_TO_PHYS(ml2);
4412 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
4414 /* Address the range points at */
4415 phys = oldl1 & ~ATTR_MASK;
4416 /* The attributed from the old l1 table to be copied */
4417 newl2 = oldl1 & ATTR_MASK;
4419 /* Create the new entries */
4420 for (i = 0; i < Ln_ENTRIES; i++) {
4421 l2[i] = newl2 | phys;
4424 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
4425 ("Invalid l2 page (%lx != %lx)", l2[0],
4426 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
4429 pmap_kenter(tmpl1, PAGE_SIZE,
4430 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY);
4431 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
4434 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
4437 pmap_kremove(tmpl1);
4438 kva_free(tmpl1, PAGE_SIZE);
4445 * Create an L3 table to map all addresses within an L2 mapping.
4448 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
4449 struct rwlock **lockp)
4451 pt_entry_t *l3, newl3, oldl2;
4453 vm_paddr_t l3phys, phys;
4457 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4459 oldl2 = pmap_load(l2);
4460 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
4461 ("pmap_demote_l2: Demoting a non-block entry"));
4462 KASSERT((va & L2_OFFSET) == 0,
4463 ("pmap_demote_l2: Invalid virtual address %#lx", va));
4466 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
4467 tmpl2 = kva_alloc(PAGE_SIZE);
4472 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
4473 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
4474 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4475 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
4477 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
4478 " in pmap %p", va, pmap);
4481 if (va < VM_MAXUSER_ADDRESS)
4482 pmap_resident_count_inc(pmap, 1);
4485 l3phys = VM_PAGE_TO_PHYS(ml3);
4486 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
4488 /* Address the range points at */
4489 phys = oldl2 & ~ATTR_MASK;
4490 /* The attributed from the old l2 table to be copied */
4491 newl3 = (oldl2 & (ATTR_MASK & ~ATTR_DESCR_MASK)) | L3_PAGE;
4494 * If the page table page is new, initialize it.
4496 if (ml3->wire_count == 1) {
4497 for (i = 0; i < Ln_ENTRIES; i++) {
4498 l3[i] = newl3 | phys;
4502 KASSERT(l3[0] == ((oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE),
4503 ("Invalid l3 page (%lx != %lx)", l3[0],
4504 (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE));
4507 * Map the temporary page so we don't lose access to the l2 table.
4510 pmap_kenter(tmpl2, PAGE_SIZE,
4511 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY);
4512 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
4516 * The spare PV entries must be reserved prior to demoting the
4517 * mapping, that is, prior to changing the PDE. Otherwise, the state
4518 * of the L2 and the PV lists will be inconsistent, which can result
4519 * in reclaim_pv_chunk() attempting to remove a PV entry from the
4520 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
4521 * PV entry for the 2MB page mapping that is being demoted.
4523 if ((oldl2 & ATTR_SW_MANAGED) != 0)
4524 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
4526 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
4529 * Demote the PV entry.
4531 if ((oldl2 & ATTR_SW_MANAGED) != 0)
4532 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
4534 atomic_add_long(&pmap_l2_demotions, 1);
4535 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
4536 " in pmap %p %lx", va, pmap, l3[0]);
4540 pmap_kremove(tmpl2);
4541 kva_free(tmpl2, PAGE_SIZE);
4549 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
4551 struct rwlock *lock;
4555 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
4562 * perform the pmap work for mincore
4565 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
4567 pd_entry_t *l1p, l1;
4568 pd_entry_t *l2p, l2;
4569 pt_entry_t *l3p, l3;
4580 l1p = pmap_l1(pmap, addr);
4581 if (l1p == NULL) /* No l1 */
4584 l1 = pmap_load(l1p);
4585 if ((l1 & ATTR_DESCR_MASK) == L1_INVAL)
4588 if ((l1 & ATTR_DESCR_MASK) == L1_BLOCK) {
4589 pa = (l1 & ~ATTR_MASK) | (addr & L1_OFFSET);
4590 managed = (l1 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4591 val = MINCORE_SUPER | MINCORE_INCORE;
4592 if (pmap_page_dirty(l1))
4593 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4594 if ((l1 & ATTR_AF) == ATTR_AF)
4595 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4599 l2p = pmap_l1_to_l2(l1p, addr);
4600 if (l2p == NULL) /* No l2 */
4603 l2 = pmap_load(l2p);
4604 if ((l2 & ATTR_DESCR_MASK) == L2_INVAL)
4607 if ((l2 & ATTR_DESCR_MASK) == L2_BLOCK) {
4608 pa = (l2 & ~ATTR_MASK) | (addr & L2_OFFSET);
4609 managed = (l2 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4610 val = MINCORE_SUPER | MINCORE_INCORE;
4611 if (pmap_page_dirty(l2))
4612 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4613 if ((l2 & ATTR_AF) == ATTR_AF)
4614 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4618 l3p = pmap_l2_to_l3(l2p, addr);
4619 if (l3p == NULL) /* No l3 */
4622 l3 = pmap_load(l2p);
4623 if ((l3 & ATTR_DESCR_MASK) == L3_INVAL)
4626 if ((l3 & ATTR_DESCR_MASK) == L3_PAGE) {
4627 pa = (l3 & ~ATTR_MASK) | (addr & L3_OFFSET);
4628 managed = (l3 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4629 val = MINCORE_INCORE;
4630 if (pmap_page_dirty(l3))
4631 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4632 if ((l3 & ATTR_AF) == ATTR_AF)
4633 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4637 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
4638 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
4639 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
4640 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
4643 PA_UNLOCK_COND(*locked_pa);
4650 pmap_activate(struct thread *td)
4655 pmap = vmspace_pmap(td->td_proc->p_vmspace);
4656 td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0);
4657 __asm __volatile("msr ttbr0_el1, %0" : :
4658 "r"(td->td_proc->p_md.md_l0addr));
4659 pmap_invalidate_all(pmap);
4664 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
4667 if (va >= VM_MIN_KERNEL_ADDRESS) {
4668 cpu_icache_sync_range(va, sz);
4673 /* Find the length of data in this page to flush */
4674 offset = va & PAGE_MASK;
4675 len = imin(PAGE_SIZE - offset, sz);
4678 /* Extract the physical address & find it in the DMAP */
4679 pa = pmap_extract(pmap, va);
4681 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
4683 /* Move to the next page */
4686 /* Set the length for the next iteration */
4687 len = imin(PAGE_SIZE, sz);
4693 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
4699 switch (ESR_ELx_EXCEPTION(esr)) {
4700 case EXCP_DATA_ABORT_L:
4701 case EXCP_DATA_ABORT:
4704 return (KERN_FAILURE);
4709 switch (esr & ISS_DATA_DFSC_MASK) {
4710 case ISS_DATA_DFSC_TF_L0:
4711 case ISS_DATA_DFSC_TF_L1:
4712 case ISS_DATA_DFSC_TF_L2:
4713 case ISS_DATA_DFSC_TF_L3:
4714 /* Ask the MMU to check the address */
4715 if (pmap == kernel_pmap)
4716 par = arm64_address_translate_s1e1r(far);
4718 par = arm64_address_translate_s1e0r(far);
4721 * If the translation was successful the address was invalid
4722 * due to a break-before-make sequence. We can unlock and
4723 * return success to the trap handler.
4725 if (PAR_SUCCESS(par)) {
4727 return (KERN_SUCCESS);
4736 return (KERN_FAILURE);
4740 * Increase the starting virtual address of the given mapping if a
4741 * different alignment might result in more superpage mappings.
4744 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4745 vm_offset_t *addr, vm_size_t size)
4747 vm_offset_t superpage_offset;
4751 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
4752 offset += ptoa(object->pg_color);
4753 superpage_offset = offset & L2_OFFSET;
4754 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
4755 (*addr & L2_OFFSET) == superpage_offset)
4757 if ((*addr & L2_OFFSET) < superpage_offset)
4758 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
4760 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
4764 * Get the kernel virtual address of a set of physical pages. If there are
4765 * physical addresses not covered by the DMAP perform a transient mapping
4766 * that will be removed when calling pmap_unmap_io_transient.
4768 * \param page The pages the caller wishes to obtain the virtual
4769 * address on the kernel memory map.
4770 * \param vaddr On return contains the kernel virtual memory address
4771 * of the pages passed in the page parameter.
4772 * \param count Number of pages passed in.
4773 * \param can_fault TRUE if the thread using the mapped pages can take
4774 * page faults, FALSE otherwise.
4776 * \returns TRUE if the caller must call pmap_unmap_io_transient when
4777 * finished or FALSE otherwise.
4781 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
4782 boolean_t can_fault)
4785 boolean_t needs_mapping;
4789 * Allocate any KVA space that we need, this is done in a separate
4790 * loop to prevent calling vmem_alloc while pinned.
4792 needs_mapping = FALSE;
4793 for (i = 0; i < count; i++) {
4794 paddr = VM_PAGE_TO_PHYS(page[i]);
4795 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
4796 error = vmem_alloc(kernel_arena, PAGE_SIZE,
4797 M_BESTFIT | M_WAITOK, &vaddr[i]);
4798 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
4799 needs_mapping = TRUE;
4801 vaddr[i] = PHYS_TO_DMAP(paddr);
4805 /* Exit early if everything is covered by the DMAP */
4811 for (i = 0; i < count; i++) {
4812 paddr = VM_PAGE_TO_PHYS(page[i]);
4813 if (!PHYS_IN_DMAP(paddr)) {
4815 "pmap_map_io_transient: TODO: Map out of DMAP data");
4819 return (needs_mapping);
4823 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
4824 boolean_t can_fault)
4831 for (i = 0; i < count; i++) {
4832 paddr = VM_PAGE_TO_PHYS(page[i]);
4833 if (!PHYS_IN_DMAP(paddr)) {
4834 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");