2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/msgbuf.h>
120 #include <sys/mutex.h>
121 #include <sys/proc.h>
122 #include <sys/rwlock.h>
124 #include <sys/vmem.h>
125 #include <sys/vmmeter.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/_unrhdr.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/vm_pager.h>
140 #include <vm/vm_phys.h>
141 #include <vm/vm_radix.h>
142 #include <vm/vm_reserv.h>
145 #include <machine/machdep.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
149 #include <arm/include/physmem.h>
151 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
152 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
153 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
154 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
156 #define NUL0E L0_ENTRIES
157 #define NUL1E (NUL0E * NL1PG)
158 #define NUL2E (NUL1E * NL2PG)
160 #if !defined(DIAGNOSTIC)
161 #ifdef __GNUC_GNU_INLINE__
162 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
164 #define PMAP_INLINE extern inline
171 * These are configured by the mair_el1 register. This is set up in locore.S
173 #define DEVICE_MEMORY 0
174 #define UNCACHED_MEMORY 1
175 #define CACHED_MEMORY 2
179 #define PV_STAT(x) do { x ; } while (0)
181 #define PV_STAT(x) do { } while (0)
184 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
185 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
187 #define NPV_LIST_LOCKS MAXCPU
189 #define PHYS_TO_PV_LIST_LOCK(pa) \
190 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
192 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
193 struct rwlock **_lockp = (lockp); \
194 struct rwlock *_new_lock; \
196 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
197 if (_new_lock != *_lockp) { \
198 if (*_lockp != NULL) \
199 rw_wunlock(*_lockp); \
200 *_lockp = _new_lock; \
205 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
206 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
208 #define RELEASE_PV_LIST_LOCK(lockp) do { \
209 struct rwlock **_lockp = (lockp); \
211 if (*_lockp != NULL) { \
212 rw_wunlock(*_lockp); \
217 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
218 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
221 * The presence of this flag indicates that the mapping is writeable.
222 * If the ATTR_AP_RO bit is also set, then the mapping is clean, otherwise it is
223 * dirty. This flag may only be set on managed mappings.
225 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
226 * as a software managed bit.
228 #define ATTR_SW_DBM ATTR_DBM
230 struct pmap kernel_pmap_store;
232 /* Used for mapping ACPI memory before VM is initialized */
233 #define PMAP_PREINIT_MAPPING_COUNT 32
234 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
235 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
236 static int vm_initialized = 0; /* No need to use pre-init maps when set */
239 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
240 * Always map entire L2 block for simplicity.
241 * VA of L2 block = preinit_map_va + i * L2_SIZE
243 static struct pmap_preinit_mapping {
247 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
249 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
250 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
251 vm_offset_t kernel_vm_end = 0;
254 * Data for the pv entry allocation mechanism.
256 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
257 static struct mtx pv_chunks_mutex;
258 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
259 static struct md_page *pv_table;
260 static struct md_page pv_dummy;
262 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
263 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
264 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
266 /* This code assumes all L1 DMAP entries will be used */
267 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
268 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
270 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
271 extern pt_entry_t pagetable_dmap[];
273 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
274 static vm_paddr_t physmap[PHYSMAP_SIZE];
275 static u_int physmap_idx;
277 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
279 static int superpages_enabled = 1;
280 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
281 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
282 "Are large page mappings enabled?");
285 * Internal flags for pmap_enter()'s helper functions.
287 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
288 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
290 static void free_pv_chunk(struct pv_chunk *pc);
291 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
292 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
293 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
294 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
295 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
298 static int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode);
299 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
300 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
301 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
302 vm_offset_t va, struct rwlock **lockp);
303 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
304 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
305 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
306 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
307 u_int flags, vm_page_t m, struct rwlock **lockp);
308 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
309 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
310 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
311 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
312 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
313 vm_page_t m, struct rwlock **lockp);
315 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
316 struct rwlock **lockp);
318 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
319 struct spglist *free);
320 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
321 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
324 * These load the old table data and store the new value.
325 * They need to be atomic as the System MMU may write to the table at
326 * the same time as the CPU.
328 #define pmap_clear(table) atomic_store_64(table, 0)
329 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
330 #define pmap_load(table) (*table)
331 #define pmap_load_clear(table) atomic_swap_64(table, 0)
332 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
333 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
334 #define pmap_store(table, entry) atomic_store_64(table, entry)
336 /********************/
337 /* Inline functions */
338 /********************/
341 pagecopy(void *s, void *d)
344 memcpy(d, s, PAGE_SIZE);
347 static __inline pd_entry_t *
348 pmap_l0(pmap_t pmap, vm_offset_t va)
351 return (&pmap->pm_l0[pmap_l0_index(va)]);
354 static __inline pd_entry_t *
355 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
359 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
360 return (&l1[pmap_l1_index(va)]);
363 static __inline pd_entry_t *
364 pmap_l1(pmap_t pmap, vm_offset_t va)
368 l0 = pmap_l0(pmap, va);
369 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
372 return (pmap_l0_to_l1(l0, va));
375 static __inline pd_entry_t *
376 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
380 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
381 return (&l2[pmap_l2_index(va)]);
384 static __inline pd_entry_t *
385 pmap_l2(pmap_t pmap, vm_offset_t va)
389 l1 = pmap_l1(pmap, va);
390 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
393 return (pmap_l1_to_l2(l1, va));
396 static __inline pt_entry_t *
397 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
401 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
402 return (&l3[pmap_l3_index(va)]);
406 * Returns the lowest valid pde for a given virtual address.
407 * The next level may or may not point to a valid page or block.
409 static __inline pd_entry_t *
410 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
412 pd_entry_t *l0, *l1, *l2, desc;
414 l0 = pmap_l0(pmap, va);
415 desc = pmap_load(l0) & ATTR_DESCR_MASK;
416 if (desc != L0_TABLE) {
421 l1 = pmap_l0_to_l1(l0, va);
422 desc = pmap_load(l1) & ATTR_DESCR_MASK;
423 if (desc != L1_TABLE) {
428 l2 = pmap_l1_to_l2(l1, va);
429 desc = pmap_load(l2) & ATTR_DESCR_MASK;
430 if (desc != L2_TABLE) {
440 * Returns the lowest valid pte block or table entry for a given virtual
441 * address. If there are no valid entries return NULL and set the level to
442 * the first invalid level.
444 static __inline pt_entry_t *
445 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
447 pd_entry_t *l1, *l2, desc;
450 l1 = pmap_l1(pmap, va);
455 desc = pmap_load(l1) & ATTR_DESCR_MASK;
456 if (desc == L1_BLOCK) {
461 if (desc != L1_TABLE) {
466 l2 = pmap_l1_to_l2(l1, va);
467 desc = pmap_load(l2) & ATTR_DESCR_MASK;
468 if (desc == L2_BLOCK) {
473 if (desc != L2_TABLE) {
479 l3 = pmap_l2_to_l3(l2, va);
480 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
487 pmap_ps_enabled(pmap_t pmap __unused)
490 return (superpages_enabled != 0);
494 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
495 pd_entry_t **l2, pt_entry_t **l3)
497 pd_entry_t *l0p, *l1p, *l2p;
499 if (pmap->pm_l0 == NULL)
502 l0p = pmap_l0(pmap, va);
505 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
508 l1p = pmap_l0_to_l1(l0p, va);
511 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
517 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
520 l2p = pmap_l1_to_l2(l1p, va);
523 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
528 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
531 *l3 = pmap_l2_to_l3(l2p, va);
537 pmap_l3_valid(pt_entry_t l3)
540 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
544 CTASSERT(L1_BLOCK == L2_BLOCK);
547 * Checks if the PTE is dirty.
550 pmap_pte_dirty(pt_entry_t pte)
553 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
554 KASSERT((pte & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) != 0,
555 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
557 return ((pte & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
558 (ATTR_AP(ATTR_AP_RW) | ATTR_SW_DBM));
562 pmap_resident_count_inc(pmap_t pmap, int count)
565 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
566 pmap->pm_stats.resident_count += count;
570 pmap_resident_count_dec(pmap_t pmap, int count)
573 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
574 KASSERT(pmap->pm_stats.resident_count >= count,
575 ("pmap %p resident count underflow %ld %d", pmap,
576 pmap->pm_stats.resident_count, count));
577 pmap->pm_stats.resident_count -= count;
581 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
587 l1 = (pd_entry_t *)l1pt;
588 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
590 /* Check locore has used a table L1 map */
591 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
592 ("Invalid bootstrap L1 table"));
593 /* Find the address of the L2 table */
594 l2 = (pt_entry_t *)init_pt_va;
595 *l2_slot = pmap_l2_index(va);
601 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
603 u_int l1_slot, l2_slot;
606 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
608 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
612 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
613 vm_offset_t freemempos)
617 vm_paddr_t l2_pa, pa;
618 u_int l1_slot, l2_slot, prev_l1_slot;
621 dmap_phys_base = min_pa & ~L1_OFFSET;
627 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
628 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
630 for (i = 0; i < (physmap_idx * 2); i += 2) {
631 pa = physmap[i] & ~L2_OFFSET;
632 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
634 /* Create L2 mappings at the start of the region */
635 if ((pa & L1_OFFSET) != 0) {
636 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
637 if (l1_slot != prev_l1_slot) {
638 prev_l1_slot = l1_slot;
639 l2 = (pt_entry_t *)freemempos;
640 l2_pa = pmap_early_vtophys(kern_l1,
642 freemempos += PAGE_SIZE;
644 pmap_store(&pagetable_dmap[l1_slot],
645 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
647 memset(l2, 0, PAGE_SIZE);
650 ("pmap_bootstrap_dmap: NULL l2 map"));
651 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
652 pa += L2_SIZE, va += L2_SIZE) {
654 * We are on a boundary, stop to
655 * create a level 1 block
657 if ((pa & L1_OFFSET) == 0)
660 l2_slot = pmap_l2_index(va);
661 KASSERT(l2_slot != 0, ("..."));
662 pmap_store(&l2[l2_slot],
663 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
664 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
666 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
670 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
671 (physmap[i + 1] - pa) >= L1_SIZE;
672 pa += L1_SIZE, va += L1_SIZE) {
673 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
674 pmap_store(&pagetable_dmap[l1_slot],
675 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
676 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
679 /* Create L2 mappings at the end of the region */
680 if (pa < physmap[i + 1]) {
681 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
682 if (l1_slot != prev_l1_slot) {
683 prev_l1_slot = l1_slot;
684 l2 = (pt_entry_t *)freemempos;
685 l2_pa = pmap_early_vtophys(kern_l1,
687 freemempos += PAGE_SIZE;
689 pmap_store(&pagetable_dmap[l1_slot],
690 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
692 memset(l2, 0, PAGE_SIZE);
695 ("pmap_bootstrap_dmap: NULL l2 map"));
696 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
697 pa += L2_SIZE, va += L2_SIZE) {
698 l2_slot = pmap_l2_index(va);
699 pmap_store(&l2[l2_slot],
700 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
701 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
705 if (pa > dmap_phys_max) {
717 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
724 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
726 l1 = (pd_entry_t *)l1pt;
727 l1_slot = pmap_l1_index(va);
730 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
731 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
733 pa = pmap_early_vtophys(l1pt, l2pt);
734 pmap_store(&l1[l1_slot],
735 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
739 /* Clean the L2 page table */
740 memset((void *)l2_start, 0, l2pt - l2_start);
746 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
753 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
755 l2 = pmap_l2(kernel_pmap, va);
756 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
757 l2_slot = pmap_l2_index(va);
760 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
761 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
763 pa = pmap_early_vtophys(l1pt, l3pt);
764 pmap_store(&l2[l2_slot],
765 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
769 /* Clean the L2 page table */
770 memset((void *)l3_start, 0, l3pt - l3_start);
776 * Bootstrap the system enough to run with virtual memory.
779 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
782 u_int l1_slot, l2_slot;
784 vm_offset_t va, freemempos;
785 vm_offset_t dpcpu, msgbufpv;
786 vm_paddr_t start_pa, pa, min_pa;
790 kern_delta = KERNBASE - kernstart;
792 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
793 printf("%lx\n", l1pt);
794 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
796 /* Set this early so we can use the pagetable walking functions */
797 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
798 PMAP_LOCK_INIT(kernel_pmap);
800 /* Assume the address we were loaded to is a valid physical address */
801 min_pa = KERNBASE - kern_delta;
803 physmap_idx = arm_physmem_avail(physmap, nitems(physmap));
807 * Find the minimum physical address. physmap is sorted,
808 * but may contain empty ranges.
810 for (i = 0; i < (physmap_idx * 2); i += 2) {
811 if (physmap[i] == physmap[i + 1])
813 if (physmap[i] <= min_pa)
817 freemempos = KERNBASE + kernlen;
818 freemempos = roundup2(freemempos, PAGE_SIZE);
820 /* Create a direct map region early so we can use it for pa -> va */
821 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
824 start_pa = pa = KERNBASE - kern_delta;
827 * Read the page table to find out what is already mapped.
828 * This assumes we have mapped a block of memory from KERNBASE
829 * using a single L1 entry.
831 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
833 /* Sanity check the index, KERNBASE should be the first VA */
834 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
836 /* Find how many pages we have mapped */
837 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
838 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
841 /* Check locore used L2 blocks */
842 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
843 ("Invalid bootstrap L2 table"));
844 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
845 ("Incorrect PA in L2 table"));
851 va = roundup2(va, L1_SIZE);
853 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
854 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
855 /* And the l3 tables for the early devmap */
856 freemempos = pmap_bootstrap_l3(l1pt,
857 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
861 #define alloc_pages(var, np) \
862 (var) = freemempos; \
863 freemempos += (np * PAGE_SIZE); \
864 memset((char *)(var), 0, ((np) * PAGE_SIZE));
866 /* Allocate dynamic per-cpu area. */
867 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
868 dpcpu_init((void *)dpcpu, 0);
870 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
871 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
872 msgbufp = (void *)msgbufpv;
874 /* Reserve some VA space for early BIOS/ACPI mapping */
875 preinit_map_va = roundup2(freemempos, L2_SIZE);
877 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
878 virtual_avail = roundup2(virtual_avail, L1_SIZE);
879 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
880 kernel_vm_end = virtual_avail;
882 pa = pmap_early_vtophys(l1pt, freemempos);
884 arm_physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
890 * Initialize a vm_page's machine-dependent fields.
893 pmap_page_init(vm_page_t m)
896 TAILQ_INIT(&m->md.pv_list);
897 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
901 * Initialize the pmap module.
902 * Called by vm_init, to initialize any structures that the pmap
903 * system needs to map virtual memory.
912 * Are large page mappings enabled?
914 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
915 if (superpages_enabled) {
916 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
917 ("pmap_init: can't assign to pagesizes[1]"));
918 pagesizes[1] = L2_SIZE;
922 * Initialize the pv chunk list mutex.
924 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
927 * Initialize the pool of pv list locks.
929 for (i = 0; i < NPV_LIST_LOCKS; i++)
930 rw_init(&pv_list_locks[i], "pmap pv list");
933 * Calculate the size of the pv head table for superpages.
935 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
938 * Allocate memory for the pv head table for superpages.
940 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
942 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
943 for (i = 0; i < pv_npg; i++)
944 TAILQ_INIT(&pv_table[i].pv_list);
945 TAILQ_INIT(&pv_dummy.pv_list);
950 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
951 "2MB page mapping counters");
953 static u_long pmap_l2_demotions;
954 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
955 &pmap_l2_demotions, 0, "2MB page demotions");
957 static u_long pmap_l2_mappings;
958 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
959 &pmap_l2_mappings, 0, "2MB page mappings");
961 static u_long pmap_l2_p_failures;
962 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
963 &pmap_l2_p_failures, 0, "2MB page promotion failures");
965 static u_long pmap_l2_promotions;
966 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
967 &pmap_l2_promotions, 0, "2MB page promotions");
970 * Invalidate a single TLB entry.
973 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
979 "tlbi vaae1is, %0 \n"
982 : : "r"(va >> PAGE_SHIFT));
987 pmap_invalidate_range_nopin(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
992 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
994 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
1001 static __inline void
1002 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1006 pmap_invalidate_range_nopin(pmap, sva, eva);
1010 static __inline void
1011 pmap_invalidate_all(pmap_t pmap)
1024 * Routine: pmap_extract
1026 * Extract the physical page address associated
1027 * with the given map/virtual_address pair.
1030 pmap_extract(pmap_t pmap, vm_offset_t va)
1032 pt_entry_t *pte, tpte;
1039 * Find the block or page map for this virtual address. pmap_pte
1040 * will return either a valid block/page entry, or NULL.
1042 pte = pmap_pte(pmap, va, &lvl);
1044 tpte = pmap_load(pte);
1045 pa = tpte & ~ATTR_MASK;
1048 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1049 ("pmap_extract: Invalid L1 pte found: %lx",
1050 tpte & ATTR_DESCR_MASK));
1051 pa |= (va & L1_OFFSET);
1054 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1055 ("pmap_extract: Invalid L2 pte found: %lx",
1056 tpte & ATTR_DESCR_MASK));
1057 pa |= (va & L2_OFFSET);
1060 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1061 ("pmap_extract: Invalid L3 pte found: %lx",
1062 tpte & ATTR_DESCR_MASK));
1063 pa |= (va & L3_OFFSET);
1072 * Routine: pmap_extract_and_hold
1074 * Atomically extract and hold the physical page
1075 * with the given pmap and virtual address pair
1076 * if that mapping permits the given protection.
1079 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1081 pt_entry_t *pte, tpte;
1091 pte = pmap_pte(pmap, va, &lvl);
1093 tpte = pmap_load(pte);
1095 KASSERT(lvl > 0 && lvl <= 3,
1096 ("pmap_extract_and_hold: Invalid level %d", lvl));
1097 CTASSERT(L1_BLOCK == L2_BLOCK);
1098 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1099 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1100 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1101 tpte & ATTR_DESCR_MASK));
1102 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1103 ((prot & VM_PROT_WRITE) == 0)) {
1106 off = va & L1_OFFSET;
1109 off = va & L2_OFFSET;
1115 if (vm_page_pa_tryrelock(pmap,
1116 (tpte & ~ATTR_MASK) | off, &pa))
1118 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1128 pmap_kextract(vm_offset_t va)
1130 pt_entry_t *pte, tpte;
1132 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
1133 return (DMAP_TO_PHYS(va));
1134 pte = pmap_l1(kernel_pmap, va);
1139 * A concurrent pmap_update_entry() will clear the entry's valid bit
1140 * but leave the rest of the entry unchanged. Therefore, we treat a
1141 * non-zero entry as being valid, and we ignore the valid bit when
1142 * determining whether the entry maps a block, page, or table.
1144 tpte = pmap_load(pte);
1147 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1148 return ((tpte & ~ATTR_MASK) | (va & L1_OFFSET));
1149 pte = pmap_l1_to_l2(&tpte, va);
1150 tpte = pmap_load(pte);
1153 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1154 return ((tpte & ~ATTR_MASK) | (va & L2_OFFSET));
1155 pte = pmap_l2_to_l3(&tpte, va);
1156 tpte = pmap_load(pte);
1159 return ((tpte & ~ATTR_MASK) | (va & L3_OFFSET));
1162 /***************************************************
1163 * Low level mapping routines.....
1164 ***************************************************/
1167 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1170 pt_entry_t *pte, attr;
1174 KASSERT((pa & L3_OFFSET) == 0,
1175 ("pmap_kenter: Invalid physical address"));
1176 KASSERT((sva & L3_OFFSET) == 0,
1177 ("pmap_kenter: Invalid virtual address"));
1178 KASSERT((size & PAGE_MASK) == 0,
1179 ("pmap_kenter: Mapping is not page-sized"));
1181 attr = ATTR_DEFAULT | ATTR_IDX(mode) | L3_PAGE;
1182 if (mode == DEVICE_MEMORY)
1187 pde = pmap_pde(kernel_pmap, va, &lvl);
1188 KASSERT(pde != NULL,
1189 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1190 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1192 pte = pmap_l2_to_l3(pde, va);
1193 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1199 pmap_invalidate_range(kernel_pmap, sva, va);
1203 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1206 pmap_kenter(sva, size, pa, DEVICE_MEMORY);
1210 * Remove a page from the kernel pagetables.
1213 pmap_kremove(vm_offset_t va)
1218 pte = pmap_pte(kernel_pmap, va, &lvl);
1219 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1220 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1223 pmap_invalidate_page(kernel_pmap, va);
1227 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1233 KASSERT((sva & L3_OFFSET) == 0,
1234 ("pmap_kremove_device: Invalid virtual address"));
1235 KASSERT((size & PAGE_MASK) == 0,
1236 ("pmap_kremove_device: Mapping is not page-sized"));
1240 pte = pmap_pte(kernel_pmap, va, &lvl);
1241 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1243 ("Invalid device pagetable level: %d != 3", lvl));
1249 pmap_invalidate_range(kernel_pmap, sva, va);
1253 * Used to map a range of physical addresses into kernel
1254 * virtual address space.
1256 * The value passed in '*virt' is a suggested virtual address for
1257 * the mapping. Architectures which can support a direct-mapped
1258 * physical to virtual region can return the appropriate address
1259 * within that region, leaving '*virt' unchanged. Other
1260 * architectures should map the pages starting at '*virt' and
1261 * update '*virt' with the first usable address after the mapped
1265 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1267 return PHYS_TO_DMAP(start);
1272 * Add a list of wired pages to the kva
1273 * this routine is only used for temporary
1274 * kernel mappings that do not need to have
1275 * page modification or references recorded.
1276 * Note that old mappings are simply written
1277 * over. The page *must* be wired.
1278 * Note: SMP coherent. Uses a ranged shootdown IPI.
1281 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1284 pt_entry_t *pte, pa;
1290 for (i = 0; i < count; i++) {
1291 pde = pmap_pde(kernel_pmap, va, &lvl);
1292 KASSERT(pde != NULL,
1293 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1295 ("pmap_qenter: Invalid level %d", lvl));
1298 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1299 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1300 if (m->md.pv_memattr == DEVICE_MEMORY)
1302 pte = pmap_l2_to_l3(pde, va);
1303 pmap_load_store(pte, pa);
1307 pmap_invalidate_range(kernel_pmap, sva, va);
1311 * This routine tears out page mappings from the
1312 * kernel -- it is meant only for temporary mappings.
1315 pmap_qremove(vm_offset_t sva, int count)
1321 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1324 while (count-- > 0) {
1325 pte = pmap_pte(kernel_pmap, va, &lvl);
1327 ("Invalid device pagetable level: %d != 3", lvl));
1334 pmap_invalidate_range(kernel_pmap, sva, va);
1337 /***************************************************
1338 * Page table page management routines.....
1339 ***************************************************/
1341 * Schedule the specified unused page table page to be freed. Specifically,
1342 * add the page to the specified list of pages that will be released to the
1343 * physical memory manager after the TLB has been updated.
1345 static __inline void
1346 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1347 boolean_t set_PG_ZERO)
1351 m->flags |= PG_ZERO;
1353 m->flags &= ~PG_ZERO;
1354 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1358 * Decrements a page table page's wire count, which is used to record the
1359 * number of valid page table entries within the page. If the wire count
1360 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1361 * page table page was unmapped and FALSE otherwise.
1363 static inline boolean_t
1364 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1368 if (m->wire_count == 0) {
1369 _pmap_unwire_l3(pmap, va, m, free);
1376 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1379 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1381 * unmap the page table page
1383 if (m->pindex >= (NUL2E + NUL1E)) {
1387 l0 = pmap_l0(pmap, va);
1389 } else if (m->pindex >= NUL2E) {
1393 l1 = pmap_l1(pmap, va);
1399 l2 = pmap_l2(pmap, va);
1402 pmap_resident_count_dec(pmap, 1);
1403 if (m->pindex < NUL2E) {
1404 /* We just released an l3, unhold the matching l2 */
1405 pd_entry_t *l1, tl1;
1408 l1 = pmap_l1(pmap, va);
1409 tl1 = pmap_load(l1);
1410 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1411 pmap_unwire_l3(pmap, va, l2pg, free);
1412 } else if (m->pindex < (NUL2E + NUL1E)) {
1413 /* We just released an l2, unhold the matching l1 */
1414 pd_entry_t *l0, tl0;
1417 l0 = pmap_l0(pmap, va);
1418 tl0 = pmap_load(l0);
1419 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1420 pmap_unwire_l3(pmap, va, l1pg, free);
1422 pmap_invalidate_page(pmap, va);
1425 * Put page on a list so that it is released after
1426 * *ALL* TLB shootdown is done
1428 pmap_add_delayed_free_list(m, free, TRUE);
1432 * After removing a page table entry, this routine is used to
1433 * conditionally free the page, and manage the hold/wire counts.
1436 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1437 struct spglist *free)
1441 if (va >= VM_MAXUSER_ADDRESS)
1443 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1444 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1445 return (pmap_unwire_l3(pmap, va, mpte, free));
1449 pmap_pinit0(pmap_t pmap)
1452 PMAP_LOCK_INIT(pmap);
1453 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1454 pmap->pm_l0 = kernel_pmap->pm_l0;
1455 pmap->pm_root.rt_root = 0;
1459 pmap_pinit(pmap_t pmap)
1465 * allocate the l0 page
1467 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1468 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1471 l0phys = VM_PAGE_TO_PHYS(l0pt);
1472 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1474 if ((l0pt->flags & PG_ZERO) == 0)
1475 pagezero(pmap->pm_l0);
1477 pmap->pm_root.rt_root = 0;
1478 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1484 * This routine is called if the desired page table page does not exist.
1486 * If page table page allocation fails, this routine may sleep before
1487 * returning NULL. It sleeps only if a lock pointer was given.
1489 * Note: If a page allocation fails at page table level two or three,
1490 * one or two pages may be held during the wait, only to be released
1491 * afterwards. This conservative approach is easily argued to avoid
1495 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1497 vm_page_t m, l1pg, l2pg;
1499 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1502 * Allocate a page table page.
1504 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1505 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1506 if (lockp != NULL) {
1507 RELEASE_PV_LIST_LOCK(lockp);
1514 * Indicate the need to retry. While waiting, the page table
1515 * page may have been allocated.
1519 if ((m->flags & PG_ZERO) == 0)
1523 * Because of AArch64's weak memory consistency model, we must have a
1524 * barrier here to ensure that the stores for zeroing "m", whether by
1525 * pmap_zero_page() or an earlier function, are visible before adding
1526 * "m" to the page table. Otherwise, a page table walk by another
1527 * processor's MMU could see the mapping to "m" and a stale, non-zero
1533 * Map the pagetable page into the process address space, if
1534 * it isn't already there.
1537 if (ptepindex >= (NUL2E + NUL1E)) {
1539 vm_pindex_t l0index;
1541 l0index = ptepindex - (NUL2E + NUL1E);
1542 l0 = &pmap->pm_l0[l0index];
1543 pmap_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1544 } else if (ptepindex >= NUL2E) {
1545 vm_pindex_t l0index, l1index;
1546 pd_entry_t *l0, *l1;
1549 l1index = ptepindex - NUL2E;
1550 l0index = l1index >> L0_ENTRIES_SHIFT;
1552 l0 = &pmap->pm_l0[l0index];
1553 tl0 = pmap_load(l0);
1555 /* recurse for allocating page dir */
1556 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1558 vm_page_unwire_noq(m);
1559 vm_page_free_zero(m);
1563 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1567 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1568 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1569 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1571 vm_pindex_t l0index, l1index;
1572 pd_entry_t *l0, *l1, *l2;
1573 pd_entry_t tl0, tl1;
1575 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1576 l0index = l1index >> L0_ENTRIES_SHIFT;
1578 l0 = &pmap->pm_l0[l0index];
1579 tl0 = pmap_load(l0);
1581 /* recurse for allocating page dir */
1582 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1584 vm_page_unwire_noq(m);
1585 vm_page_free_zero(m);
1588 tl0 = pmap_load(l0);
1589 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1590 l1 = &l1[l1index & Ln_ADDR_MASK];
1592 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1593 l1 = &l1[l1index & Ln_ADDR_MASK];
1594 tl1 = pmap_load(l1);
1596 /* recurse for allocating page dir */
1597 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1599 vm_page_unwire_noq(m);
1600 vm_page_free_zero(m);
1604 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1609 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1610 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1611 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1614 pmap_resident_count_inc(pmap, 1);
1620 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1624 vm_pindex_t l2pindex;
1627 l1 = pmap_l1(pmap, va);
1628 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1629 /* Add a reference to the L2 page. */
1630 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1633 /* Allocate a L2 page. */
1634 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1635 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1636 if (l2pg == NULL && lockp != NULL)
1643 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1645 vm_pindex_t ptepindex;
1646 pd_entry_t *pde, tpde;
1654 * Calculate pagetable page index
1656 ptepindex = pmap_l2_pindex(va);
1659 * Get the page directory entry
1661 pde = pmap_pde(pmap, va, &lvl);
1664 * If the page table page is mapped, we just increment the hold count,
1665 * and activate it. If we get a level 2 pde it will point to a level 3
1673 pte = pmap_l0_to_l1(pde, va);
1674 KASSERT(pmap_load(pte) == 0,
1675 ("pmap_alloc_l3: TODO: l0 superpages"));
1680 pte = pmap_l1_to_l2(pde, va);
1681 KASSERT(pmap_load(pte) == 0,
1682 ("pmap_alloc_l3: TODO: l1 superpages"));
1686 tpde = pmap_load(pde);
1688 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1694 panic("pmap_alloc_l3: Invalid level %d", lvl);
1698 * Here if the pte page isn't mapped, or if it has been deallocated.
1700 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1701 if (m == NULL && lockp != NULL)
1707 /***************************************************
1708 * Pmap allocation/deallocation routines.
1709 ***************************************************/
1712 * Release any resources held by the given physical map.
1713 * Called when a pmap initialized by pmap_pinit is being released.
1714 * Should only be called if the map contains no valid mappings.
1717 pmap_release(pmap_t pmap)
1721 KASSERT(pmap->pm_stats.resident_count == 0,
1722 ("pmap_release: pmap resident count %ld != 0",
1723 pmap->pm_stats.resident_count));
1724 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1725 ("pmap_release: pmap has reserved page table page(s)"));
1727 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1729 vm_page_unwire_noq(m);
1730 vm_page_free_zero(m);
1734 kvm_size(SYSCTL_HANDLER_ARGS)
1736 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1738 return sysctl_handle_long(oidp, &ksize, 0, req);
1740 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1741 0, 0, kvm_size, "LU", "Size of KVM");
1744 kvm_free(SYSCTL_HANDLER_ARGS)
1746 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1748 return sysctl_handle_long(oidp, &kfree, 0, req);
1750 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1751 0, 0, kvm_free, "LU", "Amount of KVM free");
1754 * grow the number of kernel page table entries, if needed
1757 pmap_growkernel(vm_offset_t addr)
1761 pd_entry_t *l0, *l1, *l2;
1763 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1765 addr = roundup2(addr, L2_SIZE);
1766 if (addr - 1 >= vm_map_max(kernel_map))
1767 addr = vm_map_max(kernel_map);
1768 while (kernel_vm_end < addr) {
1769 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1770 KASSERT(pmap_load(l0) != 0,
1771 ("pmap_growkernel: No level 0 kernel entry"));
1773 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1774 if (pmap_load(l1) == 0) {
1775 /* We need a new PDP entry */
1776 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1777 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1778 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1780 panic("pmap_growkernel: no memory to grow kernel");
1781 if ((nkpg->flags & PG_ZERO) == 0)
1782 pmap_zero_page(nkpg);
1783 /* See the dmb() in _pmap_alloc_l3(). */
1785 paddr = VM_PAGE_TO_PHYS(nkpg);
1786 pmap_store(l1, paddr | L1_TABLE);
1787 continue; /* try again */
1789 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1790 if (pmap_load(l2) != 0) {
1791 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1792 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1793 kernel_vm_end = vm_map_max(kernel_map);
1799 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1800 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1803 panic("pmap_growkernel: no memory to grow kernel");
1804 if ((nkpg->flags & PG_ZERO) == 0)
1805 pmap_zero_page(nkpg);
1806 /* See the dmb() in _pmap_alloc_l3(). */
1808 paddr = VM_PAGE_TO_PHYS(nkpg);
1809 pmap_store(l2, paddr | L2_TABLE);
1811 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1812 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1813 kernel_vm_end = vm_map_max(kernel_map);
1820 /***************************************************
1821 * page management routines.
1822 ***************************************************/
1824 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1825 CTASSERT(_NPCM == 3);
1826 CTASSERT(_NPCPV == 168);
1828 static __inline struct pv_chunk *
1829 pv_to_chunk(pv_entry_t pv)
1832 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1835 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1837 #define PC_FREE0 0xfffffffffffffffful
1838 #define PC_FREE1 0xfffffffffffffffful
1839 #define PC_FREE2 0x000000fffffffffful
1841 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1845 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1847 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1848 "Current number of pv entry chunks");
1849 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1850 "Current number of pv entry chunks allocated");
1851 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1852 "Current number of pv entry chunks frees");
1853 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1854 "Number of times tried to get a chunk page but failed.");
1856 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1857 static int pv_entry_spare;
1859 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1860 "Current number of pv entry frees");
1861 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1862 "Current number of pv entry allocs");
1863 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1864 "Current number of pv entries");
1865 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1866 "Current number of spare pv entries");
1871 * We are in a serious low memory condition. Resort to
1872 * drastic measures to free some pages so we can allocate
1873 * another pv entry chunk.
1875 * Returns NULL if PV entries were reclaimed from the specified pmap.
1877 * We do not, however, unmap 2mpages because subsequent accesses will
1878 * allocate per-page pv entries until repromotion occurs, thereby
1879 * exacerbating the shortage of free pv entries.
1882 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1884 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
1885 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
1886 struct md_page *pvh;
1888 pmap_t next_pmap, pmap;
1889 pt_entry_t *pte, tpte;
1893 struct spglist free;
1895 int bit, field, freed, lvl;
1896 static int active_reclaims = 0;
1898 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1899 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
1904 bzero(&pc_marker_b, sizeof(pc_marker_b));
1905 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
1906 pc_marker = (struct pv_chunk *)&pc_marker_b;
1907 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
1909 mtx_lock(&pv_chunks_mutex);
1911 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
1912 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
1913 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
1914 SLIST_EMPTY(&free)) {
1915 next_pmap = pc->pc_pmap;
1916 if (next_pmap == NULL) {
1918 * The next chunk is a marker. However, it is
1919 * not our marker, so active_reclaims must be
1920 * > 1. Consequently, the next_chunk code
1921 * will not rotate the pv_chunks list.
1925 mtx_unlock(&pv_chunks_mutex);
1928 * A pv_chunk can only be removed from the pc_lru list
1929 * when both pv_chunks_mutex is owned and the
1930 * corresponding pmap is locked.
1932 if (pmap != next_pmap) {
1933 if (pmap != NULL && pmap != locked_pmap)
1936 /* Avoid deadlock and lock recursion. */
1937 if (pmap > locked_pmap) {
1938 RELEASE_PV_LIST_LOCK(lockp);
1940 mtx_lock(&pv_chunks_mutex);
1942 } else if (pmap != locked_pmap) {
1943 if (PMAP_TRYLOCK(pmap)) {
1944 mtx_lock(&pv_chunks_mutex);
1947 pmap = NULL; /* pmap is not locked */
1948 mtx_lock(&pv_chunks_mutex);
1949 pc = TAILQ_NEXT(pc_marker, pc_lru);
1951 pc->pc_pmap != next_pmap)
1959 * Destroy every non-wired, 4 KB page mapping in the chunk.
1962 for (field = 0; field < _NPCM; field++) {
1963 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1964 inuse != 0; inuse &= ~(1UL << bit)) {
1965 bit = ffsl(inuse) - 1;
1966 pv = &pc->pc_pventry[field * 64 + bit];
1968 pde = pmap_pde(pmap, va, &lvl);
1971 pte = pmap_l2_to_l3(pde, va);
1972 tpte = pmap_load(pte);
1973 if ((tpte & ATTR_SW_WIRED) != 0)
1975 tpte = pmap_load_clear(pte);
1976 pmap_invalidate_page(pmap, va);
1977 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
1978 if (pmap_pte_dirty(tpte))
1980 if ((tpte & ATTR_AF) != 0)
1981 vm_page_aflag_set(m, PGA_REFERENCED);
1982 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1983 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
1985 if (TAILQ_EMPTY(&m->md.pv_list) &&
1986 (m->flags & PG_FICTITIOUS) == 0) {
1987 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
1988 if (TAILQ_EMPTY(&pvh->pv_list)) {
1989 vm_page_aflag_clear(m,
1993 pc->pc_map[field] |= 1UL << bit;
1994 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
1999 mtx_lock(&pv_chunks_mutex);
2002 /* Every freed mapping is for a 4 KB page. */
2003 pmap_resident_count_dec(pmap, freed);
2004 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2005 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2006 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2007 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2008 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2009 pc->pc_map[2] == PC_FREE2) {
2010 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2011 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2012 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2013 /* Entire chunk is free; return it. */
2014 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2015 dump_drop_page(m_pc->phys_addr);
2016 mtx_lock(&pv_chunks_mutex);
2017 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2020 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2021 mtx_lock(&pv_chunks_mutex);
2022 /* One freed pv entry in locked_pmap is sufficient. */
2023 if (pmap == locked_pmap)
2027 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2028 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2029 if (active_reclaims == 1 && pmap != NULL) {
2031 * Rotate the pv chunks list so that we do not
2032 * scan the same pv chunks that could not be
2033 * freed (because they contained a wired
2034 * and/or superpage mapping) on every
2035 * invocation of reclaim_pv_chunk().
2037 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2038 MPASS(pc->pc_pmap != NULL);
2039 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2040 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2044 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2045 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2047 mtx_unlock(&pv_chunks_mutex);
2048 if (pmap != NULL && pmap != locked_pmap)
2050 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2051 m_pc = SLIST_FIRST(&free);
2052 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2053 /* Recycle a freed page table page. */
2054 m_pc->wire_count = 1;
2056 vm_page_free_pages_toq(&free, true);
2061 * free the pv_entry back to the free list
2064 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2066 struct pv_chunk *pc;
2067 int idx, field, bit;
2069 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2070 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2071 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2072 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2073 pc = pv_to_chunk(pv);
2074 idx = pv - &pc->pc_pventry[0];
2077 pc->pc_map[field] |= 1ul << bit;
2078 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2079 pc->pc_map[2] != PC_FREE2) {
2080 /* 98% of the time, pc is already at the head of the list. */
2081 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2082 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2083 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2087 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2092 free_pv_chunk(struct pv_chunk *pc)
2096 mtx_lock(&pv_chunks_mutex);
2097 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2098 mtx_unlock(&pv_chunks_mutex);
2099 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2100 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2101 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2102 /* entire chunk is free, return it */
2103 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2104 dump_drop_page(m->phys_addr);
2105 vm_page_unwire_noq(m);
2110 * Returns a new PV entry, allocating a new PV chunk from the system when
2111 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2112 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2115 * The given PV list lock may be released.
2118 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2122 struct pv_chunk *pc;
2125 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2126 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2128 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2130 for (field = 0; field < _NPCM; field++) {
2131 if (pc->pc_map[field]) {
2132 bit = ffsl(pc->pc_map[field]) - 1;
2136 if (field < _NPCM) {
2137 pv = &pc->pc_pventry[field * 64 + bit];
2138 pc->pc_map[field] &= ~(1ul << bit);
2139 /* If this was the last item, move it to tail */
2140 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2141 pc->pc_map[2] == 0) {
2142 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2143 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2146 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2147 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2151 /* No free items, allocate another chunk */
2152 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2155 if (lockp == NULL) {
2156 PV_STAT(pc_chunk_tryfail++);
2159 m = reclaim_pv_chunk(pmap, lockp);
2163 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2164 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2165 dump_add_page(m->phys_addr);
2166 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2168 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2169 pc->pc_map[1] = PC_FREE1;
2170 pc->pc_map[2] = PC_FREE2;
2171 mtx_lock(&pv_chunks_mutex);
2172 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2173 mtx_unlock(&pv_chunks_mutex);
2174 pv = &pc->pc_pventry[0];
2175 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2176 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2177 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2182 * Ensure that the number of spare PV entries in the specified pmap meets or
2183 * exceeds the given count, "needed".
2185 * The given PV list lock may be released.
2188 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2190 struct pch new_tail;
2191 struct pv_chunk *pc;
2196 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2197 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2200 * Newly allocated PV chunks must be stored in a private list until
2201 * the required number of PV chunks have been allocated. Otherwise,
2202 * reclaim_pv_chunk() could recycle one of these chunks. In
2203 * contrast, these chunks must be added to the pmap upon allocation.
2205 TAILQ_INIT(&new_tail);
2208 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2209 bit_count((bitstr_t *)pc->pc_map, 0,
2210 sizeof(pc->pc_map) * NBBY, &free);
2214 if (avail >= needed)
2217 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2218 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2221 m = reclaim_pv_chunk(pmap, lockp);
2226 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2227 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2228 dump_add_page(m->phys_addr);
2229 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2231 pc->pc_map[0] = PC_FREE0;
2232 pc->pc_map[1] = PC_FREE1;
2233 pc->pc_map[2] = PC_FREE2;
2234 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2235 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2236 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2239 * The reclaim might have freed a chunk from the current pmap.
2240 * If that chunk contained available entries, we need to
2241 * re-count the number of available entries.
2246 if (!TAILQ_EMPTY(&new_tail)) {
2247 mtx_lock(&pv_chunks_mutex);
2248 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2249 mtx_unlock(&pv_chunks_mutex);
2254 * First find and then remove the pv entry for the specified pmap and virtual
2255 * address from the specified pv list. Returns the pv entry if found and NULL
2256 * otherwise. This operation can be performed on pv lists for either 4KB or
2257 * 2MB page mappings.
2259 static __inline pv_entry_t
2260 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2264 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2265 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2266 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2275 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2276 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2277 * entries for each of the 4KB page mappings.
2280 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2281 struct rwlock **lockp)
2283 struct md_page *pvh;
2284 struct pv_chunk *pc;
2286 vm_offset_t va_last;
2290 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2291 KASSERT((va & L2_OFFSET) == 0,
2292 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
2293 KASSERT((pa & L2_OFFSET) == 0,
2294 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2295 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2298 * Transfer the 2mpage's pv entry for this mapping to the first
2299 * page's pv list. Once this transfer begins, the pv list lock
2300 * must not be released until the last pv entry is reinstantiated.
2302 pvh = pa_to_pvh(pa);
2303 pv = pmap_pvh_remove(pvh, pmap, va);
2304 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2305 m = PHYS_TO_VM_PAGE(pa);
2306 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2308 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2309 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2310 va_last = va + L2_SIZE - PAGE_SIZE;
2312 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2313 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2314 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2315 for (field = 0; field < _NPCM; field++) {
2316 while (pc->pc_map[field]) {
2317 bit = ffsl(pc->pc_map[field]) - 1;
2318 pc->pc_map[field] &= ~(1ul << bit);
2319 pv = &pc->pc_pventry[field * 64 + bit];
2323 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2324 ("pmap_pv_demote_l2: page %p is not managed", m));
2325 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2331 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2332 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2335 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2336 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2337 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2339 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2340 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2344 * First find and then destroy the pv entry for the specified pmap and virtual
2345 * address. This operation can be performed on pv lists for either 4KB or 2MB
2349 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2353 pv = pmap_pvh_remove(pvh, pmap, va);
2354 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2355 free_pv_entry(pmap, pv);
2359 * Conditionally create the PV entry for a 4KB page mapping if the required
2360 * memory can be allocated without resorting to reclamation.
2363 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2364 struct rwlock **lockp)
2368 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2369 /* Pass NULL instead of the lock pointer to disable reclamation. */
2370 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2372 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2373 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2381 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2382 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2383 * false if the PV entry cannot be allocated without resorting to reclamation.
2386 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2387 struct rwlock **lockp)
2389 struct md_page *pvh;
2393 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2394 /* Pass NULL instead of the lock pointer to disable reclamation. */
2395 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2396 NULL : lockp)) == NULL)
2399 pa = l2e & ~ATTR_MASK;
2400 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2401 pvh = pa_to_pvh(pa);
2402 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2408 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2410 pt_entry_t newl2, oldl2;
2414 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2415 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2416 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2418 ml3 = pmap_remove_pt_page(pmap, va);
2420 panic("pmap_remove_kernel_l2: Missing pt page");
2422 ml3pa = VM_PAGE_TO_PHYS(ml3);
2423 newl2 = ml3pa | L2_TABLE;
2426 * If this page table page was unmapped by a promotion, then it
2427 * contains valid mappings. Zero it to invalidate those mappings.
2429 if (ml3->valid != 0)
2430 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2433 * Demote the mapping. The caller must have already invalidated the
2434 * mapping (i.e., the "break" in break-before-make).
2436 oldl2 = pmap_load_store(l2, newl2);
2437 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
2438 __func__, l2, oldl2));
2442 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
2445 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2446 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2448 struct md_page *pvh;
2450 vm_offset_t eva, va;
2453 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2454 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2455 old_l2 = pmap_load_clear(l2);
2456 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2457 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2460 * Since a promotion must break the 4KB page mappings before making
2461 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2463 pmap_invalidate_page(pmap, sva);
2465 if (old_l2 & ATTR_SW_WIRED)
2466 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2467 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2468 if (old_l2 & ATTR_SW_MANAGED) {
2469 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2470 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2471 pmap_pvh_free(pvh, pmap, sva);
2472 eva = sva + L2_SIZE;
2473 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2474 va < eva; va += PAGE_SIZE, m++) {
2475 if (pmap_pte_dirty(old_l2))
2477 if (old_l2 & ATTR_AF)
2478 vm_page_aflag_set(m, PGA_REFERENCED);
2479 if (TAILQ_EMPTY(&m->md.pv_list) &&
2480 TAILQ_EMPTY(&pvh->pv_list))
2481 vm_page_aflag_clear(m, PGA_WRITEABLE);
2484 if (pmap == kernel_pmap) {
2485 pmap_remove_kernel_l2(pmap, l2, sva);
2487 ml3 = pmap_remove_pt_page(pmap, sva);
2489 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
2490 ("pmap_remove_l2: l3 page not promoted"));
2491 pmap_resident_count_dec(pmap, 1);
2492 KASSERT(ml3->wire_count == NL3PG,
2493 ("pmap_remove_l2: l3 page wire count error"));
2494 ml3->wire_count = 0;
2495 pmap_add_delayed_free_list(ml3, free, FALSE);
2498 return (pmap_unuse_pt(pmap, sva, l1e, free));
2502 * pmap_remove_l3: do the things to unmap a page in a process
2505 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2506 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2508 struct md_page *pvh;
2512 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2513 old_l3 = pmap_load_clear(l3);
2514 pmap_invalidate_page(pmap, va);
2515 if (old_l3 & ATTR_SW_WIRED)
2516 pmap->pm_stats.wired_count -= 1;
2517 pmap_resident_count_dec(pmap, 1);
2518 if (old_l3 & ATTR_SW_MANAGED) {
2519 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2520 if (pmap_pte_dirty(old_l3))
2522 if (old_l3 & ATTR_AF)
2523 vm_page_aflag_set(m, PGA_REFERENCED);
2524 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2525 pmap_pvh_free(&m->md, pmap, va);
2526 if (TAILQ_EMPTY(&m->md.pv_list) &&
2527 (m->flags & PG_FICTITIOUS) == 0) {
2528 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2529 if (TAILQ_EMPTY(&pvh->pv_list))
2530 vm_page_aflag_clear(m, PGA_WRITEABLE);
2533 return (pmap_unuse_pt(pmap, va, l2e, free));
2537 * Remove the specified range of addresses from the L3 page table that is
2538 * identified by the given L2 entry.
2541 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
2542 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
2544 struct md_page *pvh;
2545 struct rwlock *new_lock;
2546 pt_entry_t *l3, old_l3;
2550 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2551 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
2552 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
2554 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
2555 if (!pmap_l3_valid(pmap_load(l3))) {
2557 pmap_invalidate_range(pmap, va, sva);
2562 old_l3 = pmap_load_clear(l3);
2563 if ((old_l3 & ATTR_SW_WIRED) != 0)
2564 pmap->pm_stats.wired_count--;
2565 pmap_resident_count_dec(pmap, 1);
2566 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
2567 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2568 if (pmap_pte_dirty(old_l3))
2570 if ((old_l3 & ATTR_AF) != 0)
2571 vm_page_aflag_set(m, PGA_REFERENCED);
2572 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
2573 if (new_lock != *lockp) {
2574 if (*lockp != NULL) {
2576 * Pending TLB invalidations must be
2577 * performed before the PV list lock is
2578 * released. Otherwise, a concurrent
2579 * pmap_remove_all() on a physical page
2580 * could return while a stale TLB entry
2581 * still provides access to that page.
2584 pmap_invalidate_range(pmap, va,
2593 pmap_pvh_free(&m->md, pmap, sva);
2594 if (TAILQ_EMPTY(&m->md.pv_list) &&
2595 (m->flags & PG_FICTITIOUS) == 0) {
2596 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2597 if (TAILQ_EMPTY(&pvh->pv_list))
2598 vm_page_aflag_clear(m, PGA_WRITEABLE);
2603 if (pmap_unuse_pt(pmap, sva, l2e, free)) {
2609 pmap_invalidate_range(pmap, va, sva);
2613 * Remove the given range of addresses from the specified map.
2615 * It is assumed that the start and end are properly
2616 * rounded to the page size.
2619 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2621 struct rwlock *lock;
2622 vm_offset_t va_next;
2623 pd_entry_t *l0, *l1, *l2;
2624 pt_entry_t l3_paddr;
2625 struct spglist free;
2628 * Perform an unsynchronized read. This is, however, safe.
2630 if (pmap->pm_stats.resident_count == 0)
2638 for (; sva < eva; sva = va_next) {
2640 if (pmap->pm_stats.resident_count == 0)
2643 l0 = pmap_l0(pmap, sva);
2644 if (pmap_load(l0) == 0) {
2645 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2651 l1 = pmap_l0_to_l1(l0, sva);
2652 if (pmap_load(l1) == 0) {
2653 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2660 * Calculate index for next page table.
2662 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2666 l2 = pmap_l1_to_l2(l1, sva);
2670 l3_paddr = pmap_load(l2);
2672 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2673 if (sva + L2_SIZE == va_next && eva >= va_next) {
2674 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2677 } else if (pmap_demote_l2_locked(pmap, l2, sva,
2680 l3_paddr = pmap_load(l2);
2684 * Weed out invalid mappings.
2686 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2690 * Limit our scan to either the end of the va represented
2691 * by the current page table page, or to the end of the
2692 * range being removed.
2697 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
2703 vm_page_free_pages_toq(&free, true);
2707 * Routine: pmap_remove_all
2709 * Removes this physical page from
2710 * all physical maps in which it resides.
2711 * Reflects back modify bits to the pager.
2714 * Original versions of this routine were very
2715 * inefficient because they iteratively called
2716 * pmap_remove (slow...)
2720 pmap_remove_all(vm_page_t m)
2722 struct md_page *pvh;
2725 struct rwlock *lock;
2726 pd_entry_t *pde, tpde;
2727 pt_entry_t *pte, tpte;
2729 struct spglist free;
2730 int lvl, pvh_gen, md_gen;
2732 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2733 ("pmap_remove_all: page %p is not managed", m));
2735 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2736 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2737 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2740 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2742 if (!PMAP_TRYLOCK(pmap)) {
2743 pvh_gen = pvh->pv_gen;
2747 if (pvh_gen != pvh->pv_gen) {
2754 pte = pmap_pte(pmap, va, &lvl);
2755 KASSERT(pte != NULL,
2756 ("pmap_remove_all: no page table entry found"));
2758 ("pmap_remove_all: invalid pte level %d", lvl));
2760 pmap_demote_l2_locked(pmap, pte, va, &lock);
2763 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2765 if (!PMAP_TRYLOCK(pmap)) {
2766 pvh_gen = pvh->pv_gen;
2767 md_gen = m->md.pv_gen;
2771 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2777 pmap_resident_count_dec(pmap, 1);
2779 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2780 KASSERT(pde != NULL,
2781 ("pmap_remove_all: no page directory entry found"));
2783 ("pmap_remove_all: invalid pde level %d", lvl));
2784 tpde = pmap_load(pde);
2786 pte = pmap_l2_to_l3(pde, pv->pv_va);
2787 tpte = pmap_load_clear(pte);
2788 pmap_invalidate_page(pmap, pv->pv_va);
2789 if (tpte & ATTR_SW_WIRED)
2790 pmap->pm_stats.wired_count--;
2791 if ((tpte & ATTR_AF) != 0)
2792 vm_page_aflag_set(m, PGA_REFERENCED);
2795 * Update the vm_page_t clean and reference bits.
2797 if (pmap_pte_dirty(tpte))
2799 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2800 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2802 free_pv_entry(pmap, pv);
2805 vm_page_aflag_clear(m, PGA_WRITEABLE);
2807 vm_page_free_pages_toq(&free, true);
2811 * pmap_protect_l2: do the things to protect a 2MB page in a pmap
2814 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
2820 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2821 KASSERT((sva & L2_OFFSET) == 0,
2822 ("pmap_protect_l2: sva is not 2mpage aligned"));
2823 old_l2 = pmap_load(l2);
2824 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2825 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
2828 * Return if the L2 entry already has the desired access restrictions
2832 if ((old_l2 & mask) == nbits)
2836 * When a dirty read/write superpage mapping is write protected,
2837 * update the dirty field of each of the superpage's constituent 4KB
2840 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
2841 (nbits & ATTR_AP(ATTR_AP_RO)) != 0 && pmap_pte_dirty(old_l2)) {
2842 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2843 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
2847 if (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
2851 * Since a promotion must break the 4KB page mappings before making
2852 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2854 pmap_invalidate_page(pmap, sva);
2858 * Set the physical protection on the
2859 * specified range of this map as requested.
2862 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2864 vm_offset_t va, va_next;
2865 pd_entry_t *l0, *l1, *l2;
2866 pt_entry_t *l3p, l3, mask, nbits;
2868 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
2869 if (prot == VM_PROT_NONE) {
2870 pmap_remove(pmap, sva, eva);
2875 if ((prot & VM_PROT_WRITE) == 0) {
2876 mask |= ATTR_AP_RW_BIT | ATTR_SW_DBM;
2877 nbits |= ATTR_AP(ATTR_AP_RO);
2879 if ((prot & VM_PROT_EXECUTE) == 0) {
2887 for (; sva < eva; sva = va_next) {
2889 l0 = pmap_l0(pmap, sva);
2890 if (pmap_load(l0) == 0) {
2891 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2897 l1 = pmap_l0_to_l1(l0, sva);
2898 if (pmap_load(l1) == 0) {
2899 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2905 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2909 l2 = pmap_l1_to_l2(l1, sva);
2910 if (pmap_load(l2) == 0)
2913 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
2914 if (sva + L2_SIZE == va_next && eva >= va_next) {
2915 pmap_protect_l2(pmap, l2, sva, mask, nbits);
2917 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
2920 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
2921 ("pmap_protect: Invalid L2 entry after demotion"));
2927 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2929 l3 = pmap_load(l3p);
2932 * Go to the next L3 entry if the current one is
2933 * invalid or already has the desired access
2934 * restrictions in place. (The latter case occurs
2935 * frequently. For example, in a "buildworld"
2936 * workload, almost 1 out of 4 L3 entries already
2937 * have the desired restrictions.)
2939 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
2940 if (va != va_next) {
2941 pmap_invalidate_range(pmap, va, sva);
2948 * When a dirty read/write mapping is write protected,
2949 * update the page's dirty field.
2951 if ((l3 & ATTR_SW_MANAGED) != 0 &&
2952 (nbits & ATTR_AP(ATTR_AP_RO)) != 0 &&
2954 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK));
2956 if (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) | nbits))
2962 pmap_invalidate_range(pmap, va, sva);
2968 * Inserts the specified page table page into the specified pmap's collection
2969 * of idle page table pages. Each of a pmap's page table pages is responsible
2970 * for mapping a distinct range of virtual addresses. The pmap's collection is
2971 * ordered by this virtual address range.
2973 * If "promoted" is false, then the page table page "mpte" must be zero filled.
2976 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
2979 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2980 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
2981 return (vm_radix_insert(&pmap->pm_root, mpte));
2985 * Removes the page table page mapping the specified virtual address from the
2986 * specified pmap's collection of idle page table pages, and returns it.
2987 * Otherwise, returns NULL if there is no page table page corresponding to the
2988 * specified virtual address.
2990 static __inline vm_page_t
2991 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2994 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2995 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
2999 * Performs a break-before-make update of a pmap entry. This is needed when
3000 * either promoting or demoting pages to ensure the TLB doesn't get into an
3001 * inconsistent state.
3004 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
3005 vm_offset_t va, vm_size_t size)
3009 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3012 * Ensure we don't get switched out with the page table in an
3013 * inconsistent state. We also need to ensure no interrupts fire
3014 * as they may make use of an address we are about to invalidate.
3016 intr = intr_disable();
3020 * Clear the old mapping's valid bit, but leave the rest of the entry
3021 * unchanged, so that a lockless, concurrent pmap_kextract() can still
3022 * lookup the physical address.
3024 pmap_clear_bits(pte, ATTR_DESCR_VALID);
3025 pmap_invalidate_range_nopin(pmap, va, va + size);
3027 /* Create the new mapping */
3028 pmap_store(pte, newpte);
3035 #if VM_NRESERVLEVEL > 0
3037 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3038 * replace the many pv entries for the 4KB page mappings by a single pv entry
3039 * for the 2MB page mapping.
3042 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3043 struct rwlock **lockp)
3045 struct md_page *pvh;
3047 vm_offset_t va_last;
3050 KASSERT((pa & L2_OFFSET) == 0,
3051 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
3052 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3055 * Transfer the first page's pv entry for this mapping to the 2mpage's
3056 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3057 * a transfer avoids the possibility that get_pv_entry() calls
3058 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3059 * mappings that is being promoted.
3061 m = PHYS_TO_VM_PAGE(pa);
3062 va = va & ~L2_OFFSET;
3063 pv = pmap_pvh_remove(&m->md, pmap, va);
3064 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
3065 pvh = pa_to_pvh(pa);
3066 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3068 /* Free the remaining NPTEPG - 1 pv entries. */
3069 va_last = va + L2_SIZE - PAGE_SIZE;
3073 pmap_pvh_free(&m->md, pmap, va);
3074 } while (va < va_last);
3078 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3079 * single level 2 table entry to a single 2MB page mapping. For promotion
3080 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3081 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3082 * identical characteristics.
3085 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
3086 struct rwlock **lockp)
3088 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
3092 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3094 sva = va & ~L2_OFFSET;
3095 firstl3 = pmap_l2_to_l3(l2, sva);
3096 newl2 = pmap_load(firstl3);
3099 if (((newl2 & (~ATTR_MASK | ATTR_AF)) & L2_OFFSET) != ATTR_AF) {
3100 atomic_add_long(&pmap_l2_p_failures, 1);
3101 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3102 " in pmap %p", va, pmap);
3106 if ((newl2 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
3107 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM)) {
3108 if (!atomic_fcmpset_64(l2, &newl2, newl2 & ~ATTR_SW_DBM))
3110 newl2 &= ~ATTR_SW_DBM;
3113 pa = newl2 + L2_SIZE - PAGE_SIZE;
3114 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
3115 oldl3 = pmap_load(l3);
3117 if ((oldl3 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
3118 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM)) {
3119 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
3122 oldl3 &= ~ATTR_SW_DBM;
3125 atomic_add_long(&pmap_l2_p_failures, 1);
3126 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3127 " in pmap %p", va, pmap);
3134 * Save the page table page in its current state until the L2
3135 * mapping the superpage is demoted by pmap_demote_l2() or
3136 * destroyed by pmap_remove_l3().
3138 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3139 KASSERT(mpte >= vm_page_array &&
3140 mpte < &vm_page_array[vm_page_array_size],
3141 ("pmap_promote_l2: page table page is out of range"));
3142 KASSERT(mpte->pindex == pmap_l2_pindex(va),
3143 ("pmap_promote_l2: page table page's pindex is wrong"));
3144 if (pmap_insert_pt_page(pmap, mpte, true)) {
3145 atomic_add_long(&pmap_l2_p_failures, 1);
3147 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
3152 if ((newl2 & ATTR_SW_MANAGED) != 0)
3153 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
3155 newl2 &= ~ATTR_DESCR_MASK;
3158 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
3160 atomic_add_long(&pmap_l2_promotions, 1);
3161 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
3164 #endif /* VM_NRESERVLEVEL > 0 */
3167 * Insert the given physical page (p) at
3168 * the specified virtual address (v) in the
3169 * target physical map with the protection requested.
3171 * If specified, the page will be wired down, meaning
3172 * that the related pte can not be reclaimed.
3174 * NB: This is the only routine which MAY NOT lazy-evaluate
3175 * or lose information. That is, this routine must actually
3176 * insert this page into the given map NOW.
3179 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3180 u_int flags, int8_t psind)
3182 struct rwlock *lock;
3184 pt_entry_t new_l3, orig_l3;
3185 pt_entry_t *l2, *l3;
3192 va = trunc_page(va);
3193 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3194 VM_OBJECT_ASSERT_LOCKED(m->object);
3195 pa = VM_PAGE_TO_PHYS(m);
3196 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3198 if ((prot & VM_PROT_WRITE) == 0)
3199 new_l3 |= ATTR_AP(ATTR_AP_RO);
3200 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3202 if ((flags & PMAP_ENTER_WIRED) != 0)
3203 new_l3 |= ATTR_SW_WIRED;
3204 if (va < VM_MAXUSER_ADDRESS)
3205 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3206 if ((m->oflags & VPO_UNMANAGED) == 0) {
3207 new_l3 |= ATTR_SW_MANAGED;
3208 if ((prot & VM_PROT_WRITE) != 0) {
3209 new_l3 |= ATTR_SW_DBM;
3210 if ((flags & VM_PROT_WRITE) == 0)
3211 new_l3 |= ATTR_AP(ATTR_AP_RO);
3215 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3220 /* Assert the required virtual and physical alignment. */
3221 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3222 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3223 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3230 * In the case that a page table page is not
3231 * resident, we are creating it here.
3234 pde = pmap_pde(pmap, va, &lvl);
3235 if (pde != NULL && lvl == 2) {
3236 l3 = pmap_l2_to_l3(pde, va);
3237 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3238 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3242 } else if (pde != NULL && lvl == 1) {
3243 l2 = pmap_l1_to_l2(pde, va);
3244 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3245 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
3246 l3 = &l3[pmap_l3_index(va)];
3247 if (va < VM_MAXUSER_ADDRESS) {
3248 mpte = PHYS_TO_VM_PAGE(
3249 pmap_load(l2) & ~ATTR_MASK);
3254 /* We need to allocate an L3 table. */
3256 if (va < VM_MAXUSER_ADDRESS) {
3257 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
3260 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
3261 * to handle the possibility that a superpage mapping for "va"
3262 * was created while we slept.
3264 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
3265 nosleep ? NULL : &lock);
3266 if (mpte == NULL && nosleep) {
3267 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3268 rv = KERN_RESOURCE_SHORTAGE;
3273 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
3276 orig_l3 = pmap_load(l3);
3277 opa = orig_l3 & ~ATTR_MASK;
3281 * Is the specified virtual address already mapped?
3283 if (pmap_l3_valid(orig_l3)) {
3285 * Wiring change, just update stats. We don't worry about
3286 * wiring PT pages as they remain resident as long as there
3287 * are valid mappings in them. Hence, if a user page is wired,
3288 * the PT page will be also.
3290 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3291 (orig_l3 & ATTR_SW_WIRED) == 0)
3292 pmap->pm_stats.wired_count++;
3293 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3294 (orig_l3 & ATTR_SW_WIRED) != 0)
3295 pmap->pm_stats.wired_count--;
3298 * Remove the extra PT page reference.
3302 KASSERT(mpte->wire_count > 0,
3303 ("pmap_enter: missing reference to page table page,"
3308 * Has the physical page changed?
3312 * No, might be a protection or wiring change.
3314 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3315 (new_l3 & ATTR_SW_DBM) != 0)
3316 vm_page_aflag_set(m, PGA_WRITEABLE);
3321 * The physical page has changed. Temporarily invalidate
3324 orig_l3 = pmap_load_clear(l3);
3325 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
3326 ("pmap_enter: unexpected pa update for %#lx", va));
3327 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3328 om = PHYS_TO_VM_PAGE(opa);
3331 * The pmap lock is sufficient to synchronize with
3332 * concurrent calls to pmap_page_test_mappings() and
3333 * pmap_ts_referenced().
3335 if (pmap_pte_dirty(orig_l3))
3337 if ((orig_l3 & ATTR_AF) != 0)
3338 vm_page_aflag_set(om, PGA_REFERENCED);
3339 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3340 pv = pmap_pvh_remove(&om->md, pmap, va);
3341 if ((m->oflags & VPO_UNMANAGED) != 0)
3342 free_pv_entry(pmap, pv);
3343 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3344 TAILQ_EMPTY(&om->md.pv_list) &&
3345 ((om->flags & PG_FICTITIOUS) != 0 ||
3346 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3347 vm_page_aflag_clear(om, PGA_WRITEABLE);
3349 pmap_invalidate_page(pmap, va);
3353 * Increment the counters.
3355 if ((new_l3 & ATTR_SW_WIRED) != 0)
3356 pmap->pm_stats.wired_count++;
3357 pmap_resident_count_inc(pmap, 1);
3360 * Enter on the PV list if part of our managed memory.
3362 if ((m->oflags & VPO_UNMANAGED) == 0) {
3364 pv = get_pv_entry(pmap, &lock);
3367 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3368 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3370 if ((new_l3 & ATTR_SW_DBM) != 0)
3371 vm_page_aflag_set(m, PGA_WRITEABLE);
3376 * Sync icache if exec permission and attribute VM_MEMATTR_WRITE_BACK
3377 * is set. Do it now, before the mapping is stored and made
3378 * valid for hardware table walk. If done later, then other can
3379 * access this page before caches are properly synced.
3380 * Don't do it for kernel memory which is mapped with exec
3381 * permission even if the memory isn't going to hold executable
3382 * code. The only time when icache sync is needed is after
3383 * kernel module is loaded and the relocation info is processed.
3384 * And it's done in elf_cpu_load_file().
3386 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3387 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3388 (opa != pa || (orig_l3 & ATTR_XN)))
3389 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3392 * Update the L3 entry
3394 if (pmap_l3_valid(orig_l3)) {
3395 KASSERT(opa == pa, ("pmap_enter: invalid update"));
3396 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3397 /* same PA, different attributes */
3398 /* XXXMJ need to reload orig_l3 for hardware DBM. */
3399 pmap_load_store(l3, new_l3);
3400 pmap_invalidate_page(pmap, va);
3401 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3402 pmap_pte_dirty(orig_l3))
3407 * This can happens if multiple threads simultaneously
3408 * access not yet mapped page. This bad for performance
3409 * since this can cause full demotion-NOP-promotion
3411 * Another possible reasons are:
3412 * - VM and pmap memory layout are diverged
3413 * - tlb flush is missing somewhere and CPU doesn't see
3416 CTR4(KTR_PMAP, "%s: already mapped page - "
3417 "pmap %p va 0x%#lx pte 0x%lx",
3418 __func__, pmap, va, new_l3);
3422 pmap_store(l3, new_l3);
3426 #if VM_NRESERVLEVEL > 0
3427 if ((mpte == NULL || mpte->wire_count == NL3PG) &&
3428 pmap_ps_enabled(pmap) &&
3429 (m->flags & PG_FICTITIOUS) == 0 &&
3430 vm_reserv_level_iffullpop(m) == 0) {
3431 pmap_promote_l2(pmap, pde, va, &lock);
3444 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
3445 * if successful. Returns false if (1) a page table page cannot be allocated
3446 * without sleeping, (2) a mapping already exists at the specified virtual
3447 * address, or (3) a PV entry cannot be allocated without reclaiming another
3451 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3452 struct rwlock **lockp)
3456 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3458 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
3459 ATTR_IDX(m->md.pv_memattr) | ATTR_AP(ATTR_AP_RO) | L2_BLOCK);
3460 if ((m->oflags & VPO_UNMANAGED) == 0) {
3461 new_l2 |= ATTR_SW_MANAGED;
3464 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3466 if (va < VM_MAXUSER_ADDRESS)
3467 new_l2 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3468 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
3469 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
3474 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
3475 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
3476 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
3477 * a mapping already exists at the specified virtual address. Returns
3478 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
3479 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
3480 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3482 * The parameter "m" is only used when creating a managed, writeable mapping.
3485 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
3486 vm_page_t m, struct rwlock **lockp)
3488 struct spglist free;
3489 pd_entry_t *l2, old_l2;
3492 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3494 if ((l2pg = pmap_alloc_l2(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
3495 NULL : lockp)) == NULL) {
3496 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
3498 return (KERN_RESOURCE_SHORTAGE);
3501 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
3502 l2 = &l2[pmap_l2_index(va)];
3503 if ((old_l2 = pmap_load(l2)) != 0) {
3504 KASSERT(l2pg->wire_count > 1,
3505 ("pmap_enter_l2: l2pg's wire count is too low"));
3506 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3509 "pmap_enter_l2: failure for va %#lx in pmap %p",
3511 return (KERN_FAILURE);
3514 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
3515 (void)pmap_remove_l2(pmap, l2, va,
3516 pmap_load(pmap_l1(pmap, va)), &free, lockp);
3518 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
3520 vm_page_free_pages_toq(&free, true);
3521 if (va >= VM_MAXUSER_ADDRESS) {
3523 * Both pmap_remove_l2() and pmap_remove_l3_range()
3524 * will leave the kernel page table page zero filled.
3525 * Nonetheless, the TLB could have an intermediate
3526 * entry for the kernel page table page.
3528 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3529 if (pmap_insert_pt_page(pmap, mt, false))
3530 panic("pmap_enter_l2: trie insert failed");
3532 pmap_invalidate_page(pmap, va);
3534 KASSERT(pmap_load(l2) == 0,
3535 ("pmap_enter_l2: non-zero L2 entry %p", l2));
3538 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
3540 * Abort this mapping if its PV entry could not be created.
3542 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
3544 if (pmap_unwire_l3(pmap, va, l2pg, &free)) {
3546 * Although "va" is not mapped, the TLB could
3547 * nonetheless have intermediate entries that
3548 * refer to the freed page table pages.
3549 * Invalidate those entries.
3551 * XXX redundant invalidation (See
3552 * _pmap_unwire_l3().)
3554 pmap_invalidate_page(pmap, va);
3555 vm_page_free_pages_toq(&free, true);
3558 "pmap_enter_l2: failure for va %#lx in pmap %p",
3560 return (KERN_RESOURCE_SHORTAGE);
3562 if ((new_l2 & ATTR_SW_DBM) != 0)
3563 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3564 vm_page_aflag_set(mt, PGA_WRITEABLE);
3568 * Increment counters.
3570 if ((new_l2 & ATTR_SW_WIRED) != 0)
3571 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
3572 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
3575 * Map the superpage.
3577 pmap_store(l2, new_l2);
3580 atomic_add_long(&pmap_l2_mappings, 1);
3581 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
3584 return (KERN_SUCCESS);
3588 * Maps a sequence of resident pages belonging to the same object.
3589 * The sequence begins with the given page m_start. This page is
3590 * mapped at the given virtual address start. Each subsequent page is
3591 * mapped at a virtual address that is offset from start by the same
3592 * amount as the page is offset from m_start within the object. The
3593 * last page in the sequence is the page with the largest offset from
3594 * m_start that can be mapped at a virtual address less than the given
3595 * virtual address end. Not every virtual page between start and end
3596 * is mapped; only those for which a resident page exists with the
3597 * corresponding offset from m_start are mapped.
3600 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3601 vm_page_t m_start, vm_prot_t prot)
3603 struct rwlock *lock;
3606 vm_pindex_t diff, psize;
3608 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3610 psize = atop(end - start);
3615 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3616 va = start + ptoa(diff);
3617 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
3618 m->psind == 1 && pmap_ps_enabled(pmap) &&
3619 pmap_enter_2mpage(pmap, va, m, prot, &lock))
3620 m = &m[L2_SIZE / PAGE_SIZE - 1];
3622 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
3624 m = TAILQ_NEXT(m, listq);
3632 * this code makes some *MAJOR* assumptions:
3633 * 1. Current pmap & pmap exists.
3636 * 4. No page table pages.
3637 * but is *MUCH* faster than pmap_enter...
3641 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3643 struct rwlock *lock;
3647 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3654 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3655 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3657 struct spglist free;
3659 pt_entry_t *l2, *l3, l3_val;
3663 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3664 (m->oflags & VPO_UNMANAGED) != 0,
3665 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3666 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3668 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3670 * In the case that a page table page is not
3671 * resident, we are creating it here.
3673 if (va < VM_MAXUSER_ADDRESS) {
3674 vm_pindex_t l2pindex;
3677 * Calculate pagetable page index
3679 l2pindex = pmap_l2_pindex(va);
3680 if (mpte && (mpte->pindex == l2pindex)) {
3686 pde = pmap_pde(pmap, va, &lvl);
3689 * If the page table page is mapped, we just increment
3690 * the hold count, and activate it. Otherwise, we
3691 * attempt to allocate a page table page. If this
3692 * attempt fails, we don't retry. Instead, we give up.
3695 l2 = pmap_l1_to_l2(pde, va);
3696 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3700 if (lvl == 2 && pmap_load(pde) != 0) {
3702 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3706 * Pass NULL instead of the PV list lock
3707 * pointer, because we don't intend to sleep.
3709 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3714 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3715 l3 = &l3[pmap_l3_index(va)];
3718 pde = pmap_pde(kernel_pmap, va, &lvl);
3719 KASSERT(pde != NULL,
3720 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3723 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3724 l3 = pmap_l2_to_l3(pde, va);
3728 * Abort if a mapping already exists.
3730 if (pmap_load(l3) != 0) {
3739 * Enter on the PV list if part of our managed memory.
3741 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3742 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3745 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
3746 pmap_invalidate_page(pmap, va);
3747 vm_page_free_pages_toq(&free, true);
3755 * Increment counters
3757 pmap_resident_count_inc(pmap, 1);
3759 pa = VM_PAGE_TO_PHYS(m);
3760 l3_val = pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3761 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3762 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3764 else if (va < VM_MAXUSER_ADDRESS)
3768 * Now validate mapping with RO protection
3770 if ((m->oflags & VPO_UNMANAGED) == 0) {
3771 l3_val |= ATTR_SW_MANAGED;
3775 /* Sync icache before the mapping is stored to PTE */
3776 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3777 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
3778 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3780 pmap_store(l3, l3_val);
3787 * This code maps large physical mmap regions into the
3788 * processor address space. Note that some shortcuts
3789 * are taken, but the code works.
3792 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3793 vm_pindex_t pindex, vm_size_t size)
3796 VM_OBJECT_ASSERT_WLOCKED(object);
3797 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3798 ("pmap_object_init_pt: non-device object"));
3802 * Clear the wired attribute from the mappings for the specified range of
3803 * addresses in the given pmap. Every valid mapping within that range
3804 * must have the wired attribute set. In contrast, invalid mappings
3805 * cannot have the wired attribute set, so they are ignored.
3807 * The wired attribute of the page table entry is not a hardware feature,
3808 * so there is no need to invalidate any TLB entries.
3811 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3813 vm_offset_t va_next;
3814 pd_entry_t *l0, *l1, *l2;
3818 for (; sva < eva; sva = va_next) {
3819 l0 = pmap_l0(pmap, sva);
3820 if (pmap_load(l0) == 0) {
3821 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3827 l1 = pmap_l0_to_l1(l0, sva);
3828 if (pmap_load(l1) == 0) {
3829 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3835 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3839 l2 = pmap_l1_to_l2(l1, sva);
3840 if (pmap_load(l2) == 0)
3843 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3844 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
3845 panic("pmap_unwire: l2 %#jx is missing "
3846 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
3849 * Are we unwiring the entire large page? If not,
3850 * demote the mapping and fall through.
3852 if (sva + L2_SIZE == va_next && eva >= va_next) {
3853 pmap_clear_bits(l2, ATTR_SW_WIRED);
3854 pmap->pm_stats.wired_count -= L2_SIZE /
3857 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3858 panic("pmap_unwire: demotion failed");
3860 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3861 ("pmap_unwire: Invalid l2 entry after demotion"));
3865 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3867 if (pmap_load(l3) == 0)
3869 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
3870 panic("pmap_unwire: l3 %#jx is missing "
3871 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
3874 * ATTR_SW_WIRED must be cleared atomically. Although
3875 * the pmap lock synchronizes access to ATTR_SW_WIRED,
3876 * the System MMU may write to the entry concurrently.
3878 pmap_clear_bits(l3, ATTR_SW_WIRED);
3879 pmap->pm_stats.wired_count--;
3886 * Copy the range specified by src_addr/len
3887 * from the source map to the range dst_addr/len
3888 * in the destination map.
3890 * This routine is only advisory and need not do anything.
3892 * Because the executable mappings created by this routine are copied,
3893 * it should not have to flush the instruction cache.
3896 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3897 vm_offset_t src_addr)
3899 struct rwlock *lock;
3900 struct spglist free;
3901 pd_entry_t *l0, *l1, *l2, srcptepaddr;
3902 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
3903 vm_offset_t addr, end_addr, va_next;
3904 vm_page_t dst_l2pg, dstmpte, srcmpte;
3906 if (dst_addr != src_addr)
3908 end_addr = src_addr + len;
3910 if (dst_pmap < src_pmap) {
3911 PMAP_LOCK(dst_pmap);
3912 PMAP_LOCK(src_pmap);
3914 PMAP_LOCK(src_pmap);
3915 PMAP_LOCK(dst_pmap);
3917 for (addr = src_addr; addr < end_addr; addr = va_next) {
3918 l0 = pmap_l0(src_pmap, addr);
3919 if (pmap_load(l0) == 0) {
3920 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
3925 l1 = pmap_l0_to_l1(l0, addr);
3926 if (pmap_load(l1) == 0) {
3927 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
3932 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
3935 l2 = pmap_l1_to_l2(l1, addr);
3936 srcptepaddr = pmap_load(l2);
3937 if (srcptepaddr == 0)
3939 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
3940 if ((addr & L2_OFFSET) != 0 ||
3941 addr + L2_SIZE > end_addr)
3943 dst_l2pg = pmap_alloc_l2(dst_pmap, addr, NULL);
3944 if (dst_l2pg == NULL)
3947 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_l2pg));
3948 l2 = &l2[pmap_l2_index(addr)];
3949 if (pmap_load(l2) == 0 &&
3950 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
3951 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
3952 PMAP_ENTER_NORECLAIM, &lock))) {
3953 mask = ATTR_AF | ATTR_SW_WIRED;
3955 if ((srcptepaddr & ATTR_SW_DBM) != 0)
3956 nbits |= ATTR_AP_RW_BIT;
3957 pmap_store(l2, (srcptepaddr & ~mask) | nbits);
3958 pmap_resident_count_inc(dst_pmap, L2_SIZE /
3960 atomic_add_long(&pmap_l2_mappings, 1);
3962 dst_l2pg->wire_count--;
3965 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
3966 ("pmap_copy: invalid L2 entry"));
3967 srcptepaddr &= ~ATTR_MASK;
3968 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
3969 KASSERT(srcmpte->wire_count > 0,
3970 ("pmap_copy: source page table page is unused"));
3971 if (va_next > end_addr)
3973 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
3974 src_pte = &src_pte[pmap_l3_index(addr)];
3976 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
3977 ptetemp = pmap_load(src_pte);
3980 * We only virtual copy managed pages.
3982 if ((ptetemp & ATTR_SW_MANAGED) == 0)
3985 if (dstmpte != NULL) {
3986 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
3987 ("dstmpte pindex/addr mismatch"));
3988 dstmpte->wire_count++;
3989 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
3992 dst_pte = (pt_entry_t *)
3993 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
3994 dst_pte = &dst_pte[pmap_l3_index(addr)];
3995 if (pmap_load(dst_pte) == 0 &&
3996 pmap_try_insert_pv_entry(dst_pmap, addr,
3997 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
3999 * Clear the wired, modified, and accessed
4000 * (referenced) bits during the copy.
4002 mask = ATTR_AF | ATTR_SW_WIRED;
4004 if ((ptetemp & ATTR_SW_DBM) != 0)
4005 nbits |= ATTR_AP_RW_BIT;
4006 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
4007 pmap_resident_count_inc(dst_pmap, 1);
4010 if (pmap_unwire_l3(dst_pmap, addr, dstmpte,
4013 * Although "addr" is not mapped,
4014 * the TLB could nonetheless have
4015 * intermediate entries that refer
4016 * to the freed page table pages.
4017 * Invalidate those entries.
4019 * XXX redundant invalidation
4021 pmap_invalidate_page(dst_pmap, addr);
4022 vm_page_free_pages_toq(&free, true);
4026 /* Have we copied all of the valid mappings? */
4027 if (dstmpte->wire_count >= srcmpte->wire_count)
4033 * XXX This barrier may not be needed because the destination pmap is
4040 PMAP_UNLOCK(src_pmap);
4041 PMAP_UNLOCK(dst_pmap);
4045 * pmap_zero_page zeros the specified hardware page by mapping
4046 * the page into KVM and using bzero to clear its contents.
4049 pmap_zero_page(vm_page_t m)
4051 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4053 pagezero((void *)va);
4057 * pmap_zero_page_area zeros the specified hardware page by mapping
4058 * the page into KVM and using bzero to clear its contents.
4060 * off and size may not cover an area beyond a single hardware page.
4063 pmap_zero_page_area(vm_page_t m, int off, int size)
4065 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4067 if (off == 0 && size == PAGE_SIZE)
4068 pagezero((void *)va);
4070 bzero((char *)va + off, size);
4074 * pmap_copy_page copies the specified (machine independent)
4075 * page by mapping the page into virtual memory and using
4076 * bcopy to copy the page, one machine dependent page at a
4080 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4082 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4083 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4085 pagecopy((void *)src, (void *)dst);
4088 int unmapped_buf_allowed = 1;
4091 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4092 vm_offset_t b_offset, int xfersize)
4096 vm_paddr_t p_a, p_b;
4097 vm_offset_t a_pg_offset, b_pg_offset;
4100 while (xfersize > 0) {
4101 a_pg_offset = a_offset & PAGE_MASK;
4102 m_a = ma[a_offset >> PAGE_SHIFT];
4103 p_a = m_a->phys_addr;
4104 b_pg_offset = b_offset & PAGE_MASK;
4105 m_b = mb[b_offset >> PAGE_SHIFT];
4106 p_b = m_b->phys_addr;
4107 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4108 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4109 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
4110 panic("!DMAP a %lx", p_a);
4112 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
4114 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
4115 panic("!DMAP b %lx", p_b);
4117 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
4119 bcopy(a_cp, b_cp, cnt);
4127 pmap_quick_enter_page(vm_page_t m)
4130 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
4134 pmap_quick_remove_page(vm_offset_t addr)
4139 * Returns true if the pmap's pv is one of the first
4140 * 16 pvs linked to from this page. This count may
4141 * be changed upwards or downwards in the future; it
4142 * is only necessary that true be returned for a small
4143 * subset of pmaps for proper page aging.
4146 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4148 struct md_page *pvh;
4149 struct rwlock *lock;
4154 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4155 ("pmap_page_exists_quick: page %p is not managed", m));
4157 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4159 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4160 if (PV_PMAP(pv) == pmap) {
4168 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4169 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4170 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4171 if (PV_PMAP(pv) == pmap) {
4185 * pmap_page_wired_mappings:
4187 * Return the number of managed mappings to the given physical page
4191 pmap_page_wired_mappings(vm_page_t m)
4193 struct rwlock *lock;
4194 struct md_page *pvh;
4198 int count, lvl, md_gen, pvh_gen;
4200 if ((m->oflags & VPO_UNMANAGED) != 0)
4202 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4206 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4208 if (!PMAP_TRYLOCK(pmap)) {
4209 md_gen = m->md.pv_gen;
4213 if (md_gen != m->md.pv_gen) {
4218 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4219 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4223 if ((m->flags & PG_FICTITIOUS) == 0) {
4224 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4225 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4227 if (!PMAP_TRYLOCK(pmap)) {
4228 md_gen = m->md.pv_gen;
4229 pvh_gen = pvh->pv_gen;
4233 if (md_gen != m->md.pv_gen ||
4234 pvh_gen != pvh->pv_gen) {
4239 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4241 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4251 * Destroy all managed, non-wired mappings in the given user-space
4252 * pmap. This pmap cannot be active on any processor besides the
4255 * This function cannot be applied to the kernel pmap. Moreover, it
4256 * is not intended for general use. It is only to be used during
4257 * process termination. Consequently, it can be implemented in ways
4258 * that make it faster than pmap_remove(). First, it can more quickly
4259 * destroy mappings by iterating over the pmap's collection of PV
4260 * entries, rather than searching the page table. Second, it doesn't
4261 * have to test and clear the page table entries atomically, because
4262 * no processor is currently accessing the user address space. In
4263 * particular, a page table entry's dirty bit won't change state once
4264 * this function starts.
4267 pmap_remove_pages(pmap_t pmap)
4270 pt_entry_t *pte, tpte;
4271 struct spglist free;
4272 vm_page_t m, ml3, mt;
4274 struct md_page *pvh;
4275 struct pv_chunk *pc, *npc;
4276 struct rwlock *lock;
4278 uint64_t inuse, bitmask;
4279 int allfree, field, freed, idx, lvl;
4286 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4289 for (field = 0; field < _NPCM; field++) {
4290 inuse = ~pc->pc_map[field] & pc_freemask[field];
4291 while (inuse != 0) {
4292 bit = ffsl(inuse) - 1;
4293 bitmask = 1UL << bit;
4294 idx = field * 64 + bit;
4295 pv = &pc->pc_pventry[idx];
4298 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4299 KASSERT(pde != NULL,
4300 ("Attempting to remove an unmapped page"));
4304 pte = pmap_l1_to_l2(pde, pv->pv_va);
4305 tpte = pmap_load(pte);
4306 KASSERT((tpte & ATTR_DESCR_MASK) ==
4308 ("Attempting to remove an invalid "
4309 "block: %lx", tpte));
4310 tpte = pmap_load(pte);
4313 pte = pmap_l2_to_l3(pde, pv->pv_va);
4314 tpte = pmap_load(pte);
4315 KASSERT((tpte & ATTR_DESCR_MASK) ==
4317 ("Attempting to remove an invalid "
4318 "page: %lx", tpte));
4322 "Invalid page directory level: %d",
4327 * We cannot remove wired pages from a process' mapping at this time
4329 if (tpte & ATTR_SW_WIRED) {
4334 pa = tpte & ~ATTR_MASK;
4336 m = PHYS_TO_VM_PAGE(pa);
4337 KASSERT(m->phys_addr == pa,
4338 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4339 m, (uintmax_t)m->phys_addr,
4342 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4343 m < &vm_page_array[vm_page_array_size],
4344 ("pmap_remove_pages: bad pte %#jx",
4348 * Because this pmap is not active on other
4349 * processors, the dirty bit cannot have
4350 * changed state since we last loaded pte.
4355 * Update the vm_page_t clean/reference bits.
4357 if (pmap_pte_dirty(tpte)) {
4360 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4369 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4372 pc->pc_map[field] |= bitmask;
4375 pmap_resident_count_dec(pmap,
4376 L2_SIZE / PAGE_SIZE);
4377 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
4378 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
4380 if (TAILQ_EMPTY(&pvh->pv_list)) {
4381 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4382 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
4383 TAILQ_EMPTY(&mt->md.pv_list))
4384 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4386 ml3 = pmap_remove_pt_page(pmap,
4389 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
4390 ("pmap_remove_pages: l3 page not promoted"));
4391 pmap_resident_count_dec(pmap,1);
4392 KASSERT(ml3->wire_count == NL3PG,
4393 ("pmap_remove_pages: l3 page wire count error"));
4394 ml3->wire_count = 0;
4395 pmap_add_delayed_free_list(ml3,
4400 pmap_resident_count_dec(pmap, 1);
4401 TAILQ_REMOVE(&m->md.pv_list, pv,
4404 if ((m->aflags & PGA_WRITEABLE) != 0 &&
4405 TAILQ_EMPTY(&m->md.pv_list) &&
4406 (m->flags & PG_FICTITIOUS) == 0) {
4408 VM_PAGE_TO_PHYS(m));
4409 if (TAILQ_EMPTY(&pvh->pv_list))
4410 vm_page_aflag_clear(m,
4415 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
4420 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4421 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4422 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4424 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4428 pmap_invalidate_all(pmap);
4432 vm_page_free_pages_toq(&free, true);
4436 * This is used to check if a page has been accessed or modified. As we
4437 * don't have a bit to see if it has been modified we have to assume it
4438 * has been if the page is read/write.
4441 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
4443 struct rwlock *lock;
4445 struct md_page *pvh;
4446 pt_entry_t *pte, mask, value;
4448 int lvl, md_gen, pvh_gen;
4452 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4455 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4457 if (!PMAP_TRYLOCK(pmap)) {
4458 md_gen = m->md.pv_gen;
4462 if (md_gen != m->md.pv_gen) {
4467 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4469 ("pmap_page_test_mappings: Invalid level %d", lvl));
4473 mask |= ATTR_AP_RW_BIT;
4474 value |= ATTR_AP(ATTR_AP_RW);
4477 mask |= ATTR_AF | ATTR_DESCR_MASK;
4478 value |= ATTR_AF | L3_PAGE;
4480 rv = (pmap_load(pte) & mask) == value;
4485 if ((m->flags & PG_FICTITIOUS) == 0) {
4486 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4487 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4489 if (!PMAP_TRYLOCK(pmap)) {
4490 md_gen = m->md.pv_gen;
4491 pvh_gen = pvh->pv_gen;
4495 if (md_gen != m->md.pv_gen ||
4496 pvh_gen != pvh->pv_gen) {
4501 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4503 ("pmap_page_test_mappings: Invalid level %d", lvl));
4507 mask |= ATTR_AP_RW_BIT;
4508 value |= ATTR_AP(ATTR_AP_RW);
4511 mask |= ATTR_AF | ATTR_DESCR_MASK;
4512 value |= ATTR_AF | L2_BLOCK;
4514 rv = (pmap_load(pte) & mask) == value;
4528 * Return whether or not the specified physical page was modified
4529 * in any physical maps.
4532 pmap_is_modified(vm_page_t m)
4535 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4536 ("pmap_is_modified: page %p is not managed", m));
4539 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4540 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4541 * is clear, no PTEs can have PG_M set.
4543 VM_OBJECT_ASSERT_WLOCKED(m->object);
4544 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4546 return (pmap_page_test_mappings(m, FALSE, TRUE));
4550 * pmap_is_prefaultable:
4552 * Return whether or not the specified virtual address is eligible
4556 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4564 pte = pmap_pte(pmap, addr, &lvl);
4565 if (pte != NULL && pmap_load(pte) != 0) {
4573 * pmap_is_referenced:
4575 * Return whether or not the specified physical page was referenced
4576 * in any physical maps.
4579 pmap_is_referenced(vm_page_t m)
4582 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4583 ("pmap_is_referenced: page %p is not managed", m));
4584 return (pmap_page_test_mappings(m, TRUE, FALSE));
4588 * Clear the write and modified bits in each of the given page's mappings.
4591 pmap_remove_write(vm_page_t m)
4593 struct md_page *pvh;
4595 struct rwlock *lock;
4596 pv_entry_t next_pv, pv;
4597 pt_entry_t oldpte, *pte;
4599 int lvl, md_gen, pvh_gen;
4601 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4602 ("pmap_remove_write: page %p is not managed", m));
4605 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4606 * set by another thread while the object is locked. Thus,
4607 * if PGA_WRITEABLE is clear, no page table entries need updating.
4609 VM_OBJECT_ASSERT_WLOCKED(m->object);
4610 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4612 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4613 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4614 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4617 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4619 if (!PMAP_TRYLOCK(pmap)) {
4620 pvh_gen = pvh->pv_gen;
4624 if (pvh_gen != pvh->pv_gen) {
4631 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4632 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
4633 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
4634 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4635 ("inconsistent pv lock %p %p for page %p",
4636 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4639 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4641 if (!PMAP_TRYLOCK(pmap)) {
4642 pvh_gen = pvh->pv_gen;
4643 md_gen = m->md.pv_gen;
4647 if (pvh_gen != pvh->pv_gen ||
4648 md_gen != m->md.pv_gen) {
4654 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4655 oldpte = pmap_load(pte);
4657 if ((oldpte & ATTR_SW_DBM) != 0) {
4658 if (!atomic_fcmpset_long(pte, &oldpte,
4659 (oldpte | ATTR_AP_RW_BIT) & ~ATTR_SW_DBM))
4661 if ((oldpte & ATTR_AP_RW_BIT) ==
4662 ATTR_AP(ATTR_AP_RW))
4664 pmap_invalidate_page(pmap, pv->pv_va);
4669 vm_page_aflag_clear(m, PGA_WRITEABLE);
4673 * pmap_ts_referenced:
4675 * Return a count of reference bits for a page, clearing those bits.
4676 * It is not necessary for every reference bit to be cleared, but it
4677 * is necessary that 0 only be returned when there are truly no
4678 * reference bits set.
4680 * As an optimization, update the page's dirty field if a modified bit is
4681 * found while counting reference bits. This opportunistic update can be
4682 * performed at low cost and can eliminate the need for some future calls
4683 * to pmap_is_modified(). However, since this function stops after
4684 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4685 * dirty pages. Those dirty pages will only be detected by a future call
4686 * to pmap_is_modified().
4689 pmap_ts_referenced(vm_page_t m)
4691 struct md_page *pvh;
4694 struct rwlock *lock;
4695 pd_entry_t *pde, tpde;
4696 pt_entry_t *pte, tpte;
4699 int cleared, lvl, md_gen, not_cleared, pvh_gen;
4700 struct spglist free;
4702 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4703 ("pmap_ts_referenced: page %p is not managed", m));
4706 pa = VM_PAGE_TO_PHYS(m);
4707 lock = PHYS_TO_PV_LIST_LOCK(pa);
4708 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4712 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4713 goto small_mappings;
4719 if (!PMAP_TRYLOCK(pmap)) {
4720 pvh_gen = pvh->pv_gen;
4724 if (pvh_gen != pvh->pv_gen) {
4730 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4731 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4733 ("pmap_ts_referenced: invalid pde level %d", lvl));
4734 tpde = pmap_load(pde);
4735 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4736 ("pmap_ts_referenced: found an invalid l1 table"));
4737 pte = pmap_l1_to_l2(pde, pv->pv_va);
4738 tpte = pmap_load(pte);
4739 if (pmap_pte_dirty(tpte)) {
4741 * Although "tpte" is mapping a 2MB page, because
4742 * this function is called at a 4KB page granularity,
4743 * we only update the 4KB page under test.
4748 if ((tpte & ATTR_AF) != 0) {
4750 * Since this reference bit is shared by 512 4KB pages,
4751 * it should not be cleared every time it is tested.
4752 * Apply a simple "hash" function on the physical page
4753 * number, the virtual superpage number, and the pmap
4754 * address to select one 4KB page out of the 512 on
4755 * which testing the reference bit will result in
4756 * clearing that reference bit. This function is
4757 * designed to avoid the selection of the same 4KB page
4758 * for every 2MB page mapping.
4760 * On demotion, a mapping that hasn't been referenced
4761 * is simply destroyed. To avoid the possibility of a
4762 * subsequent page fault on a demoted wired mapping,
4763 * always leave its reference bit set. Moreover,
4764 * since the superpage is wired, the current state of
4765 * its reference bit won't affect page replacement.
4767 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4768 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4769 (tpte & ATTR_SW_WIRED) == 0) {
4770 pmap_clear_bits(pte, ATTR_AF);
4771 pmap_invalidate_page(pmap, pv->pv_va);
4777 /* Rotate the PV list if it has more than one entry. */
4778 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4779 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4780 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4783 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4785 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4787 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4794 if (!PMAP_TRYLOCK(pmap)) {
4795 pvh_gen = pvh->pv_gen;
4796 md_gen = m->md.pv_gen;
4800 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4805 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4806 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4808 ("pmap_ts_referenced: invalid pde level %d", lvl));
4809 tpde = pmap_load(pde);
4810 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4811 ("pmap_ts_referenced: found an invalid l2 table"));
4812 pte = pmap_l2_to_l3(pde, pv->pv_va);
4813 tpte = pmap_load(pte);
4814 if (pmap_pte_dirty(tpte))
4816 if ((tpte & ATTR_AF) != 0) {
4817 if ((tpte & ATTR_SW_WIRED) == 0) {
4818 pmap_clear_bits(pte, ATTR_AF);
4819 pmap_invalidate_page(pmap, pv->pv_va);
4825 /* Rotate the PV list if it has more than one entry. */
4826 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4827 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4828 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4831 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4832 not_cleared < PMAP_TS_REFERENCED_MAX);
4835 vm_page_free_pages_toq(&free, true);
4836 return (cleared + not_cleared);
4840 * Apply the given advice to the specified range of addresses within the
4841 * given pmap. Depending on the advice, clear the referenced and/or
4842 * modified flags in each mapping and set the mapped page's dirty field.
4845 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4847 struct rwlock *lock;
4848 vm_offset_t va, va_next;
4850 pd_entry_t *l0, *l1, *l2, oldl2;
4851 pt_entry_t *l3, oldl3;
4853 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4857 for (; sva < eva; sva = va_next) {
4858 l0 = pmap_l0(pmap, sva);
4859 if (pmap_load(l0) == 0) {
4860 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
4865 l1 = pmap_l0_to_l1(l0, sva);
4866 if (pmap_load(l1) == 0) {
4867 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
4872 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
4875 l2 = pmap_l1_to_l2(l1, sva);
4876 oldl2 = pmap_load(l2);
4879 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
4880 if ((oldl2 & ATTR_SW_MANAGED) == 0)
4883 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
4888 * The 2MB page mapping was destroyed.
4894 * Unless the page mappings are wired, remove the
4895 * mapping to a single page so that a subsequent
4896 * access may repromote. Choosing the last page
4897 * within the address range [sva, min(va_next, eva))
4898 * generally results in more repromotions. Since the
4899 * underlying page table page is fully populated, this
4900 * removal never frees a page table page.
4902 if ((oldl2 & ATTR_SW_WIRED) == 0) {
4908 ("pmap_advise: no address gap"));
4909 l3 = pmap_l2_to_l3(l2, va);
4910 KASSERT(pmap_load(l3) != 0,
4911 ("pmap_advise: invalid PTE"));
4912 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
4918 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
4919 ("pmap_advise: invalid L2 entry after demotion"));
4923 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
4925 oldl3 = pmap_load(l3);
4926 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
4927 (ATTR_SW_MANAGED | L3_PAGE))
4929 else if (pmap_pte_dirty(oldl3)) {
4930 if (advice == MADV_DONTNEED) {
4932 * Future calls to pmap_is_modified()
4933 * can be avoided by making the page
4936 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK);
4939 while (!atomic_fcmpset_long(l3, &oldl3,
4940 (oldl3 & ~ATTR_AF) | ATTR_AP(ATTR_AP_RO)))
4942 } else if ((oldl3 & ATTR_AF) != 0)
4943 pmap_clear_bits(l3, ATTR_AF);
4950 if (va != va_next) {
4951 pmap_invalidate_range(pmap, va, sva);
4956 pmap_invalidate_range(pmap, va, sva);
4962 * Clear the modify bits on the specified physical page.
4965 pmap_clear_modify(vm_page_t m)
4967 struct md_page *pvh;
4968 struct rwlock *lock;
4970 pv_entry_t next_pv, pv;
4971 pd_entry_t *l2, oldl2;
4972 pt_entry_t *l3, oldl3;
4974 int md_gen, pvh_gen;
4976 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4977 ("pmap_clear_modify: page %p is not managed", m));
4978 VM_OBJECT_ASSERT_WLOCKED(m->object);
4979 KASSERT(!vm_page_xbusied(m),
4980 ("pmap_clear_modify: page %p is exclusive busied", m));
4983 * If the page is not PGA_WRITEABLE, then no PTEs can have ATTR_SW_DBM
4984 * set. If the object containing the page is locked and the page is not
4985 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4987 if ((m->aflags & PGA_WRITEABLE) == 0)
4989 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4990 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4991 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4994 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4996 if (!PMAP_TRYLOCK(pmap)) {
4997 pvh_gen = pvh->pv_gen;
5001 if (pvh_gen != pvh->pv_gen) {
5007 l2 = pmap_l2(pmap, va);
5008 oldl2 = pmap_load(l2);
5009 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */
5010 if ((oldl2 & ATTR_SW_DBM) != 0 &&
5011 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
5012 (oldl2 & ATTR_SW_WIRED) == 0) {
5014 * Write protect the mapping to a single page so that
5015 * a subsequent write access may repromote.
5017 va += VM_PAGE_TO_PHYS(m) - (oldl2 & ~ATTR_MASK);
5018 l3 = pmap_l2_to_l3(l2, va);
5019 oldl3 = pmap_load(l3);
5020 while (!atomic_fcmpset_long(l3, &oldl3,
5021 (oldl3 & ~ATTR_SW_DBM) | ATTR_AP(ATTR_AP_RO)))
5024 pmap_invalidate_page(pmap, va);
5028 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5030 if (!PMAP_TRYLOCK(pmap)) {
5031 md_gen = m->md.pv_gen;
5032 pvh_gen = pvh->pv_gen;
5036 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5041 l2 = pmap_l2(pmap, pv->pv_va);
5042 l3 = pmap_l2_to_l3(l2, pv->pv_va);
5043 oldl3 = pmap_load(l3);
5044 if (pmap_l3_valid(oldl3) &&
5045 (oldl3 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM) {
5046 pmap_set_bits(l3, ATTR_AP(ATTR_AP_RO));
5047 pmap_invalidate_page(pmap, pv->pv_va);
5055 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5057 struct pmap_preinit_mapping *ppim;
5058 vm_offset_t va, offset;
5061 int i, lvl, l2_blocks, free_l2_count, start_idx;
5063 if (!vm_initialized) {
5065 * No L3 ptables so map entire L2 blocks where start VA is:
5066 * preinit_map_va + start_idx * L2_SIZE
5067 * There may be duplicate mappings (multiple VA -> same PA) but
5068 * ARM64 dcache is always PIPT so that's acceptable.
5073 /* Calculate how many L2 blocks are needed for the mapping */
5074 l2_blocks = (roundup2(pa + size, L2_SIZE) -
5075 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
5077 offset = pa & L2_OFFSET;
5079 if (preinit_map_va == 0)
5082 /* Map 2MiB L2 blocks from reserved VA space */
5086 /* Find enough free contiguous VA space */
5087 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5088 ppim = pmap_preinit_mapping + i;
5089 if (free_l2_count > 0 && ppim->pa != 0) {
5090 /* Not enough space here */
5096 if (ppim->pa == 0) {
5098 if (start_idx == -1)
5101 if (free_l2_count == l2_blocks)
5105 if (free_l2_count != l2_blocks)
5106 panic("%s: too many preinit mappings", __func__);
5108 va = preinit_map_va + (start_idx * L2_SIZE);
5109 for (i = start_idx; i < start_idx + l2_blocks; i++) {
5110 /* Mark entries as allocated */
5111 ppim = pmap_preinit_mapping + i;
5113 ppim->va = va + offset;
5118 pa = rounddown2(pa, L2_SIZE);
5119 for (i = 0; i < l2_blocks; i++) {
5120 pde = pmap_pde(kernel_pmap, va, &lvl);
5121 KASSERT(pde != NULL,
5122 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
5125 ("pmap_mapbios: Invalid level %d", lvl));
5127 /* Insert L2_BLOCK */
5128 l2 = pmap_l1_to_l2(pde, va);
5130 pa | ATTR_DEFAULT | ATTR_XN |
5131 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
5136 pmap_invalidate_all(kernel_pmap);
5138 va = preinit_map_va + (start_idx * L2_SIZE);
5141 /* kva_alloc may be used to map the pages */
5142 offset = pa & PAGE_MASK;
5143 size = round_page(offset + size);
5145 va = kva_alloc(size);
5147 panic("%s: Couldn't allocate KVA", __func__);
5149 pde = pmap_pde(kernel_pmap, va, &lvl);
5150 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
5152 /* L3 table is linked */
5153 va = trunc_page(va);
5154 pa = trunc_page(pa);
5155 pmap_kenter(va, size, pa, CACHED_MEMORY);
5158 return ((void *)(va + offset));
5162 pmap_unmapbios(vm_offset_t va, vm_size_t size)
5164 struct pmap_preinit_mapping *ppim;
5165 vm_offset_t offset, tmpsize, va_trunc;
5168 int i, lvl, l2_blocks, block;
5172 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
5173 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
5175 /* Remove preinit mapping */
5176 preinit_map = false;
5178 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5179 ppim = pmap_preinit_mapping + i;
5180 if (ppim->va == va) {
5181 KASSERT(ppim->size == size,
5182 ("pmap_unmapbios: size mismatch"));
5187 offset = block * L2_SIZE;
5188 va_trunc = rounddown2(va, L2_SIZE) + offset;
5190 /* Remove L2_BLOCK */
5191 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
5192 KASSERT(pde != NULL,
5193 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
5195 l2 = pmap_l1_to_l2(pde, va_trunc);
5198 if (block == (l2_blocks - 1))
5204 pmap_invalidate_all(kernel_pmap);
5208 /* Unmap the pages reserved with kva_alloc. */
5209 if (vm_initialized) {
5210 offset = va & PAGE_MASK;
5211 size = round_page(offset + size);
5212 va = trunc_page(va);
5214 pde = pmap_pde(kernel_pmap, va, &lvl);
5215 KASSERT(pde != NULL,
5216 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
5217 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
5219 /* Unmap and invalidate the pages */
5220 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5221 pmap_kremove(va + tmpsize);
5228 * Sets the memory attribute for the specified page.
5231 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5234 m->md.pv_memattr = ma;
5237 * If "m" is a normal page, update its direct mapping. This update
5238 * can be relied upon to perform any cache operations that are
5239 * required for data coherence.
5241 if ((m->flags & PG_FICTITIOUS) == 0 &&
5242 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
5243 m->md.pv_memattr) != 0)
5244 panic("memory attribute change on the direct map failed");
5248 * Changes the specified virtual address range's memory type to that given by
5249 * the parameter "mode". The specified virtual address range must be
5250 * completely contained within either the direct map or the kernel map. If
5251 * the virtual address range is contained within the kernel map, then the
5252 * memory type for each of the corresponding ranges of the direct map is also
5253 * changed. (The corresponding ranges of the direct map are those ranges that
5254 * map the same physical pages as the specified virtual address range.) These
5255 * changes to the direct map are necessary because Intel describes the
5256 * behavior of their processors as "undefined" if two or more mappings to the
5257 * same physical page have different memory types.
5259 * Returns zero if the change completed successfully, and either EINVAL or
5260 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5261 * of the virtual address range was not mapped, and ENOMEM is returned if
5262 * there was insufficient memory available to complete the change. In the
5263 * latter case, the memory type may have been changed on some part of the
5264 * virtual address range or the direct map.
5267 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5271 PMAP_LOCK(kernel_pmap);
5272 error = pmap_change_attr_locked(va, size, mode);
5273 PMAP_UNLOCK(kernel_pmap);
5278 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
5280 vm_offset_t base, offset, tmpva;
5281 pt_entry_t l3, *pte, *newpte;
5284 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
5285 base = trunc_page(va);
5286 offset = va & PAGE_MASK;
5287 size = round_page(offset + size);
5289 if (!VIRT_IN_DMAP(base))
5292 for (tmpva = base; tmpva < base + size; ) {
5293 pte = pmap_pte(kernel_pmap, tmpva, &lvl);
5297 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
5299 * We already have the correct attribute,
5300 * ignore this entry.
5304 panic("Invalid DMAP table level: %d\n", lvl);
5306 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
5309 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
5317 * Split the entry to an level 3 table, then
5318 * set the new attribute.
5322 panic("Invalid DMAP table level: %d\n", lvl);
5324 newpte = pmap_demote_l1(kernel_pmap, pte,
5325 tmpva & ~L1_OFFSET);
5328 pte = pmap_l1_to_l2(pte, tmpva);
5330 newpte = pmap_demote_l2(kernel_pmap, pte,
5334 pte = pmap_l2_to_l3(pte, tmpva);
5336 /* Update the entry */
5337 l3 = pmap_load(pte);
5338 l3 &= ~ATTR_IDX_MASK;
5339 l3 |= ATTR_IDX(mode);
5340 if (mode == DEVICE_MEMORY)
5343 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
5347 * If moving to a non-cacheable entry flush
5350 if (mode == VM_MEMATTR_UNCACHEABLE)
5351 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
5363 * Create an L2 table to map all addresses within an L1 mapping.
5366 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
5368 pt_entry_t *l2, newl2, oldl1;
5370 vm_paddr_t l2phys, phys;
5374 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5375 oldl1 = pmap_load(l1);
5376 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
5377 ("pmap_demote_l1: Demoting a non-block entry"));
5378 KASSERT((va & L1_OFFSET) == 0,
5379 ("pmap_demote_l1: Invalid virtual address %#lx", va));
5380 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
5381 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
5384 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
5385 tmpl1 = kva_alloc(PAGE_SIZE);
5390 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
5391 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
5392 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
5393 " in pmap %p", va, pmap);
5397 l2phys = VM_PAGE_TO_PHYS(ml2);
5398 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
5400 /* Address the range points at */
5401 phys = oldl1 & ~ATTR_MASK;
5402 /* The attributed from the old l1 table to be copied */
5403 newl2 = oldl1 & ATTR_MASK;
5405 /* Create the new entries */
5406 for (i = 0; i < Ln_ENTRIES; i++) {
5407 l2[i] = newl2 | phys;
5410 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
5411 ("Invalid l2 page (%lx != %lx)", l2[0],
5412 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
5415 pmap_kenter(tmpl1, PAGE_SIZE,
5416 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY);
5417 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
5420 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
5423 pmap_kremove(tmpl1);
5424 kva_free(tmpl1, PAGE_SIZE);
5431 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
5435 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
5442 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
5443 struct rwlock **lockp)
5445 struct spglist free;
5448 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
5450 vm_page_free_pages_toq(&free, true);
5454 * Create an L3 table to map all addresses within an L2 mapping.
5457 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
5458 struct rwlock **lockp)
5460 pt_entry_t *l3, newl3, oldl2;
5465 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5467 oldl2 = pmap_load(l2);
5468 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
5469 ("pmap_demote_l2: Demoting a non-block entry"));
5473 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
5474 tmpl2 = kva_alloc(PAGE_SIZE);
5480 * Invalidate the 2MB page mapping and return "failure" if the
5481 * mapping was never accessed.
5483 if ((oldl2 & ATTR_AF) == 0) {
5484 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5485 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
5486 pmap_demote_l2_abort(pmap, va, l2, lockp);
5487 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
5492 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
5493 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5494 ("pmap_demote_l2: page table page for a wired mapping"
5498 * If the page table page is missing and the mapping
5499 * is for a kernel address, the mapping must belong to
5500 * the direct map. Page table pages are preallocated
5501 * for every other part of the kernel address space,
5502 * so the direct map region is the only part of the
5503 * kernel address space that must be handled here.
5505 KASSERT(va < VM_MAXUSER_ADDRESS || VIRT_IN_DMAP(va),
5506 ("pmap_demote_l2: No saved mpte for va %#lx", va));
5509 * If the 2MB page mapping belongs to the direct map
5510 * region of the kernel's address space, then the page
5511 * allocation request specifies the highest possible
5512 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5513 * priority is normal.
5515 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
5516 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5517 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5520 * If the allocation of the new page table page fails,
5521 * invalidate the 2MB page mapping and return "failure".
5524 pmap_demote_l2_abort(pmap, va, l2, lockp);
5525 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
5526 " in pmap %p", va, pmap);
5530 if (va < VM_MAXUSER_ADDRESS) {
5531 ml3->wire_count = NL3PG;
5532 pmap_resident_count_inc(pmap, 1);
5535 l3phys = VM_PAGE_TO_PHYS(ml3);
5536 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
5537 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
5538 KASSERT((oldl2 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) !=
5539 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM),
5540 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
5543 * If the page table page is not leftover from an earlier promotion,
5544 * or the mapping attributes have changed, (re)initialize the L3 table.
5546 * When pmap_update_entry() clears the old L2 mapping, it (indirectly)
5547 * performs a dsb(). That dsb() ensures that the stores for filling
5548 * "l3" are visible before "l3" is added to the page table.
5550 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK))
5551 pmap_fill_l3(l3, newl3);
5554 * Map the temporary page so we don't lose access to the l2 table.
5557 pmap_kenter(tmpl2, PAGE_SIZE,
5558 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY);
5559 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
5563 * The spare PV entries must be reserved prior to demoting the
5564 * mapping, that is, prior to changing the PDE. Otherwise, the state
5565 * of the L2 and the PV lists will be inconsistent, which can result
5566 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5567 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
5568 * PV entry for the 2MB page mapping that is being demoted.
5570 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5571 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
5574 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
5575 * the 2MB page mapping.
5577 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
5580 * Demote the PV entry.
5582 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5583 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
5585 atomic_add_long(&pmap_l2_demotions, 1);
5586 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
5587 " in pmap %p %lx", va, pmap, l3[0]);
5591 pmap_kremove(tmpl2);
5592 kva_free(tmpl2, PAGE_SIZE);
5600 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
5602 struct rwlock *lock;
5606 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
5613 * perform the pmap work for mincore
5616 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5618 pt_entry_t *pte, tpte;
5619 vm_paddr_t mask, pa;
5626 pte = pmap_pte(pmap, addr, &lvl);
5628 tpte = pmap_load(pte);
5641 panic("pmap_mincore: invalid level %d", lvl);
5644 managed = (tpte & ATTR_SW_MANAGED) != 0;
5645 val = MINCORE_INCORE;
5647 val |= MINCORE_SUPER;
5648 if ((managed && pmap_pte_dirty(tpte)) || (!managed &&
5649 (tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)))
5650 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5651 if ((tpte & ATTR_AF) == ATTR_AF)
5652 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5654 pa = (tpte & ~ATTR_MASK) | (addr & mask);
5658 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5659 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
5660 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5661 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5664 PA_UNLOCK_COND(*locked_pa);
5671 pmap_activate(struct thread *td)
5676 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5677 td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0);
5679 "msr ttbr0_el1, %0 \n"
5681 : : "r"(td->td_proc->p_md.md_l0addr));
5682 pmap_invalidate_all(pmap);
5687 pmap_switch(struct thread *old, struct thread *new)
5689 pcpu_bp_harden bp_harden;
5692 /* Store the new curthread */
5693 PCPU_SET(curthread, new);
5695 /* And the new pcb */
5697 PCPU_SET(curpcb, pcb);
5700 * TODO: We may need to flush the cache here if switching
5701 * to a user process.
5705 old->td_proc->p_md.md_l0addr != new->td_proc->p_md.md_l0addr) {
5707 /* Switch to the new pmap */
5708 "msr ttbr0_el1, %0 \n"
5711 /* Invalidate the TLB */
5716 : : "r"(new->td_proc->p_md.md_l0addr));
5719 * Stop userspace from training the branch predictor against
5720 * other processes. This will call into a CPU specific
5721 * function that clears the branch predictor state.
5723 bp_harden = PCPU_GET(bp_harden);
5724 if (bp_harden != NULL)
5732 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
5735 if (va >= VM_MIN_KERNEL_ADDRESS) {
5736 cpu_icache_sync_range(va, sz);
5741 /* Find the length of data in this page to flush */
5742 offset = va & PAGE_MASK;
5743 len = imin(PAGE_SIZE - offset, sz);
5746 /* Extract the physical address & find it in the DMAP */
5747 pa = pmap_extract(pmap, va);
5749 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
5751 /* Move to the next page */
5754 /* Set the length for the next iteration */
5755 len = imin(PAGE_SIZE, sz);
5761 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
5763 pt_entry_t pte, *ptep;
5770 ec = ESR_ELx_EXCEPTION(esr);
5772 case EXCP_INSN_ABORT_L:
5773 case EXCP_INSN_ABORT:
5774 case EXCP_DATA_ABORT_L:
5775 case EXCP_DATA_ABORT:
5781 /* Data and insn aborts use same encoding for FSC field. */
5782 switch (esr & ISS_DATA_DFSC_MASK) {
5783 case ISS_DATA_DFSC_AFF_L1:
5784 case ISS_DATA_DFSC_AFF_L2:
5785 case ISS_DATA_DFSC_AFF_L3:
5787 ptep = pmap_pte(pmap, far, &lvl);
5789 pmap_set_bits(ptep, ATTR_AF);
5792 * XXXMJ as an optimization we could mark the entry
5793 * dirty if this is a write fault.
5798 case ISS_DATA_DFSC_PF_L1:
5799 case ISS_DATA_DFSC_PF_L2:
5800 case ISS_DATA_DFSC_PF_L3:
5801 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
5802 (esr & ISS_DATA_WnR) == 0)
5805 ptep = pmap_pte(pmap, far, &lvl);
5807 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
5808 if ((pte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RO)) {
5809 pmap_clear_bits(ptep, ATTR_AP_RW_BIT);
5810 pmap_invalidate_page(pmap, far);
5816 case ISS_DATA_DFSC_TF_L0:
5817 case ISS_DATA_DFSC_TF_L1:
5818 case ISS_DATA_DFSC_TF_L2:
5819 case ISS_DATA_DFSC_TF_L3:
5821 /* Ask the MMU to check the address */
5822 intr = intr_disable();
5823 if (pmap == kernel_pmap)
5824 par = arm64_address_translate_s1e1r(far);
5826 par = arm64_address_translate_s1e0r(far);
5831 * If the translation was successful the address was invalid
5832 * due to a break-before-make sequence. We can unlock and
5833 * return success to the trap handler.
5835 if (PAR_SUCCESS(par))
5844 * Increase the starting virtual address of the given mapping if a
5845 * different alignment might result in more superpage mappings.
5848 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5849 vm_offset_t *addr, vm_size_t size)
5851 vm_offset_t superpage_offset;
5855 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5856 offset += ptoa(object->pg_color);
5857 superpage_offset = offset & L2_OFFSET;
5858 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
5859 (*addr & L2_OFFSET) == superpage_offset)
5861 if ((*addr & L2_OFFSET) < superpage_offset)
5862 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
5864 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
5868 * Get the kernel virtual address of a set of physical pages. If there are
5869 * physical addresses not covered by the DMAP perform a transient mapping
5870 * that will be removed when calling pmap_unmap_io_transient.
5872 * \param page The pages the caller wishes to obtain the virtual
5873 * address on the kernel memory map.
5874 * \param vaddr On return contains the kernel virtual memory address
5875 * of the pages passed in the page parameter.
5876 * \param count Number of pages passed in.
5877 * \param can_fault TRUE if the thread using the mapped pages can take
5878 * page faults, FALSE otherwise.
5880 * \returns TRUE if the caller must call pmap_unmap_io_transient when
5881 * finished or FALSE otherwise.
5885 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
5886 boolean_t can_fault)
5889 boolean_t needs_mapping;
5893 * Allocate any KVA space that we need, this is done in a separate
5894 * loop to prevent calling vmem_alloc while pinned.
5896 needs_mapping = FALSE;
5897 for (i = 0; i < count; i++) {
5898 paddr = VM_PAGE_TO_PHYS(page[i]);
5899 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
5900 error = vmem_alloc(kernel_arena, PAGE_SIZE,
5901 M_BESTFIT | M_WAITOK, &vaddr[i]);
5902 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
5903 needs_mapping = TRUE;
5905 vaddr[i] = PHYS_TO_DMAP(paddr);
5909 /* Exit early if everything is covered by the DMAP */
5915 for (i = 0; i < count; i++) {
5916 paddr = VM_PAGE_TO_PHYS(page[i]);
5917 if (!PHYS_IN_DMAP(paddr)) {
5919 "pmap_map_io_transient: TODO: Map out of DMAP data");
5923 return (needs_mapping);
5927 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
5928 boolean_t can_fault)
5935 for (i = 0; i < count; i++) {
5936 paddr = VM_PAGE_TO_PHYS(page[i]);
5937 if (!PHYS_IN_DMAP(paddr)) {
5938 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
5944 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
5947 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);