2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
108 #include <sys/param.h>
109 #include <sys/bitstring.h>
111 #include <sys/systm.h>
112 #include <sys/kernel.h>
114 #include <sys/lock.h>
115 #include <sys/malloc.h>
116 #include <sys/mman.h>
117 #include <sys/msgbuf.h>
118 #include <sys/mutex.h>
119 #include <sys/proc.h>
120 #include <sys/rwlock.h>
122 #include <sys/vmem.h>
123 #include <sys/vmmeter.h>
124 #include <sys/sched.h>
125 #include <sys/sysctl.h>
126 #include <sys/_unrhdr.h>
130 #include <vm/vm_param.h>
131 #include <vm/vm_kern.h>
132 #include <vm/vm_page.h>
133 #include <vm/vm_map.h>
134 #include <vm/vm_object.h>
135 #include <vm/vm_extern.h>
136 #include <vm/vm_pageout.h>
137 #include <vm/vm_pager.h>
138 #include <vm/vm_phys.h>
139 #include <vm/vm_radix.h>
140 #include <vm/vm_reserv.h>
143 #include <machine/machdep.h>
144 #include <machine/md_var.h>
145 #include <machine/pcb.h>
147 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
148 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
149 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
150 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
152 #define NUL0E L0_ENTRIES
153 #define NUL1E (NUL0E * NL1PG)
154 #define NUL2E (NUL1E * NL2PG)
156 #if !defined(DIAGNOSTIC)
157 #ifdef __GNUC_GNU_INLINE__
158 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
160 #define PMAP_INLINE extern inline
167 * These are configured by the mair_el1 register. This is set up in locore.S
169 #define DEVICE_MEMORY 0
170 #define UNCACHED_MEMORY 1
171 #define CACHED_MEMORY 2
175 #define PV_STAT(x) do { x ; } while (0)
177 #define PV_STAT(x) do { } while (0)
180 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
181 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
183 #define NPV_LIST_LOCKS MAXCPU
185 #define PHYS_TO_PV_LIST_LOCK(pa) \
186 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
188 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
189 struct rwlock **_lockp = (lockp); \
190 struct rwlock *_new_lock; \
192 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
193 if (_new_lock != *_lockp) { \
194 if (*_lockp != NULL) \
195 rw_wunlock(*_lockp); \
196 *_lockp = _new_lock; \
201 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
202 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
204 #define RELEASE_PV_LIST_LOCK(lockp) do { \
205 struct rwlock **_lockp = (lockp); \
207 if (*_lockp != NULL) { \
208 rw_wunlock(*_lockp); \
213 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
214 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
216 struct pmap kernel_pmap_store;
218 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
219 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
220 vm_offset_t kernel_vm_end = 0;
222 struct msgbuf *msgbufp = NULL;
225 * Data for the pv entry allocation mechanism.
226 * Updates to pv_invl_gen are protected by the pv_list_locks[]
227 * elements, but reads are not.
229 static struct md_page *pv_table;
230 static struct md_page pv_dummy;
232 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
233 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
234 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
236 /* This code assumes all L1 DMAP entries will be used */
237 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
238 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
240 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
241 extern pt_entry_t pagetable_dmap[];
243 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
245 static int superpages_enabled = 1;
246 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
247 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
248 "Are large page mappings enabled?");
251 * Data for the pv entry allocation mechanism
253 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
254 static struct mtx pv_chunks_mutex;
255 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
257 static void free_pv_chunk(struct pv_chunk *pc);
258 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
259 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
260 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
261 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
262 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
265 static int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode);
266 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
267 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
268 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
269 vm_offset_t va, struct rwlock **lockp);
270 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
271 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
272 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
273 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
274 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
275 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
276 vm_page_t m, struct rwlock **lockp);
278 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
279 struct rwlock **lockp);
281 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
282 struct spglist *free);
283 static int pmap_unuse_l3(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
286 * These load the old table data and store the new value.
287 * They need to be atomic as the System MMU may write to the table at
288 * the same time as the CPU.
290 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
291 #define pmap_set(table, mask) atomic_set_64(table, mask)
292 #define pmap_load_clear(table) atomic_swap_64(table, 0)
293 #define pmap_load(table) (*table)
295 /********************/
296 /* Inline functions */
297 /********************/
300 pagecopy(void *s, void *d)
303 memcpy(d, s, PAGE_SIZE);
306 #define pmap_l0_index(va) (((va) >> L0_SHIFT) & L0_ADDR_MASK)
307 #define pmap_l1_index(va) (((va) >> L1_SHIFT) & Ln_ADDR_MASK)
308 #define pmap_l2_index(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK)
309 #define pmap_l3_index(va) (((va) >> L3_SHIFT) & Ln_ADDR_MASK)
311 static __inline pd_entry_t *
312 pmap_l0(pmap_t pmap, vm_offset_t va)
315 return (&pmap->pm_l0[pmap_l0_index(va)]);
318 static __inline pd_entry_t *
319 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
323 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
324 return (&l1[pmap_l1_index(va)]);
327 static __inline pd_entry_t *
328 pmap_l1(pmap_t pmap, vm_offset_t va)
332 l0 = pmap_l0(pmap, va);
333 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
336 return (pmap_l0_to_l1(l0, va));
339 static __inline pd_entry_t *
340 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
344 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
345 return (&l2[pmap_l2_index(va)]);
348 static __inline pd_entry_t *
349 pmap_l2(pmap_t pmap, vm_offset_t va)
353 l1 = pmap_l1(pmap, va);
354 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
357 return (pmap_l1_to_l2(l1, va));
360 static __inline pt_entry_t *
361 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
365 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
366 return (&l3[pmap_l3_index(va)]);
370 * Returns the lowest valid pde for a given virtual address.
371 * The next level may or may not point to a valid page or block.
373 static __inline pd_entry_t *
374 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
376 pd_entry_t *l0, *l1, *l2, desc;
378 l0 = pmap_l0(pmap, va);
379 desc = pmap_load(l0) & ATTR_DESCR_MASK;
380 if (desc != L0_TABLE) {
385 l1 = pmap_l0_to_l1(l0, va);
386 desc = pmap_load(l1) & ATTR_DESCR_MASK;
387 if (desc != L1_TABLE) {
392 l2 = pmap_l1_to_l2(l1, va);
393 desc = pmap_load(l2) & ATTR_DESCR_MASK;
394 if (desc != L2_TABLE) {
404 * Returns the lowest valid pte block or table entry for a given virtual
405 * address. If there are no valid entries return NULL and set the level to
406 * the first invalid level.
408 static __inline pt_entry_t *
409 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
411 pd_entry_t *l1, *l2, desc;
414 l1 = pmap_l1(pmap, va);
419 desc = pmap_load(l1) & ATTR_DESCR_MASK;
420 if (desc == L1_BLOCK) {
425 if (desc != L1_TABLE) {
430 l2 = pmap_l1_to_l2(l1, va);
431 desc = pmap_load(l2) & ATTR_DESCR_MASK;
432 if (desc == L2_BLOCK) {
437 if (desc != L2_TABLE) {
443 l3 = pmap_l2_to_l3(l2, va);
444 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
451 pmap_superpages_enabled(void)
454 return (superpages_enabled != 0);
458 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
459 pd_entry_t **l2, pt_entry_t **l3)
461 pd_entry_t *l0p, *l1p, *l2p;
463 if (pmap->pm_l0 == NULL)
466 l0p = pmap_l0(pmap, va);
469 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
472 l1p = pmap_l0_to_l1(l0p, va);
475 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
481 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
484 l2p = pmap_l1_to_l2(l1p, va);
487 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
492 *l3 = pmap_l2_to_l3(l2p, va);
498 pmap_is_current(pmap_t pmap)
501 return ((pmap == pmap_kernel()) ||
502 (pmap == curthread->td_proc->p_vmspace->vm_map.pmap));
506 pmap_l3_valid(pt_entry_t l3)
509 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
513 /* Is a level 1 or 2entry a valid block and cacheable */
514 CTASSERT(L1_BLOCK == L2_BLOCK);
516 pmap_pte_valid_cacheable(pt_entry_t pte)
519 return (((pte & ATTR_DESCR_MASK) == L1_BLOCK) &&
520 ((pte & ATTR_IDX_MASK) == ATTR_IDX(CACHED_MEMORY)));
524 pmap_l3_valid_cacheable(pt_entry_t l3)
527 return (((l3 & ATTR_DESCR_MASK) == L3_PAGE) &&
528 ((l3 & ATTR_IDX_MASK) == ATTR_IDX(CACHED_MEMORY)));
531 #define PTE_SYNC(pte) cpu_dcache_wb_range((vm_offset_t)pte, sizeof(*pte))
534 * Checks if the page is dirty. We currently lack proper tracking of this on
535 * arm64 so for now assume is a page mapped as rw was accessed it is.
538 pmap_page_dirty(pt_entry_t pte)
541 return ((pte & (ATTR_AF | ATTR_AP_RW_BIT)) ==
542 (ATTR_AF | ATTR_AP(ATTR_AP_RW)));
546 pmap_resident_count_inc(pmap_t pmap, int count)
549 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
550 pmap->pm_stats.resident_count += count;
554 pmap_resident_count_dec(pmap_t pmap, int count)
557 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
558 KASSERT(pmap->pm_stats.resident_count >= count,
559 ("pmap %p resident count underflow %ld %d", pmap,
560 pmap->pm_stats.resident_count, count));
561 pmap->pm_stats.resident_count -= count;
565 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
571 l1 = (pd_entry_t *)l1pt;
572 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
574 /* Check locore has used a table L1 map */
575 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
576 ("Invalid bootstrap L1 table"));
577 /* Find the address of the L2 table */
578 l2 = (pt_entry_t *)init_pt_va;
579 *l2_slot = pmap_l2_index(va);
585 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
587 u_int l1_slot, l2_slot;
590 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
592 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
596 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa, vm_paddr_t max_pa)
602 pa = dmap_phys_base = min_pa & ~L1_OFFSET;
603 va = DMAP_MIN_ADDRESS;
604 for (; va < DMAP_MAX_ADDRESS && pa < max_pa;
605 pa += L1_SIZE, va += L1_SIZE, l1_slot++) {
606 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
608 pmap_load_store(&pagetable_dmap[l1_slot],
609 (pa & ~L1_OFFSET) | ATTR_DEFAULT |
610 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
613 /* Set the upper limit of the DMAP region */
617 cpu_dcache_wb_range((vm_offset_t)pagetable_dmap,
618 PAGE_SIZE * DMAP_TABLES);
623 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
630 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
632 l1 = (pd_entry_t *)l1pt;
633 l1_slot = pmap_l1_index(va);
636 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
637 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
639 pa = pmap_early_vtophys(l1pt, l2pt);
640 pmap_load_store(&l1[l1_slot],
641 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
645 /* Clean the L2 page table */
646 memset((void *)l2_start, 0, l2pt - l2_start);
647 cpu_dcache_wb_range(l2_start, l2pt - l2_start);
649 /* Flush the l1 table to ram */
650 cpu_dcache_wb_range((vm_offset_t)l1, PAGE_SIZE);
656 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
658 vm_offset_t l2pt, l3pt;
663 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
665 l2 = pmap_l2(kernel_pmap, va);
666 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
667 l2pt = (vm_offset_t)l2;
668 l2_slot = pmap_l2_index(va);
671 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
672 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
674 pa = pmap_early_vtophys(l1pt, l3pt);
675 pmap_load_store(&l2[l2_slot],
676 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
680 /* Clean the L2 page table */
681 memset((void *)l3_start, 0, l3pt - l3_start);
682 cpu_dcache_wb_range(l3_start, l3pt - l3_start);
684 cpu_dcache_wb_range((vm_offset_t)l2, PAGE_SIZE);
690 * Bootstrap the system enough to run with virtual memory.
693 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
696 u_int l1_slot, l2_slot, avail_slot, map_slot, used_map_slot;
699 vm_offset_t va, freemempos;
700 vm_offset_t dpcpu, msgbufpv;
701 vm_paddr_t pa, max_pa, min_pa;
704 kern_delta = KERNBASE - kernstart;
707 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
708 printf("%lx\n", l1pt);
709 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
711 /* Set this early so we can use the pagetable walking functions */
712 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
713 PMAP_LOCK_INIT(kernel_pmap);
715 /* Assume the address we were loaded to is a valid physical address */
716 min_pa = max_pa = KERNBASE - kern_delta;
719 * Find the minimum physical address. physmap is sorted,
720 * but may contain empty ranges.
722 for (i = 0; i < (physmap_idx * 2); i += 2) {
723 if (physmap[i] == physmap[i + 1])
725 if (physmap[i] <= min_pa)
727 if (physmap[i + 1] > max_pa)
728 max_pa = physmap[i + 1];
731 /* Create a direct map region early so we can use it for pa -> va */
732 pmap_bootstrap_dmap(l1pt, min_pa, max_pa);
735 pa = KERNBASE - kern_delta;
738 * Start to initialise phys_avail by copying from physmap
739 * up to the physical address KERNBASE points at.
741 map_slot = avail_slot = 0;
742 for (; map_slot < (physmap_idx * 2) &&
743 avail_slot < (PHYS_AVAIL_SIZE - 2); map_slot += 2) {
744 if (physmap[map_slot] == physmap[map_slot + 1])
747 if (physmap[map_slot] <= pa &&
748 physmap[map_slot + 1] > pa)
751 phys_avail[avail_slot] = physmap[map_slot];
752 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
753 physmem += (phys_avail[avail_slot + 1] -
754 phys_avail[avail_slot]) >> PAGE_SHIFT;
758 /* Add the memory before the kernel */
759 if (physmap[avail_slot] < pa && avail_slot < (PHYS_AVAIL_SIZE - 2)) {
760 phys_avail[avail_slot] = physmap[map_slot];
761 phys_avail[avail_slot + 1] = pa;
762 physmem += (phys_avail[avail_slot + 1] -
763 phys_avail[avail_slot]) >> PAGE_SHIFT;
766 used_map_slot = map_slot;
769 * Read the page table to find out what is already mapped.
770 * This assumes we have mapped a block of memory from KERNBASE
771 * using a single L1 entry.
773 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
775 /* Sanity check the index, KERNBASE should be the first VA */
776 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
778 /* Find how many pages we have mapped */
779 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
780 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
783 /* Check locore used L2 blocks */
784 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
785 ("Invalid bootstrap L2 table"));
786 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
787 ("Incorrect PA in L2 table"));
793 va = roundup2(va, L1_SIZE);
795 freemempos = KERNBASE + kernlen;
796 freemempos = roundup2(freemempos, PAGE_SIZE);
797 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
798 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
799 /* And the l3 tables for the early devmap */
800 freemempos = pmap_bootstrap_l3(l1pt,
801 VM_MAX_KERNEL_ADDRESS - L2_SIZE, freemempos);
805 #define alloc_pages(var, np) \
806 (var) = freemempos; \
807 freemempos += (np * PAGE_SIZE); \
808 memset((char *)(var), 0, ((np) * PAGE_SIZE));
810 /* Allocate dynamic per-cpu area. */
811 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
812 dpcpu_init((void *)dpcpu, 0);
814 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
815 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
816 msgbufp = (void *)msgbufpv;
818 virtual_avail = roundup2(freemempos, L1_SIZE);
819 virtual_end = VM_MAX_KERNEL_ADDRESS - L2_SIZE;
820 kernel_vm_end = virtual_avail;
822 pa = pmap_early_vtophys(l1pt, freemempos);
824 /* Finish initialising physmap */
825 map_slot = used_map_slot;
826 for (; avail_slot < (PHYS_AVAIL_SIZE - 2) &&
827 map_slot < (physmap_idx * 2); map_slot += 2) {
828 if (physmap[map_slot] == physmap[map_slot + 1])
831 /* Have we used the current range? */
832 if (physmap[map_slot + 1] <= pa)
835 /* Do we need to split the entry? */
836 if (physmap[map_slot] < pa) {
837 phys_avail[avail_slot] = pa;
838 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
840 phys_avail[avail_slot] = physmap[map_slot];
841 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
843 physmem += (phys_avail[avail_slot + 1] -
844 phys_avail[avail_slot]) >> PAGE_SHIFT;
848 phys_avail[avail_slot] = 0;
849 phys_avail[avail_slot + 1] = 0;
852 * Maxmem isn't the "maximum memory", it's one larger than the
853 * highest page of the physical address space. It should be
854 * called something like "Maxphyspage".
856 Maxmem = atop(phys_avail[avail_slot - 1]);
862 * Initialize a vm_page's machine-dependent fields.
865 pmap_page_init(vm_page_t m)
868 TAILQ_INIT(&m->md.pv_list);
869 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
873 * Initialize the pmap module.
874 * Called by vm_init, to initialize any structures that the pmap
875 * system needs to map virtual memory.
884 * Are large page mappings enabled?
886 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
889 * Initialize the pv chunk list mutex.
891 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
894 * Initialize the pool of pv list locks.
896 for (i = 0; i < NPV_LIST_LOCKS; i++)
897 rw_init(&pv_list_locks[i], "pmap pv list");
900 * Calculate the size of the pv head table for superpages.
902 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
905 * Allocate memory for the pv head table for superpages.
907 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
909 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
911 for (i = 0; i < pv_npg; i++)
912 TAILQ_INIT(&pv_table[i].pv_list);
913 TAILQ_INIT(&pv_dummy.pv_list);
916 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
917 "2MB page mapping counters");
919 static u_long pmap_l2_demotions;
920 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
921 &pmap_l2_demotions, 0, "2MB page demotions");
923 static u_long pmap_l2_p_failures;
924 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
925 &pmap_l2_p_failures, 0, "2MB page promotion failures");
927 static u_long pmap_l2_promotions;
928 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
929 &pmap_l2_promotions, 0, "2MB page promotions");
932 * Invalidate a single TLB entry.
935 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
941 "tlbi vaae1is, %0 \n"
944 : : "r"(va >> PAGE_SHIFT));
949 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
955 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
957 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
966 pmap_invalidate_all(pmap_t pmap)
979 * Routine: pmap_extract
981 * Extract the physical page address associated
982 * with the given map/virtual_address pair.
985 pmap_extract(pmap_t pmap, vm_offset_t va)
987 pt_entry_t *pte, tpte;
994 * Find the block or page map for this virtual address. pmap_pte
995 * will return either a valid block/page entry, or NULL.
997 pte = pmap_pte(pmap, va, &lvl);
999 tpte = pmap_load(pte);
1000 pa = tpte & ~ATTR_MASK;
1003 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1004 ("pmap_extract: Invalid L1 pte found: %lx",
1005 tpte & ATTR_DESCR_MASK));
1006 pa |= (va & L1_OFFSET);
1009 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1010 ("pmap_extract: Invalid L2 pte found: %lx",
1011 tpte & ATTR_DESCR_MASK));
1012 pa |= (va & L2_OFFSET);
1015 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1016 ("pmap_extract: Invalid L3 pte found: %lx",
1017 tpte & ATTR_DESCR_MASK));
1018 pa |= (va & L3_OFFSET);
1027 * Routine: pmap_extract_and_hold
1029 * Atomically extract and hold the physical page
1030 * with the given pmap and virtual address pair
1031 * if that mapping permits the given protection.
1034 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1036 pt_entry_t *pte, tpte;
1046 pte = pmap_pte(pmap, va, &lvl);
1048 tpte = pmap_load(pte);
1050 KASSERT(lvl > 0 && lvl <= 3,
1051 ("pmap_extract_and_hold: Invalid level %d", lvl));
1052 CTASSERT(L1_BLOCK == L2_BLOCK);
1053 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1054 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1055 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1056 tpte & ATTR_DESCR_MASK));
1057 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1058 ((prot & VM_PROT_WRITE) == 0)) {
1061 off = va & L1_OFFSET;
1064 off = va & L2_OFFSET;
1070 if (vm_page_pa_tryrelock(pmap,
1071 (tpte & ~ATTR_MASK) | off, &pa))
1073 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1083 pmap_kextract(vm_offset_t va)
1085 pt_entry_t *pte, tpte;
1089 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1090 pa = DMAP_TO_PHYS(va);
1093 pte = pmap_pte(kernel_pmap, va, &lvl);
1095 tpte = pmap_load(pte);
1096 pa = tpte & ~ATTR_MASK;
1099 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1100 ("pmap_kextract: Invalid L1 pte found: %lx",
1101 tpte & ATTR_DESCR_MASK));
1102 pa |= (va & L1_OFFSET);
1105 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1106 ("pmap_kextract: Invalid L2 pte found: %lx",
1107 tpte & ATTR_DESCR_MASK));
1108 pa |= (va & L2_OFFSET);
1111 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1112 ("pmap_kextract: Invalid L3 pte found: %lx",
1113 tpte & ATTR_DESCR_MASK));
1114 pa |= (va & L3_OFFSET);
1122 /***************************************************
1123 * Low level mapping routines.....
1124 ***************************************************/
1127 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1134 KASSERT((pa & L3_OFFSET) == 0,
1135 ("pmap_kenter: Invalid physical address"));
1136 KASSERT((sva & L3_OFFSET) == 0,
1137 ("pmap_kenter: Invalid virtual address"));
1138 KASSERT((size & PAGE_MASK) == 0,
1139 ("pmap_kenter: Mapping is not page-sized"));
1143 pde = pmap_pde(kernel_pmap, va, &lvl);
1144 KASSERT(pde != NULL,
1145 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1146 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1148 pte = pmap_l2_to_l3(pde, va);
1149 pmap_load_store(pte, (pa & ~L3_OFFSET) | ATTR_DEFAULT |
1150 ATTR_IDX(mode) | L3_PAGE);
1157 pmap_invalidate_range(kernel_pmap, sva, va);
1161 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1164 pmap_kenter(sva, size, pa, DEVICE_MEMORY);
1168 * Remove a page from the kernel pagetables.
1171 pmap_kremove(vm_offset_t va)
1176 pte = pmap_pte(kernel_pmap, va, &lvl);
1177 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1178 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1180 if (pmap_l3_valid_cacheable(pmap_load(pte)))
1181 cpu_dcache_wb_range(va, L3_SIZE);
1182 pmap_load_clear(pte);
1184 pmap_invalidate_page(kernel_pmap, va);
1188 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1194 KASSERT((sva & L3_OFFSET) == 0,
1195 ("pmap_kremove_device: Invalid virtual address"));
1196 KASSERT((size & PAGE_MASK) == 0,
1197 ("pmap_kremove_device: Mapping is not page-sized"));
1201 pte = pmap_pte(kernel_pmap, va, &lvl);
1202 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1204 ("Invalid device pagetable level: %d != 3", lvl));
1205 pmap_load_clear(pte);
1211 pmap_invalidate_range(kernel_pmap, sva, va);
1215 * Used to map a range of physical addresses into kernel
1216 * virtual address space.
1218 * The value passed in '*virt' is a suggested virtual address for
1219 * the mapping. Architectures which can support a direct-mapped
1220 * physical to virtual region can return the appropriate address
1221 * within that region, leaving '*virt' unchanged. Other
1222 * architectures should map the pages starting at '*virt' and
1223 * update '*virt' with the first usable address after the mapped
1227 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1229 return PHYS_TO_DMAP(start);
1234 * Add a list of wired pages to the kva
1235 * this routine is only used for temporary
1236 * kernel mappings that do not need to have
1237 * page modification or references recorded.
1238 * Note that old mappings are simply written
1239 * over. The page *must* be wired.
1240 * Note: SMP coherent. Uses a ranged shootdown IPI.
1243 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1246 pt_entry_t *pte, pa;
1252 for (i = 0; i < count; i++) {
1253 pde = pmap_pde(kernel_pmap, va, &lvl);
1254 KASSERT(pde != NULL,
1255 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1257 ("pmap_qenter: Invalid level %d", lvl));
1260 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1261 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1262 pte = pmap_l2_to_l3(pde, va);
1263 pmap_load_store(pte, pa);
1268 pmap_invalidate_range(kernel_pmap, sva, va);
1272 * This routine tears out page mappings from the
1273 * kernel -- it is meant only for temporary mappings.
1276 pmap_qremove(vm_offset_t sva, int count)
1282 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1285 while (count-- > 0) {
1286 pte = pmap_pte(kernel_pmap, va, &lvl);
1288 ("Invalid device pagetable level: %d != 3", lvl));
1290 if (pmap_l3_valid_cacheable(pmap_load(pte)))
1291 cpu_dcache_wb_range(va, L3_SIZE);
1292 pmap_load_clear(pte);
1298 pmap_invalidate_range(kernel_pmap, sva, va);
1301 /***************************************************
1302 * Page table page management routines.....
1303 ***************************************************/
1304 static __inline void
1305 pmap_free_zero_pages(struct spglist *free)
1309 while ((m = SLIST_FIRST(free)) != NULL) {
1310 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1311 /* Preserve the page's PG_ZERO setting. */
1312 vm_page_free_toq(m);
1317 * Schedule the specified unused page table page to be freed. Specifically,
1318 * add the page to the specified list of pages that will be released to the
1319 * physical memory manager after the TLB has been updated.
1321 static __inline void
1322 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1323 boolean_t set_PG_ZERO)
1327 m->flags |= PG_ZERO;
1329 m->flags &= ~PG_ZERO;
1330 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1334 * Decrements a page table page's wire count, which is used to record the
1335 * number of valid page table entries within the page. If the wire count
1336 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1337 * page table page was unmapped and FALSE otherwise.
1339 static inline boolean_t
1340 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1344 if (m->wire_count == 0) {
1345 _pmap_unwire_l3(pmap, va, m, free);
1352 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1355 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1357 * unmap the page table page
1359 if (m->pindex >= (NUL2E + NUL1E)) {
1363 l0 = pmap_l0(pmap, va);
1364 pmap_load_clear(l0);
1366 } else if (m->pindex >= NUL2E) {
1370 l1 = pmap_l1(pmap, va);
1371 pmap_load_clear(l1);
1377 l2 = pmap_l2(pmap, va);
1378 pmap_load_clear(l2);
1381 pmap_resident_count_dec(pmap, 1);
1382 if (m->pindex < NUL2E) {
1383 /* We just released an l3, unhold the matching l2 */
1384 pd_entry_t *l1, tl1;
1387 l1 = pmap_l1(pmap, va);
1388 tl1 = pmap_load(l1);
1389 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1390 pmap_unwire_l3(pmap, va, l2pg, free);
1391 } else if (m->pindex < (NUL2E + NUL1E)) {
1392 /* We just released an l2, unhold the matching l1 */
1393 pd_entry_t *l0, tl0;
1396 l0 = pmap_l0(pmap, va);
1397 tl0 = pmap_load(l0);
1398 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1399 pmap_unwire_l3(pmap, va, l1pg, free);
1401 pmap_invalidate_page(pmap, va);
1404 * This is a release store so that the ordinary store unmapping
1405 * the page table page is globally performed before TLB shoot-
1408 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
1411 * Put page on a list so that it is released after
1412 * *ALL* TLB shootdown is done
1414 pmap_add_delayed_free_list(m, free, TRUE);
1418 * After removing an l3 entry, this routine is used to
1419 * conditionally free the page, and manage the hold/wire counts.
1422 pmap_unuse_l3(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1423 struct spglist *free)
1427 if (va >= VM_MAXUSER_ADDRESS)
1429 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1430 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1431 return (pmap_unwire_l3(pmap, va, mpte, free));
1435 pmap_pinit0(pmap_t pmap)
1438 PMAP_LOCK_INIT(pmap);
1439 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1440 pmap->pm_l0 = kernel_pmap->pm_l0;
1441 pmap->pm_root.rt_root = 0;
1445 pmap_pinit(pmap_t pmap)
1451 * allocate the l0 page
1453 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1454 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1457 l0phys = VM_PAGE_TO_PHYS(l0pt);
1458 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1460 if ((l0pt->flags & PG_ZERO) == 0)
1461 pagezero(pmap->pm_l0);
1463 pmap->pm_root.rt_root = 0;
1464 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1470 * This routine is called if the desired page table page does not exist.
1472 * If page table page allocation fails, this routine may sleep before
1473 * returning NULL. It sleeps only if a lock pointer was given.
1475 * Note: If a page allocation fails at page table level two or three,
1476 * one or two pages may be held during the wait, only to be released
1477 * afterwards. This conservative approach is easily argued to avoid
1481 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1483 vm_page_t m, l1pg, l2pg;
1485 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1488 * Allocate a page table page.
1490 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1491 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1492 if (lockp != NULL) {
1493 RELEASE_PV_LIST_LOCK(lockp);
1500 * Indicate the need to retry. While waiting, the page table
1501 * page may have been allocated.
1505 if ((m->flags & PG_ZERO) == 0)
1509 * Map the pagetable page into the process address space, if
1510 * it isn't already there.
1513 if (ptepindex >= (NUL2E + NUL1E)) {
1515 vm_pindex_t l0index;
1517 l0index = ptepindex - (NUL2E + NUL1E);
1518 l0 = &pmap->pm_l0[l0index];
1519 pmap_load_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1521 } else if (ptepindex >= NUL2E) {
1522 vm_pindex_t l0index, l1index;
1523 pd_entry_t *l0, *l1;
1526 l1index = ptepindex - NUL2E;
1527 l0index = l1index >> L0_ENTRIES_SHIFT;
1529 l0 = &pmap->pm_l0[l0index];
1530 tl0 = pmap_load(l0);
1532 /* recurse for allocating page dir */
1533 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1536 /* XXX: release mem barrier? */
1537 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1538 vm_page_free_zero(m);
1542 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1546 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1547 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1548 pmap_load_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1551 vm_pindex_t l0index, l1index;
1552 pd_entry_t *l0, *l1, *l2;
1553 pd_entry_t tl0, tl1;
1555 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1556 l0index = l1index >> L0_ENTRIES_SHIFT;
1558 l0 = &pmap->pm_l0[l0index];
1559 tl0 = pmap_load(l0);
1561 /* recurse for allocating page dir */
1562 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1565 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1566 vm_page_free_zero(m);
1569 tl0 = pmap_load(l0);
1570 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1571 l1 = &l1[l1index & Ln_ADDR_MASK];
1573 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1574 l1 = &l1[l1index & Ln_ADDR_MASK];
1575 tl1 = pmap_load(l1);
1577 /* recurse for allocating page dir */
1578 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1581 /* XXX: release mem barrier? */
1582 atomic_subtract_int(
1583 &vm_cnt.v_wire_count, 1);
1584 vm_page_free_zero(m);
1588 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1593 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1594 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1595 pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1599 pmap_resident_count_inc(pmap, 1);
1605 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1607 vm_pindex_t ptepindex;
1608 pd_entry_t *pde, tpde;
1616 * Calculate pagetable page index
1618 ptepindex = pmap_l2_pindex(va);
1621 * Get the page directory entry
1623 pde = pmap_pde(pmap, va, &lvl);
1626 * If the page table page is mapped, we just increment the hold count,
1627 * and activate it. If we get a level 2 pde it will point to a level 3
1635 pte = pmap_l0_to_l1(pde, va);
1636 KASSERT(pmap_load(pte) == 0,
1637 ("pmap_alloc_l3: TODO: l0 superpages"));
1642 pte = pmap_l1_to_l2(pde, va);
1643 KASSERT(pmap_load(pte) == 0,
1644 ("pmap_alloc_l3: TODO: l1 superpages"));
1648 tpde = pmap_load(pde);
1650 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1656 panic("pmap_alloc_l3: Invalid level %d", lvl);
1660 * Here if the pte page isn't mapped, or if it has been deallocated.
1662 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1663 if (m == NULL && lockp != NULL)
1670 /***************************************************
1671 * Pmap allocation/deallocation routines.
1672 ***************************************************/
1675 * Release any resources held by the given physical map.
1676 * Called when a pmap initialized by pmap_pinit is being released.
1677 * Should only be called if the map contains no valid mappings.
1680 pmap_release(pmap_t pmap)
1684 KASSERT(pmap->pm_stats.resident_count == 0,
1685 ("pmap_release: pmap resident count %ld != 0",
1686 pmap->pm_stats.resident_count));
1687 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1688 ("pmap_release: pmap has reserved page table page(s)"));
1690 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1693 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1694 vm_page_free_zero(m);
1698 kvm_size(SYSCTL_HANDLER_ARGS)
1700 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1702 return sysctl_handle_long(oidp, &ksize, 0, req);
1704 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1705 0, 0, kvm_size, "LU", "Size of KVM");
1708 kvm_free(SYSCTL_HANDLER_ARGS)
1710 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1712 return sysctl_handle_long(oidp, &kfree, 0, req);
1714 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1715 0, 0, kvm_free, "LU", "Amount of KVM free");
1718 * grow the number of kernel page table entries, if needed
1721 pmap_growkernel(vm_offset_t addr)
1725 pd_entry_t *l0, *l1, *l2;
1727 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1729 addr = roundup2(addr, L2_SIZE);
1730 if (addr - 1 >= kernel_map->max_offset)
1731 addr = kernel_map->max_offset;
1732 while (kernel_vm_end < addr) {
1733 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1734 KASSERT(pmap_load(l0) != 0,
1735 ("pmap_growkernel: No level 0 kernel entry"));
1737 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1738 if (pmap_load(l1) == 0) {
1739 /* We need a new PDP entry */
1740 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1741 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1742 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1744 panic("pmap_growkernel: no memory to grow kernel");
1745 if ((nkpg->flags & PG_ZERO) == 0)
1746 pmap_zero_page(nkpg);
1747 paddr = VM_PAGE_TO_PHYS(nkpg);
1748 pmap_load_store(l1, paddr | L1_TABLE);
1750 continue; /* try again */
1752 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1753 if ((pmap_load(l2) & ATTR_AF) != 0) {
1754 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1755 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1756 kernel_vm_end = kernel_map->max_offset;
1762 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1763 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1766 panic("pmap_growkernel: no memory to grow kernel");
1767 if ((nkpg->flags & PG_ZERO) == 0)
1768 pmap_zero_page(nkpg);
1769 paddr = VM_PAGE_TO_PHYS(nkpg);
1770 pmap_load_store(l2, paddr | L2_TABLE);
1772 pmap_invalidate_page(kernel_pmap, kernel_vm_end);
1774 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1775 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1776 kernel_vm_end = kernel_map->max_offset;
1783 /***************************************************
1784 * page management routines.
1785 ***************************************************/
1787 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1788 CTASSERT(_NPCM == 3);
1789 CTASSERT(_NPCPV == 168);
1791 static __inline struct pv_chunk *
1792 pv_to_chunk(pv_entry_t pv)
1795 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1798 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1800 #define PC_FREE0 0xfffffffffffffffful
1801 #define PC_FREE1 0xfffffffffffffffful
1802 #define PC_FREE2 0x000000fffffffffful
1804 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1808 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1810 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1811 "Current number of pv entry chunks");
1812 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1813 "Current number of pv entry chunks allocated");
1814 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1815 "Current number of pv entry chunks frees");
1816 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1817 "Number of times tried to get a chunk page but failed.");
1819 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1820 static int pv_entry_spare;
1822 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1823 "Current number of pv entry frees");
1824 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1825 "Current number of pv entry allocs");
1826 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1827 "Current number of pv entries");
1828 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1829 "Current number of spare pv entries");
1834 * We are in a serious low memory condition. Resort to
1835 * drastic measures to free some pages so we can allocate
1836 * another pv entry chunk.
1838 * Returns NULL if PV entries were reclaimed from the specified pmap.
1840 * We do not, however, unmap 2mpages because subsequent accesses will
1841 * allocate per-page pv entries until repromotion occurs, thereby
1842 * exacerbating the shortage of free pv entries.
1845 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1848 panic("ARM64TODO: reclaim_pv_chunk");
1852 * free the pv_entry back to the free list
1855 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1857 struct pv_chunk *pc;
1858 int idx, field, bit;
1860 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1861 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
1862 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
1863 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
1864 pc = pv_to_chunk(pv);
1865 idx = pv - &pc->pc_pventry[0];
1868 pc->pc_map[field] |= 1ul << bit;
1869 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
1870 pc->pc_map[2] != PC_FREE2) {
1871 /* 98% of the time, pc is already at the head of the list. */
1872 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
1873 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1874 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1878 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1883 free_pv_chunk(struct pv_chunk *pc)
1887 mtx_lock(&pv_chunks_mutex);
1888 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1889 mtx_unlock(&pv_chunks_mutex);
1890 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1891 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1892 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1893 /* entire chunk is free, return it */
1894 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1895 dump_drop_page(m->phys_addr);
1896 vm_page_unwire(m, PQ_NONE);
1901 * Returns a new PV entry, allocating a new PV chunk from the system when
1902 * needed. If this PV chunk allocation fails and a PV list lock pointer was
1903 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
1906 * The given PV list lock may be released.
1909 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
1913 struct pv_chunk *pc;
1916 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1917 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
1919 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1921 for (field = 0; field < _NPCM; field++) {
1922 if (pc->pc_map[field]) {
1923 bit = ffsl(pc->pc_map[field]) - 1;
1927 if (field < _NPCM) {
1928 pv = &pc->pc_pventry[field * 64 + bit];
1929 pc->pc_map[field] &= ~(1ul << bit);
1930 /* If this was the last item, move it to tail */
1931 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
1932 pc->pc_map[2] == 0) {
1933 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1934 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
1937 PV_STAT(atomic_add_long(&pv_entry_count, 1));
1938 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
1942 /* No free items, allocate another chunk */
1943 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1946 if (lockp == NULL) {
1947 PV_STAT(pc_chunk_tryfail++);
1950 m = reclaim_pv_chunk(pmap, lockp);
1954 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
1955 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
1956 dump_add_page(m->phys_addr);
1957 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
1959 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
1960 pc->pc_map[1] = PC_FREE1;
1961 pc->pc_map[2] = PC_FREE2;
1962 mtx_lock(&pv_chunks_mutex);
1963 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
1964 mtx_unlock(&pv_chunks_mutex);
1965 pv = &pc->pc_pventry[0];
1966 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1967 PV_STAT(atomic_add_long(&pv_entry_count, 1));
1968 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
1973 * Ensure that the number of spare PV entries in the specified pmap meets or
1974 * exceeds the given count, "needed".
1976 * The given PV list lock may be released.
1979 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
1981 struct pch new_tail;
1982 struct pv_chunk *pc;
1986 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1987 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
1990 * Newly allocated PV chunks must be stored in a private list until
1991 * the required number of PV chunks have been allocated. Otherwise,
1992 * reclaim_pv_chunk() could recycle one of these chunks. In
1993 * contrast, these chunks must be added to the pmap upon allocation.
1995 TAILQ_INIT(&new_tail);
1998 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
1999 bit_count((bitstr_t *)pc->pc_map, 0,
2000 sizeof(pc->pc_map) * NBBY, &free);
2004 if (avail >= needed)
2007 for (; avail < needed; avail += _NPCPV) {
2008 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2011 m = reclaim_pv_chunk(pmap, lockp);
2015 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2016 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2017 dump_add_page(m->phys_addr);
2018 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2020 pc->pc_map[0] = PC_FREE0;
2021 pc->pc_map[1] = PC_FREE1;
2022 pc->pc_map[2] = PC_FREE2;
2023 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2024 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2025 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2027 if (!TAILQ_EMPTY(&new_tail)) {
2028 mtx_lock(&pv_chunks_mutex);
2029 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2030 mtx_unlock(&pv_chunks_mutex);
2035 * First find and then remove the pv entry for the specified pmap and virtual
2036 * address from the specified pv list. Returns the pv entry if found and NULL
2037 * otherwise. This operation can be performed on pv lists for either 4KB or
2038 * 2MB page mappings.
2040 static __inline pv_entry_t
2041 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2045 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2046 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2047 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2056 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2057 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2058 * entries for each of the 4KB page mappings.
2061 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2062 struct rwlock **lockp)
2064 struct md_page *pvh;
2065 struct pv_chunk *pc;
2067 vm_offset_t va_last;
2071 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2072 KASSERT((pa & L2_OFFSET) == 0,
2073 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2074 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2077 * Transfer the 2mpage's pv entry for this mapping to the first
2078 * page's pv list. Once this transfer begins, the pv list lock
2079 * must not be released until the last pv entry is reinstantiated.
2081 pvh = pa_to_pvh(pa);
2082 va = va & ~L2_OFFSET;
2083 pv = pmap_pvh_remove(pvh, pmap, va);
2084 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2085 m = PHYS_TO_VM_PAGE(pa);
2086 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2088 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2089 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2090 va_last = va + L2_SIZE - PAGE_SIZE;
2092 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2093 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2094 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2095 for (field = 0; field < _NPCM; field++) {
2096 while (pc->pc_map[field]) {
2097 bit = ffsl(pc->pc_map[field]) - 1;
2098 pc->pc_map[field] &= ~(1ul << bit);
2099 pv = &pc->pc_pventry[field * 64 + bit];
2103 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2104 ("pmap_pv_demote_l2: page %p is not managed", m));
2105 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2111 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2112 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2115 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2116 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2117 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2119 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2120 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2124 * First find and then destroy the pv entry for the specified pmap and virtual
2125 * address. This operation can be performed on pv lists for either 4KB or 2MB
2129 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2133 pv = pmap_pvh_remove(pvh, pmap, va);
2134 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2135 free_pv_entry(pmap, pv);
2139 * Conditionally create the PV entry for a 4KB page mapping if the required
2140 * memory can be allocated without resorting to reclamation.
2143 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2144 struct rwlock **lockp)
2148 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2149 /* Pass NULL instead of the lock pointer to disable reclamation. */
2150 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2152 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2153 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2161 * pmap_remove_l3: do the things to unmap a page in a process
2164 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2165 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2167 struct md_page *pvh;
2171 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2172 if (pmap_is_current(pmap) && pmap_l3_valid_cacheable(pmap_load(l3)))
2173 cpu_dcache_wb_range(va, L3_SIZE);
2174 old_l3 = pmap_load_clear(l3);
2176 pmap_invalidate_page(pmap, va);
2177 if (old_l3 & ATTR_SW_WIRED)
2178 pmap->pm_stats.wired_count -= 1;
2179 pmap_resident_count_dec(pmap, 1);
2180 if (old_l3 & ATTR_SW_MANAGED) {
2181 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2182 if (pmap_page_dirty(old_l3))
2184 if (old_l3 & ATTR_AF)
2185 vm_page_aflag_set(m, PGA_REFERENCED);
2186 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2187 pmap_pvh_free(&m->md, pmap, va);
2188 if (TAILQ_EMPTY(&m->md.pv_list) &&
2189 (m->flags & PG_FICTITIOUS) == 0) {
2190 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2191 if (TAILQ_EMPTY(&pvh->pv_list))
2192 vm_page_aflag_clear(m, PGA_WRITEABLE);
2195 return (pmap_unuse_l3(pmap, va, l2e, free));
2199 * Remove the given range of addresses from the specified map.
2201 * It is assumed that the start and end are properly
2202 * rounded to the page size.
2205 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2207 struct rwlock *lock;
2208 vm_offset_t va, va_next;
2209 pd_entry_t *l0, *l1, *l2;
2210 pt_entry_t l3_paddr, *l3;
2211 struct spglist free;
2215 * Perform an unsynchronized read. This is, however, safe.
2217 if (pmap->pm_stats.resident_count == 0)
2226 for (; sva < eva; sva = va_next) {
2228 if (pmap->pm_stats.resident_count == 0)
2231 l0 = pmap_l0(pmap, sva);
2232 if (pmap_load(l0) == 0) {
2233 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2239 l1 = pmap_l0_to_l1(l0, sva);
2240 if (pmap_load(l1) == 0) {
2241 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2248 * Calculate index for next page table.
2250 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2254 l2 = pmap_l1_to_l2(l1, sva);
2258 l3_paddr = pmap_load(l2);
2260 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2261 /* TODO: Add pmap_remove_l2 */
2262 if (pmap_demote_l2_locked(pmap, l2, sva & ~L2_OFFSET,
2265 l3_paddr = pmap_load(l2);
2269 * Weed out invalid mappings.
2271 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2275 * Limit our scan to either the end of the va represented
2276 * by the current page table page, or to the end of the
2277 * range being removed.
2283 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2286 panic("l3 == NULL");
2287 if (pmap_load(l3) == 0) {
2288 if (va != va_next) {
2289 pmap_invalidate_range(pmap, va, sva);
2296 if (pmap_remove_l3(pmap, l3, sva, l3_paddr, &free,
2303 pmap_invalidate_range(pmap, va, sva);
2308 pmap_invalidate_all(pmap);
2310 pmap_free_zero_pages(&free);
2314 * Routine: pmap_remove_all
2316 * Removes this physical page from
2317 * all physical maps in which it resides.
2318 * Reflects back modify bits to the pager.
2321 * Original versions of this routine were very
2322 * inefficient because they iteratively called
2323 * pmap_remove (slow...)
2327 pmap_remove_all(vm_page_t m)
2329 struct md_page *pvh;
2332 struct rwlock *lock;
2333 pd_entry_t *pde, tpde;
2334 pt_entry_t *pte, tpte;
2336 struct spglist free;
2337 int lvl, pvh_gen, md_gen;
2339 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2340 ("pmap_remove_all: page %p is not managed", m));
2342 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2343 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2344 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2347 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2349 if (!PMAP_TRYLOCK(pmap)) {
2350 pvh_gen = pvh->pv_gen;
2354 if (pvh_gen != pvh->pv_gen) {
2361 pte = pmap_pte(pmap, va, &lvl);
2362 KASSERT(pte != NULL,
2363 ("pmap_remove_all: no page table entry found"));
2365 ("pmap_remove_all: invalid pte level %d", lvl));
2367 pmap_demote_l2_locked(pmap, pte, va, &lock);
2370 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2372 if (!PMAP_TRYLOCK(pmap)) {
2373 pvh_gen = pvh->pv_gen;
2374 md_gen = m->md.pv_gen;
2378 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2384 pmap_resident_count_dec(pmap, 1);
2386 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2387 KASSERT(pde != NULL,
2388 ("pmap_remove_all: no page directory entry found"));
2390 ("pmap_remove_all: invalid pde level %d", lvl));
2391 tpde = pmap_load(pde);
2393 pte = pmap_l2_to_l3(pde, pv->pv_va);
2394 tpte = pmap_load(pte);
2395 if (pmap_is_current(pmap) &&
2396 pmap_l3_valid_cacheable(tpte))
2397 cpu_dcache_wb_range(pv->pv_va, L3_SIZE);
2398 pmap_load_clear(pte);
2400 pmap_invalidate_page(pmap, pv->pv_va);
2401 if (tpte & ATTR_SW_WIRED)
2402 pmap->pm_stats.wired_count--;
2403 if ((tpte & ATTR_AF) != 0)
2404 vm_page_aflag_set(m, PGA_REFERENCED);
2407 * Update the vm_page_t clean and reference bits.
2409 if (pmap_page_dirty(tpte))
2411 pmap_unuse_l3(pmap, pv->pv_va, tpde, &free);
2412 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2414 free_pv_entry(pmap, pv);
2417 vm_page_aflag_clear(m, PGA_WRITEABLE);
2419 pmap_free_zero_pages(&free);
2423 * Set the physical protection on the
2424 * specified range of this map as requested.
2427 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2429 vm_offset_t va, va_next;
2430 pd_entry_t *l0, *l1, *l2;
2431 pt_entry_t *l3p, l3;
2433 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2434 pmap_remove(pmap, sva, eva);
2438 if ((prot & VM_PROT_WRITE) == VM_PROT_WRITE)
2442 for (; sva < eva; sva = va_next) {
2444 l0 = pmap_l0(pmap, sva);
2445 if (pmap_load(l0) == 0) {
2446 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2452 l1 = pmap_l0_to_l1(l0, sva);
2453 if (pmap_load(l1) == 0) {
2454 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2460 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2464 l2 = pmap_l1_to_l2(l1, sva);
2465 if (pmap_load(l2) == 0)
2468 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
2469 l3p = pmap_demote_l2(pmap, l2, sva);
2473 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
2474 ("pmap_protect: Invalid L2 entry after demotion"));
2480 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2482 l3 = pmap_load(l3p);
2483 if (pmap_l3_valid(l3)) {
2484 pmap_set(l3p, ATTR_AP(ATTR_AP_RO));
2486 /* XXX: Use pmap_invalidate_range */
2487 pmap_invalidate_page(pmap, va);
2493 /* TODO: Only invalidate entries we are touching */
2494 pmap_invalidate_all(pmap);
2498 * Inserts the specified page table page into the specified pmap's collection
2499 * of idle page table pages. Each of a pmap's page table pages is responsible
2500 * for mapping a distinct range of virtual addresses. The pmap's collection is
2501 * ordered by this virtual address range.
2504 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2507 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2508 return (vm_radix_insert(&pmap->pm_root, mpte));
2512 * Removes the page table page mapping the specified virtual address from the
2513 * specified pmap's collection of idle page table pages, and returns it.
2514 * Otherwise, returns NULL if there is no page table page corresponding to the
2515 * specified virtual address.
2517 static __inline vm_page_t
2518 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2521 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2522 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
2526 * Performs a break-before-make update of a pmap entry. This is needed when
2527 * either promoting or demoting pages to ensure the TLB doesn't get into an
2528 * inconsistent state.
2531 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
2532 vm_offset_t va, vm_size_t size)
2536 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2539 * Ensure we don't get switched out with the page table in an
2540 * inconsistent state. We also need to ensure no interrupts fire
2541 * as they may make use of an address we are about to invalidate.
2543 intr = intr_disable();
2546 /* Clear the old mapping */
2547 pmap_load_clear(pte);
2549 pmap_invalidate_range(pmap, va, va + size);
2551 /* Create the new mapping */
2552 pmap_load_store(pte, newpte);
2560 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
2561 * replace the many pv entries for the 4KB page mappings by a single pv entry
2562 * for the 2MB page mapping.
2565 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2566 struct rwlock **lockp)
2568 struct md_page *pvh;
2570 vm_offset_t va_last;
2573 KASSERT((pa & L2_OFFSET) == 0,
2574 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
2575 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2578 * Transfer the first page's pv entry for this mapping to the 2mpage's
2579 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
2580 * a transfer avoids the possibility that get_pv_entry() calls
2581 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
2582 * mappings that is being promoted.
2584 m = PHYS_TO_VM_PAGE(pa);
2585 va = va & ~L2_OFFSET;
2586 pv = pmap_pvh_remove(&m->md, pmap, va);
2587 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
2588 pvh = pa_to_pvh(pa);
2589 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2591 /* Free the remaining NPTEPG - 1 pv entries. */
2592 va_last = va + L2_SIZE - PAGE_SIZE;
2596 pmap_pvh_free(&m->md, pmap, va);
2597 } while (va < va_last);
2601 * Tries to promote the 512, contiguous 4KB page mappings that are within a
2602 * single level 2 table entry to a single 2MB page mapping. For promotion
2603 * to occur, two conditions must be met: (1) the 4KB page mappings must map
2604 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
2605 * identical characteristics.
2608 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
2609 struct rwlock **lockp)
2611 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
2615 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2617 sva = va & ~L2_OFFSET;
2618 firstl3 = pmap_l2_to_l3(l2, sva);
2619 newl2 = pmap_load(firstl3);
2621 /* Check the alingment is valid */
2622 if (((newl2 & ~ATTR_MASK) & L2_OFFSET) != 0) {
2623 atomic_add_long(&pmap_l2_p_failures, 1);
2624 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2625 " in pmap %p", va, pmap);
2629 pa = newl2 + L2_SIZE - PAGE_SIZE;
2630 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
2631 oldl3 = pmap_load(l3);
2633 atomic_add_long(&pmap_l2_p_failures, 1);
2634 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2635 " in pmap %p", va, pmap);
2642 * Save the page table page in its current state until the L2
2643 * mapping the superpage is demoted by pmap_demote_l2() or
2644 * destroyed by pmap_remove_l3().
2646 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
2647 KASSERT(mpte >= vm_page_array &&
2648 mpte < &vm_page_array[vm_page_array_size],
2649 ("pmap_promote_l2: page table page is out of range"));
2650 KASSERT(mpte->pindex == pmap_l2_pindex(va),
2651 ("pmap_promote_l2: page table page's pindex is wrong"));
2652 if (pmap_insert_pt_page(pmap, mpte)) {
2653 atomic_add_long(&pmap_l2_p_failures, 1);
2655 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
2660 if ((newl2 & ATTR_SW_MANAGED) != 0)
2661 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
2663 newl2 &= ~ATTR_DESCR_MASK;
2666 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
2668 atomic_add_long(&pmap_l2_promotions, 1);
2669 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
2674 * Insert the given physical page (p) at
2675 * the specified virtual address (v) in the
2676 * target physical map with the protection requested.
2678 * If specified, the page will be wired down, meaning
2679 * that the related pte can not be reclaimed.
2681 * NB: This is the only routine which MAY NOT lazy-evaluate
2682 * or lose information. That is, this routine must actually
2683 * insert this page into the given map NOW.
2686 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2687 u_int flags, int8_t psind __unused)
2689 struct rwlock *lock;
2691 pt_entry_t new_l3, orig_l3;
2692 pt_entry_t *l2, *l3;
2694 vm_paddr_t opa, pa, l1_pa, l2_pa, l3_pa;
2695 vm_page_t mpte, om, l1_m, l2_m, l3_m;
2699 va = trunc_page(va);
2700 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2701 VM_OBJECT_ASSERT_LOCKED(m->object);
2702 pa = VM_PAGE_TO_PHYS(m);
2703 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
2705 if ((prot & VM_PROT_WRITE) == 0)
2706 new_l3 |= ATTR_AP(ATTR_AP_RO);
2707 if ((flags & PMAP_ENTER_WIRED) != 0)
2708 new_l3 |= ATTR_SW_WIRED;
2709 if ((va >> 63) == 0)
2710 new_l3 |= ATTR_AP(ATTR_AP_USER);
2712 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
2719 pde = pmap_pde(pmap, va, &lvl);
2720 if (pde != NULL && lvl == 1) {
2721 l2 = pmap_l1_to_l2(pde, va);
2722 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
2723 (l3 = pmap_demote_l2_locked(pmap, l2, va & ~L2_OFFSET,
2725 l3 = &l3[pmap_l3_index(va)];
2726 if (va < VM_MAXUSER_ADDRESS) {
2727 mpte = PHYS_TO_VM_PAGE(
2728 pmap_load(l2) & ~ATTR_MASK);
2735 if (va < VM_MAXUSER_ADDRESS) {
2736 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
2737 mpte = pmap_alloc_l3(pmap, va, nosleep ? NULL : &lock);
2738 if (mpte == NULL && nosleep) {
2739 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
2743 return (KERN_RESOURCE_SHORTAGE);
2745 pde = pmap_pde(pmap, va, &lvl);
2746 KASSERT(pde != NULL,
2747 ("pmap_enter: Invalid page entry, va: 0x%lx", va));
2749 ("pmap_enter: Invalid level %d", lvl));
2751 l3 = pmap_l2_to_l3(pde, va);
2754 * If we get a level 2 pde it must point to a level 3 entry
2755 * otherwise we will need to create the intermediate tables
2761 /* Get the l0 pde to update */
2762 pde = pmap_l0(pmap, va);
2763 KASSERT(pde != NULL, ("..."));
2765 l1_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2766 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2769 panic("pmap_enter: l1 pte_m == NULL");
2770 if ((l1_m->flags & PG_ZERO) == 0)
2771 pmap_zero_page(l1_m);
2773 l1_pa = VM_PAGE_TO_PHYS(l1_m);
2774 pmap_load_store(pde, l1_pa | L0_TABLE);
2778 /* Get the l1 pde to update */
2779 pde = pmap_l1_to_l2(pde, va);
2780 KASSERT(pde != NULL, ("..."));
2782 l2_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2783 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2786 panic("pmap_enter: l2 pte_m == NULL");
2787 if ((l2_m->flags & PG_ZERO) == 0)
2788 pmap_zero_page(l2_m);
2790 l2_pa = VM_PAGE_TO_PHYS(l2_m);
2791 pmap_load_store(pde, l2_pa | L1_TABLE);
2795 /* Get the l2 pde to update */
2796 pde = pmap_l1_to_l2(pde, va);
2798 l3_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2799 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2802 panic("pmap_enter: l3 pte_m == NULL");
2803 if ((l3_m->flags & PG_ZERO) == 0)
2804 pmap_zero_page(l3_m);
2806 l3_pa = VM_PAGE_TO_PHYS(l3_m);
2807 pmap_load_store(pde, l3_pa | L2_TABLE);
2812 l3 = pmap_l2_to_l3(pde, va);
2813 pmap_invalidate_page(pmap, va);
2818 orig_l3 = pmap_load(l3);
2819 opa = orig_l3 & ~ATTR_MASK;
2822 * Is the specified virtual address already mapped?
2824 if (pmap_l3_valid(orig_l3)) {
2826 * Wiring change, just update stats. We don't worry about
2827 * wiring PT pages as they remain resident as long as there
2828 * are valid mappings in them. Hence, if a user page is wired,
2829 * the PT page will be also.
2831 if ((flags & PMAP_ENTER_WIRED) != 0 &&
2832 (orig_l3 & ATTR_SW_WIRED) == 0)
2833 pmap->pm_stats.wired_count++;
2834 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
2835 (orig_l3 & ATTR_SW_WIRED) != 0)
2836 pmap->pm_stats.wired_count--;
2839 * Remove the extra PT page reference.
2843 KASSERT(mpte->wire_count > 0,
2844 ("pmap_enter: missing reference to page table page,"
2849 * Has the physical page changed?
2853 * No, might be a protection or wiring change.
2855 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
2856 new_l3 |= ATTR_SW_MANAGED;
2857 if ((new_l3 & ATTR_AP(ATTR_AP_RW)) ==
2858 ATTR_AP(ATTR_AP_RW)) {
2859 vm_page_aflag_set(m, PGA_WRITEABLE);
2865 /* Flush the cache, there might be uncommitted data in it */
2866 if (pmap_is_current(pmap) && pmap_l3_valid_cacheable(orig_l3))
2867 cpu_dcache_wb_range(va, L3_SIZE);
2870 * Increment the counters.
2872 if ((new_l3 & ATTR_SW_WIRED) != 0)
2873 pmap->pm_stats.wired_count++;
2874 pmap_resident_count_inc(pmap, 1);
2877 * Enter on the PV list if part of our managed memory.
2879 if ((m->oflags & VPO_UNMANAGED) == 0) {
2880 new_l3 |= ATTR_SW_MANAGED;
2881 pv = get_pv_entry(pmap, &lock);
2883 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
2884 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2886 if ((new_l3 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
2887 vm_page_aflag_set(m, PGA_WRITEABLE);
2891 * Update the L3 entry.
2895 orig_l3 = pmap_load(l3);
2896 opa = orig_l3 & ~ATTR_MASK;
2899 pmap_update_entry(pmap, l3, new_l3, va, PAGE_SIZE);
2900 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
2901 om = PHYS_TO_VM_PAGE(opa);
2902 if (pmap_page_dirty(orig_l3))
2904 if ((orig_l3 & ATTR_AF) != 0)
2905 vm_page_aflag_set(om, PGA_REFERENCED);
2906 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
2907 pmap_pvh_free(&om->md, pmap, va);
2908 if ((om->aflags & PGA_WRITEABLE) != 0 &&
2909 TAILQ_EMPTY(&om->md.pv_list) &&
2910 ((om->flags & PG_FICTITIOUS) != 0 ||
2911 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
2912 vm_page_aflag_clear(om, PGA_WRITEABLE);
2915 pmap_load_store(l3, new_l3);
2917 pmap_invalidate_page(pmap, va);
2918 if (pmap_page_dirty(orig_l3) &&
2919 (orig_l3 & ATTR_SW_MANAGED) != 0)
2923 pmap_load_store(l3, new_l3);
2927 pmap_invalidate_page(pmap, va);
2929 if (pmap != pmap_kernel()) {
2930 if (pmap == &curproc->p_vmspace->vm_pmap &&
2931 (prot & VM_PROT_EXECUTE) != 0)
2932 cpu_icache_sync_range(va, PAGE_SIZE);
2934 if ((mpte == NULL || mpte->wire_count == NL3PG) &&
2935 pmap_superpages_enabled() &&
2936 (m->flags & PG_FICTITIOUS) == 0 &&
2937 vm_reserv_level_iffullpop(m) == 0) {
2938 pmap_promote_l2(pmap, pde, va, &lock);
2945 return (KERN_SUCCESS);
2949 * Maps a sequence of resident pages belonging to the same object.
2950 * The sequence begins with the given page m_start. This page is
2951 * mapped at the given virtual address start. Each subsequent page is
2952 * mapped at a virtual address that is offset from start by the same
2953 * amount as the page is offset from m_start within the object. The
2954 * last page in the sequence is the page with the largest offset from
2955 * m_start that can be mapped at a virtual address less than the given
2956 * virtual address end. Not every virtual page between start and end
2957 * is mapped; only those for which a resident page exists with the
2958 * corresponding offset from m_start are mapped.
2961 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
2962 vm_page_t m_start, vm_prot_t prot)
2964 struct rwlock *lock;
2967 vm_pindex_t diff, psize;
2969 VM_OBJECT_ASSERT_LOCKED(m_start->object);
2971 psize = atop(end - start);
2976 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2977 va = start + ptoa(diff);
2978 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte, &lock);
2979 m = TAILQ_NEXT(m, listq);
2987 * this code makes some *MAJOR* assumptions:
2988 * 1. Current pmap & pmap exists.
2991 * 4. No page table pages.
2992 * but is *MUCH* faster than pmap_enter...
2996 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
2998 struct rwlock *lock;
3002 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3009 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3010 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3012 struct spglist free;
3014 pt_entry_t *l2, *l3;
3018 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3019 (m->oflags & VPO_UNMANAGED) != 0,
3020 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3021 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3023 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3025 * In the case that a page table page is not
3026 * resident, we are creating it here.
3028 if (va < VM_MAXUSER_ADDRESS) {
3029 vm_pindex_t l2pindex;
3032 * Calculate pagetable page index
3034 l2pindex = pmap_l2_pindex(va);
3035 if (mpte && (mpte->pindex == l2pindex)) {
3041 pde = pmap_pde(pmap, va, &lvl);
3044 * If the page table page is mapped, we just increment
3045 * the hold count, and activate it. Otherwise, we
3046 * attempt to allocate a page table page. If this
3047 * attempt fails, we don't retry. Instead, we give up.
3050 l2 = pmap_l1_to_l2(pde, va);
3051 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3055 if (lvl == 2 && pmap_load(pde) != 0) {
3057 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3061 * Pass NULL instead of the PV list lock
3062 * pointer, because we don't intend to sleep.
3064 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3069 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3070 l3 = &l3[pmap_l3_index(va)];
3073 pde = pmap_pde(kernel_pmap, va, &lvl);
3074 KASSERT(pde != NULL,
3075 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3078 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3079 l3 = pmap_l2_to_l3(pde, va);
3082 if (pmap_load(l3) != 0) {
3091 * Enter on the PV list if part of our managed memory.
3093 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3094 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3097 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
3098 pmap_invalidate_page(pmap, va);
3099 pmap_free_zero_pages(&free);
3107 * Increment counters
3109 pmap_resident_count_inc(pmap, 1);
3111 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3112 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3115 * Now validate mapping with RO protection
3117 if ((m->oflags & VPO_UNMANAGED) == 0)
3118 pa |= ATTR_SW_MANAGED;
3119 pmap_load_store(l3, pa);
3121 pmap_invalidate_page(pmap, va);
3126 * This code maps large physical mmap regions into the
3127 * processor address space. Note that some shortcuts
3128 * are taken, but the code works.
3131 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3132 vm_pindex_t pindex, vm_size_t size)
3135 VM_OBJECT_ASSERT_WLOCKED(object);
3136 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3137 ("pmap_object_init_pt: non-device object"));
3141 * Clear the wired attribute from the mappings for the specified range of
3142 * addresses in the given pmap. Every valid mapping within that range
3143 * must have the wired attribute set. In contrast, invalid mappings
3144 * cannot have the wired attribute set, so they are ignored.
3146 * The wired attribute of the page table entry is not a hardware feature,
3147 * so there is no need to invalidate any TLB entries.
3150 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3152 vm_offset_t va_next;
3153 pd_entry_t *l0, *l1, *l2;
3157 for (; sva < eva; sva = va_next) {
3158 l0 = pmap_l0(pmap, sva);
3159 if (pmap_load(l0) == 0) {
3160 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3166 l1 = pmap_l0_to_l1(l0, sva);
3167 if (pmap_load(l1) == 0) {
3168 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3174 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3178 l2 = pmap_l1_to_l2(l1, sva);
3179 if (pmap_load(l2) == 0)
3182 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3183 l3 = pmap_demote_l2(pmap, l2, sva);
3187 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3188 ("pmap_unwire: Invalid l2 entry after demotion"));
3192 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3194 if (pmap_load(l3) == 0)
3196 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
3197 panic("pmap_unwire: l3 %#jx is missing "
3198 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
3201 * PG_W must be cleared atomically. Although the pmap
3202 * lock synchronizes access to PG_W, another processor
3203 * could be setting PG_M and/or PG_A concurrently.
3205 atomic_clear_long(l3, ATTR_SW_WIRED);
3206 pmap->pm_stats.wired_count--;
3213 * Copy the range specified by src_addr/len
3214 * from the source map to the range dst_addr/len
3215 * in the destination map.
3217 * This routine is only advisory and need not do anything.
3221 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3222 vm_offset_t src_addr)
3227 * pmap_zero_page zeros the specified hardware page by mapping
3228 * the page into KVM and using bzero to clear its contents.
3231 pmap_zero_page(vm_page_t m)
3233 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3235 pagezero((void *)va);
3239 * pmap_zero_page_area zeros the specified hardware page by mapping
3240 * the page into KVM and using bzero to clear its contents.
3242 * off and size may not cover an area beyond a single hardware page.
3245 pmap_zero_page_area(vm_page_t m, int off, int size)
3247 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3249 if (off == 0 && size == PAGE_SIZE)
3250 pagezero((void *)va);
3252 bzero((char *)va + off, size);
3256 * pmap_copy_page copies the specified (machine independent)
3257 * page by mapping the page into virtual memory and using
3258 * bcopy to copy the page, one machine dependent page at a
3262 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
3264 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
3265 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
3267 pagecopy((void *)src, (void *)dst);
3270 int unmapped_buf_allowed = 1;
3273 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
3274 vm_offset_t b_offset, int xfersize)
3278 vm_paddr_t p_a, p_b;
3279 vm_offset_t a_pg_offset, b_pg_offset;
3282 while (xfersize > 0) {
3283 a_pg_offset = a_offset & PAGE_MASK;
3284 m_a = ma[a_offset >> PAGE_SHIFT];
3285 p_a = m_a->phys_addr;
3286 b_pg_offset = b_offset & PAGE_MASK;
3287 m_b = mb[b_offset >> PAGE_SHIFT];
3288 p_b = m_b->phys_addr;
3289 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
3290 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
3291 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
3292 panic("!DMAP a %lx", p_a);
3294 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
3296 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
3297 panic("!DMAP b %lx", p_b);
3299 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
3301 bcopy(a_cp, b_cp, cnt);
3309 pmap_quick_enter_page(vm_page_t m)
3312 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
3316 pmap_quick_remove_page(vm_offset_t addr)
3321 * Returns true if the pmap's pv is one of the first
3322 * 16 pvs linked to from this page. This count may
3323 * be changed upwards or downwards in the future; it
3324 * is only necessary that true be returned for a small
3325 * subset of pmaps for proper page aging.
3328 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3330 struct md_page *pvh;
3331 struct rwlock *lock;
3336 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3337 ("pmap_page_exists_quick: page %p is not managed", m));
3339 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3341 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3342 if (PV_PMAP(pv) == pmap) {
3350 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
3351 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3352 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3353 if (PV_PMAP(pv) == pmap) {
3367 * pmap_page_wired_mappings:
3369 * Return the number of managed mappings to the given physical page
3373 pmap_page_wired_mappings(vm_page_t m)
3375 struct rwlock *lock;
3376 struct md_page *pvh;
3380 int count, lvl, md_gen, pvh_gen;
3382 if ((m->oflags & VPO_UNMANAGED) != 0)
3384 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3388 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3390 if (!PMAP_TRYLOCK(pmap)) {
3391 md_gen = m->md.pv_gen;
3395 if (md_gen != m->md.pv_gen) {
3400 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3401 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3405 if ((m->flags & PG_FICTITIOUS) == 0) {
3406 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3407 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3409 if (!PMAP_TRYLOCK(pmap)) {
3410 md_gen = m->md.pv_gen;
3411 pvh_gen = pvh->pv_gen;
3415 if (md_gen != m->md.pv_gen ||
3416 pvh_gen != pvh->pv_gen) {
3421 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3423 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3433 * Destroy all managed, non-wired mappings in the given user-space
3434 * pmap. This pmap cannot be active on any processor besides the
3437 * This function cannot be applied to the kernel pmap. Moreover, it
3438 * is not intended for general use. It is only to be used during
3439 * process termination. Consequently, it can be implemented in ways
3440 * that make it faster than pmap_remove(). First, it can more quickly
3441 * destroy mappings by iterating over the pmap's collection of PV
3442 * entries, rather than searching the page table. Second, it doesn't
3443 * have to test and clear the page table entries atomically, because
3444 * no processor is currently accessing the user address space. In
3445 * particular, a page table entry's dirty bit won't change state once
3446 * this function starts.
3449 pmap_remove_pages(pmap_t pmap)
3452 pt_entry_t *pte, tpte;
3453 struct spglist free;
3454 vm_page_t m, ml3, mt;
3456 struct md_page *pvh;
3457 struct pv_chunk *pc, *npc;
3458 struct rwlock *lock;
3460 uint64_t inuse, bitmask;
3461 int allfree, field, freed, idx, lvl;
3468 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
3471 for (field = 0; field < _NPCM; field++) {
3472 inuse = ~pc->pc_map[field] & pc_freemask[field];
3473 while (inuse != 0) {
3474 bit = ffsl(inuse) - 1;
3475 bitmask = 1UL << bit;
3476 idx = field * 64 + bit;
3477 pv = &pc->pc_pventry[idx];
3480 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3481 KASSERT(pde != NULL,
3482 ("Attempting to remove an unmapped page"));
3486 pte = pmap_l1_to_l2(pde, pv->pv_va);
3487 tpte = pmap_load(pte);
3488 KASSERT((tpte & ATTR_DESCR_MASK) ==
3490 ("Attempting to remove an invalid "
3491 "block: %lx", tpte));
3492 tpte = pmap_load(pte);
3495 pte = pmap_l2_to_l3(pde, pv->pv_va);
3496 tpte = pmap_load(pte);
3497 KASSERT((tpte & ATTR_DESCR_MASK) ==
3499 ("Attempting to remove an invalid "
3500 "page: %lx", tpte));
3504 "Invalid page directory level: %d",
3509 * We cannot remove wired pages from a process' mapping at this time
3511 if (tpte & ATTR_SW_WIRED) {
3516 pa = tpte & ~ATTR_MASK;
3518 m = PHYS_TO_VM_PAGE(pa);
3519 KASSERT(m->phys_addr == pa,
3520 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
3521 m, (uintmax_t)m->phys_addr,
3524 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
3525 m < &vm_page_array[vm_page_array_size],
3526 ("pmap_remove_pages: bad pte %#jx",
3529 if (pmap_is_current(pmap)) {
3531 pmap_l3_valid_cacheable(tpte)) {
3532 cpu_dcache_wb_range(pv->pv_va,
3534 } else if (lvl == 1 &&
3535 pmap_pte_valid_cacheable(tpte)) {
3536 cpu_dcache_wb_range(pv->pv_va,
3540 pmap_load_clear(pte);
3542 pmap_invalidate_page(pmap, pv->pv_va);
3545 * Update the vm_page_t clean/reference bits.
3547 if ((tpte & ATTR_AP_RW_BIT) ==
3548 ATTR_AP(ATTR_AP_RW)) {
3551 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3560 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
3563 pc->pc_map[field] |= bitmask;
3566 pmap_resident_count_dec(pmap,
3567 L2_SIZE / PAGE_SIZE);
3568 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
3569 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
3571 if (TAILQ_EMPTY(&pvh->pv_list)) {
3572 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3573 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
3574 TAILQ_EMPTY(&mt->md.pv_list))
3575 vm_page_aflag_clear(mt, PGA_WRITEABLE);
3577 ml3 = pmap_remove_pt_page(pmap,
3580 pmap_resident_count_dec(pmap,1);
3581 KASSERT(ml3->wire_count == NL3PG,
3582 ("pmap_remove_pages: l3 page wire count error"));
3583 ml3->wire_count = 0;
3584 pmap_add_delayed_free_list(ml3,
3586 atomic_subtract_int(
3587 &vm_cnt.v_wire_count, 1);
3591 pmap_resident_count_dec(pmap, 1);
3592 TAILQ_REMOVE(&m->md.pv_list, pv,
3595 if ((m->aflags & PGA_WRITEABLE) != 0 &&
3596 TAILQ_EMPTY(&m->md.pv_list) &&
3597 (m->flags & PG_FICTITIOUS) == 0) {
3599 VM_PAGE_TO_PHYS(m));
3600 if (TAILQ_EMPTY(&pvh->pv_list))
3601 vm_page_aflag_clear(m,
3606 pmap_unuse_l3(pmap, pv->pv_va, pmap_load(pde),
3611 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3612 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3613 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3615 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3619 pmap_invalidate_all(pmap);
3623 pmap_free_zero_pages(&free);
3627 * This is used to check if a page has been accessed or modified. As we
3628 * don't have a bit to see if it has been modified we have to assume it
3629 * has been if the page is read/write.
3632 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
3634 struct rwlock *lock;
3636 struct md_page *pvh;
3637 pt_entry_t *pte, mask, value;
3639 int lvl, md_gen, pvh_gen;
3643 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3646 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3648 if (!PMAP_TRYLOCK(pmap)) {
3649 md_gen = m->md.pv_gen;
3653 if (md_gen != m->md.pv_gen) {
3658 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3660 ("pmap_page_test_mappings: Invalid level %d", lvl));
3664 mask |= ATTR_AP_RW_BIT;
3665 value |= ATTR_AP(ATTR_AP_RW);
3668 mask |= ATTR_AF | ATTR_DESCR_MASK;
3669 value |= ATTR_AF | L3_PAGE;
3671 rv = (pmap_load(pte) & mask) == value;
3676 if ((m->flags & PG_FICTITIOUS) == 0) {
3677 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3678 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3680 if (!PMAP_TRYLOCK(pmap)) {
3681 md_gen = m->md.pv_gen;
3682 pvh_gen = pvh->pv_gen;
3686 if (md_gen != m->md.pv_gen ||
3687 pvh_gen != pvh->pv_gen) {
3692 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3694 ("pmap_page_test_mappings: Invalid level %d", lvl));
3698 mask |= ATTR_AP_RW_BIT;
3699 value |= ATTR_AP(ATTR_AP_RW);
3702 mask |= ATTR_AF | ATTR_DESCR_MASK;
3703 value |= ATTR_AF | L2_BLOCK;
3705 rv = (pmap_load(pte) & mask) == value;
3719 * Return whether or not the specified physical page was modified
3720 * in any physical maps.
3723 pmap_is_modified(vm_page_t m)
3726 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3727 ("pmap_is_modified: page %p is not managed", m));
3730 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3731 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
3732 * is clear, no PTEs can have PG_M set.
3734 VM_OBJECT_ASSERT_WLOCKED(m->object);
3735 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3737 return (pmap_page_test_mappings(m, FALSE, TRUE));
3741 * pmap_is_prefaultable:
3743 * Return whether or not the specified virtual address is eligible
3747 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3755 pte = pmap_pte(pmap, addr, &lvl);
3756 if (pte != NULL && pmap_load(pte) != 0) {
3764 * pmap_is_referenced:
3766 * Return whether or not the specified physical page was referenced
3767 * in any physical maps.
3770 pmap_is_referenced(vm_page_t m)
3773 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3774 ("pmap_is_referenced: page %p is not managed", m));
3775 return (pmap_page_test_mappings(m, TRUE, FALSE));
3779 * Clear the write and modified bits in each of the given page's mappings.
3782 pmap_remove_write(vm_page_t m)
3784 struct md_page *pvh;
3786 struct rwlock *lock;
3787 pv_entry_t next_pv, pv;
3788 pt_entry_t oldpte, *pte;
3790 int lvl, md_gen, pvh_gen;
3792 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3793 ("pmap_remove_write: page %p is not managed", m));
3796 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3797 * set by another thread while the object is locked. Thus,
3798 * if PGA_WRITEABLE is clear, no page table entries need updating.
3800 VM_OBJECT_ASSERT_WLOCKED(m->object);
3801 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3803 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3804 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
3805 pa_to_pvh(VM_PAGE_TO_PHYS(m));
3808 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
3810 if (!PMAP_TRYLOCK(pmap)) {
3811 pvh_gen = pvh->pv_gen;
3815 if (pvh_gen != pvh->pv_gen) {
3822 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3823 if ((pmap_load(pte) & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3824 pmap_demote_l2_locked(pmap, pte, va & ~L2_OFFSET,
3826 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
3827 ("inconsistent pv lock %p %p for page %p",
3828 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
3831 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3833 if (!PMAP_TRYLOCK(pmap)) {
3834 pvh_gen = pvh->pv_gen;
3835 md_gen = m->md.pv_gen;
3839 if (pvh_gen != pvh->pv_gen ||
3840 md_gen != m->md.pv_gen) {
3846 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3848 oldpte = pmap_load(pte);
3849 if ((oldpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) {
3850 if (!atomic_cmpset_long(pte, oldpte,
3851 oldpte | ATTR_AP(ATTR_AP_RO)))
3853 if ((oldpte & ATTR_AF) != 0)
3855 pmap_invalidate_page(pmap, pv->pv_va);
3860 vm_page_aflag_clear(m, PGA_WRITEABLE);
3863 static __inline boolean_t
3864 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
3871 * pmap_ts_referenced:
3873 * Return a count of reference bits for a page, clearing those bits.
3874 * It is not necessary for every reference bit to be cleared, but it
3875 * is necessary that 0 only be returned when there are truly no
3876 * reference bits set.
3878 * As an optimization, update the page's dirty field if a modified bit is
3879 * found while counting reference bits. This opportunistic update can be
3880 * performed at low cost and can eliminate the need for some future calls
3881 * to pmap_is_modified(). However, since this function stops after
3882 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
3883 * dirty pages. Those dirty pages will only be detected by a future call
3884 * to pmap_is_modified().
3887 pmap_ts_referenced(vm_page_t m)
3889 struct md_page *pvh;
3892 struct rwlock *lock;
3893 pd_entry_t *pde, tpde;
3894 pt_entry_t *pte, tpte;
3898 int cleared, md_gen, not_cleared, lvl, pvh_gen;
3899 struct spglist free;
3902 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3903 ("pmap_ts_referenced: page %p is not managed", m));
3906 pa = VM_PAGE_TO_PHYS(m);
3907 lock = PHYS_TO_PV_LIST_LOCK(pa);
3908 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
3912 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
3913 goto small_mappings;
3919 if (!PMAP_TRYLOCK(pmap)) {
3920 pvh_gen = pvh->pv_gen;
3924 if (pvh_gen != pvh->pv_gen) {
3930 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3931 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
3933 ("pmap_ts_referenced: invalid pde level %d", lvl));
3934 tpde = pmap_load(pde);
3935 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
3936 ("pmap_ts_referenced: found an invalid l1 table"));
3937 pte = pmap_l1_to_l2(pde, pv->pv_va);
3938 tpte = pmap_load(pte);
3939 if (pmap_page_dirty(tpte)) {
3941 * Although "tpte" is mapping a 2MB page, because
3942 * this function is called at a 4KB page granularity,
3943 * we only update the 4KB page under test.
3947 if ((tpte & ATTR_AF) != 0) {
3949 * Since this reference bit is shared by 512 4KB
3950 * pages, it should not be cleared every time it is
3951 * tested. Apply a simple "hash" function on the
3952 * physical page number, the virtual superpage number,
3953 * and the pmap address to select one 4KB page out of
3954 * the 512 on which testing the reference bit will
3955 * result in clearing that reference bit. This
3956 * function is designed to avoid the selection of the
3957 * same 4KB page for every 2MB page mapping.
3959 * On demotion, a mapping that hasn't been referenced
3960 * is simply destroyed. To avoid the possibility of a
3961 * subsequent page fault on a demoted wired mapping,
3962 * always leave its reference bit set. Moreover,
3963 * since the superpage is wired, the current state of
3964 * its reference bit won't affect page replacement.
3966 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
3967 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
3968 (tpte & ATTR_SW_WIRED) == 0) {
3969 if (safe_to_clear_referenced(pmap, tpte)) {
3971 * TODO: We don't handle the access
3972 * flag at all. We need to be able
3973 * to set it in the exception handler.
3976 "safe_to_clear_referenced\n");
3977 } else if (pmap_demote_l2_locked(pmap, pte,
3978 pv->pv_va, &lock) != NULL) {
3980 va += VM_PAGE_TO_PHYS(m) -
3981 (tpte & ~ATTR_MASK);
3982 l3 = pmap_l2_to_l3(pte, va);
3983 pmap_remove_l3(pmap, l3, va,
3984 pmap_load(pte), NULL, &lock);
3990 * The superpage mapping was removed
3991 * entirely and therefore 'pv' is no
3999 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4000 ("inconsistent pv lock %p %p for page %p",
4001 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4006 /* Rotate the PV list if it has more than one entry. */
4007 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4008 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4009 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4012 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4014 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4016 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4023 if (!PMAP_TRYLOCK(pmap)) {
4024 pvh_gen = pvh->pv_gen;
4025 md_gen = m->md.pv_gen;
4029 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4034 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4035 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4037 ("pmap_ts_referenced: invalid pde level %d", lvl));
4038 tpde = pmap_load(pde);
4039 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4040 ("pmap_ts_referenced: found an invalid l2 table"));
4041 pte = pmap_l2_to_l3(pde, pv->pv_va);
4042 tpte = pmap_load(pte);
4043 if (pmap_page_dirty(tpte))
4045 if ((tpte & ATTR_AF) != 0) {
4046 if (safe_to_clear_referenced(pmap, tpte)) {
4048 * TODO: We don't handle the access flag
4049 * at all. We need to be able to set it in
4050 * the exception handler.
4052 panic("ARM64TODO: safe_to_clear_referenced\n");
4053 } else if ((tpte & ATTR_SW_WIRED) == 0) {
4055 * Wired pages cannot be paged out so
4056 * doing accessed bit emulation for
4057 * them is wasted effort. We do the
4058 * hard work for unwired pages only.
4060 pmap_remove_l3(pmap, pte, pv->pv_va, tpde,
4062 pmap_invalidate_page(pmap, pv->pv_va);
4067 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4068 ("inconsistent pv lock %p %p for page %p",
4069 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4074 /* Rotate the PV list if it has more than one entry. */
4075 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4076 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4077 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4080 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4081 not_cleared < PMAP_TS_REFERENCED_MAX);
4084 pmap_free_zero_pages(&free);
4085 return (cleared + not_cleared);
4089 * Apply the given advice to the specified range of addresses within the
4090 * given pmap. Depending on the advice, clear the referenced and/or
4091 * modified flags in each mapping and set the mapped page's dirty field.
4094 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4099 * Clear the modify bits on the specified physical page.
4102 pmap_clear_modify(vm_page_t m)
4105 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4106 ("pmap_clear_modify: page %p is not managed", m));
4107 VM_OBJECT_ASSERT_WLOCKED(m->object);
4108 KASSERT(!vm_page_xbusied(m),
4109 ("pmap_clear_modify: page %p is exclusive busied", m));
4112 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4113 * If the object containing the page is locked and the page is not
4114 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4116 if ((m->aflags & PGA_WRITEABLE) == 0)
4119 /* ARM64TODO: We lack support for tracking if a page is modified */
4123 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4126 return ((void *)PHYS_TO_DMAP(pa));
4130 pmap_unmapbios(vm_paddr_t pa, vm_size_t size)
4135 * Sets the memory attribute for the specified page.
4138 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4141 m->md.pv_memattr = ma;
4144 * If "m" is a normal page, update its direct mapping. This update
4145 * can be relied upon to perform any cache operations that are
4146 * required for data coherence.
4148 if ((m->flags & PG_FICTITIOUS) == 0 &&
4149 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
4150 m->md.pv_memattr) != 0)
4151 panic("memory attribute change on the direct map failed");
4155 * Changes the specified virtual address range's memory type to that given by
4156 * the parameter "mode". The specified virtual address range must be
4157 * completely contained within either the direct map or the kernel map. If
4158 * the virtual address range is contained within the kernel map, then the
4159 * memory type for each of the corresponding ranges of the direct map is also
4160 * changed. (The corresponding ranges of the direct map are those ranges that
4161 * map the same physical pages as the specified virtual address range.) These
4162 * changes to the direct map are necessary because Intel describes the
4163 * behavior of their processors as "undefined" if two or more mappings to the
4164 * same physical page have different memory types.
4166 * Returns zero if the change completed successfully, and either EINVAL or
4167 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
4168 * of the virtual address range was not mapped, and ENOMEM is returned if
4169 * there was insufficient memory available to complete the change. In the
4170 * latter case, the memory type may have been changed on some part of the
4171 * virtual address range or the direct map.
4174 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
4178 PMAP_LOCK(kernel_pmap);
4179 error = pmap_change_attr_locked(va, size, mode);
4180 PMAP_UNLOCK(kernel_pmap);
4185 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
4187 vm_offset_t base, offset, tmpva;
4188 pt_entry_t l3, *pte, *newpte;
4191 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
4192 base = trunc_page(va);
4193 offset = va & PAGE_MASK;
4194 size = round_page(offset + size);
4196 if (!VIRT_IN_DMAP(base))
4199 for (tmpva = base; tmpva < base + size; ) {
4200 pte = pmap_pte(kernel_pmap, va, &lvl);
4204 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
4206 * We already have the correct attribute,
4207 * ignore this entry.
4211 panic("Invalid DMAP table level: %d\n", lvl);
4213 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
4216 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
4224 * Split the entry to an level 3 table, then
4225 * set the new attribute.
4229 panic("Invalid DMAP table level: %d\n", lvl);
4231 newpte = pmap_demote_l1(kernel_pmap, pte,
4232 tmpva & ~L1_OFFSET);
4235 pte = pmap_l1_to_l2(pte, tmpva);
4237 newpte = pmap_demote_l2(kernel_pmap, pte,
4238 tmpva & ~L2_OFFSET);
4241 pte = pmap_l2_to_l3(pte, tmpva);
4243 /* Update the entry */
4244 l3 = pmap_load(pte);
4245 l3 &= ~ATTR_IDX_MASK;
4246 l3 |= ATTR_IDX(mode);
4248 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
4252 * If moving to a non-cacheable entry flush
4255 if (mode == VM_MEMATTR_UNCACHEABLE)
4256 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
4268 * Create an L2 table to map all addresses within an L1 mapping.
4271 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
4273 pt_entry_t *l2, newl2, oldl1;
4275 vm_paddr_t l2phys, phys;
4279 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4280 oldl1 = pmap_load(l1);
4281 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
4282 ("pmap_demote_l1: Demoting a non-block entry"));
4283 KASSERT((va & L1_OFFSET) == 0,
4284 ("pmap_demote_l1: Invalid virtual address %#lx", va));
4285 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
4286 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
4289 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
4290 tmpl1 = kva_alloc(PAGE_SIZE);
4295 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
4296 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
4297 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
4298 " in pmap %p", va, pmap);
4302 l2phys = VM_PAGE_TO_PHYS(ml2);
4303 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
4305 /* Address the range points at */
4306 phys = oldl1 & ~ATTR_MASK;
4307 /* The attributed from the old l1 table to be copied */
4308 newl2 = oldl1 & ATTR_MASK;
4310 /* Create the new entries */
4311 for (i = 0; i < Ln_ENTRIES; i++) {
4312 l2[i] = newl2 | phys;
4315 cpu_dcache_wb_range((vm_offset_t)l2, PAGE_SIZE);
4316 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
4317 ("Invalid l2 page (%lx != %lx)", l2[0],
4318 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
4321 pmap_kenter(tmpl1, PAGE_SIZE,
4322 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY);
4323 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
4326 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
4329 pmap_kremove(tmpl1);
4330 kva_free(tmpl1, PAGE_SIZE);
4337 * Create an L3 table to map all addresses within an L2 mapping.
4340 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
4341 struct rwlock **lockp)
4343 pt_entry_t *l3, newl3, oldl2;
4345 vm_paddr_t l3phys, phys;
4349 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4351 oldl2 = pmap_load(l2);
4352 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
4353 ("pmap_demote_l2: Demoting a non-block entry"));
4354 KASSERT((va & L2_OFFSET) == 0,
4355 ("pmap_demote_l2: Invalid virtual address %#lx", va));
4358 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
4359 tmpl2 = kva_alloc(PAGE_SIZE);
4364 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
4365 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
4366 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4367 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
4369 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
4370 " in pmap %p", va, pmap);
4373 if (va < VM_MAXUSER_ADDRESS)
4374 pmap_resident_count_inc(pmap, 1);
4377 l3phys = VM_PAGE_TO_PHYS(ml3);
4378 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
4380 /* Address the range points at */
4381 phys = oldl2 & ~ATTR_MASK;
4382 /* The attributed from the old l2 table to be copied */
4383 newl3 = (oldl2 & (ATTR_MASK & ~ATTR_DESCR_MASK)) | L3_PAGE;
4386 * If the page table page is new, initialize it.
4388 if (ml3->wire_count == 1) {
4389 for (i = 0; i < Ln_ENTRIES; i++) {
4390 l3[i] = newl3 | phys;
4393 cpu_dcache_wb_range((vm_offset_t)l3, PAGE_SIZE);
4395 KASSERT(l3[0] == ((oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE),
4396 ("Invalid l3 page (%lx != %lx)", l3[0],
4397 (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE));
4400 * Map the temporary page so we don't lose access to the l2 table.
4403 pmap_kenter(tmpl2, PAGE_SIZE,
4404 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY);
4405 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
4409 * The spare PV entries must be reserved prior to demoting the
4410 * mapping, that is, prior to changing the PDE. Otherwise, the state
4411 * of the L2 and the PV lists will be inconsistent, which can result
4412 * in reclaim_pv_chunk() attempting to remove a PV entry from the
4413 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
4414 * PV entry for the 2MB page mapping that is being demoted.
4416 if ((oldl2 & ATTR_SW_MANAGED) != 0)
4417 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
4419 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
4422 * Demote the PV entry.
4424 if ((oldl2 & ATTR_SW_MANAGED) != 0)
4425 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
4427 atomic_add_long(&pmap_l2_demotions, 1);
4428 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
4429 " in pmap %p %lx", va, pmap, l3[0]);
4433 pmap_kremove(tmpl2);
4434 kva_free(tmpl2, PAGE_SIZE);
4442 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
4444 struct rwlock *lock;
4448 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
4455 * perform the pmap work for mincore
4458 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
4460 pd_entry_t *l1p, l1;
4461 pd_entry_t *l2p, l2;
4462 pt_entry_t *l3p, l3;
4473 l1p = pmap_l1(pmap, addr);
4474 if (l1p == NULL) /* No l1 */
4477 l1 = pmap_load(l1p);
4478 if ((l1 & ATTR_DESCR_MASK) == L1_INVAL)
4481 if ((l1 & ATTR_DESCR_MASK) == L1_BLOCK) {
4482 pa = (l1 & ~ATTR_MASK) | (addr & L1_OFFSET);
4483 managed = (l1 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4484 val = MINCORE_SUPER | MINCORE_INCORE;
4485 if (pmap_page_dirty(l1))
4486 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4487 if ((l1 & ATTR_AF) == ATTR_AF)
4488 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4492 l2p = pmap_l1_to_l2(l1p, addr);
4493 if (l2p == NULL) /* No l2 */
4496 l2 = pmap_load(l2p);
4497 if ((l2 & ATTR_DESCR_MASK) == L2_INVAL)
4500 if ((l2 & ATTR_DESCR_MASK) == L2_BLOCK) {
4501 pa = (l2 & ~ATTR_MASK) | (addr & L2_OFFSET);
4502 managed = (l2 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4503 val = MINCORE_SUPER | MINCORE_INCORE;
4504 if (pmap_page_dirty(l2))
4505 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4506 if ((l2 & ATTR_AF) == ATTR_AF)
4507 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4511 l3p = pmap_l2_to_l3(l2p, addr);
4512 if (l3p == NULL) /* No l3 */
4515 l3 = pmap_load(l2p);
4516 if ((l3 & ATTR_DESCR_MASK) == L3_INVAL)
4519 if ((l3 & ATTR_DESCR_MASK) == L3_PAGE) {
4520 pa = (l3 & ~ATTR_MASK) | (addr & L3_OFFSET);
4521 managed = (l3 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4522 val = MINCORE_INCORE;
4523 if (pmap_page_dirty(l3))
4524 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4525 if ((l3 & ATTR_AF) == ATTR_AF)
4526 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4530 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
4531 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
4532 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
4533 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
4536 PA_UNLOCK_COND(*locked_pa);
4543 pmap_activate(struct thread *td)
4548 pmap = vmspace_pmap(td->td_proc->p_vmspace);
4549 td->td_pcb->pcb_l0addr = vtophys(pmap->pm_l0);
4550 __asm __volatile("msr ttbr0_el1, %0" : : "r"(td->td_pcb->pcb_l0addr));
4551 pmap_invalidate_all(pmap);
4556 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
4559 if (va >= VM_MIN_KERNEL_ADDRESS) {
4560 cpu_icache_sync_range(va, sz);
4565 /* Find the length of data in this page to flush */
4566 offset = va & PAGE_MASK;
4567 len = imin(PAGE_SIZE - offset, sz);
4570 /* Extract the physical address & find it in the DMAP */
4571 pa = pmap_extract(pmap, va);
4573 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
4575 /* Move to the next page */
4578 /* Set the length for the next iteration */
4579 len = imin(PAGE_SIZE, sz);
4585 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
4591 switch (ESR_ELx_EXCEPTION(esr)) {
4592 case EXCP_DATA_ABORT_L:
4593 case EXCP_DATA_ABORT:
4596 return (KERN_FAILURE);
4601 switch (esr & ISS_DATA_DFSC_MASK) {
4602 case ISS_DATA_DFSC_TF_L0:
4603 case ISS_DATA_DFSC_TF_L1:
4604 case ISS_DATA_DFSC_TF_L2:
4605 case ISS_DATA_DFSC_TF_L3:
4606 /* Ask the MMU to check the address */
4607 if (pmap == kernel_pmap)
4608 par = arm64_address_translate_s1e1r(far);
4610 par = arm64_address_translate_s1e0r(far);
4613 * If the translation was successful the address was invalid
4614 * due to a break-before-make sequence. We can unlock and
4615 * return success to the trap handler.
4617 if (PAR_SUCCESS(par)) {
4619 return (KERN_SUCCESS);
4628 return (KERN_FAILURE);
4632 * Increase the starting virtual address of the given mapping if a
4633 * different alignment might result in more superpage mappings.
4636 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4637 vm_offset_t *addr, vm_size_t size)
4639 vm_offset_t superpage_offset;
4643 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
4644 offset += ptoa(object->pg_color);
4645 superpage_offset = offset & L2_OFFSET;
4646 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
4647 (*addr & L2_OFFSET) == superpage_offset)
4649 if ((*addr & L2_OFFSET) < superpage_offset)
4650 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
4652 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
4656 * Get the kernel virtual address of a set of physical pages. If there are
4657 * physical addresses not covered by the DMAP perform a transient mapping
4658 * that will be removed when calling pmap_unmap_io_transient.
4660 * \param page The pages the caller wishes to obtain the virtual
4661 * address on the kernel memory map.
4662 * \param vaddr On return contains the kernel virtual memory address
4663 * of the pages passed in the page parameter.
4664 * \param count Number of pages passed in.
4665 * \param can_fault TRUE if the thread using the mapped pages can take
4666 * page faults, FALSE otherwise.
4668 * \returns TRUE if the caller must call pmap_unmap_io_transient when
4669 * finished or FALSE otherwise.
4673 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
4674 boolean_t can_fault)
4677 boolean_t needs_mapping;
4681 * Allocate any KVA space that we need, this is done in a separate
4682 * loop to prevent calling vmem_alloc while pinned.
4684 needs_mapping = FALSE;
4685 for (i = 0; i < count; i++) {
4686 paddr = VM_PAGE_TO_PHYS(page[i]);
4687 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
4688 error = vmem_alloc(kernel_arena, PAGE_SIZE,
4689 M_BESTFIT | M_WAITOK, &vaddr[i]);
4690 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
4691 needs_mapping = TRUE;
4693 vaddr[i] = PHYS_TO_DMAP(paddr);
4697 /* Exit early if everything is covered by the DMAP */
4703 for (i = 0; i < count; i++) {
4704 paddr = VM_PAGE_TO_PHYS(page[i]);
4705 if (!PHYS_IN_DMAP(paddr)) {
4707 "pmap_map_io_transient: TODO: Map out of DMAP data");
4711 return (needs_mapping);
4715 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
4716 boolean_t can_fault)
4723 for (i = 0; i < count; i++) {
4724 paddr = VM_PAGE_TO_PHYS(page[i]);
4725 if (!PHYS_IN_DMAP(paddr)) {
4726 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");