2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/msgbuf.h>
120 #include <sys/mutex.h>
121 #include <sys/proc.h>
122 #include <sys/rwlock.h>
124 #include <sys/vmem.h>
125 #include <sys/vmmeter.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/_unrhdr.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/vm_pager.h>
140 #include <vm/vm_phys.h>
141 #include <vm/vm_radix.h>
142 #include <vm/vm_reserv.h>
145 #include <machine/machdep.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
149 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
150 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
151 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
152 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
154 #define NUL0E L0_ENTRIES
155 #define NUL1E (NUL0E * NL1PG)
156 #define NUL2E (NUL1E * NL2PG)
158 #if !defined(DIAGNOSTIC)
159 #ifdef __GNUC_GNU_INLINE__
160 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
162 #define PMAP_INLINE extern inline
169 * These are configured by the mair_el1 register. This is set up in locore.S
171 #define DEVICE_MEMORY 0
172 #define UNCACHED_MEMORY 1
173 #define CACHED_MEMORY 2
177 #define PV_STAT(x) do { x ; } while (0)
179 #define PV_STAT(x) do { } while (0)
182 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
183 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
185 #define NPV_LIST_LOCKS MAXCPU
187 #define PHYS_TO_PV_LIST_LOCK(pa) \
188 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
190 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
191 struct rwlock **_lockp = (lockp); \
192 struct rwlock *_new_lock; \
194 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
195 if (_new_lock != *_lockp) { \
196 if (*_lockp != NULL) \
197 rw_wunlock(*_lockp); \
198 *_lockp = _new_lock; \
203 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
204 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
206 #define RELEASE_PV_LIST_LOCK(lockp) do { \
207 struct rwlock **_lockp = (lockp); \
209 if (*_lockp != NULL) { \
210 rw_wunlock(*_lockp); \
215 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
216 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
218 struct pmap kernel_pmap_store;
220 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
221 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
222 vm_offset_t kernel_vm_end = 0;
225 * Data for the pv entry allocation mechanism.
226 * Updates to pv_invl_gen are protected by the pv_list_locks[]
227 * elements, but reads are not.
229 static struct md_page *pv_table;
230 static struct md_page pv_dummy;
232 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
233 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
234 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
236 /* This code assumes all L1 DMAP entries will be used */
237 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
238 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
240 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
241 extern pt_entry_t pagetable_dmap[];
243 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
245 static int superpages_enabled = 1;
246 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
247 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
248 "Are large page mappings enabled?");
251 * Data for the pv entry allocation mechanism
253 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
254 static struct mtx pv_chunks_mutex;
255 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
257 static void free_pv_chunk(struct pv_chunk *pc);
258 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
259 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
260 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
261 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
262 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
265 static int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode);
266 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
267 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
268 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
269 vm_offset_t va, struct rwlock **lockp);
270 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
271 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
272 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
273 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
274 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
275 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
276 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
277 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
278 vm_page_t m, struct rwlock **lockp);
280 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
281 struct rwlock **lockp);
283 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
284 struct spglist *free);
285 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
286 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
289 * These load the old table data and store the new value.
290 * They need to be atomic as the System MMU may write to the table at
291 * the same time as the CPU.
293 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
294 #define pmap_set(table, mask) atomic_set_64(table, mask)
295 #define pmap_load_clear(table) atomic_swap_64(table, 0)
296 #define pmap_load(table) (*table)
298 /********************/
299 /* Inline functions */
300 /********************/
303 pagecopy(void *s, void *d)
306 memcpy(d, s, PAGE_SIZE);
309 static __inline pd_entry_t *
310 pmap_l0(pmap_t pmap, vm_offset_t va)
313 return (&pmap->pm_l0[pmap_l0_index(va)]);
316 static __inline pd_entry_t *
317 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
321 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
322 return (&l1[pmap_l1_index(va)]);
325 static __inline pd_entry_t *
326 pmap_l1(pmap_t pmap, vm_offset_t va)
330 l0 = pmap_l0(pmap, va);
331 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
334 return (pmap_l0_to_l1(l0, va));
337 static __inline pd_entry_t *
338 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
342 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
343 return (&l2[pmap_l2_index(va)]);
346 static __inline pd_entry_t *
347 pmap_l2(pmap_t pmap, vm_offset_t va)
351 l1 = pmap_l1(pmap, va);
352 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
355 return (pmap_l1_to_l2(l1, va));
358 static __inline pt_entry_t *
359 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
363 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
364 return (&l3[pmap_l3_index(va)]);
368 * Returns the lowest valid pde for a given virtual address.
369 * The next level may or may not point to a valid page or block.
371 static __inline pd_entry_t *
372 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
374 pd_entry_t *l0, *l1, *l2, desc;
376 l0 = pmap_l0(pmap, va);
377 desc = pmap_load(l0) & ATTR_DESCR_MASK;
378 if (desc != L0_TABLE) {
383 l1 = pmap_l0_to_l1(l0, va);
384 desc = pmap_load(l1) & ATTR_DESCR_MASK;
385 if (desc != L1_TABLE) {
390 l2 = pmap_l1_to_l2(l1, va);
391 desc = pmap_load(l2) & ATTR_DESCR_MASK;
392 if (desc != L2_TABLE) {
402 * Returns the lowest valid pte block or table entry for a given virtual
403 * address. If there are no valid entries return NULL and set the level to
404 * the first invalid level.
406 static __inline pt_entry_t *
407 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
409 pd_entry_t *l1, *l2, desc;
412 l1 = pmap_l1(pmap, va);
417 desc = pmap_load(l1) & ATTR_DESCR_MASK;
418 if (desc == L1_BLOCK) {
423 if (desc != L1_TABLE) {
428 l2 = pmap_l1_to_l2(l1, va);
429 desc = pmap_load(l2) & ATTR_DESCR_MASK;
430 if (desc == L2_BLOCK) {
435 if (desc != L2_TABLE) {
441 l3 = pmap_l2_to_l3(l2, va);
442 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
449 pmap_superpages_enabled(void)
452 return (superpages_enabled != 0);
456 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
457 pd_entry_t **l2, pt_entry_t **l3)
459 pd_entry_t *l0p, *l1p, *l2p;
461 if (pmap->pm_l0 == NULL)
464 l0p = pmap_l0(pmap, va);
467 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
470 l1p = pmap_l0_to_l1(l0p, va);
473 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
479 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
482 l2p = pmap_l1_to_l2(l1p, va);
485 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
490 *l3 = pmap_l2_to_l3(l2p, va);
496 pmap_l3_valid(pt_entry_t l3)
499 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
503 CTASSERT(L1_BLOCK == L2_BLOCK);
506 * Checks if the page is dirty. We currently lack proper tracking of this on
507 * arm64 so for now assume is a page mapped as rw was accessed it is.
510 pmap_page_dirty(pt_entry_t pte)
513 return ((pte & (ATTR_AF | ATTR_AP_RW_BIT)) ==
514 (ATTR_AF | ATTR_AP(ATTR_AP_RW)));
518 pmap_resident_count_inc(pmap_t pmap, int count)
521 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
522 pmap->pm_stats.resident_count += count;
526 pmap_resident_count_dec(pmap_t pmap, int count)
529 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
530 KASSERT(pmap->pm_stats.resident_count >= count,
531 ("pmap %p resident count underflow %ld %d", pmap,
532 pmap->pm_stats.resident_count, count));
533 pmap->pm_stats.resident_count -= count;
537 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
543 l1 = (pd_entry_t *)l1pt;
544 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
546 /* Check locore has used a table L1 map */
547 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
548 ("Invalid bootstrap L1 table"));
549 /* Find the address of the L2 table */
550 l2 = (pt_entry_t *)init_pt_va;
551 *l2_slot = pmap_l2_index(va);
557 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
559 u_int l1_slot, l2_slot;
562 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
564 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
568 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa, vm_paddr_t max_pa)
574 pa = dmap_phys_base = min_pa & ~L1_OFFSET;
575 va = DMAP_MIN_ADDRESS;
576 for (; va < DMAP_MAX_ADDRESS && pa < max_pa;
577 pa += L1_SIZE, va += L1_SIZE, l1_slot++) {
578 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
580 pmap_load_store(&pagetable_dmap[l1_slot],
581 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
582 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
585 /* Set the upper limit of the DMAP region */
593 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
600 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
602 l1 = (pd_entry_t *)l1pt;
603 l1_slot = pmap_l1_index(va);
606 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
607 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
609 pa = pmap_early_vtophys(l1pt, l2pt);
610 pmap_load_store(&l1[l1_slot],
611 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
615 /* Clean the L2 page table */
616 memset((void *)l2_start, 0, l2pt - l2_start);
622 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
629 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
631 l2 = pmap_l2(kernel_pmap, va);
632 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
633 l2_slot = pmap_l2_index(va);
636 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
637 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
639 pa = pmap_early_vtophys(l1pt, l3pt);
640 pmap_load_store(&l2[l2_slot],
641 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
645 /* Clean the L2 page table */
646 memset((void *)l3_start, 0, l3pt - l3_start);
652 * Bootstrap the system enough to run with virtual memory.
655 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
658 u_int l1_slot, l2_slot, avail_slot, map_slot, used_map_slot;
661 vm_offset_t va, freemempos;
662 vm_offset_t dpcpu, msgbufpv;
663 vm_paddr_t pa, max_pa, min_pa;
666 kern_delta = KERNBASE - kernstart;
669 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
670 printf("%lx\n", l1pt);
671 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
673 /* Set this early so we can use the pagetable walking functions */
674 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
675 PMAP_LOCK_INIT(kernel_pmap);
677 /* Assume the address we were loaded to is a valid physical address */
678 min_pa = max_pa = KERNBASE - kern_delta;
681 * Find the minimum physical address. physmap is sorted,
682 * but may contain empty ranges.
684 for (i = 0; i < (physmap_idx * 2); i += 2) {
685 if (physmap[i] == physmap[i + 1])
687 if (physmap[i] <= min_pa)
689 if (physmap[i + 1] > max_pa)
690 max_pa = physmap[i + 1];
693 /* Create a direct map region early so we can use it for pa -> va */
694 pmap_bootstrap_dmap(l1pt, min_pa, max_pa);
697 pa = KERNBASE - kern_delta;
700 * Start to initialise phys_avail by copying from physmap
701 * up to the physical address KERNBASE points at.
703 map_slot = avail_slot = 0;
704 for (; map_slot < (physmap_idx * 2) &&
705 avail_slot < (PHYS_AVAIL_SIZE - 2); map_slot += 2) {
706 if (physmap[map_slot] == physmap[map_slot + 1])
709 if (physmap[map_slot] <= pa &&
710 physmap[map_slot + 1] > pa)
713 phys_avail[avail_slot] = physmap[map_slot];
714 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
715 physmem += (phys_avail[avail_slot + 1] -
716 phys_avail[avail_slot]) >> PAGE_SHIFT;
720 /* Add the memory before the kernel */
721 if (physmap[avail_slot] < pa && avail_slot < (PHYS_AVAIL_SIZE - 2)) {
722 phys_avail[avail_slot] = physmap[map_slot];
723 phys_avail[avail_slot + 1] = pa;
724 physmem += (phys_avail[avail_slot + 1] -
725 phys_avail[avail_slot]) >> PAGE_SHIFT;
728 used_map_slot = map_slot;
731 * Read the page table to find out what is already mapped.
732 * This assumes we have mapped a block of memory from KERNBASE
733 * using a single L1 entry.
735 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
737 /* Sanity check the index, KERNBASE should be the first VA */
738 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
740 /* Find how many pages we have mapped */
741 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
742 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
745 /* Check locore used L2 blocks */
746 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
747 ("Invalid bootstrap L2 table"));
748 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
749 ("Incorrect PA in L2 table"));
755 va = roundup2(va, L1_SIZE);
757 freemempos = KERNBASE + kernlen;
758 freemempos = roundup2(freemempos, PAGE_SIZE);
759 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
760 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
761 /* And the l3 tables for the early devmap */
762 freemempos = pmap_bootstrap_l3(l1pt,
763 VM_MAX_KERNEL_ADDRESS - L2_SIZE, freemempos);
767 #define alloc_pages(var, np) \
768 (var) = freemempos; \
769 freemempos += (np * PAGE_SIZE); \
770 memset((char *)(var), 0, ((np) * PAGE_SIZE));
772 /* Allocate dynamic per-cpu area. */
773 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
774 dpcpu_init((void *)dpcpu, 0);
776 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
777 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
778 msgbufp = (void *)msgbufpv;
780 virtual_avail = roundup2(freemempos, L1_SIZE);
781 virtual_end = VM_MAX_KERNEL_ADDRESS - L2_SIZE;
782 kernel_vm_end = virtual_avail;
784 pa = pmap_early_vtophys(l1pt, freemempos);
786 /* Finish initialising physmap */
787 map_slot = used_map_slot;
788 for (; avail_slot < (PHYS_AVAIL_SIZE - 2) &&
789 map_slot < (physmap_idx * 2); map_slot += 2) {
790 if (physmap[map_slot] == physmap[map_slot + 1])
793 /* Have we used the current range? */
794 if (physmap[map_slot + 1] <= pa)
797 /* Do we need to split the entry? */
798 if (physmap[map_slot] < pa) {
799 phys_avail[avail_slot] = pa;
800 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
802 phys_avail[avail_slot] = physmap[map_slot];
803 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
805 physmem += (phys_avail[avail_slot + 1] -
806 phys_avail[avail_slot]) >> PAGE_SHIFT;
810 phys_avail[avail_slot] = 0;
811 phys_avail[avail_slot + 1] = 0;
814 * Maxmem isn't the "maximum memory", it's one larger than the
815 * highest page of the physical address space. It should be
816 * called something like "Maxphyspage".
818 Maxmem = atop(phys_avail[avail_slot - 1]);
824 * Initialize a vm_page's machine-dependent fields.
827 pmap_page_init(vm_page_t m)
830 TAILQ_INIT(&m->md.pv_list);
831 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
835 * Initialize the pmap module.
836 * Called by vm_init, to initialize any structures that the pmap
837 * system needs to map virtual memory.
846 * Are large page mappings enabled?
848 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
851 * Initialize the pv chunk list mutex.
853 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
856 * Initialize the pool of pv list locks.
858 for (i = 0; i < NPV_LIST_LOCKS; i++)
859 rw_init(&pv_list_locks[i], "pmap pv list");
862 * Calculate the size of the pv head table for superpages.
864 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
867 * Allocate memory for the pv head table for superpages.
869 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
871 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
873 for (i = 0; i < pv_npg; i++)
874 TAILQ_INIT(&pv_table[i].pv_list);
875 TAILQ_INIT(&pv_dummy.pv_list);
878 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
879 "2MB page mapping counters");
881 static u_long pmap_l2_demotions;
882 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
883 &pmap_l2_demotions, 0, "2MB page demotions");
885 static u_long pmap_l2_p_failures;
886 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
887 &pmap_l2_p_failures, 0, "2MB page promotion failures");
889 static u_long pmap_l2_promotions;
890 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
891 &pmap_l2_promotions, 0, "2MB page promotions");
894 * Invalidate a single TLB entry.
897 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
903 "tlbi vaae1is, %0 \n"
906 : : "r"(va >> PAGE_SHIFT));
911 pmap_invalidate_range_nopin(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
916 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
918 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
926 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
930 pmap_invalidate_range_nopin(pmap, sva, eva);
935 pmap_invalidate_all(pmap_t pmap)
948 * Routine: pmap_extract
950 * Extract the physical page address associated
951 * with the given map/virtual_address pair.
954 pmap_extract(pmap_t pmap, vm_offset_t va)
956 pt_entry_t *pte, tpte;
963 * Find the block or page map for this virtual address. pmap_pte
964 * will return either a valid block/page entry, or NULL.
966 pte = pmap_pte(pmap, va, &lvl);
968 tpte = pmap_load(pte);
969 pa = tpte & ~ATTR_MASK;
972 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
973 ("pmap_extract: Invalid L1 pte found: %lx",
974 tpte & ATTR_DESCR_MASK));
975 pa |= (va & L1_OFFSET);
978 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
979 ("pmap_extract: Invalid L2 pte found: %lx",
980 tpte & ATTR_DESCR_MASK));
981 pa |= (va & L2_OFFSET);
984 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
985 ("pmap_extract: Invalid L3 pte found: %lx",
986 tpte & ATTR_DESCR_MASK));
987 pa |= (va & L3_OFFSET);
996 * Routine: pmap_extract_and_hold
998 * Atomically extract and hold the physical page
999 * with the given pmap and virtual address pair
1000 * if that mapping permits the given protection.
1003 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1005 pt_entry_t *pte, tpte;
1015 pte = pmap_pte(pmap, va, &lvl);
1017 tpte = pmap_load(pte);
1019 KASSERT(lvl > 0 && lvl <= 3,
1020 ("pmap_extract_and_hold: Invalid level %d", lvl));
1021 CTASSERT(L1_BLOCK == L2_BLOCK);
1022 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1023 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1024 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1025 tpte & ATTR_DESCR_MASK));
1026 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1027 ((prot & VM_PROT_WRITE) == 0)) {
1030 off = va & L1_OFFSET;
1033 off = va & L2_OFFSET;
1039 if (vm_page_pa_tryrelock(pmap,
1040 (tpte & ~ATTR_MASK) | off, &pa))
1042 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1052 pmap_kextract(vm_offset_t va)
1054 pt_entry_t *pte, tpte;
1058 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1059 pa = DMAP_TO_PHYS(va);
1062 pte = pmap_pte(kernel_pmap, va, &lvl);
1064 tpte = pmap_load(pte);
1065 pa = tpte & ~ATTR_MASK;
1068 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1069 ("pmap_kextract: Invalid L1 pte found: %lx",
1070 tpte & ATTR_DESCR_MASK));
1071 pa |= (va & L1_OFFSET);
1074 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1075 ("pmap_kextract: Invalid L2 pte found: %lx",
1076 tpte & ATTR_DESCR_MASK));
1077 pa |= (va & L2_OFFSET);
1080 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1081 ("pmap_kextract: Invalid L3 pte found: %lx",
1082 tpte & ATTR_DESCR_MASK));
1083 pa |= (va & L3_OFFSET);
1091 /***************************************************
1092 * Low level mapping routines.....
1093 ***************************************************/
1096 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1099 pt_entry_t *pte, attr;
1103 KASSERT((pa & L3_OFFSET) == 0,
1104 ("pmap_kenter: Invalid physical address"));
1105 KASSERT((sva & L3_OFFSET) == 0,
1106 ("pmap_kenter: Invalid virtual address"));
1107 KASSERT((size & PAGE_MASK) == 0,
1108 ("pmap_kenter: Mapping is not page-sized"));
1110 attr = ATTR_DEFAULT | ATTR_IDX(mode) | L3_PAGE;
1111 if (mode == DEVICE_MEMORY)
1116 pde = pmap_pde(kernel_pmap, va, &lvl);
1117 KASSERT(pde != NULL,
1118 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1119 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1121 pte = pmap_l2_to_l3(pde, va);
1122 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1128 pmap_invalidate_range(kernel_pmap, sva, va);
1132 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1135 pmap_kenter(sva, size, pa, DEVICE_MEMORY);
1139 * Remove a page from the kernel pagetables.
1142 pmap_kremove(vm_offset_t va)
1147 pte = pmap_pte(kernel_pmap, va, &lvl);
1148 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1149 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1151 pmap_load_clear(pte);
1152 pmap_invalidate_page(kernel_pmap, va);
1156 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1162 KASSERT((sva & L3_OFFSET) == 0,
1163 ("pmap_kremove_device: Invalid virtual address"));
1164 KASSERT((size & PAGE_MASK) == 0,
1165 ("pmap_kremove_device: Mapping is not page-sized"));
1169 pte = pmap_pte(kernel_pmap, va, &lvl);
1170 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1172 ("Invalid device pagetable level: %d != 3", lvl));
1173 pmap_load_clear(pte);
1178 pmap_invalidate_range(kernel_pmap, sva, va);
1182 * Used to map a range of physical addresses into kernel
1183 * virtual address space.
1185 * The value passed in '*virt' is a suggested virtual address for
1186 * the mapping. Architectures which can support a direct-mapped
1187 * physical to virtual region can return the appropriate address
1188 * within that region, leaving '*virt' unchanged. Other
1189 * architectures should map the pages starting at '*virt' and
1190 * update '*virt' with the first usable address after the mapped
1194 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1196 return PHYS_TO_DMAP(start);
1201 * Add a list of wired pages to the kva
1202 * this routine is only used for temporary
1203 * kernel mappings that do not need to have
1204 * page modification or references recorded.
1205 * Note that old mappings are simply written
1206 * over. The page *must* be wired.
1207 * Note: SMP coherent. Uses a ranged shootdown IPI.
1210 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1213 pt_entry_t *pte, pa;
1219 for (i = 0; i < count; i++) {
1220 pde = pmap_pde(kernel_pmap, va, &lvl);
1221 KASSERT(pde != NULL,
1222 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1224 ("pmap_qenter: Invalid level %d", lvl));
1227 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1228 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1229 if (m->md.pv_memattr == DEVICE_MEMORY)
1231 pte = pmap_l2_to_l3(pde, va);
1232 pmap_load_store(pte, pa);
1236 pmap_invalidate_range(kernel_pmap, sva, va);
1240 * This routine tears out page mappings from the
1241 * kernel -- it is meant only for temporary mappings.
1244 pmap_qremove(vm_offset_t sva, int count)
1250 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1253 while (count-- > 0) {
1254 pte = pmap_pte(kernel_pmap, va, &lvl);
1256 ("Invalid device pagetable level: %d != 3", lvl));
1258 pmap_load_clear(pte);
1263 pmap_invalidate_range(kernel_pmap, sva, va);
1266 /***************************************************
1267 * Page table page management routines.....
1268 ***************************************************/
1269 static __inline void
1270 pmap_free_zero_pages(struct spglist *free)
1274 while ((m = SLIST_FIRST(free)) != NULL) {
1275 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1276 /* Preserve the page's PG_ZERO setting. */
1277 vm_page_free_toq(m);
1282 * Schedule the specified unused page table page to be freed. Specifically,
1283 * add the page to the specified list of pages that will be released to the
1284 * physical memory manager after the TLB has been updated.
1286 static __inline void
1287 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1288 boolean_t set_PG_ZERO)
1292 m->flags |= PG_ZERO;
1294 m->flags &= ~PG_ZERO;
1295 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1299 * Decrements a page table page's wire count, which is used to record the
1300 * number of valid page table entries within the page. If the wire count
1301 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1302 * page table page was unmapped and FALSE otherwise.
1304 static inline boolean_t
1305 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1309 if (m->wire_count == 0) {
1310 _pmap_unwire_l3(pmap, va, m, free);
1317 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1320 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1322 * unmap the page table page
1324 if (m->pindex >= (NUL2E + NUL1E)) {
1328 l0 = pmap_l0(pmap, va);
1329 pmap_load_clear(l0);
1330 } else if (m->pindex >= NUL2E) {
1334 l1 = pmap_l1(pmap, va);
1335 pmap_load_clear(l1);
1340 l2 = pmap_l2(pmap, va);
1341 pmap_load_clear(l2);
1343 pmap_resident_count_dec(pmap, 1);
1344 if (m->pindex < NUL2E) {
1345 /* We just released an l3, unhold the matching l2 */
1346 pd_entry_t *l1, tl1;
1349 l1 = pmap_l1(pmap, va);
1350 tl1 = pmap_load(l1);
1351 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1352 pmap_unwire_l3(pmap, va, l2pg, free);
1353 } else if (m->pindex < (NUL2E + NUL1E)) {
1354 /* We just released an l2, unhold the matching l1 */
1355 pd_entry_t *l0, tl0;
1358 l0 = pmap_l0(pmap, va);
1359 tl0 = pmap_load(l0);
1360 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1361 pmap_unwire_l3(pmap, va, l1pg, free);
1363 pmap_invalidate_page(pmap, va);
1368 * Put page on a list so that it is released after
1369 * *ALL* TLB shootdown is done
1371 pmap_add_delayed_free_list(m, free, TRUE);
1375 * After removing a page table entry, this routine is used to
1376 * conditionally free the page, and manage the hold/wire counts.
1379 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1380 struct spglist *free)
1384 if (va >= VM_MAXUSER_ADDRESS)
1386 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1387 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1388 return (pmap_unwire_l3(pmap, va, mpte, free));
1392 pmap_pinit0(pmap_t pmap)
1395 PMAP_LOCK_INIT(pmap);
1396 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1397 pmap->pm_l0 = kernel_pmap->pm_l0;
1398 pmap->pm_root.rt_root = 0;
1402 pmap_pinit(pmap_t pmap)
1408 * allocate the l0 page
1410 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1411 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1414 l0phys = VM_PAGE_TO_PHYS(l0pt);
1415 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1417 if ((l0pt->flags & PG_ZERO) == 0)
1418 pagezero(pmap->pm_l0);
1420 pmap->pm_root.rt_root = 0;
1421 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1427 * This routine is called if the desired page table page does not exist.
1429 * If page table page allocation fails, this routine may sleep before
1430 * returning NULL. It sleeps only if a lock pointer was given.
1432 * Note: If a page allocation fails at page table level two or three,
1433 * one or two pages may be held during the wait, only to be released
1434 * afterwards. This conservative approach is easily argued to avoid
1438 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1440 vm_page_t m, l1pg, l2pg;
1442 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1445 * Allocate a page table page.
1447 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1448 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1449 if (lockp != NULL) {
1450 RELEASE_PV_LIST_LOCK(lockp);
1457 * Indicate the need to retry. While waiting, the page table
1458 * page may have been allocated.
1462 if ((m->flags & PG_ZERO) == 0)
1466 * Map the pagetable page into the process address space, if
1467 * it isn't already there.
1470 if (ptepindex >= (NUL2E + NUL1E)) {
1472 vm_pindex_t l0index;
1474 l0index = ptepindex - (NUL2E + NUL1E);
1475 l0 = &pmap->pm_l0[l0index];
1476 pmap_load_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1477 } else if (ptepindex >= NUL2E) {
1478 vm_pindex_t l0index, l1index;
1479 pd_entry_t *l0, *l1;
1482 l1index = ptepindex - NUL2E;
1483 l0index = l1index >> L0_ENTRIES_SHIFT;
1485 l0 = &pmap->pm_l0[l0index];
1486 tl0 = pmap_load(l0);
1488 /* recurse for allocating page dir */
1489 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1491 vm_page_unwire_noq(m);
1492 vm_page_free_zero(m);
1496 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1500 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1501 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1502 pmap_load_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1504 vm_pindex_t l0index, l1index;
1505 pd_entry_t *l0, *l1, *l2;
1506 pd_entry_t tl0, tl1;
1508 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1509 l0index = l1index >> L0_ENTRIES_SHIFT;
1511 l0 = &pmap->pm_l0[l0index];
1512 tl0 = pmap_load(l0);
1514 /* recurse for allocating page dir */
1515 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1517 vm_page_unwire_noq(m);
1518 vm_page_free_zero(m);
1521 tl0 = pmap_load(l0);
1522 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1523 l1 = &l1[l1index & Ln_ADDR_MASK];
1525 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1526 l1 = &l1[l1index & Ln_ADDR_MASK];
1527 tl1 = pmap_load(l1);
1529 /* recurse for allocating page dir */
1530 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1532 vm_page_unwire_noq(m);
1533 vm_page_free_zero(m);
1537 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1542 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1543 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1544 pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1547 pmap_resident_count_inc(pmap, 1);
1553 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1555 vm_pindex_t ptepindex;
1556 pd_entry_t *pde, tpde;
1564 * Calculate pagetable page index
1566 ptepindex = pmap_l2_pindex(va);
1569 * Get the page directory entry
1571 pde = pmap_pde(pmap, va, &lvl);
1574 * If the page table page is mapped, we just increment the hold count,
1575 * and activate it. If we get a level 2 pde it will point to a level 3
1583 pte = pmap_l0_to_l1(pde, va);
1584 KASSERT(pmap_load(pte) == 0,
1585 ("pmap_alloc_l3: TODO: l0 superpages"));
1590 pte = pmap_l1_to_l2(pde, va);
1591 KASSERT(pmap_load(pte) == 0,
1592 ("pmap_alloc_l3: TODO: l1 superpages"));
1596 tpde = pmap_load(pde);
1598 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1604 panic("pmap_alloc_l3: Invalid level %d", lvl);
1608 * Here if the pte page isn't mapped, or if it has been deallocated.
1610 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1611 if (m == NULL && lockp != NULL)
1618 /***************************************************
1619 * Pmap allocation/deallocation routines.
1620 ***************************************************/
1623 * Release any resources held by the given physical map.
1624 * Called when a pmap initialized by pmap_pinit is being released.
1625 * Should only be called if the map contains no valid mappings.
1628 pmap_release(pmap_t pmap)
1632 KASSERT(pmap->pm_stats.resident_count == 0,
1633 ("pmap_release: pmap resident count %ld != 0",
1634 pmap->pm_stats.resident_count));
1635 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1636 ("pmap_release: pmap has reserved page table page(s)"));
1638 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1640 vm_page_unwire_noq(m);
1641 vm_page_free_zero(m);
1645 kvm_size(SYSCTL_HANDLER_ARGS)
1647 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1649 return sysctl_handle_long(oidp, &ksize, 0, req);
1651 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1652 0, 0, kvm_size, "LU", "Size of KVM");
1655 kvm_free(SYSCTL_HANDLER_ARGS)
1657 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1659 return sysctl_handle_long(oidp, &kfree, 0, req);
1661 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1662 0, 0, kvm_free, "LU", "Amount of KVM free");
1665 * grow the number of kernel page table entries, if needed
1668 pmap_growkernel(vm_offset_t addr)
1672 pd_entry_t *l0, *l1, *l2;
1674 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1676 addr = roundup2(addr, L2_SIZE);
1677 if (addr - 1 >= kernel_map->max_offset)
1678 addr = kernel_map->max_offset;
1679 while (kernel_vm_end < addr) {
1680 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1681 KASSERT(pmap_load(l0) != 0,
1682 ("pmap_growkernel: No level 0 kernel entry"));
1684 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1685 if (pmap_load(l1) == 0) {
1686 /* We need a new PDP entry */
1687 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1688 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1689 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1691 panic("pmap_growkernel: no memory to grow kernel");
1692 if ((nkpg->flags & PG_ZERO) == 0)
1693 pmap_zero_page(nkpg);
1694 paddr = VM_PAGE_TO_PHYS(nkpg);
1695 pmap_load_store(l1, paddr | L1_TABLE);
1696 continue; /* try again */
1698 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1699 if ((pmap_load(l2) & ATTR_AF) != 0) {
1700 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1701 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1702 kernel_vm_end = kernel_map->max_offset;
1708 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1709 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1712 panic("pmap_growkernel: no memory to grow kernel");
1713 if ((nkpg->flags & PG_ZERO) == 0)
1714 pmap_zero_page(nkpg);
1715 paddr = VM_PAGE_TO_PHYS(nkpg);
1716 pmap_load_store(l2, paddr | L2_TABLE);
1717 pmap_invalidate_page(kernel_pmap, kernel_vm_end);
1719 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1720 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1721 kernel_vm_end = kernel_map->max_offset;
1728 /***************************************************
1729 * page management routines.
1730 ***************************************************/
1732 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1733 CTASSERT(_NPCM == 3);
1734 CTASSERT(_NPCPV == 168);
1736 static __inline struct pv_chunk *
1737 pv_to_chunk(pv_entry_t pv)
1740 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1743 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1745 #define PC_FREE0 0xfffffffffffffffful
1746 #define PC_FREE1 0xfffffffffffffffful
1747 #define PC_FREE2 0x000000fffffffffful
1749 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1753 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1755 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1756 "Current number of pv entry chunks");
1757 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1758 "Current number of pv entry chunks allocated");
1759 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1760 "Current number of pv entry chunks frees");
1761 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1762 "Number of times tried to get a chunk page but failed.");
1764 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1765 static int pv_entry_spare;
1767 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1768 "Current number of pv entry frees");
1769 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1770 "Current number of pv entry allocs");
1771 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1772 "Current number of pv entries");
1773 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1774 "Current number of spare pv entries");
1779 * We are in a serious low memory condition. Resort to
1780 * drastic measures to free some pages so we can allocate
1781 * another pv entry chunk.
1783 * Returns NULL if PV entries were reclaimed from the specified pmap.
1785 * We do not, however, unmap 2mpages because subsequent accesses will
1786 * allocate per-page pv entries until repromotion occurs, thereby
1787 * exacerbating the shortage of free pv entries.
1790 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1792 struct pch new_tail;
1793 struct pv_chunk *pc;
1794 struct md_page *pvh;
1797 pt_entry_t *pte, tpte;
1801 struct spglist free;
1803 int bit, field, freed, lvl;
1805 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1806 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
1810 TAILQ_INIT(&new_tail);
1811 mtx_lock(&pv_chunks_mutex);
1812 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) {
1813 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1814 mtx_unlock(&pv_chunks_mutex);
1815 if (pmap != pc->pc_pmap) {
1816 if (pmap != NULL && pmap != locked_pmap)
1819 /* Avoid deadlock and lock recursion. */
1820 if (pmap > locked_pmap) {
1821 RELEASE_PV_LIST_LOCK(lockp);
1823 } else if (pmap != locked_pmap &&
1824 !PMAP_TRYLOCK(pmap)) {
1826 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1827 mtx_lock(&pv_chunks_mutex);
1833 * Destroy every non-wired, 4 KB page mapping in the chunk.
1836 for (field = 0; field < _NPCM; field++) {
1837 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1838 inuse != 0; inuse &= ~(1UL << bit)) {
1839 bit = ffsl(inuse) - 1;
1840 pv = &pc->pc_pventry[field * 64 + bit];
1842 pde = pmap_pde(pmap, va, &lvl);
1845 pte = pmap_l2_to_l3(pde, va);
1846 tpte = pmap_load(pte);
1847 if ((tpte & ATTR_SW_WIRED) != 0)
1849 tpte = pmap_load_clear(pte);
1850 pmap_invalidate_page(pmap, va);
1851 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
1852 if (pmap_page_dirty(tpte))
1854 if ((tpte & ATTR_AF) != 0)
1855 vm_page_aflag_set(m, PGA_REFERENCED);
1856 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1857 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
1859 if (TAILQ_EMPTY(&m->md.pv_list) &&
1860 (m->flags & PG_FICTITIOUS) == 0) {
1861 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
1862 if (TAILQ_EMPTY(&pvh->pv_list)) {
1863 vm_page_aflag_clear(m,
1867 pc->pc_map[field] |= 1UL << bit;
1868 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
1873 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1874 mtx_lock(&pv_chunks_mutex);
1877 /* Every freed mapping is for a 4 KB page. */
1878 pmap_resident_count_dec(pmap, freed);
1879 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
1880 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
1881 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
1882 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1883 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
1884 pc->pc_map[2] == PC_FREE2) {
1885 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1886 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1887 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1888 /* Entire chunk is free; return it. */
1889 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1890 dump_drop_page(m_pc->phys_addr);
1891 mtx_lock(&pv_chunks_mutex);
1894 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1895 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1896 mtx_lock(&pv_chunks_mutex);
1897 /* One freed pv entry in locked_pmap is sufficient. */
1898 if (pmap == locked_pmap)
1901 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
1902 mtx_unlock(&pv_chunks_mutex);
1903 if (pmap != NULL && pmap != locked_pmap)
1905 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
1906 m_pc = SLIST_FIRST(&free);
1907 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
1908 /* Recycle a freed page table page. */
1909 m_pc->wire_count = 1;
1912 pmap_free_zero_pages(&free);
1917 * free the pv_entry back to the free list
1920 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1922 struct pv_chunk *pc;
1923 int idx, field, bit;
1925 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1926 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
1927 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
1928 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
1929 pc = pv_to_chunk(pv);
1930 idx = pv - &pc->pc_pventry[0];
1933 pc->pc_map[field] |= 1ul << bit;
1934 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
1935 pc->pc_map[2] != PC_FREE2) {
1936 /* 98% of the time, pc is already at the head of the list. */
1937 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
1938 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1939 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1943 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1948 free_pv_chunk(struct pv_chunk *pc)
1952 mtx_lock(&pv_chunks_mutex);
1953 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1954 mtx_unlock(&pv_chunks_mutex);
1955 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1956 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1957 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1958 /* entire chunk is free, return it */
1959 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1960 dump_drop_page(m->phys_addr);
1961 vm_page_unwire_noq(m);
1966 * Returns a new PV entry, allocating a new PV chunk from the system when
1967 * needed. If this PV chunk allocation fails and a PV list lock pointer was
1968 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
1971 * The given PV list lock may be released.
1974 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
1978 struct pv_chunk *pc;
1981 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1982 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
1984 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1986 for (field = 0; field < _NPCM; field++) {
1987 if (pc->pc_map[field]) {
1988 bit = ffsl(pc->pc_map[field]) - 1;
1992 if (field < _NPCM) {
1993 pv = &pc->pc_pventry[field * 64 + bit];
1994 pc->pc_map[field] &= ~(1ul << bit);
1995 /* If this was the last item, move it to tail */
1996 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
1997 pc->pc_map[2] == 0) {
1998 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1999 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2002 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2003 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2007 /* No free items, allocate another chunk */
2008 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2011 if (lockp == NULL) {
2012 PV_STAT(pc_chunk_tryfail++);
2015 m = reclaim_pv_chunk(pmap, lockp);
2019 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2020 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2021 dump_add_page(m->phys_addr);
2022 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2024 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2025 pc->pc_map[1] = PC_FREE1;
2026 pc->pc_map[2] = PC_FREE2;
2027 mtx_lock(&pv_chunks_mutex);
2028 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2029 mtx_unlock(&pv_chunks_mutex);
2030 pv = &pc->pc_pventry[0];
2031 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2032 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2033 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2038 * Ensure that the number of spare PV entries in the specified pmap meets or
2039 * exceeds the given count, "needed".
2041 * The given PV list lock may be released.
2044 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2046 struct pch new_tail;
2047 struct pv_chunk *pc;
2051 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2052 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2055 * Newly allocated PV chunks must be stored in a private list until
2056 * the required number of PV chunks have been allocated. Otherwise,
2057 * reclaim_pv_chunk() could recycle one of these chunks. In
2058 * contrast, these chunks must be added to the pmap upon allocation.
2060 TAILQ_INIT(&new_tail);
2063 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2064 bit_count((bitstr_t *)pc->pc_map, 0,
2065 sizeof(pc->pc_map) * NBBY, &free);
2069 if (avail >= needed)
2072 for (; avail < needed; avail += _NPCPV) {
2073 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2076 m = reclaim_pv_chunk(pmap, lockp);
2080 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2081 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2082 dump_add_page(m->phys_addr);
2083 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2085 pc->pc_map[0] = PC_FREE0;
2086 pc->pc_map[1] = PC_FREE1;
2087 pc->pc_map[2] = PC_FREE2;
2088 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2089 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2090 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2092 if (!TAILQ_EMPTY(&new_tail)) {
2093 mtx_lock(&pv_chunks_mutex);
2094 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2095 mtx_unlock(&pv_chunks_mutex);
2100 * First find and then remove the pv entry for the specified pmap and virtual
2101 * address from the specified pv list. Returns the pv entry if found and NULL
2102 * otherwise. This operation can be performed on pv lists for either 4KB or
2103 * 2MB page mappings.
2105 static __inline pv_entry_t
2106 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2110 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2111 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2112 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2121 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2122 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2123 * entries for each of the 4KB page mappings.
2126 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2127 struct rwlock **lockp)
2129 struct md_page *pvh;
2130 struct pv_chunk *pc;
2132 vm_offset_t va_last;
2136 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2137 KASSERT((pa & L2_OFFSET) == 0,
2138 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2139 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2142 * Transfer the 2mpage's pv entry for this mapping to the first
2143 * page's pv list. Once this transfer begins, the pv list lock
2144 * must not be released until the last pv entry is reinstantiated.
2146 pvh = pa_to_pvh(pa);
2147 va = va & ~L2_OFFSET;
2148 pv = pmap_pvh_remove(pvh, pmap, va);
2149 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2150 m = PHYS_TO_VM_PAGE(pa);
2151 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2153 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2154 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2155 va_last = va + L2_SIZE - PAGE_SIZE;
2157 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2158 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2159 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2160 for (field = 0; field < _NPCM; field++) {
2161 while (pc->pc_map[field]) {
2162 bit = ffsl(pc->pc_map[field]) - 1;
2163 pc->pc_map[field] &= ~(1ul << bit);
2164 pv = &pc->pc_pventry[field * 64 + bit];
2168 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2169 ("pmap_pv_demote_l2: page %p is not managed", m));
2170 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2176 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2177 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2180 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2181 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2182 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2184 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2185 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2189 * First find and then destroy the pv entry for the specified pmap and virtual
2190 * address. This operation can be performed on pv lists for either 4KB or 2MB
2194 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2198 pv = pmap_pvh_remove(pvh, pmap, va);
2199 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2200 free_pv_entry(pmap, pv);
2204 * Conditionally create the PV entry for a 4KB page mapping if the required
2205 * memory can be allocated without resorting to reclamation.
2208 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2209 struct rwlock **lockp)
2213 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2214 /* Pass NULL instead of the lock pointer to disable reclamation. */
2215 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2217 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2218 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2226 * pmap_remove_l2: do the things to unmap a level 2 superpage in a process
2229 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2230 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2232 struct md_page *pvh;
2234 vm_offset_t eva, va;
2237 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2238 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2239 old_l2 = pmap_load_clear(l2);
2240 pmap_invalidate_range(pmap, sva, sva + L2_SIZE);
2241 if (old_l2 & ATTR_SW_WIRED)
2242 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2243 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2244 if (old_l2 & ATTR_SW_MANAGED) {
2245 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2246 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2247 pmap_pvh_free(pvh, pmap, sva);
2248 eva = sva + L2_SIZE;
2249 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2250 va < eva; va += PAGE_SIZE, m++) {
2251 if (pmap_page_dirty(old_l2))
2253 if (old_l2 & ATTR_AF)
2254 vm_page_aflag_set(m, PGA_REFERENCED);
2255 if (TAILQ_EMPTY(&m->md.pv_list) &&
2256 TAILQ_EMPTY(&pvh->pv_list))
2257 vm_page_aflag_clear(m, PGA_WRITEABLE);
2260 KASSERT(pmap != kernel_pmap,
2261 ("Attempting to remove an l2 kernel page"));
2262 ml3 = pmap_remove_pt_page(pmap, sva);
2264 pmap_resident_count_dec(pmap, 1);
2265 KASSERT(ml3->wire_count == NL3PG,
2266 ("pmap_remove_pages: l3 page wire count error"));
2267 ml3->wire_count = 1;
2268 vm_page_unwire_noq(ml3);
2269 pmap_add_delayed_free_list(ml3, free, FALSE);
2271 return (pmap_unuse_pt(pmap, sva, l1e, free));
2275 * pmap_remove_l3: do the things to unmap a page in a process
2278 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2279 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2281 struct md_page *pvh;
2285 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2286 old_l3 = pmap_load_clear(l3);
2287 pmap_invalidate_page(pmap, va);
2288 if (old_l3 & ATTR_SW_WIRED)
2289 pmap->pm_stats.wired_count -= 1;
2290 pmap_resident_count_dec(pmap, 1);
2291 if (old_l3 & ATTR_SW_MANAGED) {
2292 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2293 if (pmap_page_dirty(old_l3))
2295 if (old_l3 & ATTR_AF)
2296 vm_page_aflag_set(m, PGA_REFERENCED);
2297 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2298 pmap_pvh_free(&m->md, pmap, va);
2299 if (TAILQ_EMPTY(&m->md.pv_list) &&
2300 (m->flags & PG_FICTITIOUS) == 0) {
2301 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2302 if (TAILQ_EMPTY(&pvh->pv_list))
2303 vm_page_aflag_clear(m, PGA_WRITEABLE);
2306 return (pmap_unuse_pt(pmap, va, l2e, free));
2310 * Remove the given range of addresses from the specified map.
2312 * It is assumed that the start and end are properly
2313 * rounded to the page size.
2316 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2318 struct rwlock *lock;
2319 vm_offset_t va, va_next;
2320 pd_entry_t *l0, *l1, *l2;
2321 pt_entry_t l3_paddr, *l3;
2322 struct spglist free;
2325 * Perform an unsynchronized read. This is, however, safe.
2327 if (pmap->pm_stats.resident_count == 0)
2335 for (; sva < eva; sva = va_next) {
2337 if (pmap->pm_stats.resident_count == 0)
2340 l0 = pmap_l0(pmap, sva);
2341 if (pmap_load(l0) == 0) {
2342 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2348 l1 = pmap_l0_to_l1(l0, sva);
2349 if (pmap_load(l1) == 0) {
2350 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2357 * Calculate index for next page table.
2359 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2363 l2 = pmap_l1_to_l2(l1, sva);
2367 l3_paddr = pmap_load(l2);
2369 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2370 if (sva + L2_SIZE == va_next && eva >= va_next) {
2371 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2374 } else if (pmap_demote_l2_locked(pmap, l2,
2375 sva &~L2_OFFSET, &lock) == NULL)
2377 l3_paddr = pmap_load(l2);
2381 * Weed out invalid mappings.
2383 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2387 * Limit our scan to either the end of the va represented
2388 * by the current page table page, or to the end of the
2389 * range being removed.
2395 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2398 panic("l3 == NULL");
2399 if (pmap_load(l3) == 0) {
2400 if (va != va_next) {
2401 pmap_invalidate_range(pmap, va, sva);
2408 if (pmap_remove_l3(pmap, l3, sva, l3_paddr, &free,
2415 pmap_invalidate_range(pmap, va, sva);
2420 pmap_free_zero_pages(&free);
2424 * Routine: pmap_remove_all
2426 * Removes this physical page from
2427 * all physical maps in which it resides.
2428 * Reflects back modify bits to the pager.
2431 * Original versions of this routine were very
2432 * inefficient because they iteratively called
2433 * pmap_remove (slow...)
2437 pmap_remove_all(vm_page_t m)
2439 struct md_page *pvh;
2442 struct rwlock *lock;
2443 pd_entry_t *pde, tpde;
2444 pt_entry_t *pte, tpte;
2446 struct spglist free;
2447 int lvl, pvh_gen, md_gen;
2449 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2450 ("pmap_remove_all: page %p is not managed", m));
2452 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2453 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2454 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2457 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2459 if (!PMAP_TRYLOCK(pmap)) {
2460 pvh_gen = pvh->pv_gen;
2464 if (pvh_gen != pvh->pv_gen) {
2471 pte = pmap_pte(pmap, va, &lvl);
2472 KASSERT(pte != NULL,
2473 ("pmap_remove_all: no page table entry found"));
2475 ("pmap_remove_all: invalid pte level %d", lvl));
2477 pmap_demote_l2_locked(pmap, pte, va, &lock);
2480 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2482 if (!PMAP_TRYLOCK(pmap)) {
2483 pvh_gen = pvh->pv_gen;
2484 md_gen = m->md.pv_gen;
2488 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2494 pmap_resident_count_dec(pmap, 1);
2496 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2497 KASSERT(pde != NULL,
2498 ("pmap_remove_all: no page directory entry found"));
2500 ("pmap_remove_all: invalid pde level %d", lvl));
2501 tpde = pmap_load(pde);
2503 pte = pmap_l2_to_l3(pde, pv->pv_va);
2504 tpte = pmap_load(pte);
2505 pmap_load_clear(pte);
2506 pmap_invalidate_page(pmap, pv->pv_va);
2507 if (tpte & ATTR_SW_WIRED)
2508 pmap->pm_stats.wired_count--;
2509 if ((tpte & ATTR_AF) != 0)
2510 vm_page_aflag_set(m, PGA_REFERENCED);
2513 * Update the vm_page_t clean and reference bits.
2515 if (pmap_page_dirty(tpte))
2517 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2518 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2520 free_pv_entry(pmap, pv);
2523 vm_page_aflag_clear(m, PGA_WRITEABLE);
2525 pmap_free_zero_pages(&free);
2529 * Set the physical protection on the
2530 * specified range of this map as requested.
2533 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2535 vm_offset_t va, va_next;
2536 pd_entry_t *l0, *l1, *l2;
2537 pt_entry_t *l3p, l3, nbits;
2539 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
2540 if (prot == VM_PROT_NONE) {
2541 pmap_remove(pmap, sva, eva);
2545 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
2546 (VM_PROT_WRITE | VM_PROT_EXECUTE))
2550 for (; sva < eva; sva = va_next) {
2552 l0 = pmap_l0(pmap, sva);
2553 if (pmap_load(l0) == 0) {
2554 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2560 l1 = pmap_l0_to_l1(l0, sva);
2561 if (pmap_load(l1) == 0) {
2562 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2568 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2572 l2 = pmap_l1_to_l2(l1, sva);
2573 if (pmap_load(l2) == 0)
2576 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
2577 l3p = pmap_demote_l2(pmap, l2, sva);
2581 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
2582 ("pmap_protect: Invalid L2 entry after demotion"));
2588 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2590 l3 = pmap_load(l3p);
2591 if (!pmap_l3_valid(l3))
2595 if ((prot & VM_PROT_WRITE) == 0) {
2596 if ((l3 & ATTR_SW_MANAGED) &&
2597 pmap_page_dirty(l3)) {
2598 vm_page_dirty(PHYS_TO_VM_PAGE(l3 &
2601 nbits |= ATTR_AP(ATTR_AP_RO);
2603 if ((prot & VM_PROT_EXECUTE) == 0)
2606 pmap_set(l3p, nbits);
2607 /* XXX: Use pmap_invalidate_range */
2608 pmap_invalidate_page(pmap, sva);
2615 * Inserts the specified page table page into the specified pmap's collection
2616 * of idle page table pages. Each of a pmap's page table pages is responsible
2617 * for mapping a distinct range of virtual addresses. The pmap's collection is
2618 * ordered by this virtual address range.
2621 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2624 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2625 return (vm_radix_insert(&pmap->pm_root, mpte));
2629 * Removes the page table page mapping the specified virtual address from the
2630 * specified pmap's collection of idle page table pages, and returns it.
2631 * Otherwise, returns NULL if there is no page table page corresponding to the
2632 * specified virtual address.
2634 static __inline vm_page_t
2635 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2638 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2639 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
2643 * Performs a break-before-make update of a pmap entry. This is needed when
2644 * either promoting or demoting pages to ensure the TLB doesn't get into an
2645 * inconsistent state.
2648 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
2649 vm_offset_t va, vm_size_t size)
2653 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2656 * Ensure we don't get switched out with the page table in an
2657 * inconsistent state. We also need to ensure no interrupts fire
2658 * as they may make use of an address we are about to invalidate.
2660 intr = intr_disable();
2663 /* Clear the old mapping */
2664 pmap_load_clear(pte);
2665 pmap_invalidate_range_nopin(pmap, va, va + size);
2667 /* Create the new mapping */
2668 pmap_load_store(pte, newpte);
2674 #if VM_NRESERVLEVEL > 0
2676 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
2677 * replace the many pv entries for the 4KB page mappings by a single pv entry
2678 * for the 2MB page mapping.
2681 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2682 struct rwlock **lockp)
2684 struct md_page *pvh;
2686 vm_offset_t va_last;
2689 KASSERT((pa & L2_OFFSET) == 0,
2690 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
2691 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2694 * Transfer the first page's pv entry for this mapping to the 2mpage's
2695 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
2696 * a transfer avoids the possibility that get_pv_entry() calls
2697 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
2698 * mappings that is being promoted.
2700 m = PHYS_TO_VM_PAGE(pa);
2701 va = va & ~L2_OFFSET;
2702 pv = pmap_pvh_remove(&m->md, pmap, va);
2703 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
2704 pvh = pa_to_pvh(pa);
2705 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2707 /* Free the remaining NPTEPG - 1 pv entries. */
2708 va_last = va + L2_SIZE - PAGE_SIZE;
2712 pmap_pvh_free(&m->md, pmap, va);
2713 } while (va < va_last);
2717 * Tries to promote the 512, contiguous 4KB page mappings that are within a
2718 * single level 2 table entry to a single 2MB page mapping. For promotion
2719 * to occur, two conditions must be met: (1) the 4KB page mappings must map
2720 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
2721 * identical characteristics.
2724 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
2725 struct rwlock **lockp)
2727 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
2731 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2733 sva = va & ~L2_OFFSET;
2734 firstl3 = pmap_l2_to_l3(l2, sva);
2735 newl2 = pmap_load(firstl3);
2737 /* Check the alingment is valid */
2738 if (((newl2 & ~ATTR_MASK) & L2_OFFSET) != 0) {
2739 atomic_add_long(&pmap_l2_p_failures, 1);
2740 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2741 " in pmap %p", va, pmap);
2745 pa = newl2 + L2_SIZE - PAGE_SIZE;
2746 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
2747 oldl3 = pmap_load(l3);
2749 atomic_add_long(&pmap_l2_p_failures, 1);
2750 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2751 " in pmap %p", va, pmap);
2758 * Save the page table page in its current state until the L2
2759 * mapping the superpage is demoted by pmap_demote_l2() or
2760 * destroyed by pmap_remove_l3().
2762 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
2763 KASSERT(mpte >= vm_page_array &&
2764 mpte < &vm_page_array[vm_page_array_size],
2765 ("pmap_promote_l2: page table page is out of range"));
2766 KASSERT(mpte->pindex == pmap_l2_pindex(va),
2767 ("pmap_promote_l2: page table page's pindex is wrong"));
2768 if (pmap_insert_pt_page(pmap, mpte)) {
2769 atomic_add_long(&pmap_l2_p_failures, 1);
2771 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
2776 if ((newl2 & ATTR_SW_MANAGED) != 0)
2777 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
2779 newl2 &= ~ATTR_DESCR_MASK;
2782 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
2784 atomic_add_long(&pmap_l2_promotions, 1);
2785 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
2788 #endif /* VM_NRESERVLEVEL > 0 */
2791 * Insert the given physical page (p) at
2792 * the specified virtual address (v) in the
2793 * target physical map with the protection requested.
2795 * If specified, the page will be wired down, meaning
2796 * that the related pte can not be reclaimed.
2798 * NB: This is the only routine which MAY NOT lazy-evaluate
2799 * or lose information. That is, this routine must actually
2800 * insert this page into the given map NOW.
2803 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2804 u_int flags, int8_t psind __unused)
2806 struct rwlock *lock;
2808 pt_entry_t new_l3, orig_l3;
2809 pt_entry_t *l2, *l3;
2811 vm_paddr_t opa, pa, l1_pa, l2_pa, l3_pa;
2812 vm_page_t mpte, om, l1_m, l2_m, l3_m;
2816 va = trunc_page(va);
2817 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2818 VM_OBJECT_ASSERT_LOCKED(m->object);
2819 pa = VM_PAGE_TO_PHYS(m);
2820 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
2822 if ((prot & VM_PROT_WRITE) == 0)
2823 new_l3 |= ATTR_AP(ATTR_AP_RO);
2824 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
2826 if ((flags & PMAP_ENTER_WIRED) != 0)
2827 new_l3 |= ATTR_SW_WIRED;
2828 if (va < VM_MAXUSER_ADDRESS)
2829 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
2831 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
2838 pde = pmap_pde(pmap, va, &lvl);
2839 if (pde != NULL && lvl == 1) {
2840 l2 = pmap_l1_to_l2(pde, va);
2841 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
2842 (l3 = pmap_demote_l2_locked(pmap, l2, va & ~L2_OFFSET,
2844 l3 = &l3[pmap_l3_index(va)];
2845 if (va < VM_MAXUSER_ADDRESS) {
2846 mpte = PHYS_TO_VM_PAGE(
2847 pmap_load(l2) & ~ATTR_MASK);
2854 if (va < VM_MAXUSER_ADDRESS) {
2855 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
2856 mpte = pmap_alloc_l3(pmap, va, nosleep ? NULL : &lock);
2857 if (mpte == NULL && nosleep) {
2858 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
2862 return (KERN_RESOURCE_SHORTAGE);
2864 pde = pmap_pde(pmap, va, &lvl);
2865 KASSERT(pde != NULL,
2866 ("pmap_enter: Invalid page entry, va: 0x%lx", va));
2868 ("pmap_enter: Invalid level %d", lvl));
2871 * If we get a level 2 pde it must point to a level 3 entry
2872 * otherwise we will need to create the intermediate tables
2878 /* Get the l0 pde to update */
2879 pde = pmap_l0(pmap, va);
2880 KASSERT(pde != NULL, ("..."));
2882 l1_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2883 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2886 panic("pmap_enter: l1 pte_m == NULL");
2887 if ((l1_m->flags & PG_ZERO) == 0)
2888 pmap_zero_page(l1_m);
2890 l1_pa = VM_PAGE_TO_PHYS(l1_m);
2891 pmap_load_store(pde, l1_pa | L0_TABLE);
2894 /* Get the l1 pde to update */
2895 pde = pmap_l1_to_l2(pde, va);
2896 KASSERT(pde != NULL, ("..."));
2898 l2_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2899 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2902 panic("pmap_enter: l2 pte_m == NULL");
2903 if ((l2_m->flags & PG_ZERO) == 0)
2904 pmap_zero_page(l2_m);
2906 l2_pa = VM_PAGE_TO_PHYS(l2_m);
2907 pmap_load_store(pde, l2_pa | L1_TABLE);
2910 /* Get the l2 pde to update */
2911 pde = pmap_l1_to_l2(pde, va);
2912 KASSERT(pde != NULL, ("..."));
2914 l3_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2915 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2918 panic("pmap_enter: l3 pte_m == NULL");
2919 if ((l3_m->flags & PG_ZERO) == 0)
2920 pmap_zero_page(l3_m);
2922 l3_pa = VM_PAGE_TO_PHYS(l3_m);
2923 pmap_load_store(pde, l3_pa | L2_TABLE);
2928 l3 = pmap_l2_to_l3(pde, va);
2932 orig_l3 = pmap_load(l3);
2933 opa = orig_l3 & ~ATTR_MASK;
2936 * Is the specified virtual address already mapped?
2938 if (pmap_l3_valid(orig_l3)) {
2940 * Wiring change, just update stats. We don't worry about
2941 * wiring PT pages as they remain resident as long as there
2942 * are valid mappings in them. Hence, if a user page is wired,
2943 * the PT page will be also.
2945 if ((flags & PMAP_ENTER_WIRED) != 0 &&
2946 (orig_l3 & ATTR_SW_WIRED) == 0)
2947 pmap->pm_stats.wired_count++;
2948 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
2949 (orig_l3 & ATTR_SW_WIRED) != 0)
2950 pmap->pm_stats.wired_count--;
2953 * Remove the extra PT page reference.
2957 KASSERT(mpte->wire_count > 0,
2958 ("pmap_enter: missing reference to page table page,"
2963 * Has the physical page changed?
2967 * No, might be a protection or wiring change.
2969 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
2970 new_l3 |= ATTR_SW_MANAGED;
2971 if ((new_l3 & ATTR_AP(ATTR_AP_RW)) ==
2972 ATTR_AP(ATTR_AP_RW)) {
2973 vm_page_aflag_set(m, PGA_WRITEABLE);
2980 * Increment the counters.
2982 if ((new_l3 & ATTR_SW_WIRED) != 0)
2983 pmap->pm_stats.wired_count++;
2984 pmap_resident_count_inc(pmap, 1);
2987 * Enter on the PV list if part of our managed memory.
2989 if ((m->oflags & VPO_UNMANAGED) == 0) {
2990 new_l3 |= ATTR_SW_MANAGED;
2991 pv = get_pv_entry(pmap, &lock);
2993 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
2994 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2996 if ((new_l3 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
2997 vm_page_aflag_set(m, PGA_WRITEABLE);
3002 * Sync icache if exec permission and attribute VM_MEMATTR_WRITE_BACK
3003 * is set. Do it now, before the mapping is stored and made
3004 * valid for hardware table walk. If done later, then other can
3005 * access this page before caches are properly synced.
3006 * Don't do it for kernel memory which is mapped with exec
3007 * permission even if the memory isn't going to hold executable
3008 * code. The only time when icache sync is needed is after
3009 * kernel module is loaded and the relocation info is processed.
3010 * And it's done in elf_cpu_load_file().
3012 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3013 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3014 (opa != pa || (orig_l3 & ATTR_XN)))
3015 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3018 * Update the L3 entry
3020 if (pmap_l3_valid(orig_l3)) {
3023 pmap_update_entry(pmap, l3, new_l3, va, PAGE_SIZE);
3024 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3025 om = PHYS_TO_VM_PAGE(opa);
3026 if (pmap_page_dirty(orig_l3))
3028 if ((orig_l3 & ATTR_AF) != 0)
3029 vm_page_aflag_set(om, PGA_REFERENCED);
3030 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3031 pmap_pvh_free(&om->md, pmap, va);
3032 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3033 TAILQ_EMPTY(&om->md.pv_list) &&
3034 ((om->flags & PG_FICTITIOUS) != 0 ||
3035 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3036 vm_page_aflag_clear(om, PGA_WRITEABLE);
3038 } else if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3039 /* same PA, different attributes */
3040 pmap_load_store(l3, new_l3);
3041 pmap_invalidate_page(pmap, va);
3042 if (pmap_page_dirty(orig_l3) &&
3043 (orig_l3 & ATTR_SW_MANAGED) != 0)
3048 * This can happens if multiple threads simultaneously
3049 * access not yet mapped page. This bad for performance
3050 * since this can cause full demotion-NOP-promotion
3052 * Another possible reasons are:
3053 * - VM and pmap memory layout are diverged
3054 * - tlb flush is missing somewhere and CPU doesn't see
3057 CTR4(KTR_PMAP, "%s: already mapped page - "
3058 "pmap %p va 0x%#lx pte 0x%lx",
3059 __func__, pmap, va, new_l3);
3063 pmap_load_store(l3, new_l3);
3066 #if VM_NRESERVLEVEL > 0
3067 if (pmap != pmap_kernel() &&
3068 (mpte == NULL || mpte->wire_count == NL3PG) &&
3069 pmap_superpages_enabled() &&
3070 (m->flags & PG_FICTITIOUS) == 0 &&
3071 vm_reserv_level_iffullpop(m) == 0) {
3072 pmap_promote_l2(pmap, pde, va, &lock);
3079 return (KERN_SUCCESS);
3083 * Maps a sequence of resident pages belonging to the same object.
3084 * The sequence begins with the given page m_start. This page is
3085 * mapped at the given virtual address start. Each subsequent page is
3086 * mapped at a virtual address that is offset from start by the same
3087 * amount as the page is offset from m_start within the object. The
3088 * last page in the sequence is the page with the largest offset from
3089 * m_start that can be mapped at a virtual address less than the given
3090 * virtual address end. Not every virtual page between start and end
3091 * is mapped; only those for which a resident page exists with the
3092 * corresponding offset from m_start are mapped.
3095 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3096 vm_page_t m_start, vm_prot_t prot)
3098 struct rwlock *lock;
3101 vm_pindex_t diff, psize;
3103 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3105 psize = atop(end - start);
3110 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3111 va = start + ptoa(diff);
3112 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte, &lock);
3113 m = TAILQ_NEXT(m, listq);
3121 * this code makes some *MAJOR* assumptions:
3122 * 1. Current pmap & pmap exists.
3125 * 4. No page table pages.
3126 * but is *MUCH* faster than pmap_enter...
3130 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3132 struct rwlock *lock;
3136 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3143 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3144 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3146 struct spglist free;
3148 pt_entry_t *l2, *l3, l3_val;
3152 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3153 (m->oflags & VPO_UNMANAGED) != 0,
3154 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3155 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3157 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3159 * In the case that a page table page is not
3160 * resident, we are creating it here.
3162 if (va < VM_MAXUSER_ADDRESS) {
3163 vm_pindex_t l2pindex;
3166 * Calculate pagetable page index
3168 l2pindex = pmap_l2_pindex(va);
3169 if (mpte && (mpte->pindex == l2pindex)) {
3175 pde = pmap_pde(pmap, va, &lvl);
3178 * If the page table page is mapped, we just increment
3179 * the hold count, and activate it. Otherwise, we
3180 * attempt to allocate a page table page. If this
3181 * attempt fails, we don't retry. Instead, we give up.
3184 l2 = pmap_l1_to_l2(pde, va);
3185 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3189 if (lvl == 2 && pmap_load(pde) != 0) {
3191 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3195 * Pass NULL instead of the PV list lock
3196 * pointer, because we don't intend to sleep.
3198 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3203 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3204 l3 = &l3[pmap_l3_index(va)];
3207 pde = pmap_pde(kernel_pmap, va, &lvl);
3208 KASSERT(pde != NULL,
3209 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3212 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3213 l3 = pmap_l2_to_l3(pde, va);
3216 if (pmap_load(l3) != 0) {
3225 * Enter on the PV list if part of our managed memory.
3227 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3228 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3231 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
3232 pmap_invalidate_page(pmap, va);
3233 pmap_free_zero_pages(&free);
3241 * Increment counters
3243 pmap_resident_count_inc(pmap, 1);
3245 pa = VM_PAGE_TO_PHYS(m);
3246 l3_val = pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3247 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3248 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3250 else if (va < VM_MAXUSER_ADDRESS)
3254 * Now validate mapping with RO protection
3256 if ((m->oflags & VPO_UNMANAGED) == 0)
3257 l3_val |= ATTR_SW_MANAGED;
3259 /* Sync icache before the mapping is stored to PTE */
3260 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3261 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
3262 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3264 pmap_load_store(l3, l3_val);
3265 pmap_invalidate_page(pmap, va);
3270 * This code maps large physical mmap regions into the
3271 * processor address space. Note that some shortcuts
3272 * are taken, but the code works.
3275 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3276 vm_pindex_t pindex, vm_size_t size)
3279 VM_OBJECT_ASSERT_WLOCKED(object);
3280 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3281 ("pmap_object_init_pt: non-device object"));
3285 * Clear the wired attribute from the mappings for the specified range of
3286 * addresses in the given pmap. Every valid mapping within that range
3287 * must have the wired attribute set. In contrast, invalid mappings
3288 * cannot have the wired attribute set, so they are ignored.
3290 * The wired attribute of the page table entry is not a hardware feature,
3291 * so there is no need to invalidate any TLB entries.
3294 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3296 vm_offset_t va_next;
3297 pd_entry_t *l0, *l1, *l2;
3301 for (; sva < eva; sva = va_next) {
3302 l0 = pmap_l0(pmap, sva);
3303 if (pmap_load(l0) == 0) {
3304 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3310 l1 = pmap_l0_to_l1(l0, sva);
3311 if (pmap_load(l1) == 0) {
3312 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3318 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3322 l2 = pmap_l1_to_l2(l1, sva);
3323 if (pmap_load(l2) == 0)
3326 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3327 l3 = pmap_demote_l2(pmap, l2, sva);
3331 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3332 ("pmap_unwire: Invalid l2 entry after demotion"));
3336 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3338 if (pmap_load(l3) == 0)
3340 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
3341 panic("pmap_unwire: l3 %#jx is missing "
3342 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
3345 * PG_W must be cleared atomically. Although the pmap
3346 * lock synchronizes access to PG_W, another processor
3347 * could be setting PG_M and/or PG_A concurrently.
3349 atomic_clear_long(l3, ATTR_SW_WIRED);
3350 pmap->pm_stats.wired_count--;
3357 * Copy the range specified by src_addr/len
3358 * from the source map to the range dst_addr/len
3359 * in the destination map.
3361 * This routine is only advisory and need not do anything.
3365 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3366 vm_offset_t src_addr)
3371 * pmap_zero_page zeros the specified hardware page by mapping
3372 * the page into KVM and using bzero to clear its contents.
3375 pmap_zero_page(vm_page_t m)
3377 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3379 pagezero((void *)va);
3383 * pmap_zero_page_area zeros the specified hardware page by mapping
3384 * the page into KVM and using bzero to clear its contents.
3386 * off and size may not cover an area beyond a single hardware page.
3389 pmap_zero_page_area(vm_page_t m, int off, int size)
3391 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3393 if (off == 0 && size == PAGE_SIZE)
3394 pagezero((void *)va);
3396 bzero((char *)va + off, size);
3400 * pmap_copy_page copies the specified (machine independent)
3401 * page by mapping the page into virtual memory and using
3402 * bcopy to copy the page, one machine dependent page at a
3406 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
3408 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
3409 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
3411 pagecopy((void *)src, (void *)dst);
3414 int unmapped_buf_allowed = 1;
3417 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
3418 vm_offset_t b_offset, int xfersize)
3422 vm_paddr_t p_a, p_b;
3423 vm_offset_t a_pg_offset, b_pg_offset;
3426 while (xfersize > 0) {
3427 a_pg_offset = a_offset & PAGE_MASK;
3428 m_a = ma[a_offset >> PAGE_SHIFT];
3429 p_a = m_a->phys_addr;
3430 b_pg_offset = b_offset & PAGE_MASK;
3431 m_b = mb[b_offset >> PAGE_SHIFT];
3432 p_b = m_b->phys_addr;
3433 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
3434 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
3435 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
3436 panic("!DMAP a %lx", p_a);
3438 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
3440 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
3441 panic("!DMAP b %lx", p_b);
3443 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
3445 bcopy(a_cp, b_cp, cnt);
3453 pmap_quick_enter_page(vm_page_t m)
3456 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
3460 pmap_quick_remove_page(vm_offset_t addr)
3465 * Returns true if the pmap's pv is one of the first
3466 * 16 pvs linked to from this page. This count may
3467 * be changed upwards or downwards in the future; it
3468 * is only necessary that true be returned for a small
3469 * subset of pmaps for proper page aging.
3472 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3474 struct md_page *pvh;
3475 struct rwlock *lock;
3480 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3481 ("pmap_page_exists_quick: page %p is not managed", m));
3483 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3485 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3486 if (PV_PMAP(pv) == pmap) {
3494 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
3495 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3496 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3497 if (PV_PMAP(pv) == pmap) {
3511 * pmap_page_wired_mappings:
3513 * Return the number of managed mappings to the given physical page
3517 pmap_page_wired_mappings(vm_page_t m)
3519 struct rwlock *lock;
3520 struct md_page *pvh;
3524 int count, lvl, md_gen, pvh_gen;
3526 if ((m->oflags & VPO_UNMANAGED) != 0)
3528 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3532 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3534 if (!PMAP_TRYLOCK(pmap)) {
3535 md_gen = m->md.pv_gen;
3539 if (md_gen != m->md.pv_gen) {
3544 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3545 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3549 if ((m->flags & PG_FICTITIOUS) == 0) {
3550 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3551 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3553 if (!PMAP_TRYLOCK(pmap)) {
3554 md_gen = m->md.pv_gen;
3555 pvh_gen = pvh->pv_gen;
3559 if (md_gen != m->md.pv_gen ||
3560 pvh_gen != pvh->pv_gen) {
3565 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3567 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3577 * Destroy all managed, non-wired mappings in the given user-space
3578 * pmap. This pmap cannot be active on any processor besides the
3581 * This function cannot be applied to the kernel pmap. Moreover, it
3582 * is not intended for general use. It is only to be used during
3583 * process termination. Consequently, it can be implemented in ways
3584 * that make it faster than pmap_remove(). First, it can more quickly
3585 * destroy mappings by iterating over the pmap's collection of PV
3586 * entries, rather than searching the page table. Second, it doesn't
3587 * have to test and clear the page table entries atomically, because
3588 * no processor is currently accessing the user address space. In
3589 * particular, a page table entry's dirty bit won't change state once
3590 * this function starts.
3593 pmap_remove_pages(pmap_t pmap)
3596 pt_entry_t *pte, tpte;
3597 struct spglist free;
3598 vm_page_t m, ml3, mt;
3600 struct md_page *pvh;
3601 struct pv_chunk *pc, *npc;
3602 struct rwlock *lock;
3604 uint64_t inuse, bitmask;
3605 int allfree, field, freed, idx, lvl;
3612 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
3615 for (field = 0; field < _NPCM; field++) {
3616 inuse = ~pc->pc_map[field] & pc_freemask[field];
3617 while (inuse != 0) {
3618 bit = ffsl(inuse) - 1;
3619 bitmask = 1UL << bit;
3620 idx = field * 64 + bit;
3621 pv = &pc->pc_pventry[idx];
3624 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3625 KASSERT(pde != NULL,
3626 ("Attempting to remove an unmapped page"));
3630 pte = pmap_l1_to_l2(pde, pv->pv_va);
3631 tpte = pmap_load(pte);
3632 KASSERT((tpte & ATTR_DESCR_MASK) ==
3634 ("Attempting to remove an invalid "
3635 "block: %lx", tpte));
3636 tpte = pmap_load(pte);
3639 pte = pmap_l2_to_l3(pde, pv->pv_va);
3640 tpte = pmap_load(pte);
3641 KASSERT((tpte & ATTR_DESCR_MASK) ==
3643 ("Attempting to remove an invalid "
3644 "page: %lx", tpte));
3648 "Invalid page directory level: %d",
3653 * We cannot remove wired pages from a process' mapping at this time
3655 if (tpte & ATTR_SW_WIRED) {
3660 pa = tpte & ~ATTR_MASK;
3662 m = PHYS_TO_VM_PAGE(pa);
3663 KASSERT(m->phys_addr == pa,
3664 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
3665 m, (uintmax_t)m->phys_addr,
3668 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
3669 m < &vm_page_array[vm_page_array_size],
3670 ("pmap_remove_pages: bad pte %#jx",
3673 pmap_load_clear(pte);
3676 * Update the vm_page_t clean/reference bits.
3678 if ((tpte & ATTR_AP_RW_BIT) ==
3679 ATTR_AP(ATTR_AP_RW)) {
3682 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3691 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
3694 pc->pc_map[field] |= bitmask;
3697 pmap_resident_count_dec(pmap,
3698 L2_SIZE / PAGE_SIZE);
3699 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
3700 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
3702 if (TAILQ_EMPTY(&pvh->pv_list)) {
3703 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3704 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
3705 TAILQ_EMPTY(&mt->md.pv_list))
3706 vm_page_aflag_clear(mt, PGA_WRITEABLE);
3708 ml3 = pmap_remove_pt_page(pmap,
3711 pmap_resident_count_dec(pmap,1);
3712 KASSERT(ml3->wire_count == NL3PG,
3713 ("pmap_remove_pages: l3 page wire count error"));
3714 ml3->wire_count = 1;
3715 vm_page_unwire_noq(ml3);
3716 pmap_add_delayed_free_list(ml3,
3721 pmap_resident_count_dec(pmap, 1);
3722 TAILQ_REMOVE(&m->md.pv_list, pv,
3725 if ((m->aflags & PGA_WRITEABLE) != 0 &&
3726 TAILQ_EMPTY(&m->md.pv_list) &&
3727 (m->flags & PG_FICTITIOUS) == 0) {
3729 VM_PAGE_TO_PHYS(m));
3730 if (TAILQ_EMPTY(&pvh->pv_list))
3731 vm_page_aflag_clear(m,
3736 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
3741 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3742 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3743 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3745 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3749 pmap_invalidate_all(pmap);
3753 pmap_free_zero_pages(&free);
3757 * This is used to check if a page has been accessed or modified. As we
3758 * don't have a bit to see if it has been modified we have to assume it
3759 * has been if the page is read/write.
3762 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
3764 struct rwlock *lock;
3766 struct md_page *pvh;
3767 pt_entry_t *pte, mask, value;
3769 int lvl, md_gen, pvh_gen;
3773 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3776 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3778 if (!PMAP_TRYLOCK(pmap)) {
3779 md_gen = m->md.pv_gen;
3783 if (md_gen != m->md.pv_gen) {
3788 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3790 ("pmap_page_test_mappings: Invalid level %d", lvl));
3794 mask |= ATTR_AP_RW_BIT;
3795 value |= ATTR_AP(ATTR_AP_RW);
3798 mask |= ATTR_AF | ATTR_DESCR_MASK;
3799 value |= ATTR_AF | L3_PAGE;
3801 rv = (pmap_load(pte) & mask) == value;
3806 if ((m->flags & PG_FICTITIOUS) == 0) {
3807 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3808 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3810 if (!PMAP_TRYLOCK(pmap)) {
3811 md_gen = m->md.pv_gen;
3812 pvh_gen = pvh->pv_gen;
3816 if (md_gen != m->md.pv_gen ||
3817 pvh_gen != pvh->pv_gen) {
3822 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3824 ("pmap_page_test_mappings: Invalid level %d", lvl));
3828 mask |= ATTR_AP_RW_BIT;
3829 value |= ATTR_AP(ATTR_AP_RW);
3832 mask |= ATTR_AF | ATTR_DESCR_MASK;
3833 value |= ATTR_AF | L2_BLOCK;
3835 rv = (pmap_load(pte) & mask) == value;
3849 * Return whether or not the specified physical page was modified
3850 * in any physical maps.
3853 pmap_is_modified(vm_page_t m)
3856 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3857 ("pmap_is_modified: page %p is not managed", m));
3860 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3861 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
3862 * is clear, no PTEs can have PG_M set.
3864 VM_OBJECT_ASSERT_WLOCKED(m->object);
3865 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3867 return (pmap_page_test_mappings(m, FALSE, TRUE));
3871 * pmap_is_prefaultable:
3873 * Return whether or not the specified virtual address is eligible
3877 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3885 pte = pmap_pte(pmap, addr, &lvl);
3886 if (pte != NULL && pmap_load(pte) != 0) {
3894 * pmap_is_referenced:
3896 * Return whether or not the specified physical page was referenced
3897 * in any physical maps.
3900 pmap_is_referenced(vm_page_t m)
3903 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3904 ("pmap_is_referenced: page %p is not managed", m));
3905 return (pmap_page_test_mappings(m, TRUE, FALSE));
3909 * Clear the write and modified bits in each of the given page's mappings.
3912 pmap_remove_write(vm_page_t m)
3914 struct md_page *pvh;
3916 struct rwlock *lock;
3917 pv_entry_t next_pv, pv;
3918 pt_entry_t oldpte, *pte;
3920 int lvl, md_gen, pvh_gen;
3922 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3923 ("pmap_remove_write: page %p is not managed", m));
3926 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3927 * set by another thread while the object is locked. Thus,
3928 * if PGA_WRITEABLE is clear, no page table entries need updating.
3930 VM_OBJECT_ASSERT_WLOCKED(m->object);
3931 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3933 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3934 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
3935 pa_to_pvh(VM_PAGE_TO_PHYS(m));
3938 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
3940 if (!PMAP_TRYLOCK(pmap)) {
3941 pvh_gen = pvh->pv_gen;
3945 if (pvh_gen != pvh->pv_gen) {
3952 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3953 if ((pmap_load(pte) & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3954 pmap_demote_l2_locked(pmap, pte, va & ~L2_OFFSET,
3956 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
3957 ("inconsistent pv lock %p %p for page %p",
3958 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
3961 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3963 if (!PMAP_TRYLOCK(pmap)) {
3964 pvh_gen = pvh->pv_gen;
3965 md_gen = m->md.pv_gen;
3969 if (pvh_gen != pvh->pv_gen ||
3970 md_gen != m->md.pv_gen) {
3976 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3978 oldpte = pmap_load(pte);
3979 if ((oldpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) {
3980 if (!atomic_cmpset_long(pte, oldpte,
3981 oldpte | ATTR_AP(ATTR_AP_RO)))
3983 if ((oldpte & ATTR_AF) != 0)
3985 pmap_invalidate_page(pmap, pv->pv_va);
3990 vm_page_aflag_clear(m, PGA_WRITEABLE);
3993 static __inline boolean_t
3994 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
4001 * pmap_ts_referenced:
4003 * Return a count of reference bits for a page, clearing those bits.
4004 * It is not necessary for every reference bit to be cleared, but it
4005 * is necessary that 0 only be returned when there are truly no
4006 * reference bits set.
4008 * As an optimization, update the page's dirty field if a modified bit is
4009 * found while counting reference bits. This opportunistic update can be
4010 * performed at low cost and can eliminate the need for some future calls
4011 * to pmap_is_modified(). However, since this function stops after
4012 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4013 * dirty pages. Those dirty pages will only be detected by a future call
4014 * to pmap_is_modified().
4017 pmap_ts_referenced(vm_page_t m)
4019 struct md_page *pvh;
4022 struct rwlock *lock;
4023 pd_entry_t *pde, tpde;
4024 pt_entry_t *pte, tpte;
4028 int cleared, md_gen, not_cleared, lvl, pvh_gen;
4029 struct spglist free;
4032 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4033 ("pmap_ts_referenced: page %p is not managed", m));
4036 pa = VM_PAGE_TO_PHYS(m);
4037 lock = PHYS_TO_PV_LIST_LOCK(pa);
4038 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4042 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4043 goto small_mappings;
4049 if (!PMAP_TRYLOCK(pmap)) {
4050 pvh_gen = pvh->pv_gen;
4054 if (pvh_gen != pvh->pv_gen) {
4060 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4061 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4063 ("pmap_ts_referenced: invalid pde level %d", lvl));
4064 tpde = pmap_load(pde);
4065 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4066 ("pmap_ts_referenced: found an invalid l1 table"));
4067 pte = pmap_l1_to_l2(pde, pv->pv_va);
4068 tpte = pmap_load(pte);
4069 if (pmap_page_dirty(tpte)) {
4071 * Although "tpte" is mapping a 2MB page, because
4072 * this function is called at a 4KB page granularity,
4073 * we only update the 4KB page under test.
4077 if ((tpte & ATTR_AF) != 0) {
4079 * Since this reference bit is shared by 512 4KB
4080 * pages, it should not be cleared every time it is
4081 * tested. Apply a simple "hash" function on the
4082 * physical page number, the virtual superpage number,
4083 * and the pmap address to select one 4KB page out of
4084 * the 512 on which testing the reference bit will
4085 * result in clearing that reference bit. This
4086 * function is designed to avoid the selection of the
4087 * same 4KB page for every 2MB page mapping.
4089 * On demotion, a mapping that hasn't been referenced
4090 * is simply destroyed. To avoid the possibility of a
4091 * subsequent page fault on a demoted wired mapping,
4092 * always leave its reference bit set. Moreover,
4093 * since the superpage is wired, the current state of
4094 * its reference bit won't affect page replacement.
4096 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4097 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4098 (tpte & ATTR_SW_WIRED) == 0) {
4099 if (safe_to_clear_referenced(pmap, tpte)) {
4101 * TODO: We don't handle the access
4102 * flag at all. We need to be able
4103 * to set it in the exception handler.
4106 "safe_to_clear_referenced\n");
4107 } else if (pmap_demote_l2_locked(pmap, pte,
4108 pv->pv_va, &lock) != NULL) {
4110 va += VM_PAGE_TO_PHYS(m) -
4111 (tpte & ~ATTR_MASK);
4112 l3 = pmap_l2_to_l3(pte, va);
4113 pmap_remove_l3(pmap, l3, va,
4114 pmap_load(pte), NULL, &lock);
4120 * The superpage mapping was removed
4121 * entirely and therefore 'pv' is no
4129 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4130 ("inconsistent pv lock %p %p for page %p",
4131 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4136 /* Rotate the PV list if it has more than one entry. */
4137 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4138 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4139 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4142 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4144 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4146 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4153 if (!PMAP_TRYLOCK(pmap)) {
4154 pvh_gen = pvh->pv_gen;
4155 md_gen = m->md.pv_gen;
4159 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4164 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4165 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4167 ("pmap_ts_referenced: invalid pde level %d", lvl));
4168 tpde = pmap_load(pde);
4169 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4170 ("pmap_ts_referenced: found an invalid l2 table"));
4171 pte = pmap_l2_to_l3(pde, pv->pv_va);
4172 tpte = pmap_load(pte);
4173 if (pmap_page_dirty(tpte))
4175 if ((tpte & ATTR_AF) != 0) {
4176 if (safe_to_clear_referenced(pmap, tpte)) {
4178 * TODO: We don't handle the access flag
4179 * at all. We need to be able to set it in
4180 * the exception handler.
4182 panic("ARM64TODO: safe_to_clear_referenced\n");
4183 } else if ((tpte & ATTR_SW_WIRED) == 0) {
4185 * Wired pages cannot be paged out so
4186 * doing accessed bit emulation for
4187 * them is wasted effort. We do the
4188 * hard work for unwired pages only.
4190 pmap_remove_l3(pmap, pte, pv->pv_va, tpde,
4192 pmap_invalidate_page(pmap, pv->pv_va);
4197 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4198 ("inconsistent pv lock %p %p for page %p",
4199 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4204 /* Rotate the PV list if it has more than one entry. */
4205 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4206 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4207 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4210 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4211 not_cleared < PMAP_TS_REFERENCED_MAX);
4214 pmap_free_zero_pages(&free);
4215 return (cleared + not_cleared);
4219 * Apply the given advice to the specified range of addresses within the
4220 * given pmap. Depending on the advice, clear the referenced and/or
4221 * modified flags in each mapping and set the mapped page's dirty field.
4224 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4229 * Clear the modify bits on the specified physical page.
4232 pmap_clear_modify(vm_page_t m)
4235 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4236 ("pmap_clear_modify: page %p is not managed", m));
4237 VM_OBJECT_ASSERT_WLOCKED(m->object);
4238 KASSERT(!vm_page_xbusied(m),
4239 ("pmap_clear_modify: page %p is exclusive busied", m));
4242 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4243 * If the object containing the page is locked and the page is not
4244 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4246 if ((m->aflags & PGA_WRITEABLE) == 0)
4249 /* ARM64TODO: We lack support for tracking if a page is modified */
4253 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4256 return ((void *)PHYS_TO_DMAP(pa));
4260 pmap_unmapbios(vm_paddr_t pa, vm_size_t size)
4265 * Sets the memory attribute for the specified page.
4268 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4271 m->md.pv_memattr = ma;
4274 * If "m" is a normal page, update its direct mapping. This update
4275 * can be relied upon to perform any cache operations that are
4276 * required for data coherence.
4278 if ((m->flags & PG_FICTITIOUS) == 0 &&
4279 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
4280 m->md.pv_memattr) != 0)
4281 panic("memory attribute change on the direct map failed");
4285 * Changes the specified virtual address range's memory type to that given by
4286 * the parameter "mode". The specified virtual address range must be
4287 * completely contained within either the direct map or the kernel map. If
4288 * the virtual address range is contained within the kernel map, then the
4289 * memory type for each of the corresponding ranges of the direct map is also
4290 * changed. (The corresponding ranges of the direct map are those ranges that
4291 * map the same physical pages as the specified virtual address range.) These
4292 * changes to the direct map are necessary because Intel describes the
4293 * behavior of their processors as "undefined" if two or more mappings to the
4294 * same physical page have different memory types.
4296 * Returns zero if the change completed successfully, and either EINVAL or
4297 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
4298 * of the virtual address range was not mapped, and ENOMEM is returned if
4299 * there was insufficient memory available to complete the change. In the
4300 * latter case, the memory type may have been changed on some part of the
4301 * virtual address range or the direct map.
4304 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
4308 PMAP_LOCK(kernel_pmap);
4309 error = pmap_change_attr_locked(va, size, mode);
4310 PMAP_UNLOCK(kernel_pmap);
4315 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
4317 vm_offset_t base, offset, tmpva;
4318 pt_entry_t l3, *pte, *newpte;
4321 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
4322 base = trunc_page(va);
4323 offset = va & PAGE_MASK;
4324 size = round_page(offset + size);
4326 if (!VIRT_IN_DMAP(base))
4329 for (tmpva = base; tmpva < base + size; ) {
4330 pte = pmap_pte(kernel_pmap, va, &lvl);
4334 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
4336 * We already have the correct attribute,
4337 * ignore this entry.
4341 panic("Invalid DMAP table level: %d\n", lvl);
4343 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
4346 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
4354 * Split the entry to an level 3 table, then
4355 * set the new attribute.
4359 panic("Invalid DMAP table level: %d\n", lvl);
4361 newpte = pmap_demote_l1(kernel_pmap, pte,
4362 tmpva & ~L1_OFFSET);
4365 pte = pmap_l1_to_l2(pte, tmpva);
4367 newpte = pmap_demote_l2(kernel_pmap, pte,
4368 tmpva & ~L2_OFFSET);
4371 pte = pmap_l2_to_l3(pte, tmpva);
4373 /* Update the entry */
4374 l3 = pmap_load(pte);
4375 l3 &= ~ATTR_IDX_MASK;
4376 l3 |= ATTR_IDX(mode);
4377 if (mode == DEVICE_MEMORY)
4380 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
4384 * If moving to a non-cacheable entry flush
4387 if (mode == VM_MEMATTR_UNCACHEABLE)
4388 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
4400 * Create an L2 table to map all addresses within an L1 mapping.
4403 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
4405 pt_entry_t *l2, newl2, oldl1;
4407 vm_paddr_t l2phys, phys;
4411 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4412 oldl1 = pmap_load(l1);
4413 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
4414 ("pmap_demote_l1: Demoting a non-block entry"));
4415 KASSERT((va & L1_OFFSET) == 0,
4416 ("pmap_demote_l1: Invalid virtual address %#lx", va));
4417 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
4418 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
4421 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
4422 tmpl1 = kva_alloc(PAGE_SIZE);
4427 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
4428 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
4429 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
4430 " in pmap %p", va, pmap);
4434 l2phys = VM_PAGE_TO_PHYS(ml2);
4435 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
4437 /* Address the range points at */
4438 phys = oldl1 & ~ATTR_MASK;
4439 /* The attributed from the old l1 table to be copied */
4440 newl2 = oldl1 & ATTR_MASK;
4442 /* Create the new entries */
4443 for (i = 0; i < Ln_ENTRIES; i++) {
4444 l2[i] = newl2 | phys;
4447 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
4448 ("Invalid l2 page (%lx != %lx)", l2[0],
4449 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
4452 pmap_kenter(tmpl1, PAGE_SIZE,
4453 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY);
4454 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
4457 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
4460 pmap_kremove(tmpl1);
4461 kva_free(tmpl1, PAGE_SIZE);
4468 * Create an L3 table to map all addresses within an L2 mapping.
4471 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
4472 struct rwlock **lockp)
4474 pt_entry_t *l3, newl3, oldl2;
4476 vm_paddr_t l3phys, phys;
4480 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4482 oldl2 = pmap_load(l2);
4483 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
4484 ("pmap_demote_l2: Demoting a non-block entry"));
4485 KASSERT((va & L2_OFFSET) == 0,
4486 ("pmap_demote_l2: Invalid virtual address %#lx", va));
4489 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
4490 tmpl2 = kva_alloc(PAGE_SIZE);
4495 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
4496 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
4497 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4498 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
4500 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
4501 " in pmap %p", va, pmap);
4504 if (va < VM_MAXUSER_ADDRESS)
4505 pmap_resident_count_inc(pmap, 1);
4508 l3phys = VM_PAGE_TO_PHYS(ml3);
4509 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
4511 /* Address the range points at */
4512 phys = oldl2 & ~ATTR_MASK;
4513 /* The attributed from the old l2 table to be copied */
4514 newl3 = (oldl2 & (ATTR_MASK & ~ATTR_DESCR_MASK)) | L3_PAGE;
4517 * If the page table page is new, initialize it.
4519 if (ml3->wire_count == 1) {
4520 for (i = 0; i < Ln_ENTRIES; i++) {
4521 l3[i] = newl3 | phys;
4525 KASSERT(l3[0] == ((oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE),
4526 ("Invalid l3 page (%lx != %lx)", l3[0],
4527 (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE));
4530 * Map the temporary page so we don't lose access to the l2 table.
4533 pmap_kenter(tmpl2, PAGE_SIZE,
4534 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY);
4535 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
4539 * The spare PV entries must be reserved prior to demoting the
4540 * mapping, that is, prior to changing the PDE. Otherwise, the state
4541 * of the L2 and the PV lists will be inconsistent, which can result
4542 * in reclaim_pv_chunk() attempting to remove a PV entry from the
4543 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
4544 * PV entry for the 2MB page mapping that is being demoted.
4546 if ((oldl2 & ATTR_SW_MANAGED) != 0)
4547 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
4549 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
4552 * Demote the PV entry.
4554 if ((oldl2 & ATTR_SW_MANAGED) != 0)
4555 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
4557 atomic_add_long(&pmap_l2_demotions, 1);
4558 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
4559 " in pmap %p %lx", va, pmap, l3[0]);
4563 pmap_kremove(tmpl2);
4564 kva_free(tmpl2, PAGE_SIZE);
4572 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
4574 struct rwlock *lock;
4578 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
4585 * perform the pmap work for mincore
4588 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
4590 pd_entry_t *l1p, l1;
4591 pd_entry_t *l2p, l2;
4592 pt_entry_t *l3p, l3;
4603 l1p = pmap_l1(pmap, addr);
4604 if (l1p == NULL) /* No l1 */
4607 l1 = pmap_load(l1p);
4608 if ((l1 & ATTR_DESCR_MASK) == L1_INVAL)
4611 if ((l1 & ATTR_DESCR_MASK) == L1_BLOCK) {
4612 pa = (l1 & ~ATTR_MASK) | (addr & L1_OFFSET);
4613 managed = (l1 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4614 val = MINCORE_SUPER | MINCORE_INCORE;
4615 if (pmap_page_dirty(l1))
4616 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4617 if ((l1 & ATTR_AF) == ATTR_AF)
4618 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4622 l2p = pmap_l1_to_l2(l1p, addr);
4623 if (l2p == NULL) /* No l2 */
4626 l2 = pmap_load(l2p);
4627 if ((l2 & ATTR_DESCR_MASK) == L2_INVAL)
4630 if ((l2 & ATTR_DESCR_MASK) == L2_BLOCK) {
4631 pa = (l2 & ~ATTR_MASK) | (addr & L2_OFFSET);
4632 managed = (l2 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4633 val = MINCORE_SUPER | MINCORE_INCORE;
4634 if (pmap_page_dirty(l2))
4635 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4636 if ((l2 & ATTR_AF) == ATTR_AF)
4637 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4641 l3p = pmap_l2_to_l3(l2p, addr);
4642 if (l3p == NULL) /* No l3 */
4645 l3 = pmap_load(l2p);
4646 if ((l3 & ATTR_DESCR_MASK) == L3_INVAL)
4649 if ((l3 & ATTR_DESCR_MASK) == L3_PAGE) {
4650 pa = (l3 & ~ATTR_MASK) | (addr & L3_OFFSET);
4651 managed = (l3 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4652 val = MINCORE_INCORE;
4653 if (pmap_page_dirty(l3))
4654 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4655 if ((l3 & ATTR_AF) == ATTR_AF)
4656 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4660 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
4661 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
4662 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
4663 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
4666 PA_UNLOCK_COND(*locked_pa);
4673 pmap_activate(struct thread *td)
4678 pmap = vmspace_pmap(td->td_proc->p_vmspace);
4679 td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0);
4680 __asm __volatile("msr ttbr0_el1, %0" : :
4681 "r"(td->td_proc->p_md.md_l0addr));
4682 pmap_invalidate_all(pmap);
4687 pmap_switch(struct thread *old, struct thread *new)
4689 pcpu_bp_harden bp_harden;
4692 /* Store the new curthread */
4693 PCPU_SET(curthread, new);
4695 /* And the new pcb */
4697 PCPU_SET(curpcb, pcb);
4700 * TODO: We may need to flush the cache here if switching
4701 * to a user process.
4705 old->td_proc->p_md.md_l0addr != new->td_proc->p_md.md_l0addr) {
4707 /* Switch to the new pmap */
4708 "msr ttbr0_el1, %0 \n"
4711 /* Invalidate the TLB */
4716 : : "r"(new->td_proc->p_md.md_l0addr));
4719 * Stop userspace from training the branch predictor against
4720 * other processes. This will call into a CPU specific
4721 * function that clears the branch predictor state.
4723 bp_harden = PCPU_GET(bp_harden);
4724 if (bp_harden != NULL)
4732 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
4735 if (va >= VM_MIN_KERNEL_ADDRESS) {
4736 cpu_icache_sync_range(va, sz);
4741 /* Find the length of data in this page to flush */
4742 offset = va & PAGE_MASK;
4743 len = imin(PAGE_SIZE - offset, sz);
4746 /* Extract the physical address & find it in the DMAP */
4747 pa = pmap_extract(pmap, va);
4749 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
4751 /* Move to the next page */
4754 /* Set the length for the next iteration */
4755 len = imin(PAGE_SIZE, sz);
4761 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
4767 switch (ESR_ELx_EXCEPTION(esr)) {
4768 case EXCP_INSN_ABORT_L:
4769 case EXCP_INSN_ABORT:
4770 case EXCP_DATA_ABORT_L:
4771 case EXCP_DATA_ABORT:
4774 return (KERN_FAILURE);
4777 /* Data and insn aborts use same encoding for FCS field. */
4779 switch (esr & ISS_DATA_DFSC_MASK) {
4780 case ISS_DATA_DFSC_TF_L0:
4781 case ISS_DATA_DFSC_TF_L1:
4782 case ISS_DATA_DFSC_TF_L2:
4783 case ISS_DATA_DFSC_TF_L3:
4784 /* Ask the MMU to check the address */
4785 intr = intr_disable();
4786 if (pmap == kernel_pmap)
4787 par = arm64_address_translate_s1e1r(far);
4789 par = arm64_address_translate_s1e0r(far);
4793 * If the translation was successful the address was invalid
4794 * due to a break-before-make sequence. We can unlock and
4795 * return success to the trap handler.
4797 if (PAR_SUCCESS(par)) {
4799 return (KERN_SUCCESS);
4808 return (KERN_FAILURE);
4812 * Increase the starting virtual address of the given mapping if a
4813 * different alignment might result in more superpage mappings.
4816 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4817 vm_offset_t *addr, vm_size_t size)
4819 vm_offset_t superpage_offset;
4823 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
4824 offset += ptoa(object->pg_color);
4825 superpage_offset = offset & L2_OFFSET;
4826 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
4827 (*addr & L2_OFFSET) == superpage_offset)
4829 if ((*addr & L2_OFFSET) < superpage_offset)
4830 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
4832 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
4836 * Get the kernel virtual address of a set of physical pages. If there are
4837 * physical addresses not covered by the DMAP perform a transient mapping
4838 * that will be removed when calling pmap_unmap_io_transient.
4840 * \param page The pages the caller wishes to obtain the virtual
4841 * address on the kernel memory map.
4842 * \param vaddr On return contains the kernel virtual memory address
4843 * of the pages passed in the page parameter.
4844 * \param count Number of pages passed in.
4845 * \param can_fault TRUE if the thread using the mapped pages can take
4846 * page faults, FALSE otherwise.
4848 * \returns TRUE if the caller must call pmap_unmap_io_transient when
4849 * finished or FALSE otherwise.
4853 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
4854 boolean_t can_fault)
4857 boolean_t needs_mapping;
4861 * Allocate any KVA space that we need, this is done in a separate
4862 * loop to prevent calling vmem_alloc while pinned.
4864 needs_mapping = FALSE;
4865 for (i = 0; i < count; i++) {
4866 paddr = VM_PAGE_TO_PHYS(page[i]);
4867 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
4868 error = vmem_alloc(kernel_arena, PAGE_SIZE,
4869 M_BESTFIT | M_WAITOK, &vaddr[i]);
4870 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
4871 needs_mapping = TRUE;
4873 vaddr[i] = PHYS_TO_DMAP(paddr);
4877 /* Exit early if everything is covered by the DMAP */
4883 for (i = 0; i < count; i++) {
4884 paddr = VM_PAGE_TO_PHYS(page[i]);
4885 if (!PHYS_IN_DMAP(paddr)) {
4887 "pmap_map_io_transient: TODO: Map out of DMAP data");
4891 return (needs_mapping);
4895 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
4896 boolean_t can_fault)
4903 for (i = 0; i < count; i++) {
4904 paddr = VM_PAGE_TO_PHYS(page[i]);
4905 if (!PHYS_IN_DMAP(paddr)) {
4906 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");