2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/asan.h>
112 #include <sys/bitstring.h>
114 #include <sys/systm.h>
115 #include <sys/kernel.h>
117 #include <sys/limits.h>
118 #include <sys/lock.h>
119 #include <sys/malloc.h>
120 #include <sys/mman.h>
121 #include <sys/msgbuf.h>
122 #include <sys/mutex.h>
123 #include <sys/physmem.h>
124 #include <sys/proc.h>
125 #include <sys/rwlock.h>
126 #include <sys/sbuf.h>
128 #include <sys/vmem.h>
129 #include <sys/vmmeter.h>
130 #include <sys/sched.h>
131 #include <sys/sysctl.h>
132 #include <sys/_unrhdr.h>
136 #include <vm/vm_param.h>
137 #include <vm/vm_kern.h>
138 #include <vm/vm_page.h>
139 #include <vm/vm_map.h>
140 #include <vm/vm_object.h>
141 #include <vm/vm_extern.h>
142 #include <vm/vm_pageout.h>
143 #include <vm/vm_pager.h>
144 #include <vm/vm_phys.h>
145 #include <vm/vm_radix.h>
146 #include <vm/vm_reserv.h>
147 #include <vm/vm_dumpset.h>
150 #include <machine/asan.h>
151 #include <machine/machdep.h>
152 #include <machine/md_var.h>
153 #include <machine/pcb.h>
156 #define PMAP_MEMDOM MAXMEMDOM
158 #define PMAP_MEMDOM 1
161 #define PMAP_ASSERT_STAGE1(pmap) MPASS((pmap)->pm_stage == PM_STAGE1)
162 #define PMAP_ASSERT_STAGE2(pmap) MPASS((pmap)->pm_stage == PM_STAGE2)
164 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
165 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
166 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
167 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
169 #define NUL0E L0_ENTRIES
170 #define NUL1E (NUL0E * NL1PG)
171 #define NUL2E (NUL1E * NL2PG)
173 #if !defined(DIAGNOSTIC)
174 #ifdef __GNUC_GNU_INLINE__
175 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
177 #define PMAP_INLINE extern inline
184 #define PV_STAT(x) do { x ; } while (0)
187 #define PV_STAT(x) do { } while (0)
188 #define __pvused __unused
191 #define pmap_l0_pindex(v) (NUL2E + NUL1E + ((v) >> L0_SHIFT))
192 #define pmap_l1_pindex(v) (NUL2E + ((v) >> L1_SHIFT))
193 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
195 #define PMAP_SAN_PTE_BITS (ATTR_DEFAULT | ATTR_S1_XN | \
196 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | ATTR_S1_AP(ATTR_S1_AP_RW))
198 struct pmap_large_md_page {
199 struct rwlock pv_lock;
200 struct md_page pv_page;
201 /* Pad to a power of 2, see pmap_init_pv_table(). */
205 static struct pmap_large_md_page *
206 _pa_to_pmdp(vm_paddr_t pa)
208 struct vm_phys_seg *seg;
211 for (segind = 0; segind < vm_phys_nsegs; segind++) {
212 seg = &vm_phys_segs[segind];
213 if (pa >= seg->start && pa < seg->end)
214 return ((struct pmap_large_md_page *)seg->md_first +
215 pmap_l2_pindex(pa) - pmap_l2_pindex(seg->start));
220 static struct pmap_large_md_page *
221 pa_to_pmdp(vm_paddr_t pa)
223 struct pmap_large_md_page *pvd;
225 pvd = _pa_to_pmdp(pa);
227 panic("pa 0x%jx not within vm_phys_segs", (uintmax_t)pa);
231 static struct pmap_large_md_page *
232 page_to_pmdp(vm_page_t m)
234 struct vm_phys_seg *seg;
236 seg = &vm_phys_segs[m->segind];
237 return ((struct pmap_large_md_page *)seg->md_first +
238 pmap_l2_pindex(VM_PAGE_TO_PHYS(m)) - pmap_l2_pindex(seg->start));
241 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
242 #define page_to_pvh(m) (&(page_to_pmdp(m)->pv_page))
244 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
245 struct pmap_large_md_page *_pvd; \
246 struct rwlock *_lock; \
247 _pvd = _pa_to_pmdp(pa); \
248 if (__predict_false(_pvd == NULL)) \
249 _lock = &pv_dummy_large.pv_lock; \
251 _lock = &(_pvd->pv_lock); \
255 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
256 struct rwlock **_lockp = (lockp); \
257 struct rwlock *_new_lock; \
259 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
260 if (_new_lock != *_lockp) { \
261 if (*_lockp != NULL) \
262 rw_wunlock(*_lockp); \
263 *_lockp = _new_lock; \
268 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
269 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
271 #define RELEASE_PV_LIST_LOCK(lockp) do { \
272 struct rwlock **_lockp = (lockp); \
274 if (*_lockp != NULL) { \
275 rw_wunlock(*_lockp); \
280 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
281 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
284 * The presence of this flag indicates that the mapping is writeable.
285 * If the ATTR_S1_AP_RO bit is also set, then the mapping is clean, otherwise
286 * it is dirty. This flag may only be set on managed mappings.
288 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
289 * as a software managed bit.
291 #define ATTR_SW_DBM ATTR_DBM
293 struct pmap kernel_pmap_store;
295 /* Used for mapping ACPI memory before VM is initialized */
296 #define PMAP_PREINIT_MAPPING_COUNT 32
297 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
298 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
299 static int vm_initialized = 0; /* No need to use pre-init maps when set */
302 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
303 * Always map entire L2 block for simplicity.
304 * VA of L2 block = preinit_map_va + i * L2_SIZE
306 static struct pmap_preinit_mapping {
310 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
312 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
313 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
314 vm_offset_t kernel_vm_end = 0;
317 * Data for the pv entry allocation mechanism.
321 pc_to_domain(struct pv_chunk *pc)
323 return (vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
327 pc_to_domain(struct pv_chunk *pc __unused)
333 struct pv_chunks_list {
335 TAILQ_HEAD(pch, pv_chunk) pvc_list;
337 } __aligned(CACHE_LINE_SIZE);
339 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
341 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
342 #define pv_dummy pv_dummy_large.pv_page
343 __read_mostly static struct pmap_large_md_page *pv_table;
344 __read_mostly vm_paddr_t pmap_last_pa;
346 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
347 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
348 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
350 extern pt_entry_t pagetable_l0_ttbr1[];
352 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
353 static vm_paddr_t physmap[PHYSMAP_SIZE];
354 static u_int physmap_idx;
356 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
357 "VM/pmap parameters");
359 #if PAGE_SIZE == PAGE_SIZE_4K
360 #define L1_BLOCKS_SUPPORTED 1
362 /* TODO: Make this dynamic when we support FEAT_LPA2 (TCR_EL1.DS == 1) */
363 #define L1_BLOCKS_SUPPORTED 0
366 #define PMAP_ASSERT_L1_BLOCKS_SUPPORTED MPASS(L1_BLOCKS_SUPPORTED)
369 * This ASID allocator uses a bit vector ("asid_set") to remember which ASIDs
370 * that it has currently allocated to a pmap, a cursor ("asid_next") to
371 * optimize its search for a free ASID in the bit vector, and an epoch number
372 * ("asid_epoch") to indicate when it has reclaimed all previously allocated
373 * ASIDs that are not currently active on a processor.
375 * The current epoch number is always in the range [0, INT_MAX). Negative
376 * numbers and INT_MAX are reserved for special cases that are described
385 struct mtx asid_set_mutex;
388 static struct asid_set asids;
389 static struct asid_set vmids;
391 static SYSCTL_NODE(_vm_pmap, OID_AUTO, asid, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
393 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, bits, CTLFLAG_RD, &asids.asid_bits, 0,
394 "The number of bits in an ASID");
395 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, next, CTLFLAG_RD, &asids.asid_next, 0,
396 "The last allocated ASID plus one");
397 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, epoch, CTLFLAG_RD, &asids.asid_epoch, 0,
398 "The current epoch number");
400 static SYSCTL_NODE(_vm_pmap, OID_AUTO, vmid, CTLFLAG_RD, 0, "VMID allocator");
401 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, bits, CTLFLAG_RD, &vmids.asid_bits, 0,
402 "The number of bits in an VMID");
403 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, next, CTLFLAG_RD, &vmids.asid_next, 0,
404 "The last allocated VMID plus one");
405 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, epoch, CTLFLAG_RD, &vmids.asid_epoch, 0,
406 "The current epoch number");
408 void (*pmap_clean_stage2_tlbi)(void);
409 void (*pmap_invalidate_vpipt_icache)(void);
410 void (*pmap_stage2_invalidate_range)(uint64_t, vm_offset_t, vm_offset_t, bool);
411 void (*pmap_stage2_invalidate_all)(uint64_t);
414 * A pmap's cookie encodes an ASID and epoch number. Cookies for reserved
415 * ASIDs have a negative epoch number, specifically, INT_MIN. Cookies for
416 * dynamically allocated ASIDs have a non-negative epoch number.
418 * An invalid ASID is represented by -1.
420 * There are two special-case cookie values: (1) COOKIE_FROM(-1, INT_MIN),
421 * which indicates that an ASID should never be allocated to the pmap, and
422 * (2) COOKIE_FROM(-1, INT_MAX), which indicates that an ASID should be
423 * allocated when the pmap is next activated.
425 #define COOKIE_FROM(asid, epoch) ((long)((u_int)(asid) | \
426 ((u_long)(epoch) << 32)))
427 #define COOKIE_TO_ASID(cookie) ((int)(cookie))
428 #define COOKIE_TO_EPOCH(cookie) ((int)((u_long)(cookie) >> 32))
430 #define TLBI_VA_SHIFT 12
431 #define TLBI_VA_MASK ((1ul << 44) - 1)
432 #define TLBI_VA(addr) (((addr) >> TLBI_VA_SHIFT) & TLBI_VA_MASK)
433 #define TLBI_VA_L3_INCR (L3_SIZE >> TLBI_VA_SHIFT)
435 static int superpages_enabled = 1;
436 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
437 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
438 "Are large page mappings enabled?");
441 * Internal flags for pmap_enter()'s helper functions.
443 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
444 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
446 TAILQ_HEAD(pv_chunklist, pv_chunk);
448 static void free_pv_chunk(struct pv_chunk *pc);
449 static void free_pv_chunk_batch(struct pv_chunklist *batch);
450 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
451 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
452 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
453 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
454 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
457 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
458 static bool pmap_activate_int(pmap_t pmap);
459 static void pmap_alloc_asid(pmap_t pmap);
460 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
461 vm_prot_t prot, int mode, bool skip_unmapped);
462 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
463 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
464 vm_offset_t va, struct rwlock **lockp);
465 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
466 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
467 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
468 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
469 u_int flags, vm_page_t m, struct rwlock **lockp);
470 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
471 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
472 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
473 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
474 static void pmap_reset_asid_set(pmap_t pmap);
475 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
476 vm_page_t m, struct rwlock **lockp);
478 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
479 struct rwlock **lockp);
481 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
482 struct spglist *free);
483 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
484 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
487 * These load the old table data and store the new value.
488 * They need to be atomic as the System MMU may write to the table at
489 * the same time as the CPU.
491 #define pmap_clear(table) atomic_store_64(table, 0)
492 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
493 #define pmap_load(table) (*table)
494 #define pmap_load_clear(table) atomic_swap_64(table, 0)
495 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
496 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
497 #define pmap_store(table, entry) atomic_store_64(table, entry)
499 /********************/
500 /* Inline functions */
501 /********************/
504 pagecopy(void *s, void *d)
507 memcpy(d, s, PAGE_SIZE);
510 static __inline pd_entry_t *
511 pmap_l0(pmap_t pmap, vm_offset_t va)
514 return (&pmap->pm_l0[pmap_l0_index(va)]);
517 static __inline pd_entry_t *
518 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
522 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
523 return (&l1[pmap_l1_index(va)]);
526 static __inline pd_entry_t *
527 pmap_l1(pmap_t pmap, vm_offset_t va)
531 l0 = pmap_l0(pmap, va);
532 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
535 return (pmap_l0_to_l1(l0, va));
538 static __inline pd_entry_t *
539 pmap_l1_to_l2(pd_entry_t *l1p, vm_offset_t va)
545 KASSERT(ADDR_IS_CANONICAL(va),
546 ("%s: Address not in canonical form: %lx", __func__, va));
548 * The valid bit may be clear if pmap_update_entry() is concurrently
549 * modifying the entry, so for KVA only the entry type may be checked.
551 KASSERT(ADDR_IS_KERNEL(va) || (l1 & ATTR_DESCR_VALID) != 0,
552 ("%s: L1 entry %#lx for %#lx is invalid", __func__, l1, va));
553 KASSERT((l1 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE,
554 ("%s: L1 entry %#lx for %#lx is a leaf", __func__, l1, va));
555 l2p = (pd_entry_t *)PHYS_TO_DMAP(l1 & ~ATTR_MASK);
556 return (&l2p[pmap_l2_index(va)]);
559 static __inline pd_entry_t *
560 pmap_l2(pmap_t pmap, vm_offset_t va)
564 l1 = pmap_l1(pmap, va);
565 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
568 return (pmap_l1_to_l2(l1, va));
571 static __inline pt_entry_t *
572 pmap_l2_to_l3(pd_entry_t *l2p, vm_offset_t va)
579 KASSERT(ADDR_IS_CANONICAL(va),
580 ("%s: Address not in canonical form: %lx", __func__, va));
582 * The valid bit may be clear if pmap_update_entry() is concurrently
583 * modifying the entry, so for KVA only the entry type may be checked.
585 KASSERT(ADDR_IS_KERNEL(va) || (l2 & ATTR_DESCR_VALID) != 0,
586 ("%s: L2 entry %#lx for %#lx is invalid", __func__, l2, va));
587 KASSERT((l2 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE,
588 ("%s: L2 entry %#lx for %#lx is a leaf", __func__, l2, va));
589 l3p = (pt_entry_t *)PHYS_TO_DMAP(l2 & ~ATTR_MASK);
590 return (&l3p[pmap_l3_index(va)]);
594 * Returns the lowest valid pde for a given virtual address.
595 * The next level may or may not point to a valid page or block.
597 static __inline pd_entry_t *
598 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
600 pd_entry_t *l0, *l1, *l2, desc;
602 l0 = pmap_l0(pmap, va);
603 desc = pmap_load(l0) & ATTR_DESCR_MASK;
604 if (desc != L0_TABLE) {
609 l1 = pmap_l0_to_l1(l0, va);
610 desc = pmap_load(l1) & ATTR_DESCR_MASK;
611 if (desc != L1_TABLE) {
616 l2 = pmap_l1_to_l2(l1, va);
617 desc = pmap_load(l2) & ATTR_DESCR_MASK;
618 if (desc != L2_TABLE) {
628 * Returns the lowest valid pte block or table entry for a given virtual
629 * address. If there are no valid entries return NULL and set the level to
630 * the first invalid level.
632 static __inline pt_entry_t *
633 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
635 pd_entry_t *l1, *l2, desc;
638 l1 = pmap_l1(pmap, va);
643 desc = pmap_load(l1) & ATTR_DESCR_MASK;
644 if (desc == L1_BLOCK) {
645 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
650 if (desc != L1_TABLE) {
655 l2 = pmap_l1_to_l2(l1, va);
656 desc = pmap_load(l2) & ATTR_DESCR_MASK;
657 if (desc == L2_BLOCK) {
662 if (desc != L2_TABLE) {
668 l3 = pmap_l2_to_l3(l2, va);
669 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
676 * If the given pmap has an L{1,2}_BLOCK or L3_PAGE entry at the specified
677 * level that maps the specified virtual address, then a pointer to that entry
678 * is returned. Otherwise, NULL is returned, unless INVARIANTS are enabled
679 * and a diagnostic message is provided, in which case this function panics.
681 static __always_inline pt_entry_t *
682 pmap_pte_exists(pmap_t pmap, vm_offset_t va, int level, const char *diag)
684 pd_entry_t *l0p, *l1p, *l2p;
685 pt_entry_t desc, *l3p;
686 int walk_level __diagused;
688 KASSERT(level >= 0 && level < 4,
689 ("%s: %s passed an out-of-range level (%d)", __func__, diag,
691 l0p = pmap_l0(pmap, va);
692 desc = pmap_load(l0p) & ATTR_DESCR_MASK;
693 if (desc == L0_TABLE && level > 0) {
694 l1p = pmap_l0_to_l1(l0p, va);
695 desc = pmap_load(l1p) & ATTR_DESCR_MASK;
696 if (desc == L1_BLOCK && level == 1) {
697 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
700 if (desc == L1_TABLE && level > 1) {
701 l2p = pmap_l1_to_l2(l1p, va);
702 desc = pmap_load(l2p) & ATTR_DESCR_MASK;
703 if (desc == L2_BLOCK && level == 2)
705 else if (desc == L2_TABLE && level > 2) {
706 l3p = pmap_l2_to_l3(l2p, va);
707 desc = pmap_load(l3p) & ATTR_DESCR_MASK;
708 if (desc == L3_PAGE && level == 3)
718 KASSERT(diag == NULL,
719 ("%s: va %#lx not mapped at level %d, desc %ld at level %d",
720 diag, va, level, desc, walk_level));
725 pmap_ps_enabled(pmap_t pmap)
728 * Promotion requires a hypervisor call when the kernel is running
729 * in EL1. To stop this disable superpage support on non-stage 1
732 if (pmap->pm_stage != PM_STAGE1)
735 return (superpages_enabled != 0);
739 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
740 pd_entry_t **l2, pt_entry_t **l3)
742 pd_entry_t *l0p, *l1p, *l2p;
744 if (pmap->pm_l0 == NULL)
747 l0p = pmap_l0(pmap, va);
750 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
753 l1p = pmap_l0_to_l1(l0p, va);
756 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
757 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
763 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
766 l2p = pmap_l1_to_l2(l1p, va);
769 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
774 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
777 *l3 = pmap_l2_to_l3(l2p, va);
783 pmap_l3_valid(pt_entry_t l3)
786 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
789 CTASSERT(L1_BLOCK == L2_BLOCK);
792 pmap_pte_memattr(pmap_t pmap, vm_memattr_t memattr)
796 if (pmap->pm_stage == PM_STAGE1) {
797 val = ATTR_S1_IDX(memattr);
798 if (memattr == VM_MEMATTR_DEVICE)
806 case VM_MEMATTR_DEVICE:
807 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_DEVICE_nGnRnE) |
808 ATTR_S2_XN(ATTR_S2_XN_ALL));
809 case VM_MEMATTR_UNCACHEABLE:
810 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_NC));
811 case VM_MEMATTR_WRITE_BACK:
812 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WB));
813 case VM_MEMATTR_WRITE_THROUGH:
814 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WT));
816 panic("%s: invalid memory attribute %x", __func__, memattr);
821 pmap_pte_prot(pmap_t pmap, vm_prot_t prot)
826 if (pmap->pm_stage == PM_STAGE1) {
827 if ((prot & VM_PROT_EXECUTE) == 0)
829 if ((prot & VM_PROT_WRITE) == 0)
830 val |= ATTR_S1_AP(ATTR_S1_AP_RO);
832 if ((prot & VM_PROT_WRITE) != 0)
833 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
834 if ((prot & VM_PROT_READ) != 0)
835 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_READ);
836 if ((prot & VM_PROT_EXECUTE) == 0)
837 val |= ATTR_S2_XN(ATTR_S2_XN_ALL);
844 * Checks if the PTE is dirty.
847 pmap_pte_dirty(pmap_t pmap, pt_entry_t pte)
850 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
852 if (pmap->pm_stage == PM_STAGE1) {
853 KASSERT((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) != 0,
854 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
856 return ((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
857 (ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_SW_DBM));
860 return ((pte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
861 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE));
865 pmap_resident_count_inc(pmap_t pmap, int count)
868 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
869 pmap->pm_stats.resident_count += count;
873 pmap_resident_count_dec(pmap_t pmap, int count)
876 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
877 KASSERT(pmap->pm_stats.resident_count >= count,
878 ("pmap %p resident count underflow %ld %d", pmap,
879 pmap->pm_stats.resident_count, count));
880 pmap->pm_stats.resident_count -= count;
884 pmap_early_vtophys(vm_offset_t va)
888 pa_page = arm64_address_translate_s1e1r(va) & PAR_PA_MASK;
889 return (pa_page | (va & PAR_LOW_MASK));
892 /* State of the bootstrapped DMAP page tables */
893 struct pmap_bootstrap_state {
897 vm_offset_t freemempos;
900 pt_entry_t table_attrs;
907 /* The bootstrap state */
908 static struct pmap_bootstrap_state bs_state = {
912 .table_attrs = TATTR_PXN_TABLE,
913 .l0_slot = L0_ENTRIES,
914 .l1_slot = Ln_ENTRIES,
915 .l2_slot = Ln_ENTRIES,
920 pmap_bootstrap_l0_table(struct pmap_bootstrap_state *state)
926 /* Link the level 0 table to a level 1 table */
927 l0_slot = pmap_l0_index(state->va);
928 if (l0_slot != state->l0_slot) {
930 * Make sure we move from a low address to high address
931 * before the DMAP region is ready. This ensures we never
932 * modify an existing mapping until we can map from a
933 * physical address to a virtual address.
935 MPASS(state->l0_slot < l0_slot ||
936 state->l0_slot == L0_ENTRIES ||
939 /* Reset lower levels */
942 state->l1_slot = Ln_ENTRIES;
943 state->l2_slot = Ln_ENTRIES;
945 /* Check the existing L0 entry */
946 state->l0_slot = l0_slot;
947 if (state->dmap_valid) {
948 l0e = pagetable_l0_ttbr1[l0_slot];
949 if ((l0e & ATTR_DESCR_VALID) != 0) {
950 MPASS((l0e & ATTR_DESCR_MASK) == L0_TABLE);
951 l1_pa = l0e & ~ATTR_MASK;
952 state->l1 = (pt_entry_t *)PHYS_TO_DMAP(l1_pa);
957 /* Create a new L0 table entry */
958 state->l1 = (pt_entry_t *)state->freemempos;
959 memset(state->l1, 0, PAGE_SIZE);
960 state->freemempos += PAGE_SIZE;
962 l1_pa = pmap_early_vtophys((vm_offset_t)state->l1);
963 MPASS((l1_pa & Ln_TABLE_MASK) == 0);
964 MPASS(pagetable_l0_ttbr1[l0_slot] == 0);
965 pmap_store(&pagetable_l0_ttbr1[l0_slot], l1_pa |
966 TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0 | L0_TABLE);
968 KASSERT(state->l1 != NULL, ("%s: NULL l1", __func__));
972 pmap_bootstrap_l1_table(struct pmap_bootstrap_state *state)
978 /* Make sure there is a valid L0 -> L1 table */
979 pmap_bootstrap_l0_table(state);
981 /* Link the level 1 table to a level 2 table */
982 l1_slot = pmap_l1_index(state->va);
983 if (l1_slot != state->l1_slot) {
984 /* See pmap_bootstrap_l0_table for a description */
985 MPASS(state->l1_slot < l1_slot ||
986 state->l1_slot == Ln_ENTRIES ||
989 /* Reset lower levels */
991 state->l2_slot = Ln_ENTRIES;
993 /* Check the existing L1 entry */
994 state->l1_slot = l1_slot;
995 if (state->dmap_valid) {
996 l1e = state->l1[l1_slot];
997 if ((l1e & ATTR_DESCR_VALID) != 0) {
998 MPASS((l1e & ATTR_DESCR_MASK) == L1_TABLE);
999 l2_pa = l1e & ~ATTR_MASK;
1000 state->l2 = (pt_entry_t *)PHYS_TO_DMAP(l2_pa);
1005 /* Create a new L1 table entry */
1006 state->l2 = (pt_entry_t *)state->freemempos;
1007 memset(state->l2, 0, PAGE_SIZE);
1008 state->freemempos += PAGE_SIZE;
1010 l2_pa = pmap_early_vtophys((vm_offset_t)state->l2);
1011 MPASS((l2_pa & Ln_TABLE_MASK) == 0);
1012 MPASS(state->l1[l1_slot] == 0);
1013 pmap_store(&state->l1[l1_slot], l2_pa | state->table_attrs |
1016 KASSERT(state->l2 != NULL, ("%s: NULL l2", __func__));
1020 pmap_bootstrap_l2_table(struct pmap_bootstrap_state *state)
1026 /* Make sure there is a valid L1 -> L2 table */
1027 pmap_bootstrap_l1_table(state);
1029 /* Link the level 2 table to a level 3 table */
1030 l2_slot = pmap_l2_index(state->va);
1031 if (l2_slot != state->l2_slot) {
1032 /* See pmap_bootstrap_l0_table for a description */
1033 MPASS(state->l2_slot < l2_slot ||
1034 state->l2_slot == Ln_ENTRIES ||
1037 /* Check the existing L2 entry */
1038 state->l2_slot = l2_slot;
1039 if (state->dmap_valid) {
1040 l2e = state->l2[l2_slot];
1041 if ((l2e & ATTR_DESCR_VALID) != 0) {
1042 MPASS((l2e & ATTR_DESCR_MASK) == L2_TABLE);
1043 l3_pa = l2e & ~ATTR_MASK;
1044 state->l3 = (pt_entry_t *)PHYS_TO_DMAP(l3_pa);
1049 /* Create a new L2 table entry */
1050 state->l3 = (pt_entry_t *)state->freemempos;
1051 memset(state->l3, 0, PAGE_SIZE);
1052 state->freemempos += PAGE_SIZE;
1054 l3_pa = pmap_early_vtophys((vm_offset_t)state->l3);
1055 MPASS((l3_pa & Ln_TABLE_MASK) == 0);
1056 MPASS(state->l2[l2_slot] == 0);
1057 pmap_store(&state->l2[l2_slot], l3_pa | state->table_attrs |
1060 KASSERT(state->l3 != NULL, ("%s: NULL l3", __func__));
1064 pmap_bootstrap_l2_block(struct pmap_bootstrap_state *state, int i)
1069 if ((physmap[i + 1] - state->pa) < L2_SIZE)
1072 /* Make sure there is a valid L1 table */
1073 pmap_bootstrap_l1_table(state);
1075 MPASS((state->va & L2_OFFSET) == 0);
1077 state->va < DMAP_MAX_ADDRESS &&
1078 (physmap[i + 1] - state->pa) >= L2_SIZE;
1079 state->va += L2_SIZE, state->pa += L2_SIZE) {
1081 * Stop if we are about to walk off the end of what the
1082 * current L1 slot can address.
1084 if (!first && (state->pa & L1_OFFSET) == 0)
1088 l2_slot = pmap_l2_index(state->va);
1089 MPASS((state->pa & L2_OFFSET) == 0);
1090 MPASS(state->l2[l2_slot] == 0);
1091 pmap_store(&state->l2[l2_slot], state->pa | ATTR_DEFAULT |
1092 ATTR_S1_XN | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
1095 MPASS(state->va == (state->pa - dmap_phys_base + DMAP_MIN_ADDRESS));
1099 pmap_bootstrap_l3_page(struct pmap_bootstrap_state *state, int i)
1104 if ((physmap[i + 1] - state->pa) < L3_SIZE)
1107 /* Make sure there is a valid L2 table */
1108 pmap_bootstrap_l2_table(state);
1110 MPASS((state->va & L3_OFFSET) == 0);
1112 state->va < DMAP_MAX_ADDRESS &&
1113 (physmap[i + 1] - state->pa) >= L3_SIZE;
1114 state->va += L3_SIZE, state->pa += L3_SIZE) {
1116 * Stop if we are about to walk off the end of what the
1117 * current L2 slot can address.
1119 if (!first && (state->pa & L2_OFFSET) == 0)
1123 l3_slot = pmap_l3_index(state->va);
1124 MPASS((state->pa & L3_OFFSET) == 0);
1125 MPASS(state->l3[l3_slot] == 0);
1126 pmap_store(&state->l3[l3_slot], state->pa | ATTR_DEFAULT |
1127 ATTR_S1_XN | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
1130 MPASS(state->va == (state->pa - dmap_phys_base + DMAP_MIN_ADDRESS));
1134 pmap_bootstrap_dmap(vm_paddr_t min_pa)
1138 dmap_phys_base = min_pa & ~L1_OFFSET;
1142 for (i = 0; i < (physmap_idx * 2); i += 2) {
1143 bs_state.pa = physmap[i] & ~L3_OFFSET;
1144 bs_state.va = bs_state.pa - dmap_phys_base + DMAP_MIN_ADDRESS;
1146 /* Create L3 mappings at the start of the region */
1147 if ((bs_state.pa & L2_OFFSET) != 0)
1148 pmap_bootstrap_l3_page(&bs_state, i);
1149 MPASS(bs_state.pa <= physmap[i + 1]);
1151 if (L1_BLOCKS_SUPPORTED) {
1152 /* Create L2 mappings at the start of the region */
1153 if ((bs_state.pa & L1_OFFSET) != 0)
1154 pmap_bootstrap_l2_block(&bs_state, i);
1155 MPASS(bs_state.pa <= physmap[i + 1]);
1157 /* Create the main L1 block mappings */
1158 for (; bs_state.va < DMAP_MAX_ADDRESS &&
1159 (physmap[i + 1] - bs_state.pa) >= L1_SIZE;
1160 bs_state.va += L1_SIZE, bs_state.pa += L1_SIZE) {
1161 /* Make sure there is a valid L1 table */
1162 pmap_bootstrap_l0_table(&bs_state);
1163 MPASS((bs_state.pa & L1_OFFSET) == 0);
1165 &bs_state.l1[pmap_l1_index(bs_state.va)],
1166 bs_state.pa | ATTR_DEFAULT | ATTR_S1_XN |
1167 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
1170 MPASS(bs_state.pa <= physmap[i + 1]);
1172 /* Create L2 mappings at the end of the region */
1173 pmap_bootstrap_l2_block(&bs_state, i);
1175 while (bs_state.va < DMAP_MAX_ADDRESS &&
1176 (physmap[i + 1] - bs_state.pa) >= L2_SIZE) {
1177 pmap_bootstrap_l2_block(&bs_state, i);
1180 MPASS(bs_state.pa <= physmap[i + 1]);
1182 /* Create L3 mappings at the end of the region */
1183 pmap_bootstrap_l3_page(&bs_state, i);
1184 MPASS(bs_state.pa == physmap[i + 1]);
1186 if (bs_state.pa > dmap_phys_max) {
1187 dmap_phys_max = bs_state.pa;
1188 dmap_max_addr = bs_state.va;
1196 pmap_bootstrap_l2(vm_offset_t va)
1198 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
1200 /* Leave bs_state.pa as it's only needed to bootstrap blocks and pages*/
1203 for (; bs_state.va < VM_MAX_KERNEL_ADDRESS; bs_state.va += L1_SIZE)
1204 pmap_bootstrap_l1_table(&bs_state);
1208 pmap_bootstrap_l3(vm_offset_t va)
1210 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
1212 /* Leave bs_state.pa as it's only needed to bootstrap blocks and pages*/
1215 for (; bs_state.va < VM_MAX_KERNEL_ADDRESS; bs_state.va += L2_SIZE)
1216 pmap_bootstrap_l2_table(&bs_state);
1221 pmap_bootstrap_allocate_kasan_l2(vm_paddr_t start_pa, vm_paddr_t end_pa,
1222 vm_offset_t *start_va, int *nkasan_l2)
1230 pa = rounddown2(end_pa - L2_SIZE, L2_SIZE);
1231 l2 = pmap_l2(kernel_pmap, va);
1233 for (i = 0; pa >= start_pa && i < *nkasan_l2;
1234 i++, va += L2_SIZE, pa -= L2_SIZE, l2++) {
1236 * KASAN stack checking results in us having already allocated
1237 * part of our shadow map, so we can just skip those segments.
1239 if ((pmap_load(l2) & ATTR_DESCR_VALID) != 0) {
1244 pmap_store(l2, (pa & ~Ln_TABLE_MASK) | PMAP_SAN_PTE_BITS |
1249 * Ended the allocation due to start_pa constraint, rather than because
1250 * we allocated everything. Adjust back up to the start_pa and remove
1251 * the invalid L2 block from our accounting.
1253 if (pa < start_pa) {
1259 bzero((void *)PHYS_TO_DMAP(pa), i * L2_SIZE);
1260 physmem_exclude_region(pa, i * L2_SIZE, EXFLAG_NOALLOC);
1268 * Bootstrap the system enough to run with virtual memory.
1271 pmap_bootstrap(vm_paddr_t kernstart, vm_size_t kernlen)
1273 vm_offset_t dpcpu, msgbufpv;
1274 vm_paddr_t start_pa, pa, min_pa;
1275 uint64_t kern_delta;
1278 /* Verify that the ASID is set through TTBR0. */
1279 KASSERT((READ_SPECIALREG(tcr_el1) & TCR_A1) == 0,
1280 ("pmap_bootstrap: TCR_EL1.A1 != 0"));
1282 kern_delta = KERNBASE - kernstart;
1284 printf("pmap_bootstrap %lx %lx\n", kernstart, kernlen);
1285 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
1287 /* Set this early so we can use the pagetable walking functions */
1288 kernel_pmap_store.pm_l0 = pagetable_l0_ttbr1;
1289 PMAP_LOCK_INIT(kernel_pmap);
1290 kernel_pmap->pm_l0_paddr =
1291 pmap_early_vtophys((vm_offset_t)kernel_pmap_store.pm_l0);
1292 kernel_pmap->pm_cookie = COOKIE_FROM(-1, INT_MIN);
1293 kernel_pmap->pm_stage = PM_STAGE1;
1294 kernel_pmap->pm_levels = 4;
1295 kernel_pmap->pm_ttbr = kernel_pmap->pm_l0_paddr;
1296 kernel_pmap->pm_asid_set = &asids;
1298 /* Assume the address we were loaded to is a valid physical address */
1299 min_pa = KERNBASE - kern_delta;
1301 physmap_idx = physmem_avail(physmap, nitems(physmap));
1305 * Find the minimum physical address. physmap is sorted,
1306 * but may contain empty ranges.
1308 for (i = 0; i < physmap_idx * 2; i += 2) {
1309 if (physmap[i] == physmap[i + 1])
1311 if (physmap[i] <= min_pa)
1312 min_pa = physmap[i];
1315 bs_state.freemempos = KERNBASE + kernlen;
1316 bs_state.freemempos = roundup2(bs_state.freemempos, PAGE_SIZE);
1318 /* Create a direct map region early so we can use it for pa -> va */
1319 pmap_bootstrap_dmap(min_pa);
1320 bs_state.dmap_valid = true;
1322 * We only use PXN when we know nothing will be executed from it, e.g.
1325 bs_state.table_attrs &= ~TATTR_PXN_TABLE;
1327 start_pa = pa = KERNBASE - kern_delta;
1330 * Create the l2 tables up to VM_MAX_KERNEL_ADDRESS. We assume that the
1331 * loader allocated the first and only l2 page table page used to map
1332 * the kernel, preloaded files and module metadata.
1334 pmap_bootstrap_l2(KERNBASE + L1_SIZE);
1335 /* And the l3 tables for the early devmap */
1336 pmap_bootstrap_l3(VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE));
1340 #define alloc_pages(var, np) \
1341 (var) = bs_state.freemempos; \
1342 bs_state.freemempos += (np * PAGE_SIZE); \
1343 memset((char *)(var), 0, ((np) * PAGE_SIZE));
1345 /* Allocate dynamic per-cpu area. */
1346 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
1347 dpcpu_init((void *)dpcpu, 0);
1349 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
1350 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
1351 msgbufp = (void *)msgbufpv;
1353 /* Reserve some VA space for early BIOS/ACPI mapping */
1354 preinit_map_va = roundup2(bs_state.freemempos, L2_SIZE);
1356 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
1357 virtual_avail = roundup2(virtual_avail, L1_SIZE);
1358 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
1359 kernel_vm_end = virtual_avail;
1361 pa = pmap_early_vtophys(bs_state.freemempos);
1363 physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
1370 * Finish constructing the initial shadow map:
1371 * - Count how many pages from KERNBASE to virtual_avail (scaled for
1373 * - Map that entire range using L2 superpages.
1376 pmap_bootstrap_san(vm_paddr_t kernstart)
1379 int i, shadow_npages, nkasan_l2;
1382 * Rebuild physmap one more time, we may have excluded more regions from
1383 * allocation since pmap_bootstrap().
1385 bzero(physmap, sizeof(physmap));
1386 physmap_idx = physmem_avail(physmap, nitems(physmap));
1389 shadow_npages = (virtual_avail - VM_MIN_KERNEL_ADDRESS) / PAGE_SIZE;
1390 shadow_npages = howmany(shadow_npages, KASAN_SHADOW_SCALE);
1391 nkasan_l2 = howmany(shadow_npages, Ln_ENTRIES);
1393 /* Map the valid KVA up to this point. */
1394 va = KASAN_MIN_ADDRESS;
1397 * Find a slot in the physmap large enough for what we needed. We try to put
1398 * the shadow map as high up as we can to avoid depleting the lower 4GB in case
1399 * it's needed for, e.g., an xhci controller that can only do 32-bit DMA.
1401 for (i = (physmap_idx * 2) - 2; i >= 0 && nkasan_l2 > 0; i -= 2) {
1402 vm_paddr_t plow, phigh;
1404 /* L2 mappings must be backed by memory that is L2-aligned */
1405 plow = roundup2(physmap[i], L2_SIZE);
1406 phigh = physmap[i + 1];
1409 if (kernstart >= plow && kernstart < phigh)
1411 if (phigh - plow >= L2_SIZE)
1412 pmap_bootstrap_allocate_kasan_l2(plow, phigh, &va,
1417 panic("Could not find phys region for shadow map");
1420 * Done. We should now have a valid shadow address mapped for all KVA
1421 * that has been mapped so far, i.e., KERNBASE to virtual_avail. Thus,
1422 * shadow accesses by the kasan(9) runtime will succeed for this range.
1423 * When the kernel virtual address range is later expanded, as will
1424 * happen in vm_mem_init(), the shadow map will be grown as well. This
1425 * is handled by pmap_san_enter().
1431 * Initialize a vm_page's machine-dependent fields.
1434 pmap_page_init(vm_page_t m)
1437 TAILQ_INIT(&m->md.pv_list);
1438 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
1442 pmap_init_asids(struct asid_set *set, int bits)
1446 set->asid_bits = bits;
1449 * We may be too early in the overall initialization process to use
1452 set->asid_set_size = 1 << set->asid_bits;
1453 set->asid_set = kmem_malloc(bitstr_size(set->asid_set_size),
1455 for (i = 0; i < ASID_FIRST_AVAILABLE; i++)
1456 bit_set(set->asid_set, i);
1457 set->asid_next = ASID_FIRST_AVAILABLE;
1458 mtx_init(&set->asid_set_mutex, "asid set", NULL, MTX_SPIN);
1462 pmap_init_pv_table(void)
1464 struct vm_phys_seg *seg, *next_seg;
1465 struct pmap_large_md_page *pvd;
1467 int domain, i, j, pages;
1470 * We strongly depend on the size being a power of two, so the assert
1471 * is overzealous. However, should the struct be resized to a
1472 * different power of two, the code below needs to be revisited.
1474 CTASSERT((sizeof(*pvd) == 64));
1477 * Calculate the size of the array.
1480 for (i = 0; i < vm_phys_nsegs; i++) {
1481 seg = &vm_phys_segs[i];
1482 pages = pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) -
1483 pmap_l2_pindex(seg->start);
1484 s += round_page(pages * sizeof(*pvd));
1486 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
1487 if (pv_table == NULL)
1488 panic("%s: kva_alloc failed\n", __func__);
1491 * Iterate physical segments to allocate domain-local memory for PV
1495 for (i = 0; i < vm_phys_nsegs; i++) {
1496 seg = &vm_phys_segs[i];
1497 pages = pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) -
1498 pmap_l2_pindex(seg->start);
1499 domain = seg->domain;
1501 s = round_page(pages * sizeof(*pvd));
1503 for (j = 0; j < s; j += PAGE_SIZE) {
1504 vm_page_t m = vm_page_alloc_noobj_domain(domain,
1507 panic("failed to allocate PV table page");
1508 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
1511 for (j = 0; j < s / sizeof(*pvd); j++) {
1512 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
1513 TAILQ_INIT(&pvd->pv_page.pv_list);
1517 pvd = &pv_dummy_large;
1518 memset(pvd, 0, sizeof(*pvd));
1519 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
1520 TAILQ_INIT(&pvd->pv_page.pv_list);
1523 * Set pointers from vm_phys_segs to pv_table.
1525 for (i = 0, pvd = pv_table; i < vm_phys_nsegs; i++) {
1526 seg = &vm_phys_segs[i];
1527 seg->md_first = pvd;
1528 pvd += pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) -
1529 pmap_l2_pindex(seg->start);
1532 * If there is a following segment, and the final
1533 * superpage of this segment and the initial superpage
1534 * of the next segment are the same then adjust the
1535 * pv_table entry for that next segment down by one so
1536 * that the pv_table entries will be shared.
1538 if (i + 1 < vm_phys_nsegs) {
1539 next_seg = &vm_phys_segs[i + 1];
1540 if (pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) - 1 ==
1541 pmap_l2_pindex(next_seg->start)) {
1549 * Initialize the pmap module.
1550 * Called by vm_init, to initialize any structures that the pmap
1551 * system needs to map virtual memory.
1560 * Are large page mappings enabled?
1562 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
1563 if (superpages_enabled) {
1564 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1565 ("pmap_init: can't assign to pagesizes[1]"));
1566 pagesizes[1] = L2_SIZE;
1567 if (L1_BLOCKS_SUPPORTED) {
1568 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0,
1569 ("pmap_init: can't assign to pagesizes[2]"));
1570 pagesizes[2] = L1_SIZE;
1575 * Initialize the ASID allocator.
1577 pmap_init_asids(&asids,
1578 (READ_SPECIALREG(tcr_el1) & TCR_ASID_16) != 0 ? 16 : 8);
1581 mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1);
1584 if (ID_AA64MMFR1_VMIDBits_VAL(mmfr1) ==
1585 ID_AA64MMFR1_VMIDBits_16)
1587 pmap_init_asids(&vmids, vmid_bits);
1591 * Initialize pv chunk lists.
1593 for (i = 0; i < PMAP_MEMDOM; i++) {
1594 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL,
1596 TAILQ_INIT(&pv_chunks[i].pvc_list);
1598 pmap_init_pv_table();
1603 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1604 "2MB page mapping counters");
1606 static u_long pmap_l2_demotions;
1607 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
1608 &pmap_l2_demotions, 0, "2MB page demotions");
1610 static u_long pmap_l2_mappings;
1611 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
1612 &pmap_l2_mappings, 0, "2MB page mappings");
1614 static u_long pmap_l2_p_failures;
1615 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
1616 &pmap_l2_p_failures, 0, "2MB page promotion failures");
1618 static u_long pmap_l2_promotions;
1619 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
1620 &pmap_l2_promotions, 0, "2MB page promotions");
1623 * If the given value for "final_only" is false, then any cached intermediate-
1624 * level entries, i.e., L{0,1,2}_TABLE entries, are invalidated in addition to
1625 * any cached final-level entry, i.e., either an L{1,2}_BLOCK or L3_PAGE entry.
1626 * Otherwise, just the cached final-level entry is invalidated.
1628 static __inline void
1629 pmap_s1_invalidate_kernel(uint64_t r, bool final_only)
1632 __asm __volatile("tlbi vaale1is, %0" : : "r" (r));
1634 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1637 static __inline void
1638 pmap_s1_invalidate_user(uint64_t r, bool final_only)
1641 __asm __volatile("tlbi vale1is, %0" : : "r" (r));
1643 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1647 * Invalidates any cached final- and optionally intermediate-level TLB entries
1648 * for the specified virtual address in the given virtual address space.
1650 static __inline void
1651 pmap_s1_invalidate_page(pmap_t pmap, vm_offset_t va, bool final_only)
1655 PMAP_ASSERT_STAGE1(pmap);
1659 if (pmap == kernel_pmap) {
1660 pmap_s1_invalidate_kernel(r, final_only);
1662 r |= ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1663 pmap_s1_invalidate_user(r, final_only);
1669 static __inline void
1670 pmap_s2_invalidate_page(pmap_t pmap, vm_offset_t va, bool final_only)
1672 PMAP_ASSERT_STAGE2(pmap);
1673 MPASS(pmap_stage2_invalidate_range != NULL);
1674 pmap_stage2_invalidate_range(pmap_to_ttbr0(pmap), va, va + PAGE_SIZE,
1678 static __inline void
1679 pmap_invalidate_page(pmap_t pmap, vm_offset_t va, bool final_only)
1681 if (pmap->pm_stage == PM_STAGE1)
1682 pmap_s1_invalidate_page(pmap, va, final_only);
1684 pmap_s2_invalidate_page(pmap, va, final_only);
1688 * Invalidates any cached final- and optionally intermediate-level TLB entries
1689 * for the specified virtual address range in the given virtual address space.
1691 static __inline void
1692 pmap_s1_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1695 uint64_t end, r, start;
1697 PMAP_ASSERT_STAGE1(pmap);
1700 if (pmap == kernel_pmap) {
1701 start = TLBI_VA(sva);
1703 for (r = start; r < end; r += TLBI_VA_L3_INCR)
1704 pmap_s1_invalidate_kernel(r, final_only);
1706 start = end = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1707 start |= TLBI_VA(sva);
1708 end |= TLBI_VA(eva);
1709 for (r = start; r < end; r += TLBI_VA_L3_INCR)
1710 pmap_s1_invalidate_user(r, final_only);
1716 static __inline void
1717 pmap_s2_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1720 PMAP_ASSERT_STAGE2(pmap);
1721 MPASS(pmap_stage2_invalidate_range != NULL);
1722 pmap_stage2_invalidate_range(pmap_to_ttbr0(pmap), sva, eva, final_only);
1725 static __inline void
1726 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1729 if (pmap->pm_stage == PM_STAGE1)
1730 pmap_s1_invalidate_range(pmap, sva, eva, final_only);
1732 pmap_s2_invalidate_range(pmap, sva, eva, final_only);
1736 * Invalidates all cached intermediate- and final-level TLB entries for the
1737 * given virtual address space.
1739 static __inline void
1740 pmap_s1_invalidate_all(pmap_t pmap)
1744 PMAP_ASSERT_STAGE1(pmap);
1747 if (pmap == kernel_pmap) {
1748 __asm __volatile("tlbi vmalle1is");
1750 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1751 __asm __volatile("tlbi aside1is, %0" : : "r" (r));
1757 static __inline void
1758 pmap_s2_invalidate_all(pmap_t pmap)
1760 PMAP_ASSERT_STAGE2(pmap);
1761 MPASS(pmap_stage2_invalidate_all != NULL);
1762 pmap_stage2_invalidate_all(pmap_to_ttbr0(pmap));
1765 static __inline void
1766 pmap_invalidate_all(pmap_t pmap)
1768 if (pmap->pm_stage == PM_STAGE1)
1769 pmap_s1_invalidate_all(pmap);
1771 pmap_s2_invalidate_all(pmap);
1775 * Routine: pmap_extract
1777 * Extract the physical page address associated
1778 * with the given map/virtual_address pair.
1781 pmap_extract(pmap_t pmap, vm_offset_t va)
1783 pt_entry_t *pte, tpte;
1790 * Find the block or page map for this virtual address. pmap_pte
1791 * will return either a valid block/page entry, or NULL.
1793 pte = pmap_pte(pmap, va, &lvl);
1795 tpte = pmap_load(pte);
1796 pa = tpte & ~ATTR_MASK;
1799 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
1800 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1801 ("pmap_extract: Invalid L1 pte found: %lx",
1802 tpte & ATTR_DESCR_MASK));
1803 pa |= (va & L1_OFFSET);
1806 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1807 ("pmap_extract: Invalid L2 pte found: %lx",
1808 tpte & ATTR_DESCR_MASK));
1809 pa |= (va & L2_OFFSET);
1812 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1813 ("pmap_extract: Invalid L3 pte found: %lx",
1814 tpte & ATTR_DESCR_MASK));
1815 pa |= (va & L3_OFFSET);
1824 * Routine: pmap_extract_and_hold
1826 * Atomically extract and hold the physical page
1827 * with the given pmap and virtual address pair
1828 * if that mapping permits the given protection.
1831 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1833 pt_entry_t *pte, tpte;
1841 pte = pmap_pte(pmap, va, &lvl);
1843 tpte = pmap_load(pte);
1845 KASSERT(lvl > 0 && lvl <= 3,
1846 ("pmap_extract_and_hold: Invalid level %d", lvl));
1848 * Check that the pte is either a L3 page, or a L1 or L2 block
1849 * entry. We can assume L1_BLOCK == L2_BLOCK.
1851 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1852 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1853 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1854 tpte & ATTR_DESCR_MASK));
1857 if ((prot & VM_PROT_WRITE) == 0)
1859 else if (pmap->pm_stage == PM_STAGE1 &&
1860 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW))
1862 else if (pmap->pm_stage == PM_STAGE2 &&
1863 ((tpte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
1864 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)))
1870 off = va & L1_OFFSET;
1873 off = va & L2_OFFSET;
1879 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1880 if (m != NULL && !vm_page_wire_mapped(m))
1889 * Walks the page tables to translate a kernel virtual address to a
1890 * physical address. Returns true if the kva is valid and stores the
1891 * physical address in pa if it is not NULL.
1893 * See the comment above data_abort() for the rationale for specifying
1894 * NO_PERTHREAD_SSP here.
1896 bool NO_PERTHREAD_SSP
1897 pmap_klookup(vm_offset_t va, vm_paddr_t *pa)
1899 pt_entry_t *pte, tpte;
1904 * Disable interrupts so we don't get interrupted between asking
1905 * for address translation, and getting the result back.
1907 intr = intr_disable();
1908 par = arm64_address_translate_s1e1r(va);
1911 if (PAR_SUCCESS(par)) {
1913 *pa = (par & PAR_PA_MASK) | (va & PAR_LOW_MASK);
1918 * Fall back to walking the page table. The address translation
1919 * instruction may fail when the page is in a break-before-make
1920 * sequence. As we only clear the valid bit in said sequence we
1921 * can walk the page table to find the physical address.
1924 pte = pmap_l1(kernel_pmap, va);
1929 * A concurrent pmap_update_entry() will clear the entry's valid bit
1930 * but leave the rest of the entry unchanged. Therefore, we treat a
1931 * non-zero entry as being valid, and we ignore the valid bit when
1932 * determining whether the entry maps a block, page, or table.
1934 tpte = pmap_load(pte);
1937 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
1939 *pa = (tpte & ~ATTR_MASK) | (va & L1_OFFSET);
1942 pte = pmap_l1_to_l2(&tpte, va);
1943 tpte = pmap_load(pte);
1946 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
1948 *pa = (tpte & ~ATTR_MASK) | (va & L2_OFFSET);
1951 pte = pmap_l2_to_l3(&tpte, va);
1952 tpte = pmap_load(pte);
1956 *pa = (tpte & ~ATTR_MASK) | (va & L3_OFFSET);
1961 pmap_kextract(vm_offset_t va)
1965 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
1966 return (DMAP_TO_PHYS(va));
1968 if (pmap_klookup(va, &pa) == false)
1973 /***************************************************
1974 * Low level mapping routines.....
1975 ***************************************************/
1978 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1981 pt_entry_t *pte, attr;
1985 KASSERT((pa & L3_OFFSET) == 0,
1986 ("pmap_kenter: Invalid physical address"));
1987 KASSERT((sva & L3_OFFSET) == 0,
1988 ("pmap_kenter: Invalid virtual address"));
1989 KASSERT((size & PAGE_MASK) == 0,
1990 ("pmap_kenter: Mapping is not page-sized"));
1992 attr = ATTR_DEFAULT | ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1993 ATTR_S1_IDX(mode) | L3_PAGE;
1996 pde = pmap_pde(kernel_pmap, va, &lvl);
1997 KASSERT(pde != NULL,
1998 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1999 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
2001 pte = pmap_l2_to_l3(pde, va);
2002 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
2008 pmap_s1_invalidate_range(kernel_pmap, sva, va, true);
2012 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
2015 pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
2019 * Remove a page from the kernel pagetables.
2022 pmap_kremove(vm_offset_t va)
2026 pte = pmap_pte_exists(kernel_pmap, va, 3, __func__);
2028 pmap_s1_invalidate_page(kernel_pmap, va, true);
2032 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
2037 KASSERT((sva & L3_OFFSET) == 0,
2038 ("pmap_kremove_device: Invalid virtual address"));
2039 KASSERT((size & PAGE_MASK) == 0,
2040 ("pmap_kremove_device: Mapping is not page-sized"));
2044 pte = pmap_pte_exists(kernel_pmap, va, 3, __func__);
2050 pmap_s1_invalidate_range(kernel_pmap, sva, va, true);
2054 * Used to map a range of physical addresses into kernel
2055 * virtual address space.
2057 * The value passed in '*virt' is a suggested virtual address for
2058 * the mapping. Architectures which can support a direct-mapped
2059 * physical to virtual region can return the appropriate address
2060 * within that region, leaving '*virt' unchanged. Other
2061 * architectures should map the pages starting at '*virt' and
2062 * update '*virt' with the first usable address after the mapped
2066 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
2068 return PHYS_TO_DMAP(start);
2072 * Add a list of wired pages to the kva
2073 * this routine is only used for temporary
2074 * kernel mappings that do not need to have
2075 * page modification or references recorded.
2076 * Note that old mappings are simply written
2077 * over. The page *must* be wired.
2078 * Note: SMP coherent. Uses a ranged shootdown IPI.
2081 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
2084 pt_entry_t *pte, pa;
2090 for (i = 0; i < count; i++) {
2091 pde = pmap_pde(kernel_pmap, va, &lvl);
2092 KASSERT(pde != NULL,
2093 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
2095 ("pmap_qenter: Invalid level %d", lvl));
2098 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
2099 ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
2100 ATTR_S1_IDX(m->md.pv_memattr) | L3_PAGE;
2101 pte = pmap_l2_to_l3(pde, va);
2102 pmap_load_store(pte, pa);
2106 pmap_s1_invalidate_range(kernel_pmap, sva, va, true);
2110 * This routine tears out page mappings from the
2111 * kernel -- it is meant only for temporary mappings.
2114 pmap_qremove(vm_offset_t sva, int count)
2119 KASSERT(ADDR_IS_CANONICAL(sva),
2120 ("%s: Address not in canonical form: %lx", __func__, sva));
2121 KASSERT(ADDR_IS_KERNEL(sva), ("usermode va %lx", sva));
2124 while (count-- > 0) {
2125 pte = pmap_pte_exists(kernel_pmap, va, 3, NULL);
2132 pmap_s1_invalidate_range(kernel_pmap, sva, va, true);
2135 /***************************************************
2136 * Page table page management routines.....
2137 ***************************************************/
2139 * Schedule the specified unused page table page to be freed. Specifically,
2140 * add the page to the specified list of pages that will be released to the
2141 * physical memory manager after the TLB has been updated.
2143 static __inline void
2144 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2145 boolean_t set_PG_ZERO)
2149 m->flags |= PG_ZERO;
2151 m->flags &= ~PG_ZERO;
2152 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2156 * Decrements a page table page's reference count, which is used to record the
2157 * number of valid page table entries within the page. If the reference count
2158 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2159 * page table page was unmapped and FALSE otherwise.
2161 static inline boolean_t
2162 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2166 if (m->ref_count == 0) {
2167 _pmap_unwire_l3(pmap, va, m, free);
2174 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2177 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2179 * unmap the page table page
2181 if (m->pindex >= (NUL2E + NUL1E)) {
2185 l0 = pmap_l0(pmap, va);
2187 } else if (m->pindex >= NUL2E) {
2191 l1 = pmap_l1(pmap, va);
2197 l2 = pmap_l2(pmap, va);
2200 pmap_resident_count_dec(pmap, 1);
2201 if (m->pindex < NUL2E) {
2202 /* We just released an l3, unhold the matching l2 */
2203 pd_entry_t *l1, tl1;
2206 l1 = pmap_l1(pmap, va);
2207 tl1 = pmap_load(l1);
2208 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
2209 pmap_unwire_l3(pmap, va, l2pg, free);
2210 } else if (m->pindex < (NUL2E + NUL1E)) {
2211 /* We just released an l2, unhold the matching l1 */
2212 pd_entry_t *l0, tl0;
2215 l0 = pmap_l0(pmap, va);
2216 tl0 = pmap_load(l0);
2217 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
2218 pmap_unwire_l3(pmap, va, l1pg, free);
2220 pmap_invalidate_page(pmap, va, false);
2223 * Put page on a list so that it is released after
2224 * *ALL* TLB shootdown is done
2226 pmap_add_delayed_free_list(m, free, TRUE);
2230 * After removing a page table entry, this routine is used to
2231 * conditionally free the page, and manage the reference count.
2234 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2235 struct spglist *free)
2239 KASSERT(ADDR_IS_CANONICAL(va),
2240 ("%s: Address not in canonical form: %lx", __func__, va));
2241 if (ADDR_IS_KERNEL(va))
2243 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2244 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
2245 return (pmap_unwire_l3(pmap, va, mpte, free));
2249 * Release a page table page reference after a failed attempt to create a
2253 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
2255 struct spglist free;
2258 if (pmap_unwire_l3(pmap, va, mpte, &free))
2259 vm_page_free_pages_toq(&free, true);
2263 pmap_pinit0(pmap_t pmap)
2266 PMAP_LOCK_INIT(pmap);
2267 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
2268 pmap->pm_l0_paddr = READ_SPECIALREG(ttbr0_el1);
2269 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
2270 vm_radix_init(&pmap->pm_root);
2271 pmap->pm_cookie = COOKIE_FROM(ASID_RESERVED_FOR_PID_0, INT_MIN);
2272 pmap->pm_stage = PM_STAGE1;
2273 pmap->pm_levels = 4;
2274 pmap->pm_ttbr = pmap->pm_l0_paddr;
2275 pmap->pm_asid_set = &asids;
2277 PCPU_SET(curpmap, pmap);
2281 pmap_pinit_stage(pmap_t pmap, enum pmap_stage stage, int levels)
2286 * allocate the l0 page
2288 m = vm_page_alloc_noobj(VM_ALLOC_WAITOK | VM_ALLOC_WIRED |
2290 pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(m);
2291 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
2293 vm_radix_init(&pmap->pm_root);
2294 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
2295 pmap->pm_cookie = COOKIE_FROM(-1, INT_MAX);
2297 MPASS(levels == 3 || levels == 4);
2298 pmap->pm_levels = levels;
2299 pmap->pm_stage = stage;
2302 pmap->pm_asid_set = &asids;
2305 pmap->pm_asid_set = &vmids;
2308 panic("%s: Invalid pmap type %d", __func__, stage);
2312 /* XXX Temporarily disable deferred ASID allocation. */
2313 pmap_alloc_asid(pmap);
2316 * Allocate the level 1 entry to use as the root. This will increase
2317 * the refcount on the level 1 page so it won't be removed until
2318 * pmap_release() is called.
2320 if (pmap->pm_levels == 3) {
2322 m = _pmap_alloc_l3(pmap, NUL2E + NUL1E, NULL);
2325 pmap->pm_ttbr = VM_PAGE_TO_PHYS(m);
2331 pmap_pinit(pmap_t pmap)
2334 return (pmap_pinit_stage(pmap, PM_STAGE1, 4));
2338 * This routine is called if the desired page table page does not exist.
2340 * If page table page allocation fails, this routine may sleep before
2341 * returning NULL. It sleeps only if a lock pointer was given.
2343 * Note: If a page allocation fails at page table level two or three,
2344 * one or two pages may be held during the wait, only to be released
2345 * afterwards. This conservative approach is easily argued to avoid
2349 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
2351 vm_page_t m, l1pg, l2pg;
2353 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2356 * Allocate a page table page.
2358 if ((m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2359 if (lockp != NULL) {
2360 RELEASE_PV_LIST_LOCK(lockp);
2367 * Indicate the need to retry. While waiting, the page table
2368 * page may have been allocated.
2372 m->pindex = ptepindex;
2375 * Because of AArch64's weak memory consistency model, we must have a
2376 * barrier here to ensure that the stores for zeroing "m", whether by
2377 * pmap_zero_page() or an earlier function, are visible before adding
2378 * "m" to the page table. Otherwise, a page table walk by another
2379 * processor's MMU could see the mapping to "m" and a stale, non-zero
2385 * Map the pagetable page into the process address space, if
2386 * it isn't already there.
2389 if (ptepindex >= (NUL2E + NUL1E)) {
2390 pd_entry_t *l0p, l0e;
2391 vm_pindex_t l0index;
2393 l0index = ptepindex - (NUL2E + NUL1E);
2394 l0p = &pmap->pm_l0[l0index];
2395 KASSERT((pmap_load(l0p) & ATTR_DESCR_VALID) == 0,
2396 ("%s: L0 entry %#lx is valid", __func__, pmap_load(l0p)));
2397 l0e = VM_PAGE_TO_PHYS(m) | L0_TABLE;
2400 * Mark all kernel memory as not accessible from userspace
2401 * and userspace memory as not executable from the kernel.
2402 * This has been done for the bootstrap L0 entries in
2405 if (pmap == kernel_pmap)
2406 l0e |= TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0;
2408 l0e |= TATTR_PXN_TABLE;
2409 pmap_store(l0p, l0e);
2410 } else if (ptepindex >= NUL2E) {
2411 vm_pindex_t l0index, l1index;
2412 pd_entry_t *l0, *l1;
2415 l1index = ptepindex - NUL2E;
2416 l0index = l1index >> Ln_ENTRIES_SHIFT;
2418 l0 = &pmap->pm_l0[l0index];
2419 tl0 = pmap_load(l0);
2421 /* recurse for allocating page dir */
2422 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
2424 vm_page_unwire_noq(m);
2425 vm_page_free_zero(m);
2429 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
2433 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
2434 l1 = &l1[ptepindex & Ln_ADDR_MASK];
2435 KASSERT((pmap_load(l1) & ATTR_DESCR_VALID) == 0,
2436 ("%s: L1 entry %#lx is valid", __func__, pmap_load(l1)));
2437 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
2439 vm_pindex_t l0index, l1index;
2440 pd_entry_t *l0, *l1, *l2;
2441 pd_entry_t tl0, tl1;
2443 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
2444 l0index = l1index >> Ln_ENTRIES_SHIFT;
2446 l0 = &pmap->pm_l0[l0index];
2447 tl0 = pmap_load(l0);
2449 /* recurse for allocating page dir */
2450 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
2452 vm_page_unwire_noq(m);
2453 vm_page_free_zero(m);
2456 tl0 = pmap_load(l0);
2457 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
2458 l1 = &l1[l1index & Ln_ADDR_MASK];
2460 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
2461 l1 = &l1[l1index & Ln_ADDR_MASK];
2462 tl1 = pmap_load(l1);
2464 /* recurse for allocating page dir */
2465 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
2467 vm_page_unwire_noq(m);
2468 vm_page_free_zero(m);
2472 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
2477 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
2478 l2 = &l2[ptepindex & Ln_ADDR_MASK];
2479 KASSERT((pmap_load(l2) & ATTR_DESCR_VALID) == 0,
2480 ("%s: L2 entry %#lx is valid", __func__, pmap_load(l2)));
2481 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
2484 pmap_resident_count_inc(pmap, 1);
2490 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, vm_page_t *l2pgp,
2491 struct rwlock **lockp)
2493 pd_entry_t *l1, *l2;
2495 vm_pindex_t l2pindex;
2497 KASSERT(ADDR_IS_CANONICAL(va),
2498 ("%s: Address not in canonical form: %lx", __func__, va));
2501 l1 = pmap_l1(pmap, va);
2502 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
2503 l2 = pmap_l1_to_l2(l1, va);
2504 if (!ADDR_IS_KERNEL(va)) {
2505 /* Add a reference to the L2 page. */
2506 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
2510 } else if (!ADDR_IS_KERNEL(va)) {
2511 /* Allocate a L2 page. */
2512 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
2513 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
2520 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
2521 l2 = &l2[pmap_l2_index(va)];
2523 panic("pmap_alloc_l2: missing page table page for va %#lx",
2530 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2532 vm_pindex_t ptepindex;
2533 pd_entry_t *pde, tpde;
2541 * Calculate pagetable page index
2543 ptepindex = pmap_l2_pindex(va);
2546 * Get the page directory entry
2548 pde = pmap_pde(pmap, va, &lvl);
2551 * If the page table page is mapped, we just increment the hold count,
2552 * and activate it. If we get a level 2 pde it will point to a level 3
2560 pte = pmap_l0_to_l1(pde, va);
2561 KASSERT(pmap_load(pte) == 0,
2562 ("pmap_alloc_l3: TODO: l0 superpages"));
2567 pte = pmap_l1_to_l2(pde, va);
2568 KASSERT(pmap_load(pte) == 0,
2569 ("pmap_alloc_l3: TODO: l1 superpages"));
2573 tpde = pmap_load(pde);
2575 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
2581 panic("pmap_alloc_l3: Invalid level %d", lvl);
2585 * Here if the pte page isn't mapped, or if it has been deallocated.
2587 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
2588 if (m == NULL && lockp != NULL)
2594 /***************************************************
2595 * Pmap allocation/deallocation routines.
2596 ***************************************************/
2599 * Release any resources held by the given physical map.
2600 * Called when a pmap initialized by pmap_pinit is being released.
2601 * Should only be called if the map contains no valid mappings.
2604 pmap_release(pmap_t pmap)
2606 boolean_t rv __diagused;
2607 struct spglist free;
2608 struct asid_set *set;
2612 if (pmap->pm_levels != 4) {
2613 PMAP_ASSERT_STAGE2(pmap);
2614 KASSERT(pmap->pm_stats.resident_count == 1,
2615 ("pmap_release: pmap resident count %ld != 0",
2616 pmap->pm_stats.resident_count));
2617 KASSERT((pmap->pm_l0[0] & ATTR_DESCR_VALID) == ATTR_DESCR_VALID,
2618 ("pmap_release: Invalid l0 entry: %lx", pmap->pm_l0[0]));
2621 m = PHYS_TO_VM_PAGE(pmap->pm_ttbr);
2623 rv = pmap_unwire_l3(pmap, 0, m, &free);
2626 vm_page_free_pages_toq(&free, true);
2629 KASSERT(pmap->pm_stats.resident_count == 0,
2630 ("pmap_release: pmap resident count %ld != 0",
2631 pmap->pm_stats.resident_count));
2632 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2633 ("pmap_release: pmap has reserved page table page(s)"));
2635 set = pmap->pm_asid_set;
2636 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
2639 * Allow the ASID to be reused. In stage 2 VMIDs we don't invalidate
2640 * the entries when removing them so rely on a later tlb invalidation.
2641 * this will happen when updating the VMID generation. Because of this
2642 * we don't reuse VMIDs within a generation.
2644 if (pmap->pm_stage == PM_STAGE1) {
2645 mtx_lock_spin(&set->asid_set_mutex);
2646 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch) {
2647 asid = COOKIE_TO_ASID(pmap->pm_cookie);
2648 KASSERT(asid >= ASID_FIRST_AVAILABLE &&
2649 asid < set->asid_set_size,
2650 ("pmap_release: pmap cookie has out-of-range asid"));
2651 bit_clear(set->asid_set, asid);
2653 mtx_unlock_spin(&set->asid_set_mutex);
2656 m = PHYS_TO_VM_PAGE(pmap->pm_l0_paddr);
2657 vm_page_unwire_noq(m);
2658 vm_page_free_zero(m);
2662 kvm_size(SYSCTL_HANDLER_ARGS)
2664 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
2666 return sysctl_handle_long(oidp, &ksize, 0, req);
2668 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
2669 0, 0, kvm_size, "LU",
2673 kvm_free(SYSCTL_HANDLER_ARGS)
2675 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2677 return sysctl_handle_long(oidp, &kfree, 0, req);
2679 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
2680 0, 0, kvm_free, "LU",
2681 "Amount of KVM free");
2684 * grow the number of kernel page table entries, if needed
2687 pmap_growkernel(vm_offset_t addr)
2691 pd_entry_t *l0, *l1, *l2;
2693 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2695 addr = roundup2(addr, L2_SIZE);
2696 if (addr - 1 >= vm_map_max(kernel_map))
2697 addr = vm_map_max(kernel_map);
2698 if (kernel_vm_end < addr)
2699 kasan_shadow_map(kernel_vm_end, addr - kernel_vm_end);
2700 while (kernel_vm_end < addr) {
2701 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
2702 KASSERT(pmap_load(l0) != 0,
2703 ("pmap_growkernel: No level 0 kernel entry"));
2705 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
2706 if (pmap_load(l1) == 0) {
2707 /* We need a new PDP entry */
2708 nkpg = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT |
2709 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2711 panic("pmap_growkernel: no memory to grow kernel");
2712 nkpg->pindex = kernel_vm_end >> L1_SHIFT;
2713 /* See the dmb() in _pmap_alloc_l3(). */
2715 paddr = VM_PAGE_TO_PHYS(nkpg);
2716 pmap_store(l1, paddr | L1_TABLE);
2717 continue; /* try again */
2719 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
2720 if (pmap_load(l2) != 0) {
2721 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2722 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2723 kernel_vm_end = vm_map_max(kernel_map);
2729 nkpg = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED |
2732 panic("pmap_growkernel: no memory to grow kernel");
2733 nkpg->pindex = kernel_vm_end >> L2_SHIFT;
2734 /* See the dmb() in _pmap_alloc_l3(). */
2736 paddr = VM_PAGE_TO_PHYS(nkpg);
2737 pmap_store(l2, paddr | L2_TABLE);
2739 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2740 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2741 kernel_vm_end = vm_map_max(kernel_map);
2747 /***************************************************
2748 * page management routines.
2749 ***************************************************/
2751 static const uint64_t pc_freemask[_NPCM] = {
2752 [0 ... _NPCM - 2] = PC_FREEN,
2753 [_NPCM - 1] = PC_FREEL
2757 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2759 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2760 "Current number of pv entry chunks");
2761 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2762 "Current number of pv entry chunks allocated");
2763 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2764 "Current number of pv entry chunks frees");
2765 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2766 "Number of times tried to get a chunk page but failed.");
2768 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2769 static int pv_entry_spare;
2771 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2772 "Current number of pv entry frees");
2773 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2774 "Current number of pv entry allocs");
2775 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2776 "Current number of pv entries");
2777 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2778 "Current number of spare pv entries");
2782 * We are in a serious low memory condition. Resort to
2783 * drastic measures to free some pages so we can allocate
2784 * another pv entry chunk.
2786 * Returns NULL if PV entries were reclaimed from the specified pmap.
2788 * We do not, however, unmap 2mpages because subsequent accesses will
2789 * allocate per-page pv entries until repromotion occurs, thereby
2790 * exacerbating the shortage of free pv entries.
2793 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
2795 struct pv_chunks_list *pvc;
2796 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
2797 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
2798 struct md_page *pvh;
2800 pmap_t next_pmap, pmap;
2801 pt_entry_t *pte, tpte;
2805 struct spglist free;
2807 int bit, field, freed, lvl;
2809 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2810 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2815 bzero(&pc_marker_b, sizeof(pc_marker_b));
2816 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
2817 pc_marker = (struct pv_chunk *)&pc_marker_b;
2818 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
2820 pvc = &pv_chunks[domain];
2821 mtx_lock(&pvc->pvc_lock);
2822 pvc->active_reclaims++;
2823 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
2824 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
2825 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
2826 SLIST_EMPTY(&free)) {
2827 next_pmap = pc->pc_pmap;
2828 if (next_pmap == NULL) {
2830 * The next chunk is a marker. However, it is
2831 * not our marker, so active_reclaims must be
2832 * > 1. Consequently, the next_chunk code
2833 * will not rotate the pv_chunks list.
2837 mtx_unlock(&pvc->pvc_lock);
2840 * A pv_chunk can only be removed from the pc_lru list
2841 * when both pvc->pvc_lock is owned and the
2842 * corresponding pmap is locked.
2844 if (pmap != next_pmap) {
2845 if (pmap != NULL && pmap != locked_pmap)
2848 /* Avoid deadlock and lock recursion. */
2849 if (pmap > locked_pmap) {
2850 RELEASE_PV_LIST_LOCK(lockp);
2852 mtx_lock(&pvc->pvc_lock);
2854 } else if (pmap != locked_pmap) {
2855 if (PMAP_TRYLOCK(pmap)) {
2856 mtx_lock(&pvc->pvc_lock);
2859 pmap = NULL; /* pmap is not locked */
2860 mtx_lock(&pvc->pvc_lock);
2861 pc = TAILQ_NEXT(pc_marker, pc_lru);
2863 pc->pc_pmap != next_pmap)
2871 * Destroy every non-wired, 4 KB page mapping in the chunk.
2874 for (field = 0; field < _NPCM; field++) {
2875 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2876 inuse != 0; inuse &= ~(1UL << bit)) {
2877 bit = ffsl(inuse) - 1;
2878 pv = &pc->pc_pventry[field * 64 + bit];
2880 pde = pmap_pde(pmap, va, &lvl);
2883 pte = pmap_l2_to_l3(pde, va);
2884 tpte = pmap_load(pte);
2885 if ((tpte & ATTR_SW_WIRED) != 0)
2887 tpte = pmap_load_clear(pte);
2888 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
2889 if (pmap_pte_dirty(pmap, tpte))
2891 if ((tpte & ATTR_AF) != 0) {
2892 pmap_s1_invalidate_page(pmap, va, true);
2893 vm_page_aflag_set(m, PGA_REFERENCED);
2895 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2896 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2898 if (TAILQ_EMPTY(&m->md.pv_list) &&
2899 (m->flags & PG_FICTITIOUS) == 0) {
2900 pvh = page_to_pvh(m);
2901 if (TAILQ_EMPTY(&pvh->pv_list)) {
2902 vm_page_aflag_clear(m,
2906 pc->pc_map[field] |= 1UL << bit;
2907 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
2912 mtx_lock(&pvc->pvc_lock);
2915 /* Every freed mapping is for a 4 KB page. */
2916 pmap_resident_count_dec(pmap, freed);
2917 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2918 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2919 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2920 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2921 if (pc_is_free(pc)) {
2922 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2923 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2924 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2925 /* Entire chunk is free; return it. */
2926 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2927 dump_drop_page(m_pc->phys_addr);
2928 mtx_lock(&pvc->pvc_lock);
2929 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
2932 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2933 mtx_lock(&pvc->pvc_lock);
2934 /* One freed pv entry in locked_pmap is sufficient. */
2935 if (pmap == locked_pmap)
2939 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
2940 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
2941 if (pvc->active_reclaims == 1 && pmap != NULL) {
2943 * Rotate the pv chunks list so that we do not
2944 * scan the same pv chunks that could not be
2945 * freed (because they contained a wired
2946 * and/or superpage mapping) on every
2947 * invocation of reclaim_pv_chunk().
2949 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker){
2950 MPASS(pc->pc_pmap != NULL);
2951 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
2952 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
2956 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
2957 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
2958 pvc->active_reclaims--;
2959 mtx_unlock(&pvc->pvc_lock);
2960 if (pmap != NULL && pmap != locked_pmap)
2962 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2963 m_pc = SLIST_FIRST(&free);
2964 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2965 /* Recycle a freed page table page. */
2966 m_pc->ref_count = 1;
2968 vm_page_free_pages_toq(&free, true);
2973 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2978 domain = PCPU_GET(domain);
2979 for (i = 0; i < vm_ndomains; i++) {
2980 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
2983 domain = (domain + 1) % vm_ndomains;
2990 * free the pv_entry back to the free list
2993 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2995 struct pv_chunk *pc;
2996 int idx, field, bit;
2998 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2999 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
3000 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
3001 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
3002 pc = pv_to_chunk(pv);
3003 idx = pv - &pc->pc_pventry[0];
3006 pc->pc_map[field] |= 1ul << bit;
3007 if (!pc_is_free(pc)) {
3008 /* 98% of the time, pc is already at the head of the list. */
3009 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
3010 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3011 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3015 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3020 free_pv_chunk_dequeued(struct pv_chunk *pc)
3024 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3025 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3026 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3027 /* entire chunk is free, return it */
3028 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3029 dump_drop_page(m->phys_addr);
3030 vm_page_unwire_noq(m);
3035 free_pv_chunk(struct pv_chunk *pc)
3037 struct pv_chunks_list *pvc;
3039 pvc = &pv_chunks[pc_to_domain(pc)];
3040 mtx_lock(&pvc->pvc_lock);
3041 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
3042 mtx_unlock(&pvc->pvc_lock);
3043 free_pv_chunk_dequeued(pc);
3047 free_pv_chunk_batch(struct pv_chunklist *batch)
3049 struct pv_chunks_list *pvc;
3050 struct pv_chunk *pc, *npc;
3053 for (i = 0; i < vm_ndomains; i++) {
3054 if (TAILQ_EMPTY(&batch[i]))
3056 pvc = &pv_chunks[i];
3057 mtx_lock(&pvc->pvc_lock);
3058 TAILQ_FOREACH(pc, &batch[i], pc_list) {
3059 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
3061 mtx_unlock(&pvc->pvc_lock);
3064 for (i = 0; i < vm_ndomains; i++) {
3065 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
3066 free_pv_chunk_dequeued(pc);
3072 * Returns a new PV entry, allocating a new PV chunk from the system when
3073 * needed. If this PV chunk allocation fails and a PV list lock pointer was
3074 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
3077 * The given PV list lock may be released.
3080 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
3082 struct pv_chunks_list *pvc;
3085 struct pv_chunk *pc;
3088 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3089 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
3091 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3093 for (field = 0; field < _NPCM; field++) {
3094 if (pc->pc_map[field]) {
3095 bit = ffsl(pc->pc_map[field]) - 1;
3099 if (field < _NPCM) {
3100 pv = &pc->pc_pventry[field * 64 + bit];
3101 pc->pc_map[field] &= ~(1ul << bit);
3102 /* If this was the last item, move it to tail */
3103 if (pc_is_full(pc)) {
3104 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3105 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
3108 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3109 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
3113 /* No free items, allocate another chunk */
3114 m = vm_page_alloc_noobj(VM_ALLOC_WIRED);
3116 if (lockp == NULL) {
3117 PV_STAT(pc_chunk_tryfail++);
3120 m = reclaim_pv_chunk(pmap, lockp);
3124 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3125 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3126 dump_add_page(m->phys_addr);
3127 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3129 memcpy(pc->pc_map, pc_freemask, sizeof(pc_freemask));
3130 pc->pc_map[0] &= ~1ul; /* preallocated bit 0 */
3131 pvc = &pv_chunks[vm_page_domain(m)];
3132 mtx_lock(&pvc->pvc_lock);
3133 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
3134 mtx_unlock(&pvc->pvc_lock);
3135 pv = &pc->pc_pventry[0];
3136 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3137 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3138 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
3143 * Ensure that the number of spare PV entries in the specified pmap meets or
3144 * exceeds the given count, "needed".
3146 * The given PV list lock may be released.
3149 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
3151 struct pv_chunks_list *pvc;
3152 struct pch new_tail[PMAP_MEMDOM];
3153 struct pv_chunk *pc;
3158 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3159 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
3162 * Newly allocated PV chunks must be stored in a private list until
3163 * the required number of PV chunks have been allocated. Otherwise,
3164 * reclaim_pv_chunk() could recycle one of these chunks. In
3165 * contrast, these chunks must be added to the pmap upon allocation.
3167 for (i = 0; i < PMAP_MEMDOM; i++)
3168 TAILQ_INIT(&new_tail[i]);
3171 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
3172 bit_count((bitstr_t *)pc->pc_map, 0,
3173 sizeof(pc->pc_map) * NBBY, &free);
3177 if (avail >= needed)
3180 for (reclaimed = false; avail < needed; avail += _NPCPV) {
3181 m = vm_page_alloc_noobj(VM_ALLOC_WIRED);
3183 m = reclaim_pv_chunk(pmap, lockp);
3188 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3189 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3190 dump_add_page(m->phys_addr);
3191 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3193 memcpy(pc->pc_map, pc_freemask, sizeof(pc_freemask));
3194 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3195 TAILQ_INSERT_TAIL(&new_tail[vm_page_domain(m)], pc, pc_lru);
3196 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3199 * The reclaim might have freed a chunk from the current pmap.
3200 * If that chunk contained available entries, we need to
3201 * re-count the number of available entries.
3206 for (i = 0; i < vm_ndomains; i++) {
3207 if (TAILQ_EMPTY(&new_tail[i]))
3209 pvc = &pv_chunks[i];
3210 mtx_lock(&pvc->pvc_lock);
3211 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
3212 mtx_unlock(&pvc->pvc_lock);
3217 * First find and then remove the pv entry for the specified pmap and virtual
3218 * address from the specified pv list. Returns the pv entry if found and NULL
3219 * otherwise. This operation can be performed on pv lists for either 4KB or
3220 * 2MB page mappings.
3222 static __inline pv_entry_t
3223 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3227 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3228 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3229 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3238 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3239 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3240 * entries for each of the 4KB page mappings.
3243 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3244 struct rwlock **lockp)
3246 struct md_page *pvh;
3247 struct pv_chunk *pc;
3249 vm_offset_t va_last;
3253 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3254 KASSERT((va & L2_OFFSET) == 0,
3255 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
3256 KASSERT((pa & L2_OFFSET) == 0,
3257 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
3258 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3261 * Transfer the 2mpage's pv entry for this mapping to the first
3262 * page's pv list. Once this transfer begins, the pv list lock
3263 * must not be released until the last pv entry is reinstantiated.
3265 pvh = pa_to_pvh(pa);
3266 pv = pmap_pvh_remove(pvh, pmap, va);
3267 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
3268 m = PHYS_TO_VM_PAGE(pa);
3269 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3271 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
3272 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
3273 va_last = va + L2_SIZE - PAGE_SIZE;
3275 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3276 KASSERT(!pc_is_full(pc), ("pmap_pv_demote_l2: missing spare"));
3277 for (field = 0; field < _NPCM; field++) {
3278 while (pc->pc_map[field]) {
3279 bit = ffsl(pc->pc_map[field]) - 1;
3280 pc->pc_map[field] &= ~(1ul << bit);
3281 pv = &pc->pc_pventry[field * 64 + bit];
3285 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3286 ("pmap_pv_demote_l2: page %p is not managed", m));
3287 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3293 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3294 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3297 if (pc_is_full(pc)) {
3298 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3299 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3301 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
3302 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
3306 * First find and then destroy the pv entry for the specified pmap and virtual
3307 * address. This operation can be performed on pv lists for either 4KB or 2MB
3311 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3315 pv = pmap_pvh_remove(pvh, pmap, va);
3316 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3317 free_pv_entry(pmap, pv);
3321 * Conditionally create the PV entry for a 4KB page mapping if the required
3322 * memory can be allocated without resorting to reclamation.
3325 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
3326 struct rwlock **lockp)
3330 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3331 /* Pass NULL instead of the lock pointer to disable reclamation. */
3332 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3334 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3335 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3343 * Create the PV entry for a 2MB page mapping. Always returns true unless the
3344 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
3345 * false if the PV entry cannot be allocated without resorting to reclamation.
3348 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
3349 struct rwlock **lockp)
3351 struct md_page *pvh;
3355 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3356 /* Pass NULL instead of the lock pointer to disable reclamation. */
3357 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
3358 NULL : lockp)) == NULL)
3361 pa = l2e & ~ATTR_MASK;
3362 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3363 pvh = pa_to_pvh(pa);
3364 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3370 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
3372 pt_entry_t newl2, oldl2 __diagused;
3376 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
3377 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
3378 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3380 ml3 = pmap_remove_pt_page(pmap, va);
3382 panic("pmap_remove_kernel_l2: Missing pt page");
3384 ml3pa = VM_PAGE_TO_PHYS(ml3);
3385 newl2 = ml3pa | L2_TABLE;
3388 * If this page table page was unmapped by a promotion, then it
3389 * contains valid mappings. Zero it to invalidate those mappings.
3391 if (ml3->valid != 0)
3392 pagezero((void *)PHYS_TO_DMAP(ml3pa));
3395 * Demote the mapping. The caller must have already invalidated the
3396 * mapping (i.e., the "break" in break-before-make).
3398 oldl2 = pmap_load_store(l2, newl2);
3399 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
3400 __func__, l2, oldl2));
3404 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
3407 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
3408 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
3410 struct md_page *pvh;
3412 vm_page_t m, ml3, mt;
3414 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3415 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
3416 old_l2 = pmap_load_clear(l2);
3417 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
3418 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
3421 * Since a promotion must break the 4KB page mappings before making
3422 * the 2MB page mapping, a pmap_s1_invalidate_page() suffices.
3424 pmap_s1_invalidate_page(pmap, sva, true);
3426 if (old_l2 & ATTR_SW_WIRED)
3427 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
3428 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
3429 if (old_l2 & ATTR_SW_MANAGED) {
3430 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
3431 pvh = page_to_pvh(m);
3432 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
3433 pmap_pvh_free(pvh, pmap, sva);
3434 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) {
3435 if (pmap_pte_dirty(pmap, old_l2))
3437 if (old_l2 & ATTR_AF)
3438 vm_page_aflag_set(mt, PGA_REFERENCED);
3439 if (TAILQ_EMPTY(&mt->md.pv_list) &&
3440 TAILQ_EMPTY(&pvh->pv_list))
3441 vm_page_aflag_clear(mt, PGA_WRITEABLE);
3444 if (pmap == kernel_pmap) {
3445 pmap_remove_kernel_l2(pmap, l2, sva);
3447 ml3 = pmap_remove_pt_page(pmap, sva);
3449 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
3450 ("pmap_remove_l2: l3 page not promoted"));
3451 pmap_resident_count_dec(pmap, 1);
3452 KASSERT(ml3->ref_count == NL3PG,
3453 ("pmap_remove_l2: l3 page ref count error"));
3455 pmap_add_delayed_free_list(ml3, free, FALSE);
3458 return (pmap_unuse_pt(pmap, sva, l1e, free));
3462 * pmap_remove_l3: do the things to unmap a page in a process
3465 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
3466 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
3468 struct md_page *pvh;
3472 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3473 old_l3 = pmap_load_clear(l3);
3474 pmap_s1_invalidate_page(pmap, va, true);
3475 if (old_l3 & ATTR_SW_WIRED)
3476 pmap->pm_stats.wired_count -= 1;
3477 pmap_resident_count_dec(pmap, 1);
3478 if (old_l3 & ATTR_SW_MANAGED) {
3479 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
3480 if (pmap_pte_dirty(pmap, old_l3))
3482 if (old_l3 & ATTR_AF)
3483 vm_page_aflag_set(m, PGA_REFERENCED);
3484 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3485 pmap_pvh_free(&m->md, pmap, va);
3486 if (TAILQ_EMPTY(&m->md.pv_list) &&
3487 (m->flags & PG_FICTITIOUS) == 0) {
3488 pvh = page_to_pvh(m);
3489 if (TAILQ_EMPTY(&pvh->pv_list))
3490 vm_page_aflag_clear(m, PGA_WRITEABLE);
3493 return (pmap_unuse_pt(pmap, va, l2e, free));
3497 * Remove the specified range of addresses from the L3 page table that is
3498 * identified by the given L2 entry.
3501 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
3502 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
3504 struct md_page *pvh;
3505 struct rwlock *new_lock;
3506 pt_entry_t *l3, old_l3;
3510 KASSERT(ADDR_IS_CANONICAL(sva),
3511 ("%s: Start address not in canonical form: %lx", __func__, sva));
3512 KASSERT(ADDR_IS_CANONICAL(eva) || eva == VM_MAX_USER_ADDRESS,
3513 ("%s: End address not in canonical form: %lx", __func__, eva));
3515 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3516 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
3517 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
3518 l3pg = !ADDR_IS_KERNEL(sva) ? PHYS_TO_VM_PAGE(l2e & ~ATTR_MASK) : NULL;
3520 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
3521 if (!pmap_l3_valid(pmap_load(l3))) {
3523 pmap_invalidate_range(pmap, va, sva, true);
3528 old_l3 = pmap_load_clear(l3);
3529 if ((old_l3 & ATTR_SW_WIRED) != 0)
3530 pmap->pm_stats.wired_count--;
3531 pmap_resident_count_dec(pmap, 1);
3532 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
3533 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
3534 if (pmap_pte_dirty(pmap, old_l3))
3536 if ((old_l3 & ATTR_AF) != 0)
3537 vm_page_aflag_set(m, PGA_REFERENCED);
3538 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
3539 if (new_lock != *lockp) {
3540 if (*lockp != NULL) {
3542 * Pending TLB invalidations must be
3543 * performed before the PV list lock is
3544 * released. Otherwise, a concurrent
3545 * pmap_remove_all() on a physical page
3546 * could return while a stale TLB entry
3547 * still provides access to that page.
3550 pmap_invalidate_range(pmap, va,
3559 pmap_pvh_free(&m->md, pmap, sva);
3560 if (TAILQ_EMPTY(&m->md.pv_list) &&
3561 (m->flags & PG_FICTITIOUS) == 0) {
3562 pvh = page_to_pvh(m);
3563 if (TAILQ_EMPTY(&pvh->pv_list))
3564 vm_page_aflag_clear(m, PGA_WRITEABLE);
3567 if (l3pg != NULL && pmap_unwire_l3(pmap, sva, l3pg, free)) {
3569 * _pmap_unwire_l3() has already invalidated the TLB
3570 * entries at all levels for "sva". So, we need not
3571 * perform "sva += L3_SIZE;" here. Moreover, we need
3572 * not perform "va = sva;" if "sva" is at the start
3573 * of a new valid range consisting of a single page.
3581 pmap_invalidate_range(pmap, va, sva, true);
3585 * Remove the given range of addresses from the specified map.
3587 * It is assumed that the start and end are properly
3588 * rounded to the page size.
3591 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3593 struct rwlock *lock;
3594 vm_offset_t va_next;
3595 pd_entry_t *l0, *l1, *l2;
3596 pt_entry_t l3_paddr;
3597 struct spglist free;
3600 * Perform an unsynchronized read. This is, however, safe.
3602 if (pmap->pm_stats.resident_count == 0)
3610 for (; sva < eva; sva = va_next) {
3611 if (pmap->pm_stats.resident_count == 0)
3614 l0 = pmap_l0(pmap, sva);
3615 if (pmap_load(l0) == 0) {
3616 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3622 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3625 l1 = pmap_l0_to_l1(l0, sva);
3626 if (pmap_load(l1) == 0)
3628 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
3629 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
3630 KASSERT(va_next <= eva,
3631 ("partial update of non-transparent 1G page "
3632 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
3633 pmap_load(l1), sva, eva, va_next));
3634 MPASS(pmap != kernel_pmap);
3635 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0);
3637 pmap_s1_invalidate_page(pmap, sva, true);
3638 pmap_resident_count_dec(pmap, L1_SIZE / PAGE_SIZE);
3639 pmap_unuse_pt(pmap, sva, pmap_load(l0), &free);
3644 * Calculate index for next page table.
3646 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3650 l2 = pmap_l1_to_l2(l1, sva);
3654 l3_paddr = pmap_load(l2);
3656 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
3657 if (sva + L2_SIZE == va_next && eva >= va_next) {
3658 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
3661 } else if (pmap_demote_l2_locked(pmap, l2, sva,
3664 l3_paddr = pmap_load(l2);
3668 * Weed out invalid mappings.
3670 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
3674 * Limit our scan to either the end of the va represented
3675 * by the current page table page, or to the end of the
3676 * range being removed.
3681 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
3687 vm_page_free_pages_toq(&free, true);
3691 * Routine: pmap_remove_all
3693 * Removes this physical page from
3694 * all physical maps in which it resides.
3695 * Reflects back modify bits to the pager.
3698 * Original versions of this routine were very
3699 * inefficient because they iteratively called
3700 * pmap_remove (slow...)
3704 pmap_remove_all(vm_page_t m)
3706 struct md_page *pvh;
3709 struct rwlock *lock;
3710 pd_entry_t *pde, tpde;
3711 pt_entry_t *pte, tpte;
3713 struct spglist free;
3714 int lvl, pvh_gen, md_gen;
3716 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3717 ("pmap_remove_all: page %p is not managed", m));
3719 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3720 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
3723 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3725 if (!PMAP_TRYLOCK(pmap)) {
3726 pvh_gen = pvh->pv_gen;
3730 if (pvh_gen != pvh->pv_gen) {
3736 pte = pmap_pte_exists(pmap, va, 2, __func__);
3737 pmap_demote_l2_locked(pmap, pte, va, &lock);
3740 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3742 if (!PMAP_TRYLOCK(pmap)) {
3743 pvh_gen = pvh->pv_gen;
3744 md_gen = m->md.pv_gen;
3748 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
3753 pmap_resident_count_dec(pmap, 1);
3755 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3756 KASSERT(pde != NULL,
3757 ("pmap_remove_all: no page directory entry found"));
3759 ("pmap_remove_all: invalid pde level %d", lvl));
3760 tpde = pmap_load(pde);
3762 pte = pmap_l2_to_l3(pde, pv->pv_va);
3763 tpte = pmap_load_clear(pte);
3764 if (tpte & ATTR_SW_WIRED)
3765 pmap->pm_stats.wired_count--;
3766 if ((tpte & ATTR_AF) != 0) {
3767 pmap_invalidate_page(pmap, pv->pv_va, true);
3768 vm_page_aflag_set(m, PGA_REFERENCED);
3772 * Update the vm_page_t clean and reference bits.
3774 if (pmap_pte_dirty(pmap, tpte))
3776 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
3777 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3779 free_pv_entry(pmap, pv);
3782 vm_page_aflag_clear(m, PGA_WRITEABLE);
3784 vm_page_free_pages_toq(&free, true);
3788 * Masks and sets bits in a level 2 page table entries in the specified pmap
3791 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
3797 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3798 PMAP_ASSERT_STAGE1(pmap);
3799 KASSERT((sva & L2_OFFSET) == 0,
3800 ("pmap_protect_l2: sva is not 2mpage aligned"));
3801 old_l2 = pmap_load(l2);
3802 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
3803 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
3806 * Return if the L2 entry already has the desired access restrictions
3809 if ((old_l2 & mask) == nbits)
3812 while (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
3816 * When a dirty read/write superpage mapping is write protected,
3817 * update the dirty field of each of the superpage's constituent 4KB
3820 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
3821 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3822 pmap_pte_dirty(pmap, old_l2)) {
3823 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
3824 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3829 * Since a promotion must break the 4KB page mappings before making
3830 * the 2MB page mapping, a pmap_s1_invalidate_page() suffices.
3832 pmap_s1_invalidate_page(pmap, sva, true);
3836 * Masks and sets bits in last level page table entries in the specified
3840 pmap_mask_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, pt_entry_t mask,
3841 pt_entry_t nbits, bool invalidate)
3843 vm_offset_t va, va_next;
3844 pd_entry_t *l0, *l1, *l2;
3845 pt_entry_t *l3p, l3;
3848 for (; sva < eva; sva = va_next) {
3849 l0 = pmap_l0(pmap, sva);
3850 if (pmap_load(l0) == 0) {
3851 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3857 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3860 l1 = pmap_l0_to_l1(l0, sva);
3861 if (pmap_load(l1) == 0)
3863 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
3864 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
3865 KASSERT(va_next <= eva,
3866 ("partial update of non-transparent 1G page "
3867 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
3868 pmap_load(l1), sva, eva, va_next));
3869 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0);
3870 if ((pmap_load(l1) & mask) != nbits) {
3871 pmap_store(l1, (pmap_load(l1) & ~mask) | nbits);
3873 pmap_s1_invalidate_page(pmap, sva, true);
3878 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3882 l2 = pmap_l1_to_l2(l1, sva);
3883 if (pmap_load(l2) == 0)
3886 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3887 if (sva + L2_SIZE == va_next && eva >= va_next) {
3888 pmap_protect_l2(pmap, l2, sva, mask, nbits);
3890 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3893 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3894 ("pmap_protect: Invalid L2 entry after demotion"));
3900 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
3902 l3 = pmap_load(l3p);
3905 * Go to the next L3 entry if the current one is
3906 * invalid or already has the desired access
3907 * restrictions in place. (The latter case occurs
3908 * frequently. For example, in a "buildworld"
3909 * workload, almost 1 out of 4 L3 entries already
3910 * have the desired restrictions.)
3912 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
3913 if (va != va_next) {
3915 pmap_s1_invalidate_range(pmap,
3922 while (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) |
3927 * When a dirty read/write mapping is write protected,
3928 * update the page's dirty field.
3930 if ((l3 & ATTR_SW_MANAGED) != 0 &&
3931 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3932 pmap_pte_dirty(pmap, l3))
3933 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK));
3938 if (va != va_next && invalidate)
3939 pmap_s1_invalidate_range(pmap, va, sva, true);
3945 * Set the physical protection on the
3946 * specified range of this map as requested.
3949 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3951 pt_entry_t mask, nbits;
3953 PMAP_ASSERT_STAGE1(pmap);
3954 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3955 if (prot == VM_PROT_NONE) {
3956 pmap_remove(pmap, sva, eva);
3961 if ((prot & VM_PROT_WRITE) == 0) {
3962 mask |= ATTR_S1_AP_RW_BIT | ATTR_SW_DBM;
3963 nbits |= ATTR_S1_AP(ATTR_S1_AP_RO);
3965 if ((prot & VM_PROT_EXECUTE) == 0) {
3967 nbits |= ATTR_S1_XN;
3972 pmap_mask_set(pmap, sva, eva, mask, nbits, true);
3976 pmap_disable_promotion(vm_offset_t sva, vm_size_t size)
3979 MPASS((sva & L3_OFFSET) == 0);
3980 MPASS(((sva + size) & L3_OFFSET) == 0);
3982 pmap_mask_set(kernel_pmap, sva, sva + size, ATTR_SW_NO_PROMOTE,
3983 ATTR_SW_NO_PROMOTE, false);
3987 * Inserts the specified page table page into the specified pmap's collection
3988 * of idle page table pages. Each of a pmap's page table pages is responsible
3989 * for mapping a distinct range of virtual addresses. The pmap's collection is
3990 * ordered by this virtual address range.
3992 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3995 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3998 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3999 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
4000 return (vm_radix_insert(&pmap->pm_root, mpte));
4004 * Removes the page table page mapping the specified virtual address from the
4005 * specified pmap's collection of idle page table pages, and returns it.
4006 * Otherwise, returns NULL if there is no page table page corresponding to the
4007 * specified virtual address.
4009 static __inline vm_page_t
4010 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
4013 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4014 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
4018 * Performs a break-before-make update of a pmap entry. This is needed when
4019 * either promoting or demoting pages to ensure the TLB doesn't get into an
4020 * inconsistent state.
4023 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
4024 vm_offset_t va, vm_size_t size)
4028 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4030 if ((newpte & ATTR_SW_NO_PROMOTE) != 0)
4031 panic("%s: Updating non-promote pte", __func__);
4034 * Ensure we don't get switched out with the page table in an
4035 * inconsistent state. We also need to ensure no interrupts fire
4036 * as they may make use of an address we are about to invalidate.
4038 intr = intr_disable();
4041 * Clear the old mapping's valid bit, but leave the rest of the entry
4042 * unchanged, so that a lockless, concurrent pmap_kextract() can still
4043 * lookup the physical address.
4045 pmap_clear_bits(pte, ATTR_DESCR_VALID);
4048 * When promoting, the L{1,2}_TABLE entry that is being replaced might
4049 * be cached, so we invalidate intermediate entries as well as final
4052 pmap_s1_invalidate_range(pmap, va, va + size, false);
4054 /* Create the new mapping */
4055 pmap_store(pte, newpte);
4061 #if VM_NRESERVLEVEL > 0
4063 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
4064 * replace the many pv entries for the 4KB page mappings by a single pv entry
4065 * for the 2MB page mapping.
4068 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4069 struct rwlock **lockp)
4071 struct md_page *pvh;
4073 vm_offset_t va_last;
4076 KASSERT((pa & L2_OFFSET) == 0,
4077 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
4078 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4081 * Transfer the first page's pv entry for this mapping to the 2mpage's
4082 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
4083 * a transfer avoids the possibility that get_pv_entry() calls
4084 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
4085 * mappings that is being promoted.
4087 m = PHYS_TO_VM_PAGE(pa);
4088 va = va & ~L2_OFFSET;
4089 pv = pmap_pvh_remove(&m->md, pmap, va);
4090 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
4091 pvh = page_to_pvh(m);
4092 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4094 /* Free the remaining NPTEPG - 1 pv entries. */
4095 va_last = va + L2_SIZE - PAGE_SIZE;
4099 pmap_pvh_free(&m->md, pmap, va);
4100 } while (va < va_last);
4104 * Tries to promote the 512, contiguous 4KB page mappings that are within a
4105 * single level 2 table entry to a single 2MB page mapping. For promotion
4106 * to occur, two conditions must be met: (1) the 4KB page mappings must map
4107 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
4108 * identical characteristics.
4111 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va, vm_page_t mpte,
4112 struct rwlock **lockp)
4114 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
4116 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4117 PMAP_ASSERT_STAGE1(pmap);
4120 * Examine the first L3E in the specified PTP. Abort if this L3E is
4121 * ineligible for promotion, invalid, or does not map the first 4KB
4122 * physical page within a 2MB page.
4124 firstl3 = (pt_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
4125 newl2 = pmap_load(firstl3);
4126 if ((newl2 & ATTR_SW_NO_PROMOTE) != 0)
4128 if ((newl2 & ((~ATTR_MASK & L2_OFFSET) | ATTR_DESCR_MASK)) != L3_PAGE) {
4129 atomic_add_long(&pmap_l2_p_failures, 1);
4130 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
4131 " in pmap %p", va, pmap);
4136 * Both here and in the below "for" loop, to allow for repromotion
4137 * after MADV_FREE, conditionally write protect a clean L3E before
4138 * possibly aborting the promotion due to other L3E attributes. Why?
4139 * Suppose that MADV_FREE is applied to a part of a superpage, the
4140 * address range [S, E). pmap_advise() will demote the superpage
4141 * mapping, destroy the 4KB page mapping at the end of [S, E), and
4142 * set AP_RO and clear AF in the L3Es for the rest of [S, E). Later,
4143 * imagine that the memory in [S, E) is recycled, but the last 4KB
4144 * page in [S, E) is not the last to be rewritten, or simply accessed.
4145 * In other words, there is still a 4KB page in [S, E), call it P,
4146 * that is writeable but AP_RO is set and AF is clear in P's L3E.
4147 * Unless we write protect P before aborting the promotion, if and
4148 * when P is finally rewritten, there won't be a page fault to trigger
4152 if ((newl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
4153 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
4155 * When the mapping is clean, i.e., ATTR_S1_AP_RO is set,
4156 * ATTR_SW_DBM can be cleared without a TLB invalidation.
4158 if (!atomic_fcmpset_64(firstl3, &newl2, newl2 & ~ATTR_SW_DBM))
4160 newl2 &= ~ATTR_SW_DBM;
4162 if ((newl2 & ATTR_AF) == 0) {
4163 atomic_add_long(&pmap_l2_p_failures, 1);
4164 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
4165 " in pmap %p", va, pmap);
4170 * Examine each of the other L3Es in the specified PTP. Abort if this
4171 * L3E maps an unexpected 4KB physical page or does not have identical
4172 * characteristics to the first L3E.
4174 pa = (newl2 & (~ATTR_MASK | ATTR_DESCR_MASK)) + L2_SIZE - PAGE_SIZE;
4175 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
4176 oldl3 = pmap_load(l3);
4177 if ((oldl3 & (~ATTR_MASK | ATTR_DESCR_MASK)) != pa) {
4178 atomic_add_long(&pmap_l2_p_failures, 1);
4179 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
4180 " in pmap %p", va, pmap);
4184 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
4185 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
4187 * When the mapping is clean, i.e., ATTR_S1_AP_RO is
4188 * set, ATTR_SW_DBM can be cleared without a TLB
4191 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
4194 oldl3 &= ~ATTR_SW_DBM;
4196 if ((oldl3 & ATTR_MASK) != (newl2 & ATTR_MASK)) {
4197 atomic_add_long(&pmap_l2_p_failures, 1);
4198 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
4199 " in pmap %p", va, pmap);
4206 * Save the page table page in its current state until the L2
4207 * mapping the superpage is demoted by pmap_demote_l2() or
4208 * destroyed by pmap_remove_l3().
4211 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
4212 KASSERT(mpte >= vm_page_array &&
4213 mpte < &vm_page_array[vm_page_array_size],
4214 ("pmap_promote_l2: page table page is out of range"));
4215 KASSERT(mpte->pindex == pmap_l2_pindex(va),
4216 ("pmap_promote_l2: page table page's pindex is wrong"));
4217 if (pmap_insert_pt_page(pmap, mpte, true)) {
4218 atomic_add_long(&pmap_l2_p_failures, 1);
4220 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
4225 if ((newl2 & ATTR_SW_MANAGED) != 0)
4226 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
4228 newl2 &= ~ATTR_DESCR_MASK;
4231 pmap_update_entry(pmap, l2, newl2, va & ~L2_OFFSET, L2_SIZE);
4233 atomic_add_long(&pmap_l2_promotions, 1);
4234 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
4237 #endif /* VM_NRESERVLEVEL > 0 */
4240 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags,
4243 pd_entry_t *l0p, *l1p, *l2p, origpte;
4246 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4247 KASSERT(psind > 0 && psind < MAXPAGESIZES,
4248 ("psind %d unexpected", psind));
4249 KASSERT(((newpte & ~ATTR_MASK) & (pagesizes[psind] - 1)) == 0,
4250 ("unaligned phys address %#lx newpte %#lx psind %d",
4251 (newpte & ~ATTR_MASK), newpte, psind));
4255 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
4257 l0p = pmap_l0(pmap, va);
4258 if ((pmap_load(l0p) & ATTR_DESCR_VALID) == 0) {
4259 mp = _pmap_alloc_l3(pmap, pmap_l0_pindex(va), NULL);
4261 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
4262 return (KERN_RESOURCE_SHORTAGE);
4268 l1p = pmap_l0_to_l1(l0p, va);
4269 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va));
4270 origpte = pmap_load(l1p);
4272 l1p = pmap_l0_to_l1(l0p, va);
4273 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va));
4274 origpte = pmap_load(l1p);
4275 if ((origpte & ATTR_DESCR_VALID) == 0) {
4276 mp = PHYS_TO_VM_PAGE(pmap_load(l0p) &
4281 KASSERT(((origpte & ~ATTR_MASK) == (newpte & ~ATTR_MASK) &&
4282 (origpte & ATTR_DESCR_MASK) == L1_BLOCK) ||
4283 (origpte & ATTR_DESCR_VALID) == 0,
4284 ("va %#lx changing 1G phys page l1 %#lx newpte %#lx",
4285 va, origpte, newpte));
4286 pmap_store(l1p, newpte);
4287 } else /* (psind == 1) */ {
4288 l2p = pmap_l2(pmap, va);
4290 mp = _pmap_alloc_l3(pmap, pmap_l1_pindex(va), NULL);
4292 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
4293 return (KERN_RESOURCE_SHORTAGE);
4299 l2p = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
4300 l2p = &l2p[pmap_l2_index(va)];
4301 origpte = pmap_load(l2p);
4303 l1p = pmap_l1(pmap, va);
4304 origpte = pmap_load(l2p);
4305 if ((origpte & ATTR_DESCR_VALID) == 0) {
4306 mp = PHYS_TO_VM_PAGE(pmap_load(l1p) &
4311 KASSERT((origpte & ATTR_DESCR_VALID) == 0 ||
4312 ((origpte & ATTR_DESCR_MASK) == L2_BLOCK &&
4313 (origpte & ~ATTR_MASK) == (newpte & ~ATTR_MASK)),
4314 ("va %#lx changing 2M phys page l2 %#lx newpte %#lx",
4315 va, origpte, newpte));
4316 pmap_store(l2p, newpte);
4320 if ((origpte & ATTR_DESCR_VALID) == 0)
4321 pmap_resident_count_inc(pmap, pagesizes[psind] / PAGE_SIZE);
4322 if ((newpte & ATTR_SW_WIRED) != 0 && (origpte & ATTR_SW_WIRED) == 0)
4323 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE;
4324 else if ((newpte & ATTR_SW_WIRED) == 0 &&
4325 (origpte & ATTR_SW_WIRED) != 0)
4326 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE;
4328 return (KERN_SUCCESS);
4332 * Insert the given physical page (p) at
4333 * the specified virtual address (v) in the
4334 * target physical map with the protection requested.
4336 * If specified, the page will be wired down, meaning
4337 * that the related pte can not be reclaimed.
4339 * NB: This is the only routine which MAY NOT lazy-evaluate
4340 * or lose information. That is, this routine must actually
4341 * insert this page into the given map NOW.
4344 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4345 u_int flags, int8_t psind)
4347 struct rwlock *lock;
4349 pt_entry_t new_l3, orig_l3;
4350 pt_entry_t *l2, *l3;
4357 KASSERT(ADDR_IS_CANONICAL(va),
4358 ("%s: Address not in canonical form: %lx", __func__, va));
4360 va = trunc_page(va);
4361 if ((m->oflags & VPO_UNMANAGED) == 0)
4362 VM_PAGE_OBJECT_BUSY_ASSERT(m);
4363 pa = VM_PAGE_TO_PHYS(m);
4364 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | L3_PAGE);
4365 new_l3 |= pmap_pte_memattr(pmap, m->md.pv_memattr);
4366 new_l3 |= pmap_pte_prot(pmap, prot);
4368 if ((flags & PMAP_ENTER_WIRED) != 0)
4369 new_l3 |= ATTR_SW_WIRED;
4370 if (pmap->pm_stage == PM_STAGE1) {
4371 if (!ADDR_IS_KERNEL(va))
4372 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4374 new_l3 |= ATTR_S1_UXN;
4375 if (pmap != kernel_pmap)
4376 new_l3 |= ATTR_S1_nG;
4379 * Clear the access flag on executable mappings, this will be
4380 * set later when the page is accessed. The fault handler is
4381 * required to invalidate the I-cache.
4383 * TODO: Switch to the valid flag to allow hardware management
4384 * of the access flag. Much of the pmap code assumes the
4385 * valid flag is set and fails to destroy the old page tables
4386 * correctly if it is clear.
4388 if (prot & VM_PROT_EXECUTE)
4391 if ((m->oflags & VPO_UNMANAGED) == 0) {
4392 new_l3 |= ATTR_SW_MANAGED;
4393 if ((prot & VM_PROT_WRITE) != 0) {
4394 new_l3 |= ATTR_SW_DBM;
4395 if ((flags & VM_PROT_WRITE) == 0) {
4396 if (pmap->pm_stage == PM_STAGE1)
4397 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
4400 ~ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
4405 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
4409 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) {
4410 KASSERT((m->oflags & VPO_UNMANAGED) != 0,
4411 ("managed largepage va %#lx flags %#x", va, flags));
4414 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
4416 } else /* (psind == 1) */
4418 rv = pmap_enter_largepage(pmap, va, new_l3, flags, psind);
4422 /* Assert the required virtual and physical alignment. */
4423 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
4424 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
4425 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
4432 * In the case that a page table page is not
4433 * resident, we are creating it here.
4436 pde = pmap_pde(pmap, va, &lvl);
4437 if (pde != NULL && lvl == 2) {
4438 l3 = pmap_l2_to_l3(pde, va);
4439 if (!ADDR_IS_KERNEL(va) && mpte == NULL) {
4440 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
4444 } else if (pde != NULL && lvl == 1) {
4445 l2 = pmap_l1_to_l2(pde, va);
4446 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
4447 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
4448 l3 = &l3[pmap_l3_index(va)];
4449 if (!ADDR_IS_KERNEL(va)) {
4450 mpte = PHYS_TO_VM_PAGE(
4451 pmap_load(l2) & ~ATTR_MASK);
4456 /* We need to allocate an L3 table. */
4458 if (!ADDR_IS_KERNEL(va)) {
4459 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
4462 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
4463 * to handle the possibility that a superpage mapping for "va"
4464 * was created while we slept.
4466 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
4467 nosleep ? NULL : &lock);
4468 if (mpte == NULL && nosleep) {
4469 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
4470 rv = KERN_RESOURCE_SHORTAGE;
4475 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
4478 orig_l3 = pmap_load(l3);
4479 opa = orig_l3 & ~ATTR_MASK;
4483 * Is the specified virtual address already mapped?
4485 if (pmap_l3_valid(orig_l3)) {
4487 * Wiring change, just update stats. We don't worry about
4488 * wiring PT pages as they remain resident as long as there
4489 * are valid mappings in them. Hence, if a user page is wired,
4490 * the PT page will be also.
4492 if ((flags & PMAP_ENTER_WIRED) != 0 &&
4493 (orig_l3 & ATTR_SW_WIRED) == 0)
4494 pmap->pm_stats.wired_count++;
4495 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
4496 (orig_l3 & ATTR_SW_WIRED) != 0)
4497 pmap->pm_stats.wired_count--;
4500 * Remove the extra PT page reference.
4504 KASSERT(mpte->ref_count > 0,
4505 ("pmap_enter: missing reference to page table page,"
4510 * Has the physical page changed?
4514 * No, might be a protection or wiring change.
4516 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
4517 (new_l3 & ATTR_SW_DBM) != 0)
4518 vm_page_aflag_set(m, PGA_WRITEABLE);
4523 * The physical page has changed. Temporarily invalidate
4526 orig_l3 = pmap_load_clear(l3);
4527 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
4528 ("pmap_enter: unexpected pa update for %#lx", va));
4529 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
4530 om = PHYS_TO_VM_PAGE(opa);
4533 * The pmap lock is sufficient to synchronize with
4534 * concurrent calls to pmap_page_test_mappings() and
4535 * pmap_ts_referenced().
4537 if (pmap_pte_dirty(pmap, orig_l3))
4539 if ((orig_l3 & ATTR_AF) != 0) {
4540 pmap_invalidate_page(pmap, va, true);
4541 vm_page_aflag_set(om, PGA_REFERENCED);
4543 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4544 pv = pmap_pvh_remove(&om->md, pmap, va);
4545 if ((m->oflags & VPO_UNMANAGED) != 0)
4546 free_pv_entry(pmap, pv);
4547 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
4548 TAILQ_EMPTY(&om->md.pv_list) &&
4549 ((om->flags & PG_FICTITIOUS) != 0 ||
4550 TAILQ_EMPTY(&page_to_pvh(om)->pv_list)))
4551 vm_page_aflag_clear(om, PGA_WRITEABLE);
4553 KASSERT((orig_l3 & ATTR_AF) != 0,
4554 ("pmap_enter: unmanaged mapping lacks ATTR_AF"));
4555 pmap_invalidate_page(pmap, va, true);
4560 * Increment the counters.
4562 if ((new_l3 & ATTR_SW_WIRED) != 0)
4563 pmap->pm_stats.wired_count++;
4564 pmap_resident_count_inc(pmap, 1);
4567 * Enter on the PV list if part of our managed memory.
4569 if ((m->oflags & VPO_UNMANAGED) == 0) {
4571 pv = get_pv_entry(pmap, &lock);
4574 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4575 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4577 if ((new_l3 & ATTR_SW_DBM) != 0)
4578 vm_page_aflag_set(m, PGA_WRITEABLE);
4582 if (pmap->pm_stage == PM_STAGE1) {
4584 * Sync icache if exec permission and attribute
4585 * VM_MEMATTR_WRITE_BACK is set. Do it now, before the mapping
4586 * is stored and made valid for hardware table walk. If done
4587 * later, then other can access this page before caches are
4588 * properly synced. Don't do it for kernel memory which is
4589 * mapped with exec permission even if the memory isn't going
4590 * to hold executable code. The only time when icache sync is
4591 * needed is after kernel module is loaded and the relocation
4592 * info is processed. And it's done in elf_cpu_load_file().
4594 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4595 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
4596 (opa != pa || (orig_l3 & ATTR_S1_XN))) {
4597 PMAP_ASSERT_STAGE1(pmap);
4598 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4601 cpu_dcache_wb_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4605 * Update the L3 entry
4607 if (pmap_l3_valid(orig_l3)) {
4608 KASSERT(opa == pa, ("pmap_enter: invalid update"));
4609 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
4610 /* same PA, different attributes */
4611 orig_l3 = pmap_load_store(l3, new_l3);
4612 pmap_invalidate_page(pmap, va, true);
4613 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
4614 pmap_pte_dirty(pmap, orig_l3))
4619 * This can happens if multiple threads simultaneously
4620 * access not yet mapped page. This bad for performance
4621 * since this can cause full demotion-NOP-promotion
4623 * Another possible reasons are:
4624 * - VM and pmap memory layout are diverged
4625 * - tlb flush is missing somewhere and CPU doesn't see
4628 CTR4(KTR_PMAP, "%s: already mapped page - "
4629 "pmap %p va 0x%#lx pte 0x%lx",
4630 __func__, pmap, va, new_l3);
4634 pmap_store(l3, new_l3);
4638 #if VM_NRESERVLEVEL > 0
4640 * Try to promote from level 3 pages to a level 2 superpage. This
4641 * currently only works on stage 1 pmaps as pmap_promote_l2 looks at
4642 * stage 1 specific fields and performs a break-before-make sequence
4643 * that is incorrect a stage 2 pmap.
4645 if ((mpte == NULL || mpte->ref_count == NL3PG) &&
4646 pmap_ps_enabled(pmap) && pmap->pm_stage == PM_STAGE1 &&
4647 (m->flags & PG_FICTITIOUS) == 0 &&
4648 vm_reserv_level_iffullpop(m) == 0) {
4649 pmap_promote_l2(pmap, pde, va, mpte, &lock);
4662 * Tries to create a read- and/or execute-only 2MB page mapping. Returns
4663 * KERN_SUCCESS if the mapping was created. Otherwise, returns an error
4664 * value. See pmap_enter_l2() for the possible error values when "no sleep",
4665 * "no replace", and "no reclaim" are specified.
4668 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4669 struct rwlock **lockp)
4673 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4674 PMAP_ASSERT_STAGE1(pmap);
4675 KASSERT(ADDR_IS_CANONICAL(va),
4676 ("%s: Address not in canonical form: %lx", __func__, va));
4678 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
4679 ATTR_S1_IDX(m->md.pv_memattr) | ATTR_S1_AP(ATTR_S1_AP_RO) |
4681 if ((m->oflags & VPO_UNMANAGED) == 0) {
4682 new_l2 |= ATTR_SW_MANAGED;
4685 if ((prot & VM_PROT_EXECUTE) == 0 ||
4686 m->md.pv_memattr == VM_MEMATTR_DEVICE)
4687 new_l2 |= ATTR_S1_XN;
4688 if (!ADDR_IS_KERNEL(va))
4689 new_l2 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4691 new_l2 |= ATTR_S1_UXN;
4692 if (pmap != kernel_pmap)
4693 new_l2 |= ATTR_S1_nG;
4694 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
4695 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, m, lockp));
4699 * Returns true if every page table entry in the specified page table is
4703 pmap_every_pte_zero(vm_paddr_t pa)
4705 pt_entry_t *pt_end, *pte;
4707 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
4708 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
4709 for (pt_end = pte + Ln_ENTRIES; pte < pt_end; pte++) {
4717 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
4718 * the mapping was created, and one of KERN_FAILURE, KERN_NO_SPACE, or
4719 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if
4720 * PMAP_ENTER_NOREPLACE was specified and a 4KB page mapping already exists
4721 * within the 2MB virtual address range starting at the specified virtual
4722 * address. Returns KERN_NO_SPACE if PMAP_ENTER_NOREPLACE was specified and a
4723 * 2MB page mapping already exists at the specified virtual address. Returns
4724 * KERN_RESOURCE_SHORTAGE if either (1) PMAP_ENTER_NOSLEEP was specified and a
4725 * page table page allocation failed or (2) PMAP_ENTER_NORECLAIM was specified
4726 * and a PV entry allocation failed.
4729 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
4730 vm_page_t m, struct rwlock **lockp)
4732 struct spglist free;
4733 pd_entry_t *l2, old_l2;
4736 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4737 KASSERT(ADDR_IS_CANONICAL(va),
4738 ("%s: Address not in canonical form: %lx", __func__, va));
4740 if ((l2 = pmap_alloc_l2(pmap, va, &l2pg, (flags &
4741 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
4742 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
4744 return (KERN_RESOURCE_SHORTAGE);
4748 * If there are existing mappings, either abort or remove them.
4750 if ((old_l2 = pmap_load(l2)) != 0) {
4751 KASSERT(l2pg == NULL || l2pg->ref_count > 1,
4752 ("pmap_enter_l2: l2pg's ref count is too low"));
4753 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
4754 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK) {
4758 "pmap_enter_l2: no space for va %#lx"
4759 " in pmap %p", va, pmap);
4760 return (KERN_NO_SPACE);
4761 } else if (!ADDR_IS_KERNEL(va) ||
4762 !pmap_every_pte_zero(old_l2 & ~ATTR_MASK)) {
4766 "pmap_enter_l2: failure for va %#lx"
4767 " in pmap %p", va, pmap);
4768 return (KERN_FAILURE);
4772 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
4773 (void)pmap_remove_l2(pmap, l2, va,
4774 pmap_load(pmap_l1(pmap, va)), &free, lockp);
4776 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
4778 if (!ADDR_IS_KERNEL(va)) {
4779 vm_page_free_pages_toq(&free, true);
4780 KASSERT(pmap_load(l2) == 0,
4781 ("pmap_enter_l2: non-zero L2 entry %p", l2));
4783 KASSERT(SLIST_EMPTY(&free),
4784 ("pmap_enter_l2: freed kernel page table page"));
4787 * Both pmap_remove_l2() and pmap_remove_l3_range()
4788 * will leave the kernel page table page zero filled.
4789 * Nonetheless, the TLB could have an intermediate
4790 * entry for the kernel page table page, so request
4791 * an invalidation at all levels after clearing
4792 * the L2_TABLE entry.
4794 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
4795 if (pmap_insert_pt_page(pmap, mt, false))
4796 panic("pmap_enter_l2: trie insert failed");
4798 pmap_s1_invalidate_page(pmap, va, false);
4802 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
4804 * Abort this mapping if its PV entry could not be created.
4806 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
4808 pmap_abort_ptp(pmap, va, l2pg);
4810 "pmap_enter_l2: failure for va %#lx in pmap %p",
4812 return (KERN_RESOURCE_SHORTAGE);
4814 if ((new_l2 & ATTR_SW_DBM) != 0)
4815 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4816 vm_page_aflag_set(mt, PGA_WRITEABLE);
4820 * Increment counters.
4822 if ((new_l2 & ATTR_SW_WIRED) != 0)
4823 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
4824 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
4827 * Conditionally sync the icache. See pmap_enter() for details.
4829 if ((new_l2 & ATTR_S1_XN) == 0 && ((new_l2 & ~ATTR_MASK) !=
4830 (old_l2 & ~ATTR_MASK) || (old_l2 & ATTR_S1_XN) != 0) &&
4831 pmap != kernel_pmap && m->md.pv_memattr == VM_MEMATTR_WRITE_BACK) {
4832 cpu_icache_sync_range(PHYS_TO_DMAP(new_l2 & ~ATTR_MASK),
4837 * Map the superpage.
4839 pmap_store(l2, new_l2);
4842 atomic_add_long(&pmap_l2_mappings, 1);
4843 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
4846 return (KERN_SUCCESS);
4850 * Maps a sequence of resident pages belonging to the same object.
4851 * The sequence begins with the given page m_start. This page is
4852 * mapped at the given virtual address start. Each subsequent page is
4853 * mapped at a virtual address that is offset from start by the same
4854 * amount as the page is offset from m_start within the object. The
4855 * last page in the sequence is the page with the largest offset from
4856 * m_start that can be mapped at a virtual address less than the given
4857 * virtual address end. Not every virtual page between start and end
4858 * is mapped; only those for which a resident page exists with the
4859 * corresponding offset from m_start are mapped.
4862 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4863 vm_page_t m_start, vm_prot_t prot)
4865 struct rwlock *lock;
4868 vm_pindex_t diff, psize;
4871 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4873 psize = atop(end - start);
4878 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4879 va = start + ptoa(diff);
4880 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
4881 m->psind == 1 && pmap_ps_enabled(pmap) &&
4882 ((rv = pmap_enter_2mpage(pmap, va, m, prot, &lock)) ==
4883 KERN_SUCCESS || rv == KERN_NO_SPACE))
4884 m = &m[L2_SIZE / PAGE_SIZE - 1];
4886 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
4888 m = TAILQ_NEXT(m, listq);
4896 * this code makes some *MAJOR* assumptions:
4897 * 1. Current pmap & pmap exists.
4900 * 4. No page table pages.
4901 * but is *MUCH* faster than pmap_enter...
4905 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4907 struct rwlock *lock;
4911 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
4918 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4919 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
4922 pt_entry_t *l1, *l2, *l3, l3_val;
4926 KASSERT(!VA_IS_CLEANMAP(va) ||
4927 (m->oflags & VPO_UNMANAGED) != 0,
4928 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4929 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4930 PMAP_ASSERT_STAGE1(pmap);
4931 KASSERT(ADDR_IS_CANONICAL(va),
4932 ("%s: Address not in canonical form: %lx", __func__, va));
4934 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
4936 * In the case that a page table page is not
4937 * resident, we are creating it here.
4939 if (!ADDR_IS_KERNEL(va)) {
4940 vm_pindex_t l2pindex;
4943 * Calculate pagetable page index
4945 l2pindex = pmap_l2_pindex(va);
4946 if (mpte && (mpte->pindex == l2pindex)) {
4950 * If the page table page is mapped, we just increment
4951 * the hold count, and activate it. Otherwise, we
4952 * attempt to allocate a page table page, passing NULL
4953 * instead of the PV list lock pointer because we don't
4954 * intend to sleep. If this attempt fails, we don't
4955 * retry. Instead, we give up.
4957 l1 = pmap_l1(pmap, va);
4958 if (l1 != NULL && pmap_load(l1) != 0) {
4959 if ((pmap_load(l1) & ATTR_DESCR_MASK) ==
4962 l2 = pmap_l1_to_l2(l1, va);
4963 if (pmap_load(l2) != 0) {
4964 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
4967 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) &
4971 mpte = _pmap_alloc_l3(pmap, l2pindex,
4977 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
4982 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4983 l3 = &l3[pmap_l3_index(va)];
4986 pde = pmap_pde(kernel_pmap, va, &lvl);
4987 KASSERT(pde != NULL,
4988 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
4991 ("pmap_enter_quick_locked: Invalid level %d", lvl));
4992 l3 = pmap_l2_to_l3(pde, va);
4996 * Abort if a mapping already exists.
4998 if (pmap_load(l3) != 0) {
5005 * Enter on the PV list if part of our managed memory.
5007 if ((m->oflags & VPO_UNMANAGED) == 0 &&
5008 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
5010 pmap_abort_ptp(pmap, va, mpte);
5015 * Increment counters
5017 pmap_resident_count_inc(pmap, 1);
5019 pa = VM_PAGE_TO_PHYS(m);
5020 l3_val = pa | ATTR_DEFAULT | ATTR_S1_IDX(m->md.pv_memattr) |
5021 ATTR_S1_AP(ATTR_S1_AP_RO) | L3_PAGE;
5022 if ((prot & VM_PROT_EXECUTE) == 0 ||
5023 m->md.pv_memattr == VM_MEMATTR_DEVICE)
5024 l3_val |= ATTR_S1_XN;
5025 if (!ADDR_IS_KERNEL(va))
5026 l3_val |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
5028 l3_val |= ATTR_S1_UXN;
5029 if (pmap != kernel_pmap)
5030 l3_val |= ATTR_S1_nG;
5033 * Now validate mapping with RO protection
5035 if ((m->oflags & VPO_UNMANAGED) == 0) {
5036 l3_val |= ATTR_SW_MANAGED;
5040 /* Sync icache before the mapping is stored to PTE */
5041 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
5042 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
5043 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
5045 pmap_store(l3, l3_val);
5052 * This code maps large physical mmap regions into the
5053 * processor address space. Note that some shortcuts
5054 * are taken, but the code works.
5057 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
5058 vm_pindex_t pindex, vm_size_t size)
5061 VM_OBJECT_ASSERT_WLOCKED(object);
5062 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
5063 ("pmap_object_init_pt: non-device object"));
5067 * Clear the wired attribute from the mappings for the specified range of
5068 * addresses in the given pmap. Every valid mapping within that range
5069 * must have the wired attribute set. In contrast, invalid mappings
5070 * cannot have the wired attribute set, so they are ignored.
5072 * The wired attribute of the page table entry is not a hardware feature,
5073 * so there is no need to invalidate any TLB entries.
5076 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5078 vm_offset_t va_next;
5079 pd_entry_t *l0, *l1, *l2;
5083 for (; sva < eva; sva = va_next) {
5084 l0 = pmap_l0(pmap, sva);
5085 if (pmap_load(l0) == 0) {
5086 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
5092 l1 = pmap_l0_to_l1(l0, sva);
5093 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
5096 if (pmap_load(l1) == 0)
5099 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
5100 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
5101 KASSERT(va_next <= eva,
5102 ("partial update of non-transparent 1G page "
5103 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
5104 pmap_load(l1), sva, eva, va_next));
5105 MPASS(pmap != kernel_pmap);
5106 MPASS((pmap_load(l1) & (ATTR_SW_MANAGED |
5107 ATTR_SW_WIRED)) == ATTR_SW_WIRED);
5108 pmap_clear_bits(l1, ATTR_SW_WIRED);
5109 pmap->pm_stats.wired_count -= L1_SIZE / PAGE_SIZE;
5113 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
5117 l2 = pmap_l1_to_l2(l1, sva);
5118 if (pmap_load(l2) == 0)
5121 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
5122 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
5123 panic("pmap_unwire: l2 %#jx is missing "
5124 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
5127 * Are we unwiring the entire large page? If not,
5128 * demote the mapping and fall through.
5130 if (sva + L2_SIZE == va_next && eva >= va_next) {
5131 pmap_clear_bits(l2, ATTR_SW_WIRED);
5132 pmap->pm_stats.wired_count -= L2_SIZE /
5135 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
5136 panic("pmap_unwire: demotion failed");
5138 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
5139 ("pmap_unwire: Invalid l2 entry after demotion"));
5143 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
5145 if (pmap_load(l3) == 0)
5147 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
5148 panic("pmap_unwire: l3 %#jx is missing "
5149 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
5152 * ATTR_SW_WIRED must be cleared atomically. Although
5153 * the pmap lock synchronizes access to ATTR_SW_WIRED,
5154 * the System MMU may write to the entry concurrently.
5156 pmap_clear_bits(l3, ATTR_SW_WIRED);
5157 pmap->pm_stats.wired_count--;
5164 * Copy the range specified by src_addr/len
5165 * from the source map to the range dst_addr/len
5166 * in the destination map.
5168 * This routine is only advisory and need not do anything.
5170 * Because the executable mappings created by this routine are copied,
5171 * it should not have to flush the instruction cache.
5174 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
5175 vm_offset_t src_addr)
5177 struct rwlock *lock;
5178 pd_entry_t *l0, *l1, *l2, srcptepaddr;
5179 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
5180 vm_offset_t addr, end_addr, va_next;
5181 vm_page_t dst_m, dstmpte, srcmpte;
5183 PMAP_ASSERT_STAGE1(dst_pmap);
5184 PMAP_ASSERT_STAGE1(src_pmap);
5186 if (dst_addr != src_addr)
5188 end_addr = src_addr + len;
5190 if (dst_pmap < src_pmap) {
5191 PMAP_LOCK(dst_pmap);
5192 PMAP_LOCK(src_pmap);
5194 PMAP_LOCK(src_pmap);
5195 PMAP_LOCK(dst_pmap);
5197 for (addr = src_addr; addr < end_addr; addr = va_next) {
5198 l0 = pmap_l0(src_pmap, addr);
5199 if (pmap_load(l0) == 0) {
5200 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
5206 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
5209 l1 = pmap_l0_to_l1(l0, addr);
5210 if (pmap_load(l1) == 0)
5212 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
5213 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
5214 KASSERT(va_next <= end_addr,
5215 ("partial update of non-transparent 1G page "
5216 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx",
5217 pmap_load(l1), addr, end_addr, va_next));
5218 srcptepaddr = pmap_load(l1);
5219 l1 = pmap_l1(dst_pmap, addr);
5221 if (_pmap_alloc_l3(dst_pmap,
5222 pmap_l0_pindex(addr), NULL) == NULL)
5224 l1 = pmap_l1(dst_pmap, addr);
5226 l0 = pmap_l0(dst_pmap, addr);
5227 dst_m = PHYS_TO_VM_PAGE(pmap_load(l0) &
5231 KASSERT(pmap_load(l1) == 0,
5232 ("1G mapping present in dst pmap "
5233 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx",
5234 pmap_load(l1), addr, end_addr, va_next));
5235 pmap_store(l1, srcptepaddr & ~ATTR_SW_WIRED);
5236 pmap_resident_count_inc(dst_pmap, L1_SIZE / PAGE_SIZE);
5240 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
5243 l2 = pmap_l1_to_l2(l1, addr);
5244 srcptepaddr = pmap_load(l2);
5245 if (srcptepaddr == 0)
5247 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
5249 * We can only virtual copy whole superpages.
5251 if ((addr & L2_OFFSET) != 0 ||
5252 addr + L2_SIZE > end_addr)
5254 l2 = pmap_alloc_l2(dst_pmap, addr, &dst_m, NULL);
5257 if (pmap_load(l2) == 0 &&
5258 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
5259 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
5260 PMAP_ENTER_NORECLAIM, &lock))) {
5262 * We leave the dirty bit unchanged because
5263 * managed read/write superpage mappings are
5264 * required to be dirty. However, managed
5265 * superpage mappings are not required to
5266 * have their accessed bit set, so we clear
5267 * it because we don't know if this mapping
5270 srcptepaddr &= ~ATTR_SW_WIRED;
5271 if ((srcptepaddr & ATTR_SW_MANAGED) != 0)
5272 srcptepaddr &= ~ATTR_AF;
5273 pmap_store(l2, srcptepaddr);
5274 pmap_resident_count_inc(dst_pmap, L2_SIZE /
5276 atomic_add_long(&pmap_l2_mappings, 1);
5278 pmap_abort_ptp(dst_pmap, addr, dst_m);
5281 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
5282 ("pmap_copy: invalid L2 entry"));
5283 srcptepaddr &= ~ATTR_MASK;
5284 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
5285 KASSERT(srcmpte->ref_count > 0,
5286 ("pmap_copy: source page table page is unused"));
5287 if (va_next > end_addr)
5289 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
5290 src_pte = &src_pte[pmap_l3_index(addr)];
5292 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
5293 ptetemp = pmap_load(src_pte);
5296 * We only virtual copy managed pages.
5298 if ((ptetemp & ATTR_SW_MANAGED) == 0)
5301 if (dstmpte != NULL) {
5302 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
5303 ("dstmpte pindex/addr mismatch"));
5304 dstmpte->ref_count++;
5305 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
5308 dst_pte = (pt_entry_t *)
5309 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
5310 dst_pte = &dst_pte[pmap_l3_index(addr)];
5311 if (pmap_load(dst_pte) == 0 &&
5312 pmap_try_insert_pv_entry(dst_pmap, addr,
5313 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
5315 * Clear the wired, modified, and accessed
5316 * (referenced) bits during the copy.
5318 mask = ATTR_AF | ATTR_SW_WIRED;
5320 if ((ptetemp & ATTR_SW_DBM) != 0)
5321 nbits |= ATTR_S1_AP_RW_BIT;
5322 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
5323 pmap_resident_count_inc(dst_pmap, 1);
5325 pmap_abort_ptp(dst_pmap, addr, dstmpte);
5328 /* Have we copied all of the valid mappings? */
5329 if (dstmpte->ref_count >= srcmpte->ref_count)
5335 * XXX This barrier may not be needed because the destination pmap is
5342 PMAP_UNLOCK(src_pmap);
5343 PMAP_UNLOCK(dst_pmap);
5347 * pmap_zero_page zeros the specified hardware page by mapping
5348 * the page into KVM and using bzero to clear its contents.
5351 pmap_zero_page(vm_page_t m)
5353 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5355 pagezero((void *)va);
5359 * pmap_zero_page_area zeros the specified hardware page by mapping
5360 * the page into KVM and using bzero to clear its contents.
5362 * off and size may not cover an area beyond a single hardware page.
5365 pmap_zero_page_area(vm_page_t m, int off, int size)
5367 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5369 if (off == 0 && size == PAGE_SIZE)
5370 pagezero((void *)va);
5372 bzero((char *)va + off, size);
5376 * pmap_copy_page copies the specified (machine independent)
5377 * page by mapping the page into virtual memory and using
5378 * bcopy to copy the page, one machine dependent page at a
5382 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
5384 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
5385 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
5387 pagecopy((void *)src, (void *)dst);
5390 int unmapped_buf_allowed = 1;
5393 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5394 vm_offset_t b_offset, int xfersize)
5398 vm_paddr_t p_a, p_b;
5399 vm_offset_t a_pg_offset, b_pg_offset;
5402 while (xfersize > 0) {
5403 a_pg_offset = a_offset & PAGE_MASK;
5404 m_a = ma[a_offset >> PAGE_SHIFT];
5405 p_a = m_a->phys_addr;
5406 b_pg_offset = b_offset & PAGE_MASK;
5407 m_b = mb[b_offset >> PAGE_SHIFT];
5408 p_b = m_b->phys_addr;
5409 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5410 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5411 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
5412 panic("!DMAP a %lx", p_a);
5414 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
5416 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
5417 panic("!DMAP b %lx", p_b);
5419 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
5421 bcopy(a_cp, b_cp, cnt);
5429 pmap_quick_enter_page(vm_page_t m)
5432 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
5436 pmap_quick_remove_page(vm_offset_t addr)
5441 * Returns true if the pmap's pv is one of the first
5442 * 16 pvs linked to from this page. This count may
5443 * be changed upwards or downwards in the future; it
5444 * is only necessary that true be returned for a small
5445 * subset of pmaps for proper page aging.
5448 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5450 struct md_page *pvh;
5451 struct rwlock *lock;
5456 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5457 ("pmap_page_exists_quick: page %p is not managed", m));
5459 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5461 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5462 if (PV_PMAP(pv) == pmap) {
5470 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5471 pvh = page_to_pvh(m);
5472 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5473 if (PV_PMAP(pv) == pmap) {
5487 * pmap_page_wired_mappings:
5489 * Return the number of managed mappings to the given physical page
5493 pmap_page_wired_mappings(vm_page_t m)
5495 struct rwlock *lock;
5496 struct md_page *pvh;
5500 int count, md_gen, pvh_gen;
5502 if ((m->oflags & VPO_UNMANAGED) != 0)
5504 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5508 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5510 if (!PMAP_TRYLOCK(pmap)) {
5511 md_gen = m->md.pv_gen;
5515 if (md_gen != m->md.pv_gen) {
5520 pte = pmap_pte_exists(pmap, pv->pv_va, 3, __func__);
5521 if ((pmap_load(pte) & ATTR_SW_WIRED) != 0)
5525 if ((m->flags & PG_FICTITIOUS) == 0) {
5526 pvh = page_to_pvh(m);
5527 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5529 if (!PMAP_TRYLOCK(pmap)) {
5530 md_gen = m->md.pv_gen;
5531 pvh_gen = pvh->pv_gen;
5535 if (md_gen != m->md.pv_gen ||
5536 pvh_gen != pvh->pv_gen) {
5541 pte = pmap_pte_exists(pmap, pv->pv_va, 2, __func__);
5542 if ((pmap_load(pte) & ATTR_SW_WIRED) != 0)
5552 * Returns true if the given page is mapped individually or as part of
5553 * a 2mpage. Otherwise, returns false.
5556 pmap_page_is_mapped(vm_page_t m)
5558 struct rwlock *lock;
5561 if ((m->oflags & VPO_UNMANAGED) != 0)
5563 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5565 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5566 ((m->flags & PG_FICTITIOUS) == 0 &&
5567 !TAILQ_EMPTY(&page_to_pvh(m)->pv_list));
5573 * Destroy all managed, non-wired mappings in the given user-space
5574 * pmap. This pmap cannot be active on any processor besides the
5577 * This function cannot be applied to the kernel pmap. Moreover, it
5578 * is not intended for general use. It is only to be used during
5579 * process termination. Consequently, it can be implemented in ways
5580 * that make it faster than pmap_remove(). First, it can more quickly
5581 * destroy mappings by iterating over the pmap's collection of PV
5582 * entries, rather than searching the page table. Second, it doesn't
5583 * have to test and clear the page table entries atomically, because
5584 * no processor is currently accessing the user address space. In
5585 * particular, a page table entry's dirty bit won't change state once
5586 * this function starts.
5589 pmap_remove_pages(pmap_t pmap)
5592 pt_entry_t *pte, tpte;
5593 struct spglist free;
5594 struct pv_chunklist free_chunks[PMAP_MEMDOM];
5595 vm_page_t m, ml3, mt;
5597 struct md_page *pvh;
5598 struct pv_chunk *pc, *npc;
5599 struct rwlock *lock;
5601 uint64_t inuse, bitmask;
5602 int allfree, field, i, idx, lvl;
5608 for (i = 0; i < PMAP_MEMDOM; i++)
5609 TAILQ_INIT(&free_chunks[i]);
5612 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5615 for (field = 0; field < _NPCM; field++) {
5616 inuse = ~pc->pc_map[field] & pc_freemask[field];
5617 while (inuse != 0) {
5618 bit = ffsl(inuse) - 1;
5619 bitmask = 1UL << bit;
5620 idx = field * 64 + bit;
5621 pv = &pc->pc_pventry[idx];
5624 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5625 KASSERT(pde != NULL,
5626 ("Attempting to remove an unmapped page"));
5630 pte = pmap_l1_to_l2(pde, pv->pv_va);
5631 tpte = pmap_load(pte);
5632 KASSERT((tpte & ATTR_DESCR_MASK) ==
5634 ("Attempting to remove an invalid "
5635 "block: %lx", tpte));
5638 pte = pmap_l2_to_l3(pde, pv->pv_va);
5639 tpte = pmap_load(pte);
5640 KASSERT((tpte & ATTR_DESCR_MASK) ==
5642 ("Attempting to remove an invalid "
5643 "page: %lx", tpte));
5647 "Invalid page directory level: %d",
5652 * We cannot remove wired pages from a process' mapping at this time
5654 if (tpte & ATTR_SW_WIRED) {
5660 pc->pc_map[field] |= bitmask;
5663 * Because this pmap is not active on other
5664 * processors, the dirty bit cannot have
5665 * changed state since we last loaded pte.
5669 pa = tpte & ~ATTR_MASK;
5671 m = PHYS_TO_VM_PAGE(pa);
5672 KASSERT(m->phys_addr == pa,
5673 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
5674 m, (uintmax_t)m->phys_addr,
5677 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
5678 m < &vm_page_array[vm_page_array_size],
5679 ("pmap_remove_pages: bad pte %#jx",
5683 * Update the vm_page_t clean/reference bits.
5685 if (pmap_pte_dirty(pmap, tpte)) {
5688 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
5697 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
5701 pmap_resident_count_dec(pmap,
5702 L2_SIZE / PAGE_SIZE);
5703 pvh = page_to_pvh(m);
5704 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
5706 if (TAILQ_EMPTY(&pvh->pv_list)) {
5707 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
5708 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
5709 TAILQ_EMPTY(&mt->md.pv_list))
5710 vm_page_aflag_clear(mt, PGA_WRITEABLE);
5712 ml3 = pmap_remove_pt_page(pmap,
5715 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
5716 ("pmap_remove_pages: l3 page not promoted"));
5717 pmap_resident_count_dec(pmap,1);
5718 KASSERT(ml3->ref_count == NL3PG,
5719 ("pmap_remove_pages: l3 page ref count error"));
5721 pmap_add_delayed_free_list(ml3,
5726 pmap_resident_count_dec(pmap, 1);
5727 TAILQ_REMOVE(&m->md.pv_list, pv,
5730 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
5731 TAILQ_EMPTY(&m->md.pv_list) &&
5732 (m->flags & PG_FICTITIOUS) == 0) {
5733 pvh = page_to_pvh(m);
5734 if (TAILQ_EMPTY(&pvh->pv_list))
5735 vm_page_aflag_clear(m,
5740 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
5745 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
5746 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
5747 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
5749 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5750 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc,
5756 pmap_invalidate_all(pmap);
5757 free_pv_chunk_batch(free_chunks);
5759 vm_page_free_pages_toq(&free, true);
5763 * This is used to check if a page has been accessed or modified.
5766 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
5768 struct rwlock *lock;
5770 struct md_page *pvh;
5771 pt_entry_t *pte, mask, value;
5773 int md_gen, pvh_gen;
5777 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5780 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5782 PMAP_ASSERT_STAGE1(pmap);
5783 if (!PMAP_TRYLOCK(pmap)) {
5784 md_gen = m->md.pv_gen;
5788 if (md_gen != m->md.pv_gen) {
5793 pte = pmap_pte_exists(pmap, pv->pv_va, 3, __func__);
5797 mask |= ATTR_S1_AP_RW_BIT;
5798 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
5801 mask |= ATTR_AF | ATTR_DESCR_MASK;
5802 value |= ATTR_AF | L3_PAGE;
5804 rv = (pmap_load(pte) & mask) == value;
5809 if ((m->flags & PG_FICTITIOUS) == 0) {
5810 pvh = page_to_pvh(m);
5811 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5813 PMAP_ASSERT_STAGE1(pmap);
5814 if (!PMAP_TRYLOCK(pmap)) {
5815 md_gen = m->md.pv_gen;
5816 pvh_gen = pvh->pv_gen;
5820 if (md_gen != m->md.pv_gen ||
5821 pvh_gen != pvh->pv_gen) {
5826 pte = pmap_pte_exists(pmap, pv->pv_va, 2, __func__);
5830 mask |= ATTR_S1_AP_RW_BIT;
5831 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
5834 mask |= ATTR_AF | ATTR_DESCR_MASK;
5835 value |= ATTR_AF | L2_BLOCK;
5837 rv = (pmap_load(pte) & mask) == value;
5851 * Return whether or not the specified physical page was modified
5852 * in any physical maps.
5855 pmap_is_modified(vm_page_t m)
5858 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5859 ("pmap_is_modified: page %p is not managed", m));
5862 * If the page is not busied then this check is racy.
5864 if (!pmap_page_is_write_mapped(m))
5866 return (pmap_page_test_mappings(m, FALSE, TRUE));
5870 * pmap_is_prefaultable:
5872 * Return whether or not the specified virtual address is eligible
5876 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5884 * Return TRUE if and only if the L3 entry for the specified virtual
5885 * address is allocated but invalid.
5889 pde = pmap_pde(pmap, addr, &lvl);
5890 if (pde != NULL && lvl == 2) {
5891 pte = pmap_l2_to_l3(pde, addr);
5892 rv = pmap_load(pte) == 0;
5899 * pmap_is_referenced:
5901 * Return whether or not the specified physical page was referenced
5902 * in any physical maps.
5905 pmap_is_referenced(vm_page_t m)
5908 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5909 ("pmap_is_referenced: page %p is not managed", m));
5910 return (pmap_page_test_mappings(m, TRUE, FALSE));
5914 * Clear the write and modified bits in each of the given page's mappings.
5917 pmap_remove_write(vm_page_t m)
5919 struct md_page *pvh;
5921 struct rwlock *lock;
5922 pv_entry_t next_pv, pv;
5923 pt_entry_t oldpte, *pte, set, clear, mask, val;
5925 int md_gen, pvh_gen;
5927 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5928 ("pmap_remove_write: page %p is not managed", m));
5929 vm_page_assert_busied(m);
5931 if (!pmap_page_is_write_mapped(m))
5933 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5934 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
5937 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5939 PMAP_ASSERT_STAGE1(pmap);
5940 if (!PMAP_TRYLOCK(pmap)) {
5941 pvh_gen = pvh->pv_gen;
5945 if (pvh_gen != pvh->pv_gen) {
5951 pte = pmap_pte_exists(pmap, va, 2, __func__);
5952 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
5953 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
5954 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5955 ("inconsistent pv lock %p %p for page %p",
5956 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5959 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5961 if (!PMAP_TRYLOCK(pmap)) {
5962 pvh_gen = pvh->pv_gen;
5963 md_gen = m->md.pv_gen;
5967 if (pvh_gen != pvh->pv_gen ||
5968 md_gen != m->md.pv_gen) {
5973 pte = pmap_pte_exists(pmap, pv->pv_va, 3, __func__);
5974 oldpte = pmap_load(pte);
5975 if ((oldpte & ATTR_SW_DBM) != 0) {
5976 if (pmap->pm_stage == PM_STAGE1) {
5977 set = ATTR_S1_AP_RW_BIT;
5979 mask = ATTR_S1_AP_RW_BIT;
5980 val = ATTR_S1_AP(ATTR_S1_AP_RW);
5983 clear = ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
5984 mask = ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
5985 val = ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
5987 clear |= ATTR_SW_DBM;
5988 while (!atomic_fcmpset_64(pte, &oldpte,
5989 (oldpte | set) & ~clear))
5992 if ((oldpte & mask) == val)
5994 pmap_invalidate_page(pmap, pv->pv_va, true);
5999 vm_page_aflag_clear(m, PGA_WRITEABLE);
6003 * pmap_ts_referenced:
6005 * Return a count of reference bits for a page, clearing those bits.
6006 * It is not necessary for every reference bit to be cleared, but it
6007 * is necessary that 0 only be returned when there are truly no
6008 * reference bits set.
6010 * As an optimization, update the page's dirty field if a modified bit is
6011 * found while counting reference bits. This opportunistic update can be
6012 * performed at low cost and can eliminate the need for some future calls
6013 * to pmap_is_modified(). However, since this function stops after
6014 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
6015 * dirty pages. Those dirty pages will only be detected by a future call
6016 * to pmap_is_modified().
6019 pmap_ts_referenced(vm_page_t m)
6021 struct md_page *pvh;
6024 struct rwlock *lock;
6025 pt_entry_t *pte, tpte;
6028 int cleared, md_gen, not_cleared, pvh_gen;
6029 struct spglist free;
6031 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6032 ("pmap_ts_referenced: page %p is not managed", m));
6035 pa = VM_PAGE_TO_PHYS(m);
6036 lock = PHYS_TO_PV_LIST_LOCK(pa);
6037 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
6041 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
6042 goto small_mappings;
6048 if (!PMAP_TRYLOCK(pmap)) {
6049 pvh_gen = pvh->pv_gen;
6053 if (pvh_gen != pvh->pv_gen) {
6059 pte = pmap_pte_exists(pmap, va, 2, __func__);
6060 tpte = pmap_load(pte);
6061 if (pmap_pte_dirty(pmap, tpte)) {
6063 * Although "tpte" is mapping a 2MB page, because
6064 * this function is called at a 4KB page granularity,
6065 * we only update the 4KB page under test.
6069 if ((tpte & ATTR_AF) != 0) {
6071 * Since this reference bit is shared by 512 4KB pages,
6072 * it should not be cleared every time it is tested.
6073 * Apply a simple "hash" function on the physical page
6074 * number, the virtual superpage number, and the pmap
6075 * address to select one 4KB page out of the 512 on
6076 * which testing the reference bit will result in
6077 * clearing that reference bit. This function is
6078 * designed to avoid the selection of the same 4KB page
6079 * for every 2MB page mapping.
6081 * On demotion, a mapping that hasn't been referenced
6082 * is simply destroyed. To avoid the possibility of a
6083 * subsequent page fault on a demoted wired mapping,
6084 * always leave its reference bit set. Moreover,
6085 * since the superpage is wired, the current state of
6086 * its reference bit won't affect page replacement.
6088 if ((((pa >> PAGE_SHIFT) ^ (va >> L2_SHIFT) ^
6089 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
6090 (tpte & ATTR_SW_WIRED) == 0) {
6091 pmap_clear_bits(pte, ATTR_AF);
6092 pmap_invalidate_page(pmap, va, true);
6098 /* Rotate the PV list if it has more than one entry. */
6099 if (TAILQ_NEXT(pv, pv_next) != NULL) {
6100 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6101 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
6104 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
6106 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
6108 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
6115 if (!PMAP_TRYLOCK(pmap)) {
6116 pvh_gen = pvh->pv_gen;
6117 md_gen = m->md.pv_gen;
6121 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6126 pte = pmap_pte_exists(pmap, pv->pv_va, 3, __func__);
6127 tpte = pmap_load(pte);
6128 if (pmap_pte_dirty(pmap, tpte))
6130 if ((tpte & ATTR_AF) != 0) {
6131 if ((tpte & ATTR_SW_WIRED) == 0) {
6132 pmap_clear_bits(pte, ATTR_AF);
6133 pmap_invalidate_page(pmap, pv->pv_va, true);
6139 /* Rotate the PV list if it has more than one entry. */
6140 if (TAILQ_NEXT(pv, pv_next) != NULL) {
6141 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6142 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6145 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
6146 not_cleared < PMAP_TS_REFERENCED_MAX);
6149 vm_page_free_pages_toq(&free, true);
6150 return (cleared + not_cleared);
6154 * Apply the given advice to the specified range of addresses within the
6155 * given pmap. Depending on the advice, clear the referenced and/or
6156 * modified flags in each mapping and set the mapped page's dirty field.
6159 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
6161 struct rwlock *lock;
6162 vm_offset_t va, va_next;
6164 pd_entry_t *l0, *l1, *l2, oldl2;
6165 pt_entry_t *l3, oldl3;
6167 PMAP_ASSERT_STAGE1(pmap);
6169 if (advice != MADV_DONTNEED && advice != MADV_FREE)
6173 for (; sva < eva; sva = va_next) {
6174 l0 = pmap_l0(pmap, sva);
6175 if (pmap_load(l0) == 0) {
6176 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
6182 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
6185 l1 = pmap_l0_to_l1(l0, sva);
6186 if (pmap_load(l1) == 0)
6188 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
6189 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
6193 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
6196 l2 = pmap_l1_to_l2(l1, sva);
6197 oldl2 = pmap_load(l2);
6200 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
6201 if ((oldl2 & ATTR_SW_MANAGED) == 0)
6204 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
6209 * The 2MB page mapping was destroyed.
6215 * Unless the page mappings are wired, remove the
6216 * mapping to a single page so that a subsequent
6217 * access may repromote. Choosing the last page
6218 * within the address range [sva, min(va_next, eva))
6219 * generally results in more repromotions. Since the
6220 * underlying page table page is fully populated, this
6221 * removal never frees a page table page.
6223 if ((oldl2 & ATTR_SW_WIRED) == 0) {
6229 ("pmap_advise: no address gap"));
6230 l3 = pmap_l2_to_l3(l2, va);
6231 KASSERT(pmap_load(l3) != 0,
6232 ("pmap_advise: invalid PTE"));
6233 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
6239 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
6240 ("pmap_advise: invalid L2 entry after demotion"));
6244 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
6246 oldl3 = pmap_load(l3);
6247 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
6248 (ATTR_SW_MANAGED | L3_PAGE))
6250 else if (pmap_pte_dirty(pmap, oldl3)) {
6251 if (advice == MADV_DONTNEED) {
6253 * Future calls to pmap_is_modified()
6254 * can be avoided by making the page
6257 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK);
6260 while (!atomic_fcmpset_long(l3, &oldl3,
6261 (oldl3 & ~ATTR_AF) |
6262 ATTR_S1_AP(ATTR_S1_AP_RO)))
6264 } else if ((oldl3 & ATTR_AF) != 0)
6265 pmap_clear_bits(l3, ATTR_AF);
6272 if (va != va_next) {
6273 pmap_s1_invalidate_range(pmap, va, sva, true);
6278 pmap_s1_invalidate_range(pmap, va, sva, true);
6284 * Clear the modify bits on the specified physical page.
6287 pmap_clear_modify(vm_page_t m)
6289 struct md_page *pvh;
6290 struct rwlock *lock;
6292 pv_entry_t next_pv, pv;
6293 pd_entry_t *l2, oldl2;
6294 pt_entry_t *l3, oldl3;
6296 int md_gen, pvh_gen;
6298 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6299 ("pmap_clear_modify: page %p is not managed", m));
6300 vm_page_assert_busied(m);
6302 if (!pmap_page_is_write_mapped(m))
6304 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
6305 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6308 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6310 PMAP_ASSERT_STAGE1(pmap);
6311 if (!PMAP_TRYLOCK(pmap)) {
6312 pvh_gen = pvh->pv_gen;
6316 if (pvh_gen != pvh->pv_gen) {
6322 l2 = pmap_l2(pmap, va);
6323 oldl2 = pmap_load(l2);
6324 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */
6325 if ((oldl2 & ATTR_SW_DBM) != 0 &&
6326 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
6327 (oldl2 & ATTR_SW_WIRED) == 0) {
6329 * Write protect the mapping to a single page so that
6330 * a subsequent write access may repromote.
6332 va += VM_PAGE_TO_PHYS(m) - (oldl2 & ~ATTR_MASK);
6333 l3 = pmap_l2_to_l3(l2, va);
6334 oldl3 = pmap_load(l3);
6335 while (!atomic_fcmpset_long(l3, &oldl3,
6336 (oldl3 & ~ATTR_SW_DBM) | ATTR_S1_AP(ATTR_S1_AP_RO)))
6339 pmap_s1_invalidate_page(pmap, va, true);
6343 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6345 PMAP_ASSERT_STAGE1(pmap);
6346 if (!PMAP_TRYLOCK(pmap)) {
6347 md_gen = m->md.pv_gen;
6348 pvh_gen = pvh->pv_gen;
6352 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6357 l2 = pmap_l2(pmap, pv->pv_va);
6358 l3 = pmap_l2_to_l3(l2, pv->pv_va);
6359 oldl3 = pmap_load(l3);
6360 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM){
6361 pmap_set_bits(l3, ATTR_S1_AP(ATTR_S1_AP_RO));
6362 pmap_s1_invalidate_page(pmap, pv->pv_va, true);
6370 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6372 struct pmap_preinit_mapping *ppim;
6373 vm_offset_t va, offset;
6376 int i, lvl, l2_blocks, free_l2_count, start_idx;
6378 if (!vm_initialized) {
6380 * No L3 ptables so map entire L2 blocks where start VA is:
6381 * preinit_map_va + start_idx * L2_SIZE
6382 * There may be duplicate mappings (multiple VA -> same PA) but
6383 * ARM64 dcache is always PIPT so that's acceptable.
6388 /* Calculate how many L2 blocks are needed for the mapping */
6389 l2_blocks = (roundup2(pa + size, L2_SIZE) -
6390 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
6392 offset = pa & L2_OFFSET;
6394 if (preinit_map_va == 0)
6397 /* Map 2MiB L2 blocks from reserved VA space */
6401 /* Find enough free contiguous VA space */
6402 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6403 ppim = pmap_preinit_mapping + i;
6404 if (free_l2_count > 0 && ppim->pa != 0) {
6405 /* Not enough space here */
6411 if (ppim->pa == 0) {
6413 if (start_idx == -1)
6416 if (free_l2_count == l2_blocks)
6420 if (free_l2_count != l2_blocks)
6421 panic("%s: too many preinit mappings", __func__);
6423 va = preinit_map_va + (start_idx * L2_SIZE);
6424 for (i = start_idx; i < start_idx + l2_blocks; i++) {
6425 /* Mark entries as allocated */
6426 ppim = pmap_preinit_mapping + i;
6428 ppim->va = va + offset;
6433 pa = rounddown2(pa, L2_SIZE);
6434 for (i = 0; i < l2_blocks; i++) {
6435 pde = pmap_pde(kernel_pmap, va, &lvl);
6436 KASSERT(pde != NULL,
6437 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
6440 ("pmap_mapbios: Invalid level %d", lvl));
6442 /* Insert L2_BLOCK */
6443 l2 = pmap_l1_to_l2(pde, va);
6445 pa | ATTR_DEFAULT | ATTR_S1_XN |
6446 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
6451 pmap_s1_invalidate_all(kernel_pmap);
6453 va = preinit_map_va + (start_idx * L2_SIZE);
6456 /* kva_alloc may be used to map the pages */
6457 offset = pa & PAGE_MASK;
6458 size = round_page(offset + size);
6460 va = kva_alloc(size);
6462 panic("%s: Couldn't allocate KVA", __func__);
6464 pde = pmap_pde(kernel_pmap, va, &lvl);
6465 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
6467 /* L3 table is linked */
6468 va = trunc_page(va);
6469 pa = trunc_page(pa);
6470 pmap_kenter(va, size, pa, memory_mapping_mode(pa));
6473 return ((void *)(va + offset));
6477 pmap_unmapbios(void *p, vm_size_t size)
6479 struct pmap_preinit_mapping *ppim;
6480 vm_offset_t offset, tmpsize, va, va_trunc;
6483 int i, lvl, l2_blocks, block;
6486 va = (vm_offset_t)p;
6488 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
6489 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
6491 /* Remove preinit mapping */
6492 preinit_map = false;
6494 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6495 ppim = pmap_preinit_mapping + i;
6496 if (ppim->va == va) {
6497 KASSERT(ppim->size == size,
6498 ("pmap_unmapbios: size mismatch"));
6503 offset = block * L2_SIZE;
6504 va_trunc = rounddown2(va, L2_SIZE) + offset;
6506 /* Remove L2_BLOCK */
6507 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
6508 KASSERT(pde != NULL,
6509 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
6511 l2 = pmap_l1_to_l2(pde, va_trunc);
6514 if (block == (l2_blocks - 1))
6520 pmap_s1_invalidate_all(kernel_pmap);
6524 /* Unmap the pages reserved with kva_alloc. */
6525 if (vm_initialized) {
6526 offset = va & PAGE_MASK;
6527 size = round_page(offset + size);
6528 va = trunc_page(va);
6530 pde = pmap_pde(kernel_pmap, va, &lvl);
6531 KASSERT(pde != NULL,
6532 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
6533 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
6535 /* Unmap and invalidate the pages */
6536 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6537 pmap_kremove(va + tmpsize);
6544 * Sets the memory attribute for the specified page.
6547 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
6550 m->md.pv_memattr = ma;
6553 * If "m" is a normal page, update its direct mapping. This update
6554 * can be relied upon to perform any cache operations that are
6555 * required for data coherence.
6557 if ((m->flags & PG_FICTITIOUS) == 0 &&
6558 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
6559 m->md.pv_memattr) != 0)
6560 panic("memory attribute change on the direct map failed");
6564 * Changes the specified virtual address range's memory type to that given by
6565 * the parameter "mode". The specified virtual address range must be
6566 * completely contained within either the direct map or the kernel map. If
6567 * the virtual address range is contained within the kernel map, then the
6568 * memory type for each of the corresponding ranges of the direct map is also
6569 * changed. (The corresponding ranges of the direct map are those ranges that
6570 * map the same physical pages as the specified virtual address range.) These
6571 * changes to the direct map are necessary because Intel describes the
6572 * behavior of their processors as "undefined" if two or more mappings to the
6573 * same physical page have different memory types.
6575 * Returns zero if the change completed successfully, and either EINVAL or
6576 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
6577 * of the virtual address range was not mapped, and ENOMEM is returned if
6578 * there was insufficient memory available to complete the change. In the
6579 * latter case, the memory type may have been changed on some part of the
6580 * virtual address range or the direct map.
6583 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
6587 PMAP_LOCK(kernel_pmap);
6588 error = pmap_change_props_locked(va, size, PROT_NONE, mode, false);
6589 PMAP_UNLOCK(kernel_pmap);
6594 * Changes the specified virtual address range's protections to those
6595 * specified by "prot". Like pmap_change_attr(), protections for aliases
6596 * in the direct map are updated as well. Protections on aliasing mappings may
6597 * be a subset of the requested protections; for example, mappings in the direct
6598 * map are never executable.
6601 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
6605 /* Only supported within the kernel map. */
6606 if (va < VM_MIN_KERNEL_ADDRESS)
6609 PMAP_LOCK(kernel_pmap);
6610 error = pmap_change_props_locked(va, size, prot, -1, false);
6611 PMAP_UNLOCK(kernel_pmap);
6616 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
6617 int mode, bool skip_unmapped)
6619 vm_offset_t base, offset, tmpva;
6622 pt_entry_t pte, *ptep, *newpte;
6623 pt_entry_t bits, mask;
6626 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
6627 base = trunc_page(va);
6628 offset = va & PAGE_MASK;
6629 size = round_page(offset + size);
6631 if (!VIRT_IN_DMAP(base) &&
6632 !(base >= VM_MIN_KERNEL_ADDRESS && base < VM_MAX_KERNEL_ADDRESS))
6638 bits = ATTR_S1_IDX(mode);
6639 mask = ATTR_S1_IDX_MASK;
6640 if (mode == VM_MEMATTR_DEVICE) {
6645 if (prot != VM_PROT_NONE) {
6646 /* Don't mark the DMAP as executable. It never is on arm64. */
6647 if (VIRT_IN_DMAP(base)) {
6648 prot &= ~VM_PROT_EXECUTE;
6650 * XXX Mark the DMAP as writable for now. We rely
6651 * on this in ddb & dtrace to insert breakpoint
6654 prot |= VM_PROT_WRITE;
6657 if ((prot & VM_PROT_WRITE) == 0) {
6658 bits |= ATTR_S1_AP(ATTR_S1_AP_RO);
6660 if ((prot & VM_PROT_EXECUTE) == 0) {
6661 bits |= ATTR_S1_PXN;
6663 bits |= ATTR_S1_UXN;
6664 mask |= ATTR_S1_AP_MASK | ATTR_S1_XN;
6667 for (tmpva = base; tmpva < base + size; ) {
6668 ptep = pmap_pte(kernel_pmap, tmpva, &lvl);
6669 if (ptep == NULL && !skip_unmapped) {
6671 } else if ((ptep == NULL && skip_unmapped) ||
6672 (pmap_load(ptep) & mask) == bits) {
6674 * We already have the correct attribute or there
6675 * is no memory mapped at this address and we are
6676 * skipping unmapped memory.
6680 panic("Invalid DMAP table level: %d\n", lvl);
6682 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
6685 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
6692 /* We can't demote/promote this entry */
6693 MPASS((pmap_load(ptep) & ATTR_SW_NO_PROMOTE) == 0);
6696 * Split the entry to an level 3 table, then
6697 * set the new attribute.
6701 panic("Invalid DMAP table level: %d\n", lvl);
6703 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
6704 if ((tmpva & L1_OFFSET) == 0 &&
6705 (base + size - tmpva) >= L1_SIZE) {
6709 newpte = pmap_demote_l1(kernel_pmap, ptep,
6710 tmpva & ~L1_OFFSET);
6713 ptep = pmap_l1_to_l2(ptep, tmpva);
6716 if ((tmpva & L2_OFFSET) == 0 &&
6717 (base + size - tmpva) >= L2_SIZE) {
6721 newpte = pmap_demote_l2(kernel_pmap, ptep,
6725 ptep = pmap_l2_to_l3(ptep, tmpva);
6728 pte_size = PAGE_SIZE;
6732 /* Update the entry */
6733 pte = pmap_load(ptep);
6737 pmap_update_entry(kernel_pmap, ptep, pte, tmpva,
6740 pa = pte & ~ATTR_MASK;
6741 if (!VIRT_IN_DMAP(tmpva) && PHYS_IN_DMAP(pa)) {
6743 * Keep the DMAP memory in sync.
6745 rv = pmap_change_props_locked(
6746 PHYS_TO_DMAP(pa), pte_size,
6753 * If moving to a non-cacheable entry flush
6756 if (mode == VM_MEMATTR_UNCACHEABLE)
6757 cpu_dcache_wbinv_range(tmpva, pte_size);
6766 * Create an L2 table to map all addresses within an L1 mapping.
6769 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
6771 pt_entry_t *l2, newl2, oldl1;
6773 vm_paddr_t l2phys, phys;
6777 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6778 oldl1 = pmap_load(l1);
6779 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
6780 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
6781 ("pmap_demote_l1: Demoting a non-block entry"));
6782 KASSERT((va & L1_OFFSET) == 0,
6783 ("pmap_demote_l1: Invalid virtual address %#lx", va));
6784 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
6785 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
6786 KASSERT((oldl1 & ATTR_SW_NO_PROMOTE) == 0,
6787 ("pmap_demote_l1: Demoting entry with no-demote flag set"));
6790 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
6791 tmpl1 = kva_alloc(PAGE_SIZE);
6796 if ((ml2 = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED)) ==
6798 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
6799 " in pmap %p", va, pmap);
6804 l2phys = VM_PAGE_TO_PHYS(ml2);
6805 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
6807 /* Address the range points at */
6808 phys = oldl1 & ~ATTR_MASK;
6809 /* The attributed from the old l1 table to be copied */
6810 newl2 = oldl1 & ATTR_MASK;
6812 /* Create the new entries */
6813 for (i = 0; i < Ln_ENTRIES; i++) {
6814 l2[i] = newl2 | phys;
6817 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
6818 ("Invalid l2 page (%lx != %lx)", l2[0],
6819 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
6822 pmap_kenter(tmpl1, PAGE_SIZE,
6823 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET,
6824 VM_MEMATTR_WRITE_BACK);
6825 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
6828 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
6832 pmap_kremove(tmpl1);
6833 kva_free(tmpl1, PAGE_SIZE);
6840 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
6844 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
6851 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
6852 struct rwlock **lockp)
6854 struct spglist free;
6857 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
6859 vm_page_free_pages_toq(&free, true);
6863 * Create an L3 table to map all addresses within an L2 mapping.
6866 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
6867 struct rwlock **lockp)
6869 pt_entry_t *l3, newl3, oldl2;
6874 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6875 PMAP_ASSERT_STAGE1(pmap);
6876 KASSERT(ADDR_IS_CANONICAL(va),
6877 ("%s: Address not in canonical form: %lx", __func__, va));
6880 oldl2 = pmap_load(l2);
6881 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
6882 ("pmap_demote_l2: Demoting a non-block entry"));
6883 KASSERT((oldl2 & ATTR_SW_NO_PROMOTE) == 0,
6884 ("pmap_demote_l2: Demoting entry with no-demote flag set"));
6888 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
6889 tmpl2 = kva_alloc(PAGE_SIZE);
6895 * Invalidate the 2MB page mapping and return "failure" if the
6896 * mapping was never accessed.
6898 if ((oldl2 & ATTR_AF) == 0) {
6899 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
6900 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
6901 pmap_demote_l2_abort(pmap, va, l2, lockp);
6902 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
6907 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
6908 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
6909 ("pmap_demote_l2: page table page for a wired mapping"
6913 * If the page table page is missing and the mapping
6914 * is for a kernel address, the mapping must belong to
6915 * either the direct map or the early kernel memory.
6916 * Page table pages are preallocated for every other
6917 * part of the kernel address space, so the direct map
6918 * region and early kernel memory are the only parts of the
6919 * kernel address space that must be handled here.
6921 KASSERT(!ADDR_IS_KERNEL(va) || VIRT_IN_DMAP(va) ||
6922 (va >= VM_MIN_KERNEL_ADDRESS && va < kernel_vm_end),
6923 ("pmap_demote_l2: No saved mpte for va %#lx", va));
6926 * If the 2MB page mapping belongs to the direct map
6927 * region of the kernel's address space, then the page
6928 * allocation request specifies the highest possible
6929 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
6930 * priority is normal.
6932 ml3 = vm_page_alloc_noobj(
6933 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : 0) |
6937 * If the allocation of the new page table page fails,
6938 * invalidate the 2MB page mapping and return "failure".
6941 pmap_demote_l2_abort(pmap, va, l2, lockp);
6942 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
6943 " in pmap %p", va, pmap);
6946 ml3->pindex = pmap_l2_pindex(va);
6948 if (!ADDR_IS_KERNEL(va)) {
6949 ml3->ref_count = NL3PG;
6950 pmap_resident_count_inc(pmap, 1);
6953 l3phys = VM_PAGE_TO_PHYS(ml3);
6954 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
6955 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
6956 KASSERT((oldl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) !=
6957 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM),
6958 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
6961 * If the page table page is not leftover from an earlier promotion,
6962 * or the mapping attributes have changed, (re)initialize the L3 table.
6964 * When pmap_update_entry() clears the old L2 mapping, it (indirectly)
6965 * performs a dsb(). That dsb() ensures that the stores for filling
6966 * "l3" are visible before "l3" is added to the page table.
6968 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK))
6969 pmap_fill_l3(l3, newl3);
6972 * Map the temporary page so we don't lose access to the l2 table.
6975 pmap_kenter(tmpl2, PAGE_SIZE,
6976 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET,
6977 VM_MEMATTR_WRITE_BACK);
6978 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
6982 * The spare PV entries must be reserved prior to demoting the
6983 * mapping, that is, prior to changing the PDE. Otherwise, the state
6984 * of the L2 and the PV lists will be inconsistent, which can result
6985 * in reclaim_pv_chunk() attempting to remove a PV entry from the
6986 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
6987 * PV entry for the 2MB page mapping that is being demoted.
6989 if ((oldl2 & ATTR_SW_MANAGED) != 0)
6990 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
6993 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
6994 * the 2MB page mapping.
6996 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
6999 * Demote the PV entry.
7001 if ((oldl2 & ATTR_SW_MANAGED) != 0)
7002 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
7004 atomic_add_long(&pmap_l2_demotions, 1);
7005 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
7006 " in pmap %p %lx", va, pmap, l3[0]);
7010 pmap_kremove(tmpl2);
7011 kva_free(tmpl2, PAGE_SIZE);
7019 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
7021 struct rwlock *lock;
7025 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
7032 * Perform the pmap work for mincore(2). If the page is not both referenced and
7033 * modified by this pmap, returns its physical address so that the caller can
7034 * find other mappings.
7037 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
7039 pt_entry_t *pte, tpte;
7040 vm_paddr_t mask, pa;
7044 PMAP_ASSERT_STAGE1(pmap);
7046 pte = pmap_pte(pmap, addr, &lvl);
7048 tpte = pmap_load(pte);
7061 panic("pmap_mincore: invalid level %d", lvl);
7064 managed = (tpte & ATTR_SW_MANAGED) != 0;
7065 val = MINCORE_INCORE;
7067 val |= MINCORE_PSIND(3 - lvl);
7068 if ((managed && pmap_pte_dirty(pmap, tpte)) || (!managed &&
7069 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW)))
7070 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
7071 if ((tpte & ATTR_AF) == ATTR_AF)
7072 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
7074 pa = (tpte & ~ATTR_MASK) | (addr & mask);
7080 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
7081 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
7089 * Garbage collect every ASID that is neither active on a processor nor
7093 pmap_reset_asid_set(pmap_t pmap)
7096 int asid, cpuid, epoch;
7097 struct asid_set *set;
7098 enum pmap_stage stage;
7100 set = pmap->pm_asid_set;
7101 stage = pmap->pm_stage;
7103 set = pmap->pm_asid_set;
7104 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
7105 mtx_assert(&set->asid_set_mutex, MA_OWNED);
7108 * Ensure that the store to asid_epoch is globally visible before the
7109 * loads from pc_curpmap are performed.
7111 epoch = set->asid_epoch + 1;
7112 if (epoch == INT_MAX)
7114 set->asid_epoch = epoch;
7116 if (stage == PM_STAGE1) {
7117 __asm __volatile("tlbi vmalle1is");
7119 KASSERT(pmap_clean_stage2_tlbi != NULL,
7120 ("%s: Unset stage 2 tlb invalidation callback\n",
7122 pmap_clean_stage2_tlbi();
7125 bit_nclear(set->asid_set, ASID_FIRST_AVAILABLE,
7126 set->asid_set_size - 1);
7127 CPU_FOREACH(cpuid) {
7128 if (cpuid == curcpu)
7130 if (stage == PM_STAGE1) {
7131 curpmap = pcpu_find(cpuid)->pc_curpmap;
7132 PMAP_ASSERT_STAGE1(pmap);
7134 curpmap = pcpu_find(cpuid)->pc_curvmpmap;
7135 if (curpmap == NULL)
7137 PMAP_ASSERT_STAGE2(pmap);
7139 KASSERT(curpmap->pm_asid_set == set, ("Incorrect set"));
7140 asid = COOKIE_TO_ASID(curpmap->pm_cookie);
7143 bit_set(set->asid_set, asid);
7144 curpmap->pm_cookie = COOKIE_FROM(asid, epoch);
7149 * Allocate a new ASID for the specified pmap.
7152 pmap_alloc_asid(pmap_t pmap)
7154 struct asid_set *set;
7157 set = pmap->pm_asid_set;
7158 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
7160 mtx_lock_spin(&set->asid_set_mutex);
7163 * While this processor was waiting to acquire the asid set mutex,
7164 * pmap_reset_asid_set() running on another processor might have
7165 * updated this pmap's cookie to the current epoch. In which case, we
7166 * don't need to allocate a new ASID.
7168 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch)
7171 bit_ffc_at(set->asid_set, set->asid_next, set->asid_set_size,
7173 if (new_asid == -1) {
7174 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
7175 set->asid_next, &new_asid);
7176 if (new_asid == -1) {
7177 pmap_reset_asid_set(pmap);
7178 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
7179 set->asid_set_size, &new_asid);
7180 KASSERT(new_asid != -1, ("ASID allocation failure"));
7183 bit_set(set->asid_set, new_asid);
7184 set->asid_next = new_asid + 1;
7185 pmap->pm_cookie = COOKIE_FROM(new_asid, set->asid_epoch);
7187 mtx_unlock_spin(&set->asid_set_mutex);
7190 static uint64_t __read_mostly ttbr_flags;
7193 * Compute the value that should be stored in ttbr0 to activate the specified
7194 * pmap. This value may change from time to time.
7197 pmap_to_ttbr0(pmap_t pmap)
7201 ttbr = pmap->pm_ttbr;
7202 ttbr |= ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
7209 pmap_set_cnp(void *arg)
7211 uint64_t ttbr0, ttbr1;
7214 cpuid = *(u_int *)arg;
7215 if (cpuid == curcpu) {
7217 * Set the flags while all CPUs are handling the
7218 * smp_rendezvous so will not call pmap_to_ttbr0. Any calls
7219 * to pmap_to_ttbr0 after this will have the CnP flag set.
7220 * The dsb after invalidating the TLB will act as a barrier
7221 * to ensure all CPUs can observe this change.
7223 ttbr_flags |= TTBR_CnP;
7226 ttbr0 = READ_SPECIALREG(ttbr0_el1);
7229 ttbr1 = READ_SPECIALREG(ttbr1_el1);
7232 /* Update ttbr{0,1}_el1 with the CnP flag */
7233 WRITE_SPECIALREG(ttbr0_el1, ttbr0);
7234 WRITE_SPECIALREG(ttbr1_el1, ttbr1);
7236 __asm __volatile("tlbi vmalle1is");
7242 * Defer enabling CnP until we have read the ID registers to know if it's
7243 * supported on all CPUs.
7246 pmap_init_cnp(void *dummy __unused)
7251 if (!get_kernel_reg(ID_AA64MMFR2_EL1, ®))
7254 if (ID_AA64MMFR2_CnP_VAL(reg) != ID_AA64MMFR2_CnP_NONE) {
7256 printf("Enabling CnP\n");
7258 smp_rendezvous(NULL, pmap_set_cnp, NULL, &cpuid);
7262 SYSINIT(pmap_init_cnp, SI_SUB_SMP, SI_ORDER_ANY, pmap_init_cnp, NULL);
7265 pmap_activate_int(pmap_t pmap)
7267 struct asid_set *set;
7270 KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap"));
7271 KASSERT(pmap != kernel_pmap, ("kernel pmap activation"));
7273 if ((pmap->pm_stage == PM_STAGE1 && pmap == PCPU_GET(curpmap)) ||
7274 (pmap->pm_stage == PM_STAGE2 && pmap == PCPU_GET(curvmpmap))) {
7276 * Handle the possibility that the old thread was preempted
7277 * after an "ic" or "tlbi" instruction but before it performed
7278 * a "dsb" instruction. If the old thread migrates to a new
7279 * processor, its completion of a "dsb" instruction on that
7280 * new processor does not guarantee that the "ic" or "tlbi"
7281 * instructions performed on the old processor have completed.
7287 set = pmap->pm_asid_set;
7288 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
7291 * Ensure that the store to curpmap is globally visible before the
7292 * load from asid_epoch is performed.
7294 if (pmap->pm_stage == PM_STAGE1)
7295 PCPU_SET(curpmap, pmap);
7297 PCPU_SET(curvmpmap, pmap);
7299 epoch = COOKIE_TO_EPOCH(pmap->pm_cookie);
7300 if (epoch >= 0 && epoch != set->asid_epoch)
7301 pmap_alloc_asid(pmap);
7303 if (pmap->pm_stage == PM_STAGE1) {
7304 set_ttbr0(pmap_to_ttbr0(pmap));
7305 if (PCPU_GET(bcast_tlbi_workaround) != 0)
7306 invalidate_local_icache();
7312 pmap_activate_vm(pmap_t pmap)
7315 PMAP_ASSERT_STAGE2(pmap);
7317 (void)pmap_activate_int(pmap);
7321 pmap_activate(struct thread *td)
7325 pmap = vmspace_pmap(td->td_proc->p_vmspace);
7326 PMAP_ASSERT_STAGE1(pmap);
7328 (void)pmap_activate_int(pmap);
7333 * Activate the thread we are switching to.
7334 * To simplify the assembly in cpu_throw return the new threads pcb.
7337 pmap_switch(struct thread *new)
7339 pcpu_bp_harden bp_harden;
7342 /* Store the new curthread */
7343 PCPU_SET(curthread, new);
7345 /* And the new pcb */
7347 PCPU_SET(curpcb, pcb);
7350 * TODO: We may need to flush the cache here if switching
7351 * to a user process.
7354 if (pmap_activate_int(vmspace_pmap(new->td_proc->p_vmspace))) {
7356 * Stop userspace from training the branch predictor against
7357 * other processes. This will call into a CPU specific
7358 * function that clears the branch predictor state.
7360 bp_harden = PCPU_GET(bp_harden);
7361 if (bp_harden != NULL)
7369 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
7372 PMAP_ASSERT_STAGE1(pmap);
7373 KASSERT(ADDR_IS_CANONICAL(va),
7374 ("%s: Address not in canonical form: %lx", __func__, va));
7376 if (ADDR_IS_KERNEL(va)) {
7377 cpu_icache_sync_range(va, sz);
7382 /* Find the length of data in this page to flush */
7383 offset = va & PAGE_MASK;
7384 len = imin(PAGE_SIZE - offset, sz);
7387 /* Extract the physical address & find it in the DMAP */
7388 pa = pmap_extract(pmap, va);
7390 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
7392 /* Move to the next page */
7395 /* Set the length for the next iteration */
7396 len = imin(PAGE_SIZE, sz);
7402 pmap_stage2_fault(pmap_t pmap, uint64_t esr, uint64_t far)
7405 pt_entry_t *ptep, pte;
7408 PMAP_ASSERT_STAGE2(pmap);
7411 /* Data and insn aborts use same encoding for FSC field. */
7412 dfsc = esr & ISS_DATA_DFSC_MASK;
7414 case ISS_DATA_DFSC_TF_L0:
7415 case ISS_DATA_DFSC_TF_L1:
7416 case ISS_DATA_DFSC_TF_L2:
7417 case ISS_DATA_DFSC_TF_L3:
7419 pdep = pmap_pde(pmap, far, &lvl);
7420 if (pdep == NULL || lvl != (dfsc - ISS_DATA_DFSC_TF_L1)) {
7427 ptep = pmap_l0_to_l1(pdep, far);
7430 ptep = pmap_l1_to_l2(pdep, far);
7433 ptep = pmap_l2_to_l3(pdep, far);
7436 panic("%s: Invalid pde level %d", __func__,lvl);
7440 case ISS_DATA_DFSC_AFF_L1:
7441 case ISS_DATA_DFSC_AFF_L2:
7442 case ISS_DATA_DFSC_AFF_L3:
7444 ptep = pmap_pte(pmap, far, &lvl);
7446 if (ptep != NULL && (pte = pmap_load(ptep)) != 0) {
7448 pmap_invalidate_vpipt_icache();
7451 * If accessing an executable page invalidate
7452 * the I-cache so it will be valid when we
7453 * continue execution in the guest. The D-cache
7454 * is assumed to already be clean to the Point
7457 if ((pte & ATTR_S2_XN_MASK) !=
7458 ATTR_S2_XN(ATTR_S2_XN_NONE)) {
7459 invalidate_icache();
7462 pmap_set_bits(ptep, ATTR_AF | ATTR_DESCR_VALID);
7473 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
7475 pt_entry_t pte, *ptep;
7482 ec = ESR_ELx_EXCEPTION(esr);
7484 case EXCP_INSN_ABORT_L:
7485 case EXCP_INSN_ABORT:
7486 case EXCP_DATA_ABORT_L:
7487 case EXCP_DATA_ABORT:
7493 if (pmap->pm_stage == PM_STAGE2)
7494 return (pmap_stage2_fault(pmap, esr, far));
7496 /* Data and insn aborts use same encoding for FSC field. */
7497 switch (esr & ISS_DATA_DFSC_MASK) {
7498 case ISS_DATA_DFSC_AFF_L1:
7499 case ISS_DATA_DFSC_AFF_L2:
7500 case ISS_DATA_DFSC_AFF_L3:
7502 ptep = pmap_pte(pmap, far, &lvl);
7504 pmap_set_bits(ptep, ATTR_AF);
7507 * XXXMJ as an optimization we could mark the entry
7508 * dirty if this is a write fault.
7513 case ISS_DATA_DFSC_PF_L1:
7514 case ISS_DATA_DFSC_PF_L2:
7515 case ISS_DATA_DFSC_PF_L3:
7516 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
7517 (esr & ISS_DATA_WnR) == 0)
7520 ptep = pmap_pte(pmap, far, &lvl);
7522 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
7523 if ((pte & ATTR_S1_AP_RW_BIT) ==
7524 ATTR_S1_AP(ATTR_S1_AP_RO)) {
7525 pmap_clear_bits(ptep, ATTR_S1_AP_RW_BIT);
7526 pmap_s1_invalidate_page(pmap, far, true);
7532 case ISS_DATA_DFSC_TF_L0:
7533 case ISS_DATA_DFSC_TF_L1:
7534 case ISS_DATA_DFSC_TF_L2:
7535 case ISS_DATA_DFSC_TF_L3:
7537 * Retry the translation. A break-before-make sequence can
7538 * produce a transient fault.
7540 if (pmap == kernel_pmap) {
7542 * The translation fault may have occurred within a
7543 * critical section. Therefore, we must check the
7544 * address without acquiring the kernel pmap's lock.
7546 if (pmap_klookup(far, NULL))
7550 /* Ask the MMU to check the address. */
7551 intr = intr_disable();
7552 par = arm64_address_translate_s1e0r(far);
7557 * If the translation was successful, then we can
7558 * return success to the trap handler.
7560 if (PAR_SUCCESS(par))
7570 * Increase the starting virtual address of the given mapping if a
7571 * different alignment might result in more superpage mappings.
7574 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
7575 vm_offset_t *addr, vm_size_t size)
7577 vm_offset_t superpage_offset;
7581 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
7582 offset += ptoa(object->pg_color);
7583 superpage_offset = offset & L2_OFFSET;
7584 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
7585 (*addr & L2_OFFSET) == superpage_offset)
7587 if ((*addr & L2_OFFSET) < superpage_offset)
7588 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
7590 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
7594 * Get the kernel virtual address of a set of physical pages. If there are
7595 * physical addresses not covered by the DMAP perform a transient mapping
7596 * that will be removed when calling pmap_unmap_io_transient.
7598 * \param page The pages the caller wishes to obtain the virtual
7599 * address on the kernel memory map.
7600 * \param vaddr On return contains the kernel virtual memory address
7601 * of the pages passed in the page parameter.
7602 * \param count Number of pages passed in.
7603 * \param can_fault TRUE if the thread using the mapped pages can take
7604 * page faults, FALSE otherwise.
7606 * \returns TRUE if the caller must call pmap_unmap_io_transient when
7607 * finished or FALSE otherwise.
7611 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7612 boolean_t can_fault)
7615 boolean_t needs_mapping;
7616 int error __diagused, i;
7619 * Allocate any KVA space that we need, this is done in a separate
7620 * loop to prevent calling vmem_alloc while pinned.
7622 needs_mapping = FALSE;
7623 for (i = 0; i < count; i++) {
7624 paddr = VM_PAGE_TO_PHYS(page[i]);
7625 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
7626 error = vmem_alloc(kernel_arena, PAGE_SIZE,
7627 M_BESTFIT | M_WAITOK, &vaddr[i]);
7628 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
7629 needs_mapping = TRUE;
7631 vaddr[i] = PHYS_TO_DMAP(paddr);
7635 /* Exit early if everything is covered by the DMAP */
7641 for (i = 0; i < count; i++) {
7642 paddr = VM_PAGE_TO_PHYS(page[i]);
7643 if (!PHYS_IN_DMAP(paddr)) {
7645 "pmap_map_io_transient: TODO: Map out of DMAP data");
7649 return (needs_mapping);
7653 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7654 boolean_t can_fault)
7661 for (i = 0; i < count; i++) {
7662 paddr = VM_PAGE_TO_PHYS(page[i]);
7663 if (!PHYS_IN_DMAP(paddr)) {
7664 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
7670 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
7673 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);
7677 static vm_paddr_t pmap_san_early_kernstart;
7678 static pd_entry_t *pmap_san_early_l2;
7680 void __nosanitizeaddress
7681 pmap_san_bootstrap(struct arm64_bootparams *abp)
7684 pmap_san_early_kernstart = KERNBASE - abp->kern_delta;
7685 kasan_init_early(abp->kern_stack, KSTACK_PAGES * PAGE_SIZE);
7688 #define SAN_BOOTSTRAP_L2_SIZE (1 * L2_SIZE)
7689 #define SAN_BOOTSTRAP_SIZE (2 * PAGE_SIZE)
7690 static vm_offset_t __nosanitizeaddress
7691 pmap_san_enter_bootstrap_alloc_l2(void)
7693 static uint8_t bootstrap_data[SAN_BOOTSTRAP_L2_SIZE] __aligned(L2_SIZE);
7694 static size_t offset = 0;
7697 if (offset + L2_SIZE > sizeof(bootstrap_data)) {
7698 panic("%s: out of memory for the bootstrap shadow map L2 entries",
7702 addr = (uintptr_t)&bootstrap_data[offset];
7708 * SAN L1 + L2 pages, maybe L3 entries later?
7710 static vm_offset_t __nosanitizeaddress
7711 pmap_san_enter_bootstrap_alloc_pages(int npages)
7713 static uint8_t bootstrap_data[SAN_BOOTSTRAP_SIZE] __aligned(PAGE_SIZE);
7714 static size_t offset = 0;
7717 if (offset + (npages * PAGE_SIZE) > sizeof(bootstrap_data)) {
7718 panic("%s: out of memory for the bootstrap shadow map",
7722 addr = (uintptr_t)&bootstrap_data[offset];
7723 offset += (npages * PAGE_SIZE);
7727 static void __nosanitizeaddress
7728 pmap_san_enter_bootstrap(void)
7730 vm_offset_t freemempos;
7733 freemempos = pmap_san_enter_bootstrap_alloc_pages(2);
7734 bs_state.freemempos = freemempos;
7735 bs_state.va = KASAN_MIN_ADDRESS;
7736 pmap_bootstrap_l1_table(&bs_state);
7737 pmap_san_early_l2 = bs_state.l2;
7741 pmap_san_enter_alloc_l3(void)
7745 m = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED |
7748 panic("%s: no memory to grow shadow map", __func__);
7753 pmap_san_enter_alloc_l2(void)
7755 return (vm_page_alloc_noobj_contig(VM_ALLOC_WIRED | VM_ALLOC_ZERO,
7756 Ln_ENTRIES, 0, ~0ul, L2_SIZE, 0, VM_MEMATTR_DEFAULT));
7759 void __nosanitizeaddress
7760 pmap_san_enter(vm_offset_t va)
7762 pd_entry_t *l1, *l2;
7766 if (virtual_avail == 0) {
7771 /* Temporary shadow map prior to pmap_bootstrap(). */
7772 first = pmap_san_early_l2 == NULL;
7774 pmap_san_enter_bootstrap();
7776 l2 = pmap_san_early_l2;
7777 slot = pmap_l2_index(va);
7779 if ((pmap_load(&l2[slot]) & ATTR_DESCR_VALID) == 0) {
7781 block = pmap_san_enter_bootstrap_alloc_l2();
7782 pmap_store(&l2[slot], pmap_early_vtophys(block) |
7783 PMAP_SAN_PTE_BITS | L2_BLOCK);
7790 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
7791 l1 = pmap_l1(kernel_pmap, va);
7793 if ((pmap_load(l1) & ATTR_DESCR_VALID) == 0) {
7794 m = pmap_san_enter_alloc_l3();
7795 pmap_store(l1, (VM_PAGE_TO_PHYS(m) & ~Ln_TABLE_MASK) |
7798 l2 = pmap_l1_to_l2(l1, va);
7799 if ((pmap_load(l2) & ATTR_DESCR_VALID) == 0) {
7800 m = pmap_san_enter_alloc_l2();
7802 pmap_store(l2, VM_PAGE_TO_PHYS(m) | PMAP_SAN_PTE_BITS |
7805 m = pmap_san_enter_alloc_l3();
7806 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
7810 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK)
7812 l3 = pmap_l2_to_l3(l2, va);
7813 if ((pmap_load(l3) & ATTR_DESCR_VALID) != 0)
7815 m = pmap_san_enter_alloc_l3();
7816 pmap_store(l3, VM_PAGE_TO_PHYS(m) | PMAP_SAN_PTE_BITS | L3_PAGE);
7822 * Track a range of the kernel's virtual address space that is contiguous
7823 * in various mapping attributes.
7825 struct pmap_kernel_map_range {
7835 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
7841 if (eva <= range->sva)
7844 index = range->attrs & ATTR_S1_IDX_MASK;
7846 case ATTR_S1_IDX(VM_MEMATTR_DEVICE):
7849 case ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE):
7852 case ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK):
7855 case ATTR_S1_IDX(VM_MEMATTR_WRITE_THROUGH):
7860 "%s: unknown memory type %x for range 0x%016lx-0x%016lx\n",
7861 __func__, index, range->sva, eva);
7866 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %3s %d %d %d %d\n",
7868 (range->attrs & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP_RW ? 'w' : '-',
7869 (range->attrs & ATTR_S1_PXN) != 0 ? '-' : 'x',
7870 (range->attrs & ATTR_S1_UXN) != 0 ? '-' : 'X',
7871 (range->attrs & ATTR_S1_AP(ATTR_S1_AP_USER)) != 0 ? 'u' : 's',
7872 mode, range->l1blocks, range->l2blocks, range->l3contig,
7875 /* Reset to sentinel value. */
7876 range->sva = 0xfffffffffffffffful;
7880 * Determine whether the attributes specified by a page table entry match those
7881 * being tracked by the current range.
7884 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
7887 return (range->attrs == attrs);
7891 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
7895 memset(range, 0, sizeof(*range));
7897 range->attrs = attrs;
7900 /* Get the block/page attributes that correspond to the table attributes */
7902 sysctl_kmaps_table_attrs(pd_entry_t table)
7907 if ((table & TATTR_UXN_TABLE) != 0)
7908 attrs |= ATTR_S1_UXN;
7909 if ((table & TATTR_PXN_TABLE) != 0)
7910 attrs |= ATTR_S1_PXN;
7911 if ((table & TATTR_AP_TABLE_RO) != 0)
7912 attrs |= ATTR_S1_AP(ATTR_S1_AP_RO);
7917 /* Read the block/page attributes we care about */
7919 sysctl_kmaps_block_attrs(pt_entry_t block)
7921 return (block & (ATTR_S1_AP_MASK | ATTR_S1_XN | ATTR_S1_IDX_MASK));
7925 * Given a leaf PTE, derive the mapping's attributes. If they do not match
7926 * those of the current run, dump the address range and its attributes, and
7930 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
7931 vm_offset_t va, pd_entry_t l0e, pd_entry_t l1e, pd_entry_t l2e,
7936 attrs = sysctl_kmaps_table_attrs(l0e);
7938 if ((l1e & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
7939 attrs |= sysctl_kmaps_block_attrs(l1e);
7942 attrs |= sysctl_kmaps_table_attrs(l1e);
7944 if ((l2e & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
7945 attrs |= sysctl_kmaps_block_attrs(l2e);
7948 attrs |= sysctl_kmaps_table_attrs(l2e);
7949 attrs |= sysctl_kmaps_block_attrs(l3e);
7952 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
7953 sysctl_kmaps_dump(sb, range, va);
7954 sysctl_kmaps_reinit(range, va, attrs);
7959 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
7961 struct pmap_kernel_map_range range;
7962 struct sbuf sbuf, *sb;
7963 pd_entry_t l0e, *l1, l1e, *l2, l2e;
7964 pt_entry_t *l3, l3e;
7967 int error, i, j, k, l;
7969 error = sysctl_wire_old_buffer(req, 0);
7973 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
7975 /* Sentinel value. */
7976 range.sva = 0xfffffffffffffffful;
7979 * Iterate over the kernel page tables without holding the kernel pmap
7980 * lock. Kernel page table pages are never freed, so at worst we will
7981 * observe inconsistencies in the output.
7983 for (sva = 0xffff000000000000ul, i = pmap_l0_index(sva); i < Ln_ENTRIES;
7985 if (i == pmap_l0_index(DMAP_MIN_ADDRESS))
7986 sbuf_printf(sb, "\nDirect map:\n");
7987 else if (i == pmap_l0_index(VM_MIN_KERNEL_ADDRESS))
7988 sbuf_printf(sb, "\nKernel map:\n");
7990 else if (i == pmap_l0_index(KASAN_MIN_ADDRESS))
7991 sbuf_printf(sb, "\nKASAN shadow map:\n");
7994 l0e = kernel_pmap->pm_l0[i];
7995 if ((l0e & ATTR_DESCR_VALID) == 0) {
7996 sysctl_kmaps_dump(sb, &range, sva);
8000 pa = l0e & ~ATTR_MASK;
8001 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa);
8003 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
8005 if ((l1e & ATTR_DESCR_VALID) == 0) {
8006 sysctl_kmaps_dump(sb, &range, sva);
8010 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
8011 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
8012 sysctl_kmaps_check(sb, &range, sva, l0e, l1e,
8018 pa = l1e & ~ATTR_MASK;
8019 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa);
8021 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
8023 if ((l2e & ATTR_DESCR_VALID) == 0) {
8024 sysctl_kmaps_dump(sb, &range, sva);
8028 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK) {
8029 sysctl_kmaps_check(sb, &range, sva,
8035 pa = l2e & ~ATTR_MASK;
8036 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
8038 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
8039 l++, sva += L3_SIZE) {
8041 if ((l3e & ATTR_DESCR_VALID) == 0) {
8042 sysctl_kmaps_dump(sb, &range,
8046 sysctl_kmaps_check(sb, &range, sva,
8047 l0e, l1e, l2e, l3e);
8048 if ((l3e & ATTR_CONTIGUOUS) != 0)
8049 range.l3contig += l % 16 == 0 ?
8058 error = sbuf_finish(sb);
8062 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
8063 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP,
8064 NULL, 0, sysctl_kmaps, "A",
8065 "Dump kernel address layout");