2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
108 #include <sys/param.h>
110 #include <sys/systm.h>
111 #include <sys/kernel.h>
113 #include <sys/lock.h>
114 #include <sys/malloc.h>
115 #include <sys/mman.h>
116 #include <sys/msgbuf.h>
117 #include <sys/mutex.h>
118 #include <sys/proc.h>
119 #include <sys/rwlock.h>
121 #include <sys/vmem.h>
122 #include <sys/vmmeter.h>
123 #include <sys/sched.h>
124 #include <sys/sysctl.h>
125 #include <sys/_unrhdr.h>
129 #include <vm/vm_param.h>
130 #include <vm/vm_kern.h>
131 #include <vm/vm_page.h>
132 #include <vm/vm_map.h>
133 #include <vm/vm_object.h>
134 #include <vm/vm_extern.h>
135 #include <vm/vm_pageout.h>
136 #include <vm/vm_pager.h>
137 #include <vm/vm_radix.h>
138 #include <vm/vm_reserv.h>
141 #include <machine/machdep.h>
142 #include <machine/md_var.h>
143 #include <machine/pcb.h>
145 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
146 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
147 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
148 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
150 #define NUL0E L0_ENTRIES
151 #define NUL1E (NUL0E * NL1PG)
152 #define NUL2E (NUL1E * NL2PG)
154 #if !defined(DIAGNOSTIC)
155 #ifdef __GNUC_GNU_INLINE__
156 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
158 #define PMAP_INLINE extern inline
165 * These are configured by the mair_el1 register. This is set up in locore.S
167 #define DEVICE_MEMORY 0
168 #define UNCACHED_MEMORY 1
169 #define CACHED_MEMORY 2
173 #define PV_STAT(x) do { x ; } while (0)
175 #define PV_STAT(x) do { } while (0)
178 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
180 #define NPV_LIST_LOCKS MAXCPU
182 #define PHYS_TO_PV_LIST_LOCK(pa) \
183 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
185 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
186 struct rwlock **_lockp = (lockp); \
187 struct rwlock *_new_lock; \
189 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
190 if (_new_lock != *_lockp) { \
191 if (*_lockp != NULL) \
192 rw_wunlock(*_lockp); \
193 *_lockp = _new_lock; \
198 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
199 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
201 #define RELEASE_PV_LIST_LOCK(lockp) do { \
202 struct rwlock **_lockp = (lockp); \
204 if (*_lockp != NULL) { \
205 rw_wunlock(*_lockp); \
210 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
211 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
213 struct pmap kernel_pmap_store;
215 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
216 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
217 vm_offset_t kernel_vm_end = 0;
219 struct msgbuf *msgbufp = NULL;
221 static struct rwlock_padalign pvh_global_lock;
223 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
225 /* This code assumes all L1 DMAP entries will be used */
226 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
227 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
229 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
230 extern pt_entry_t pagetable_dmap[];
233 * Data for the pv entry allocation mechanism
235 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
236 static struct mtx pv_chunks_mutex;
237 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
239 static void free_pv_chunk(struct pv_chunk *pc);
240 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
241 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
242 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
243 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
244 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
246 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
247 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
248 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
249 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
250 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
251 vm_page_t m, struct rwlock **lockp);
253 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
254 struct rwlock **lockp);
256 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
257 struct spglist *free);
258 static int pmap_unuse_l3(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
261 * These load the old table data and store the new value.
262 * They need to be atomic as the System MMU may write to the table at
263 * the same time as the CPU.
265 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
266 #define pmap_set(table, mask) atomic_set_64(table, mask)
267 #define pmap_load_clear(table) atomic_swap_64(table, 0)
268 #define pmap_load(table) (*table)
270 /********************/
271 /* Inline functions */
272 /********************/
275 pagecopy(void *s, void *d)
278 memcpy(d, s, PAGE_SIZE);
281 #define pmap_l0_index(va) (((va) >> L0_SHIFT) & L0_ADDR_MASK)
282 #define pmap_l1_index(va) (((va) >> L1_SHIFT) & Ln_ADDR_MASK)
283 #define pmap_l2_index(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK)
284 #define pmap_l3_index(va) (((va) >> L3_SHIFT) & Ln_ADDR_MASK)
286 static __inline pd_entry_t *
287 pmap_l0(pmap_t pmap, vm_offset_t va)
290 return (&pmap->pm_l0[pmap_l0_index(va)]);
293 static __inline pd_entry_t *
294 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
298 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
299 return (&l1[pmap_l1_index(va)]);
302 static __inline pd_entry_t *
303 pmap_l1(pmap_t pmap, vm_offset_t va)
307 l0 = pmap_l0(pmap, va);
308 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
311 return (pmap_l0_to_l1(l0, va));
314 static __inline pd_entry_t *
315 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
319 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
320 return (&l2[pmap_l2_index(va)]);
323 static __inline pd_entry_t *
324 pmap_l2(pmap_t pmap, vm_offset_t va)
328 l1 = pmap_l1(pmap, va);
329 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
332 return (pmap_l1_to_l2(l1, va));
335 static __inline pt_entry_t *
336 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
340 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
341 return (&l3[pmap_l3_index(va)]);
345 * Returns the lowest valid pde for a given virtual address.
346 * The next level may or may not point to a valid page or block.
348 static __inline pd_entry_t *
349 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
351 pd_entry_t *l0, *l1, *l2, desc;
353 l0 = pmap_l0(pmap, va);
354 desc = pmap_load(l0) & ATTR_DESCR_MASK;
355 if (desc != L0_TABLE) {
360 l1 = pmap_l0_to_l1(l0, va);
361 desc = pmap_load(l1) & ATTR_DESCR_MASK;
362 if (desc != L1_TABLE) {
367 l2 = pmap_l1_to_l2(l1, va);
368 desc = pmap_load(l2) & ATTR_DESCR_MASK;
369 if (desc != L2_TABLE) {
379 * Returns the lowest valid pte block or table entry for a given virtual
380 * address. If there are no valid entries return NULL and set the level to
381 * the first invalid level.
383 static __inline pt_entry_t *
384 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
386 pd_entry_t *l1, *l2, desc;
389 l1 = pmap_l1(pmap, va);
394 desc = pmap_load(l1) & ATTR_DESCR_MASK;
395 if (desc == L1_BLOCK) {
400 if (desc != L1_TABLE) {
405 l2 = pmap_l1_to_l2(l1, va);
406 desc = pmap_load(l2) & ATTR_DESCR_MASK;
407 if (desc == L2_BLOCK) {
412 if (desc != L2_TABLE) {
418 l3 = pmap_l2_to_l3(l2, va);
419 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
426 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
427 pd_entry_t **l2, pt_entry_t **l3)
429 pd_entry_t *l0p, *l1p, *l2p;
431 if (pmap->pm_l0 == NULL)
434 l0p = pmap_l0(pmap, va);
437 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
440 l1p = pmap_l0_to_l1(l0p, va);
443 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
449 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
452 l2p = pmap_l1_to_l2(l1p, va);
455 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
460 *l3 = pmap_l2_to_l3(l2p, va);
466 pmap_is_current(pmap_t pmap)
469 return ((pmap == pmap_kernel()) ||
470 (pmap == curthread->td_proc->p_vmspace->vm_map.pmap));
474 pmap_l3_valid(pt_entry_t l3)
477 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
481 pmap_l3_valid_cacheable(pt_entry_t l3)
484 return (((l3 & ATTR_DESCR_MASK) == L3_PAGE) &&
485 ((l3 & ATTR_IDX_MASK) == ATTR_IDX(CACHED_MEMORY)));
488 #define PTE_SYNC(pte) cpu_dcache_wb_range((vm_offset_t)pte, sizeof(*pte))
491 * Checks if the page is dirty. We currently lack proper tracking of this on
492 * arm64 so for now assume is a page mapped as rw was accessed it is.
495 pmap_page_dirty(pt_entry_t pte)
498 return ((pte & (ATTR_AF | ATTR_AP_RW_BIT)) ==
499 (ATTR_AF | ATTR_AP(ATTR_AP_RW)));
503 pmap_resident_count_inc(pmap_t pmap, int count)
506 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
507 pmap->pm_stats.resident_count += count;
511 pmap_resident_count_dec(pmap_t pmap, int count)
514 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
515 KASSERT(pmap->pm_stats.resident_count >= count,
516 ("pmap %p resident count underflow %ld %d", pmap,
517 pmap->pm_stats.resident_count, count));
518 pmap->pm_stats.resident_count -= count;
522 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
528 l1 = (pd_entry_t *)l1pt;
529 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
531 /* Check locore has used a table L1 map */
532 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
533 ("Invalid bootstrap L1 table"));
534 /* Find the address of the L2 table */
535 l2 = (pt_entry_t *)init_pt_va;
536 *l2_slot = pmap_l2_index(va);
542 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
544 u_int l1_slot, l2_slot;
547 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
549 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
553 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t kernstart)
559 pa = dmap_phys_base = kernstart & ~L1_OFFSET;
560 va = DMAP_MIN_ADDRESS;
561 for (; va < DMAP_MAX_ADDRESS;
562 pa += L1_SIZE, va += L1_SIZE, l1_slot++) {
563 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
565 pmap_load_store(&pagetable_dmap[l1_slot],
566 (pa & ~L1_OFFSET) | ATTR_DEFAULT |
567 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
570 cpu_dcache_wb_range((vm_offset_t)pagetable_dmap,
571 PAGE_SIZE * DMAP_TABLES);
576 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
583 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
585 l1 = (pd_entry_t *)l1pt;
586 l1_slot = pmap_l1_index(va);
589 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
590 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
592 pa = pmap_early_vtophys(l1pt, l2pt);
593 pmap_load_store(&l1[l1_slot],
594 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
598 /* Clean the L2 page table */
599 memset((void *)l2_start, 0, l2pt - l2_start);
600 cpu_dcache_wb_range(l2_start, l2pt - l2_start);
602 /* Flush the l1 table to ram */
603 cpu_dcache_wb_range((vm_offset_t)l1, PAGE_SIZE);
609 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
611 vm_offset_t l2pt, l3pt;
616 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
618 l2 = pmap_l2(kernel_pmap, va);
619 l2 = (pd_entry_t *)((uintptr_t)l2 & ~(PAGE_SIZE - 1));
620 l2pt = (vm_offset_t)l2;
621 l2_slot = pmap_l2_index(va);
624 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
625 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
627 pa = pmap_early_vtophys(l1pt, l3pt);
628 pmap_load_store(&l2[l2_slot],
629 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
633 /* Clean the L2 page table */
634 memset((void *)l3_start, 0, l3pt - l3_start);
635 cpu_dcache_wb_range(l3_start, l3pt - l3_start);
637 cpu_dcache_wb_range((vm_offset_t)l2, PAGE_SIZE);
643 * Bootstrap the system enough to run with virtual memory.
646 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
649 u_int l1_slot, l2_slot, avail_slot, map_slot, used_map_slot;
652 vm_offset_t va, freemempos;
653 vm_offset_t dpcpu, msgbufpv;
654 vm_paddr_t pa, min_pa;
657 kern_delta = KERNBASE - kernstart;
660 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
661 printf("%lx\n", l1pt);
662 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
664 /* Set this early so we can use the pagetable walking functions */
665 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
666 PMAP_LOCK_INIT(kernel_pmap);
669 * Initialize the global pv list lock.
671 rw_init(&pvh_global_lock, "pmap pv global");
673 /* Assume the address we were loaded to is a valid physical address */
674 min_pa = KERNBASE - kern_delta;
677 * Find the minimum physical address. physmap is sorted,
678 * but may contain empty ranges.
680 for (i = 0; i < (physmap_idx * 2); i += 2) {
681 if (physmap[i] == physmap[i + 1])
683 if (physmap[i] <= min_pa)
688 /* Create a direct map region early so we can use it for pa -> va */
689 pmap_bootstrap_dmap(l1pt, min_pa);
692 pa = KERNBASE - kern_delta;
695 * Start to initialise phys_avail by copying from physmap
696 * up to the physical address KERNBASE points at.
698 map_slot = avail_slot = 0;
699 for (; map_slot < (physmap_idx * 2) &&
700 avail_slot < (PHYS_AVAIL_SIZE - 2); map_slot += 2) {
701 if (physmap[map_slot] == physmap[map_slot + 1])
704 if (physmap[map_slot] <= pa &&
705 physmap[map_slot + 1] > pa)
708 phys_avail[avail_slot] = physmap[map_slot];
709 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
710 physmem += (phys_avail[avail_slot + 1] -
711 phys_avail[avail_slot]) >> PAGE_SHIFT;
715 /* Add the memory before the kernel */
716 if (physmap[avail_slot] < pa && avail_slot < (PHYS_AVAIL_SIZE - 2)) {
717 phys_avail[avail_slot] = physmap[map_slot];
718 phys_avail[avail_slot + 1] = pa;
719 physmem += (phys_avail[avail_slot + 1] -
720 phys_avail[avail_slot]) >> PAGE_SHIFT;
723 used_map_slot = map_slot;
726 * Read the page table to find out what is already mapped.
727 * This assumes we have mapped a block of memory from KERNBASE
728 * using a single L1 entry.
730 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
732 /* Sanity check the index, KERNBASE should be the first VA */
733 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
735 /* Find how many pages we have mapped */
736 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
737 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
740 /* Check locore used L2 blocks */
741 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
742 ("Invalid bootstrap L2 table"));
743 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
744 ("Incorrect PA in L2 table"));
750 va = roundup2(va, L1_SIZE);
752 freemempos = KERNBASE + kernlen;
753 freemempos = roundup2(freemempos, PAGE_SIZE);
754 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
755 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
756 /* And the l3 tables for the early devmap */
757 freemempos = pmap_bootstrap_l3(l1pt,
758 VM_MAX_KERNEL_ADDRESS - L2_SIZE, freemempos);
762 #define alloc_pages(var, np) \
763 (var) = freemempos; \
764 freemempos += (np * PAGE_SIZE); \
765 memset((char *)(var), 0, ((np) * PAGE_SIZE));
767 /* Allocate dynamic per-cpu area. */
768 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
769 dpcpu_init((void *)dpcpu, 0);
771 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
772 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
773 msgbufp = (void *)msgbufpv;
775 virtual_avail = roundup2(freemempos, L1_SIZE);
776 virtual_end = VM_MAX_KERNEL_ADDRESS - L2_SIZE;
777 kernel_vm_end = virtual_avail;
779 pa = pmap_early_vtophys(l1pt, freemempos);
781 /* Finish initialising physmap */
782 map_slot = used_map_slot;
783 for (; avail_slot < (PHYS_AVAIL_SIZE - 2) &&
784 map_slot < (physmap_idx * 2); map_slot += 2) {
785 if (physmap[map_slot] == physmap[map_slot + 1])
788 /* Have we used the current range? */
789 if (physmap[map_slot + 1] <= pa)
792 /* Do we need to split the entry? */
793 if (physmap[map_slot] < pa) {
794 phys_avail[avail_slot] = pa;
795 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
797 phys_avail[avail_slot] = physmap[map_slot];
798 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
800 physmem += (phys_avail[avail_slot + 1] -
801 phys_avail[avail_slot]) >> PAGE_SHIFT;
805 phys_avail[avail_slot] = 0;
806 phys_avail[avail_slot + 1] = 0;
809 * Maxmem isn't the "maximum memory", it's one larger than the
810 * highest page of the physical address space. It should be
811 * called something like "Maxphyspage".
813 Maxmem = atop(phys_avail[avail_slot - 1]);
819 * Initialize a vm_page's machine-dependent fields.
822 pmap_page_init(vm_page_t m)
825 TAILQ_INIT(&m->md.pv_list);
826 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
830 * Initialize the pmap module.
831 * Called by vm_init, to initialize any structures that the pmap
832 * system needs to map virtual memory.
840 * Initialize the pv chunk list mutex.
842 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
845 * Initialize the pool of pv list locks.
847 for (i = 0; i < NPV_LIST_LOCKS; i++)
848 rw_init(&pv_list_locks[i], "pmap pv list");
852 * Normal, non-SMP, invalidation functions.
853 * We inline these within pmap.c for speed.
856 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
862 "tlbi vaae1is, %0 \n"
865 : : "r"(va >> PAGE_SHIFT));
870 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
875 __asm __volatile("dsb sy");
876 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
878 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
887 pmap_invalidate_all(pmap_t pmap)
900 * Routine: pmap_extract
902 * Extract the physical page address associated
903 * with the given map/virtual_address pair.
906 pmap_extract(pmap_t pmap, vm_offset_t va)
908 pt_entry_t *pte, tpte;
915 * Find the block or page map for this virtual address. pmap_pte
916 * will return either a valid block/page entry, or NULL.
918 pte = pmap_pte(pmap, va, &lvl);
920 tpte = pmap_load(pte);
921 pa = tpte & ~ATTR_MASK;
924 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
925 ("pmap_extract: Invalid L1 pte found: %lx",
926 tpte & ATTR_DESCR_MASK));
927 pa |= (va & L1_OFFSET);
930 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
931 ("pmap_extract: Invalid L2 pte found: %lx",
932 tpte & ATTR_DESCR_MASK));
933 pa |= (va & L2_OFFSET);
936 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
937 ("pmap_extract: Invalid L3 pte found: %lx",
938 tpte & ATTR_DESCR_MASK));
939 pa |= (va & L3_OFFSET);
948 * Routine: pmap_extract_and_hold
950 * Atomically extract and hold the physical page
951 * with the given pmap and virtual address pair
952 * if that mapping permits the given protection.
955 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
957 pt_entry_t *pte, tpte;
966 pte = pmap_pte(pmap, va, &lvl);
968 tpte = pmap_load(pte);
970 KASSERT(lvl > 0 && lvl <= 3,
971 ("pmap_extract_and_hold: Invalid level %d", lvl));
972 CTASSERT(L1_BLOCK == L2_BLOCK);
973 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
974 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
975 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
976 tpte & ATTR_DESCR_MASK));
977 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
978 ((prot & VM_PROT_WRITE) == 0)) {
979 if (vm_page_pa_tryrelock(pmap, tpte & ~ATTR_MASK, &pa))
981 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
991 pmap_kextract(vm_offset_t va)
993 pt_entry_t *pte, tpte;
997 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
998 pa = DMAP_TO_PHYS(va);
1001 pte = pmap_pte(kernel_pmap, va, &lvl);
1003 tpte = pmap_load(pte);
1004 pa = tpte & ~ATTR_MASK;
1007 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1008 ("pmap_kextract: Invalid L1 pte found: %lx",
1009 tpte & ATTR_DESCR_MASK));
1010 pa |= (va & L1_OFFSET);
1013 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1014 ("pmap_kextract: Invalid L2 pte found: %lx",
1015 tpte & ATTR_DESCR_MASK));
1016 pa |= (va & L2_OFFSET);
1019 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1020 ("pmap_kextract: Invalid L3 pte found: %lx",
1021 tpte & ATTR_DESCR_MASK));
1022 pa |= (va & L3_OFFSET);
1030 /***************************************************
1031 * Low level mapping routines.....
1032 ***************************************************/
1035 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1042 KASSERT((pa & L3_OFFSET) == 0,
1043 ("pmap_kenter_device: Invalid physical address"));
1044 KASSERT((sva & L3_OFFSET) == 0,
1045 ("pmap_kenter_device: Invalid virtual address"));
1046 KASSERT((size & PAGE_MASK) == 0,
1047 ("pmap_kenter_device: Mapping is not page-sized"));
1051 pde = pmap_pde(kernel_pmap, va, &lvl);
1052 KASSERT(pde != NULL,
1053 ("pmap_kenter_device: Invalid page entry, va: 0x%lx", va));
1055 ("pmap_kenter_device: Invalid level %d", lvl));
1057 pte = pmap_l2_to_l3(pde, va);
1058 pmap_load_store(pte, (pa & ~L3_OFFSET) | ATTR_DEFAULT |
1059 ATTR_IDX(DEVICE_MEMORY) | L3_PAGE);
1066 pmap_invalidate_range(kernel_pmap, sva, va);
1070 * Remove a page from the kernel pagetables.
1073 pmap_kremove(vm_offset_t va)
1078 pte = pmap_pte(kernel_pmap, va, &lvl);
1079 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1080 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1082 if (pmap_l3_valid_cacheable(pmap_load(pte)))
1083 cpu_dcache_wb_range(va, L3_SIZE);
1084 pmap_load_clear(pte);
1086 pmap_invalidate_page(kernel_pmap, va);
1090 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1096 KASSERT((sva & L3_OFFSET) == 0,
1097 ("pmap_kremove_device: Invalid virtual address"));
1098 KASSERT((size & PAGE_MASK) == 0,
1099 ("pmap_kremove_device: Mapping is not page-sized"));
1103 pte = pmap_pte(kernel_pmap, va, &lvl);
1104 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1106 ("Invalid device pagetable level: %d != 3", lvl));
1107 pmap_load_clear(pte);
1113 pmap_invalidate_range(kernel_pmap, sva, va);
1117 * Used to map a range of physical addresses into kernel
1118 * virtual address space.
1120 * The value passed in '*virt' is a suggested virtual address for
1121 * the mapping. Architectures which can support a direct-mapped
1122 * physical to virtual region can return the appropriate address
1123 * within that region, leaving '*virt' unchanged. Other
1124 * architectures should map the pages starting at '*virt' and
1125 * update '*virt' with the first usable address after the mapped
1129 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1131 return PHYS_TO_DMAP(start);
1136 * Add a list of wired pages to the kva
1137 * this routine is only used for temporary
1138 * kernel mappings that do not need to have
1139 * page modification or references recorded.
1140 * Note that old mappings are simply written
1141 * over. The page *must* be wired.
1142 * Note: SMP coherent. Uses a ranged shootdown IPI.
1145 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1148 pt_entry_t *pte, pa;
1154 for (i = 0; i < count; i++) {
1155 pde = pmap_pde(kernel_pmap, va, &lvl);
1156 KASSERT(pde != NULL,
1157 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1159 ("pmap_qenter: Invalid level %d", lvl));
1162 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1163 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1164 pte = pmap_l2_to_l3(pde, va);
1165 pmap_load_store(pte, pa);
1170 pmap_invalidate_range(kernel_pmap, sva, va);
1174 * This routine tears out page mappings from the
1175 * kernel -- it is meant only for temporary mappings.
1178 pmap_qremove(vm_offset_t sva, int count)
1184 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1187 while (count-- > 0) {
1188 pte = pmap_pte(kernel_pmap, va, &lvl);
1190 ("Invalid device pagetable level: %d != 3", lvl));
1192 if (pmap_l3_valid_cacheable(pmap_load(pte)))
1193 cpu_dcache_wb_range(va, L3_SIZE);
1194 pmap_load_clear(pte);
1200 pmap_invalidate_range(kernel_pmap, sva, va);
1203 /***************************************************
1204 * Page table page management routines.....
1205 ***************************************************/
1206 static __inline void
1207 pmap_free_zero_pages(struct spglist *free)
1211 while ((m = SLIST_FIRST(free)) != NULL) {
1212 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1213 /* Preserve the page's PG_ZERO setting. */
1214 vm_page_free_toq(m);
1219 * Schedule the specified unused page table page to be freed. Specifically,
1220 * add the page to the specified list of pages that will be released to the
1221 * physical memory manager after the TLB has been updated.
1223 static __inline void
1224 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1225 boolean_t set_PG_ZERO)
1229 m->flags |= PG_ZERO;
1231 m->flags &= ~PG_ZERO;
1232 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1236 * Decrements a page table page's wire count, which is used to record the
1237 * number of valid page table entries within the page. If the wire count
1238 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1239 * page table page was unmapped and FALSE otherwise.
1241 static inline boolean_t
1242 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1246 if (m->wire_count == 0) {
1247 _pmap_unwire_l3(pmap, va, m, free);
1254 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1257 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1259 * unmap the page table page
1261 if (m->pindex >= (NUL2E + NUL1E)) {
1265 l0 = pmap_l0(pmap, va);
1266 pmap_load_clear(l0);
1268 } else if (m->pindex >= NUL2E) {
1272 l1 = pmap_l1(pmap, va);
1273 pmap_load_clear(l1);
1279 l2 = pmap_l2(pmap, va);
1280 pmap_load_clear(l2);
1283 pmap_resident_count_dec(pmap, 1);
1284 if (m->pindex < NUL2E) {
1285 /* We just released an l3, unhold the matching l2 */
1286 pd_entry_t *l1, tl1;
1289 l1 = pmap_l1(pmap, va);
1290 tl1 = pmap_load(l1);
1291 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1292 pmap_unwire_l3(pmap, va, l2pg, free);
1293 } else if (m->pindex < (NUL2E + NUL1E)) {
1294 /* We just released an l2, unhold the matching l1 */
1295 pd_entry_t *l0, tl0;
1298 l0 = pmap_l0(pmap, va);
1299 tl0 = pmap_load(l0);
1300 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1301 pmap_unwire_l3(pmap, va, l1pg, free);
1303 pmap_invalidate_page(pmap, va);
1306 * This is a release store so that the ordinary store unmapping
1307 * the page table page is globally performed before TLB shoot-
1310 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
1313 * Put page on a list so that it is released after
1314 * *ALL* TLB shootdown is done
1316 pmap_add_delayed_free_list(m, free, TRUE);
1320 * After removing an l3 entry, this routine is used to
1321 * conditionally free the page, and manage the hold/wire counts.
1324 pmap_unuse_l3(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1325 struct spglist *free)
1329 if (va >= VM_MAXUSER_ADDRESS)
1331 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1332 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1333 return (pmap_unwire_l3(pmap, va, mpte, free));
1337 pmap_pinit0(pmap_t pmap)
1340 PMAP_LOCK_INIT(pmap);
1341 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1342 pmap->pm_l0 = kernel_pmap->pm_l0;
1346 pmap_pinit(pmap_t pmap)
1352 * allocate the l0 page
1354 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1355 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1358 l0phys = VM_PAGE_TO_PHYS(l0pt);
1359 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1361 if ((l0pt->flags & PG_ZERO) == 0)
1362 pagezero(pmap->pm_l0);
1364 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1370 * This routine is called if the desired page table page does not exist.
1372 * If page table page allocation fails, this routine may sleep before
1373 * returning NULL. It sleeps only if a lock pointer was given.
1375 * Note: If a page allocation fails at page table level two or three,
1376 * one or two pages may be held during the wait, only to be released
1377 * afterwards. This conservative approach is easily argued to avoid
1381 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1383 vm_page_t m, l1pg, l2pg;
1385 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1388 * Allocate a page table page.
1390 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1391 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1392 if (lockp != NULL) {
1393 RELEASE_PV_LIST_LOCK(lockp);
1395 rw_runlock(&pvh_global_lock);
1397 rw_rlock(&pvh_global_lock);
1402 * Indicate the need to retry. While waiting, the page table
1403 * page may have been allocated.
1407 if ((m->flags & PG_ZERO) == 0)
1411 * Map the pagetable page into the process address space, if
1412 * it isn't already there.
1415 if (ptepindex >= (NUL2E + NUL1E)) {
1417 vm_pindex_t l0index;
1419 l0index = ptepindex - (NUL2E + NUL1E);
1420 l0 = &pmap->pm_l0[l0index];
1421 pmap_load_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1423 } else if (ptepindex >= NUL2E) {
1424 vm_pindex_t l0index, l1index;
1425 pd_entry_t *l0, *l1;
1428 l1index = ptepindex - NUL2E;
1429 l0index = l1index >> L0_ENTRIES_SHIFT;
1431 l0 = &pmap->pm_l0[l0index];
1432 tl0 = pmap_load(l0);
1434 /* recurse for allocating page dir */
1435 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1438 /* XXX: release mem barrier? */
1439 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1440 vm_page_free_zero(m);
1444 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1448 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1449 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1450 pmap_load_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1453 vm_pindex_t l0index, l1index;
1454 pd_entry_t *l0, *l1, *l2;
1455 pd_entry_t tl0, tl1;
1457 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1458 l0index = l1index >> L0_ENTRIES_SHIFT;
1460 l0 = &pmap->pm_l0[l0index];
1461 tl0 = pmap_load(l0);
1463 /* recurse for allocating page dir */
1464 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1467 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1468 vm_page_free_zero(m);
1471 tl0 = pmap_load(l0);
1472 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1473 l1 = &l1[l1index & Ln_ADDR_MASK];
1475 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1476 l1 = &l1[l1index & Ln_ADDR_MASK];
1477 tl1 = pmap_load(l1);
1479 /* recurse for allocating page dir */
1480 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1483 /* XXX: release mem barrier? */
1484 atomic_subtract_int(
1485 &vm_cnt.v_wire_count, 1);
1486 vm_page_free_zero(m);
1490 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1495 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1496 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1497 pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1501 pmap_resident_count_inc(pmap, 1);
1507 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1509 vm_pindex_t ptepindex;
1510 pd_entry_t *pde, tpde;
1515 * Calculate pagetable page index
1517 ptepindex = pmap_l2_pindex(va);
1520 * Get the page directory entry
1522 pde = pmap_pde(pmap, va, &lvl);
1525 * If the page table page is mapped, we just increment the hold count,
1526 * and activate it. If we get a level 2 pde it will point to a level 3
1530 tpde = pmap_load(pde);
1532 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1539 * Here if the pte page isn't mapped, or if it has been deallocated.
1541 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1542 if (m == NULL && lockp != NULL)
1549 /***************************************************
1550 * Pmap allocation/deallocation routines.
1551 ***************************************************/
1554 * Release any resources held by the given physical map.
1555 * Called when a pmap initialized by pmap_pinit is being released.
1556 * Should only be called if the map contains no valid mappings.
1559 pmap_release(pmap_t pmap)
1563 KASSERT(pmap->pm_stats.resident_count == 0,
1564 ("pmap_release: pmap resident count %ld != 0",
1565 pmap->pm_stats.resident_count));
1567 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1570 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1571 vm_page_free_zero(m);
1576 kvm_size(SYSCTL_HANDLER_ARGS)
1578 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1580 return sysctl_handle_long(oidp, &ksize, 0, req);
1582 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1583 0, 0, kvm_size, "LU", "Size of KVM");
1586 kvm_free(SYSCTL_HANDLER_ARGS)
1588 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1590 return sysctl_handle_long(oidp, &kfree, 0, req);
1592 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1593 0, 0, kvm_free, "LU", "Amount of KVM free");
1597 * grow the number of kernel page table entries, if needed
1600 pmap_growkernel(vm_offset_t addr)
1604 pd_entry_t *l0, *l1, *l2;
1606 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1608 addr = roundup2(addr, L2_SIZE);
1609 if (addr - 1 >= kernel_map->max_offset)
1610 addr = kernel_map->max_offset;
1611 while (kernel_vm_end < addr) {
1612 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1613 KASSERT(pmap_load(l0) != 0,
1614 ("pmap_growkernel: No level 0 kernel entry"));
1616 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1617 if (pmap_load(l1) == 0) {
1618 /* We need a new PDP entry */
1619 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1620 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1621 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1623 panic("pmap_growkernel: no memory to grow kernel");
1624 if ((nkpg->flags & PG_ZERO) == 0)
1625 pmap_zero_page(nkpg);
1626 paddr = VM_PAGE_TO_PHYS(nkpg);
1627 pmap_load_store(l1, paddr | L1_TABLE);
1629 continue; /* try again */
1631 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1632 if ((pmap_load(l2) & ATTR_AF) != 0) {
1633 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1634 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1635 kernel_vm_end = kernel_map->max_offset;
1641 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1642 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1645 panic("pmap_growkernel: no memory to grow kernel");
1646 if ((nkpg->flags & PG_ZERO) == 0)
1647 pmap_zero_page(nkpg);
1648 paddr = VM_PAGE_TO_PHYS(nkpg);
1649 pmap_load_store(l2, paddr | L2_TABLE);
1651 pmap_invalidate_page(kernel_pmap, kernel_vm_end);
1653 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1654 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1655 kernel_vm_end = kernel_map->max_offset;
1662 /***************************************************
1663 * page management routines.
1664 ***************************************************/
1666 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1667 CTASSERT(_NPCM == 3);
1668 CTASSERT(_NPCPV == 168);
1670 static __inline struct pv_chunk *
1671 pv_to_chunk(pv_entry_t pv)
1674 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1677 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1679 #define PC_FREE0 0xfffffffffffffffful
1680 #define PC_FREE1 0xfffffffffffffffful
1681 #define PC_FREE2 0x000000fffffffffful
1683 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1687 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1689 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1690 "Current number of pv entry chunks");
1691 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1692 "Current number of pv entry chunks allocated");
1693 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1694 "Current number of pv entry chunks frees");
1695 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1696 "Number of times tried to get a chunk page but failed.");
1698 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1699 static int pv_entry_spare;
1701 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1702 "Current number of pv entry frees");
1703 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1704 "Current number of pv entry allocs");
1705 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1706 "Current number of pv entries");
1707 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1708 "Current number of spare pv entries");
1713 * We are in a serious low memory condition. Resort to
1714 * drastic measures to free some pages so we can allocate
1715 * another pv entry chunk.
1717 * Returns NULL if PV entries were reclaimed from the specified pmap.
1719 * We do not, however, unmap 2mpages because subsequent accesses will
1720 * allocate per-page pv entries until repromotion occurs, thereby
1721 * exacerbating the shortage of free pv entries.
1724 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1727 panic("ARM64TODO: reclaim_pv_chunk");
1731 * free the pv_entry back to the free list
1734 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1736 struct pv_chunk *pc;
1737 int idx, field, bit;
1739 rw_assert(&pvh_global_lock, RA_LOCKED);
1740 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1741 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
1742 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
1743 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
1744 pc = pv_to_chunk(pv);
1745 idx = pv - &pc->pc_pventry[0];
1748 pc->pc_map[field] |= 1ul << bit;
1749 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
1750 pc->pc_map[2] != PC_FREE2) {
1751 /* 98% of the time, pc is already at the head of the list. */
1752 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
1753 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1754 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1758 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1763 free_pv_chunk(struct pv_chunk *pc)
1767 mtx_lock(&pv_chunks_mutex);
1768 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1769 mtx_unlock(&pv_chunks_mutex);
1770 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1771 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1772 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1773 /* entire chunk is free, return it */
1774 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1775 dump_drop_page(m->phys_addr);
1776 vm_page_unwire(m, PQ_NONE);
1781 * Returns a new PV entry, allocating a new PV chunk from the system when
1782 * needed. If this PV chunk allocation fails and a PV list lock pointer was
1783 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
1786 * The given PV list lock may be released.
1789 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
1793 struct pv_chunk *pc;
1796 rw_assert(&pvh_global_lock, RA_LOCKED);
1797 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1798 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
1800 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1802 for (field = 0; field < _NPCM; field++) {
1803 if (pc->pc_map[field]) {
1804 bit = ffsl(pc->pc_map[field]) - 1;
1808 if (field < _NPCM) {
1809 pv = &pc->pc_pventry[field * 64 + bit];
1810 pc->pc_map[field] &= ~(1ul << bit);
1811 /* If this was the last item, move it to tail */
1812 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
1813 pc->pc_map[2] == 0) {
1814 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1815 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
1818 PV_STAT(atomic_add_long(&pv_entry_count, 1));
1819 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
1823 /* No free items, allocate another chunk */
1824 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1827 if (lockp == NULL) {
1828 PV_STAT(pc_chunk_tryfail++);
1831 m = reclaim_pv_chunk(pmap, lockp);
1835 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
1836 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
1837 dump_add_page(m->phys_addr);
1838 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
1840 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
1841 pc->pc_map[1] = PC_FREE1;
1842 pc->pc_map[2] = PC_FREE2;
1843 mtx_lock(&pv_chunks_mutex);
1844 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
1845 mtx_unlock(&pv_chunks_mutex);
1846 pv = &pc->pc_pventry[0];
1847 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1848 PV_STAT(atomic_add_long(&pv_entry_count, 1));
1849 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
1854 * First find and then remove the pv entry for the specified pmap and virtual
1855 * address from the specified pv list. Returns the pv entry if found and NULL
1856 * otherwise. This operation can be performed on pv lists for either 4KB or
1857 * 2MB page mappings.
1859 static __inline pv_entry_t
1860 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1864 rw_assert(&pvh_global_lock, RA_LOCKED);
1865 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
1866 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
1867 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
1876 * First find and then destroy the pv entry for the specified pmap and virtual
1877 * address. This operation can be performed on pv lists for either 4KB or 2MB
1881 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1885 pv = pmap_pvh_remove(pvh, pmap, va);
1886 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
1887 free_pv_entry(pmap, pv);
1891 * Conditionally create the PV entry for a 4KB page mapping if the required
1892 * memory can be allocated without resorting to reclamation.
1895 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
1896 struct rwlock **lockp)
1900 rw_assert(&pvh_global_lock, RA_LOCKED);
1901 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1902 /* Pass NULL instead of the lock pointer to disable reclamation. */
1903 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
1905 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1906 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
1914 * pmap_remove_l3: do the things to unmap a page in a process
1917 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
1918 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
1923 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1924 if (pmap_is_current(pmap) && pmap_l3_valid_cacheable(pmap_load(l3)))
1925 cpu_dcache_wb_range(va, L3_SIZE);
1926 old_l3 = pmap_load_clear(l3);
1928 pmap_invalidate_page(pmap, va);
1929 if (old_l3 & ATTR_SW_WIRED)
1930 pmap->pm_stats.wired_count -= 1;
1931 pmap_resident_count_dec(pmap, 1);
1932 if (old_l3 & ATTR_SW_MANAGED) {
1933 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
1934 if (pmap_page_dirty(old_l3))
1936 if (old_l3 & ATTR_AF)
1937 vm_page_aflag_set(m, PGA_REFERENCED);
1938 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1939 pmap_pvh_free(&m->md, pmap, va);
1941 return (pmap_unuse_l3(pmap, va, l2e, free));
1945 * Remove the given range of addresses from the specified map.
1947 * It is assumed that the start and end are properly
1948 * rounded to the page size.
1951 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1953 struct rwlock *lock;
1954 vm_offset_t va, va_next;
1955 pd_entry_t *l0, *l1, *l2;
1956 pt_entry_t l3_paddr, *l3;
1957 struct spglist free;
1961 * Perform an unsynchronized read. This is, however, safe.
1963 if (pmap->pm_stats.resident_count == 0)
1969 rw_rlock(&pvh_global_lock);
1973 for (; sva < eva; sva = va_next) {
1975 if (pmap->pm_stats.resident_count == 0)
1978 l0 = pmap_l0(pmap, sva);
1979 if (pmap_load(l0) == 0) {
1980 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
1986 l1 = pmap_l0_to_l1(l0, sva);
1987 if (pmap_load(l1) == 0) {
1988 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
1995 * Calculate index for next page table.
1997 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2001 l2 = pmap_l1_to_l2(l1, sva);
2005 l3_paddr = pmap_load(l2);
2008 * Weed out invalid mappings.
2010 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2014 * Limit our scan to either the end of the va represented
2015 * by the current page table page, or to the end of the
2016 * range being removed.
2022 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2025 panic("l3 == NULL");
2026 if (pmap_load(l3) == 0) {
2027 if (va != va_next) {
2028 pmap_invalidate_range(pmap, va, sva);
2035 if (pmap_remove_l3(pmap, l3, sva, l3_paddr, &free,
2042 pmap_invalidate_range(pmap, va, sva);
2047 pmap_invalidate_all(pmap);
2048 rw_runlock(&pvh_global_lock);
2050 pmap_free_zero_pages(&free);
2054 * Routine: pmap_remove_all
2056 * Removes this physical page from
2057 * all physical maps in which it resides.
2058 * Reflects back modify bits to the pager.
2061 * Original versions of this routine were very
2062 * inefficient because they iteratively called
2063 * pmap_remove (slow...)
2067 pmap_remove_all(vm_page_t m)
2071 pd_entry_t *pde, tpde;
2072 pt_entry_t *pte, tpte;
2073 struct spglist free;
2076 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2077 ("pmap_remove_all: page %p is not managed", m));
2079 rw_wlock(&pvh_global_lock);
2080 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2083 pmap_resident_count_dec(pmap, 1);
2085 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2086 KASSERT(pde != NULL,
2087 ("pmap_remove_all: no page directory entry found"));
2089 ("pmap_remove_all: invalid pde level %d", lvl));
2090 tpde = pmap_load(pde);
2092 pte = pmap_l2_to_l3(pde, pv->pv_va);
2093 tpte = pmap_load(pte);
2094 if (pmap_is_current(pmap) &&
2095 pmap_l3_valid_cacheable(tpte))
2096 cpu_dcache_wb_range(pv->pv_va, L3_SIZE);
2097 pmap_load_clear(pte);
2099 pmap_invalidate_page(pmap, pv->pv_va);
2100 if (tpte & ATTR_SW_WIRED)
2101 pmap->pm_stats.wired_count--;
2102 if ((tpte & ATTR_AF) != 0)
2103 vm_page_aflag_set(m, PGA_REFERENCED);
2106 * Update the vm_page_t clean and reference bits.
2108 if (pmap_page_dirty(tpte))
2110 pmap_unuse_l3(pmap, pv->pv_va, tpde, &free);
2111 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2113 free_pv_entry(pmap, pv);
2116 vm_page_aflag_clear(m, PGA_WRITEABLE);
2117 rw_wunlock(&pvh_global_lock);
2118 pmap_free_zero_pages(&free);
2122 * Set the physical protection on the
2123 * specified range of this map as requested.
2126 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2128 vm_offset_t va, va_next;
2129 pd_entry_t *l0, *l1, *l2;
2130 pt_entry_t *l3p, l3;
2132 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2133 pmap_remove(pmap, sva, eva);
2137 if ((prot & VM_PROT_WRITE) == VM_PROT_WRITE)
2141 for (; sva < eva; sva = va_next) {
2143 l0 = pmap_l0(pmap, sva);
2144 if (pmap_load(l0) == 0) {
2145 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2151 l1 = pmap_l0_to_l1(l0, sva);
2152 if (pmap_load(l1) == 0) {
2153 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2159 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2163 l2 = pmap_l1_to_l2(l1, sva);
2164 if (l2 == NULL || (pmap_load(l2) & ATTR_DESCR_MASK) != L2_TABLE)
2171 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2173 l3 = pmap_load(l3p);
2174 if (pmap_l3_valid(l3)) {
2175 pmap_set(l3p, ATTR_AP(ATTR_AP_RO));
2177 /* XXX: Use pmap_invalidate_range */
2178 pmap_invalidate_page(pmap, va);
2184 /* TODO: Only invalidate entries we are touching */
2185 pmap_invalidate_all(pmap);
2189 * Insert the given physical page (p) at
2190 * the specified virtual address (v) in the
2191 * target physical map with the protection requested.
2193 * If specified, the page will be wired down, meaning
2194 * that the related pte can not be reclaimed.
2196 * NB: This is the only routine which MAY NOT lazy-evaluate
2197 * or lose information. That is, this routine must actually
2198 * insert this page into the given map NOW.
2201 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2202 u_int flags, int8_t psind __unused)
2204 struct rwlock *lock;
2206 pt_entry_t new_l3, orig_l3;
2209 vm_paddr_t opa, pa, l1_pa, l2_pa, l3_pa;
2210 vm_page_t mpte, om, l1_m, l2_m, l3_m;
2214 va = trunc_page(va);
2215 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2216 VM_OBJECT_ASSERT_LOCKED(m->object);
2217 pa = VM_PAGE_TO_PHYS(m);
2218 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
2220 if ((prot & VM_PROT_WRITE) == 0)
2221 new_l3 |= ATTR_AP(ATTR_AP_RO);
2222 if ((flags & PMAP_ENTER_WIRED) != 0)
2223 new_l3 |= ATTR_SW_WIRED;
2224 if ((va >> 63) == 0)
2225 new_l3 |= ATTR_AP(ATTR_AP_USER);
2227 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
2232 rw_rlock(&pvh_global_lock);
2235 if (va < VM_MAXUSER_ADDRESS) {
2236 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
2237 mpte = pmap_alloc_l3(pmap, va, nosleep ? NULL : &lock);
2238 if (mpte == NULL && nosleep) {
2239 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
2242 rw_runlock(&pvh_global_lock);
2244 return (KERN_RESOURCE_SHORTAGE);
2246 pde = pmap_pde(pmap, va, &lvl);
2247 KASSERT(pde != NULL,
2248 ("pmap_enter: Invalid page entry, va: 0x%lx", va));
2250 ("pmap_enter: Invalid level %d", lvl));
2252 l3 = pmap_l2_to_l3(pde, va);
2254 pde = pmap_pde(pmap, va, &lvl);
2256 * If we get a level 2 pde it must point to a level 3 entry
2257 * otherwise we will need to create the intermediate tables
2263 /* Get the l0 pde to update */
2264 pde = pmap_l0(pmap, va);
2265 KASSERT(pde != NULL, ("..."));
2267 l1_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2268 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2271 panic("pmap_enter: l1 pte_m == NULL");
2272 if ((l1_m->flags & PG_ZERO) == 0)
2273 pmap_zero_page(l1_m);
2275 l1_pa = VM_PAGE_TO_PHYS(l1_m);
2276 pmap_load_store(pde, l1_pa | L0_TABLE);
2280 /* Get the l1 pde to update */
2281 pde = pmap_l1_to_l2(pde, va);
2282 KASSERT(pde != NULL, ("..."));
2284 l2_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2285 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2288 panic("pmap_enter: l2 pte_m == NULL");
2289 if ((l2_m->flags & PG_ZERO) == 0)
2290 pmap_zero_page(l2_m);
2292 l2_pa = VM_PAGE_TO_PHYS(l2_m);
2293 pmap_load_store(pde, l2_pa | L1_TABLE);
2297 /* Get the l2 pde to update */
2298 pde = pmap_l1_to_l2(pde, va);
2300 l3_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2301 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2304 panic("pmap_enter: l3 pte_m == NULL");
2305 if ((l3_m->flags & PG_ZERO) == 0)
2306 pmap_zero_page(l3_m);
2308 l3_pa = VM_PAGE_TO_PHYS(l3_m);
2309 pmap_load_store(pde, l3_pa | L2_TABLE);
2314 l3 = pmap_l2_to_l3(pde, va);
2315 pmap_invalidate_page(pmap, va);
2319 orig_l3 = pmap_load(l3);
2320 opa = orig_l3 & ~ATTR_MASK;
2323 * Is the specified virtual address already mapped?
2325 if (pmap_l3_valid(orig_l3)) {
2327 * Wiring change, just update stats. We don't worry about
2328 * wiring PT pages as they remain resident as long as there
2329 * are valid mappings in them. Hence, if a user page is wired,
2330 * the PT page will be also.
2332 if ((flags & PMAP_ENTER_WIRED) != 0 &&
2333 (orig_l3 & ATTR_SW_WIRED) == 0)
2334 pmap->pm_stats.wired_count++;
2335 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
2336 (orig_l3 & ATTR_SW_WIRED) != 0)
2337 pmap->pm_stats.wired_count--;
2340 * Remove the extra PT page reference.
2344 KASSERT(mpte->wire_count > 0,
2345 ("pmap_enter: missing reference to page table page,"
2350 * Has the physical page changed?
2354 * No, might be a protection or wiring change.
2356 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
2357 new_l3 |= ATTR_SW_MANAGED;
2358 if ((new_l3 & ATTR_AP(ATTR_AP_RW)) ==
2359 ATTR_AP(ATTR_AP_RW)) {
2360 vm_page_aflag_set(m, PGA_WRITEABLE);
2366 /* Flush the cache, there might be uncommitted data in it */
2367 if (pmap_is_current(pmap) && pmap_l3_valid_cacheable(orig_l3))
2368 cpu_dcache_wb_range(va, L3_SIZE);
2371 * Increment the counters.
2373 if ((new_l3 & ATTR_SW_WIRED) != 0)
2374 pmap->pm_stats.wired_count++;
2375 pmap_resident_count_inc(pmap, 1);
2378 * Enter on the PV list if part of our managed memory.
2380 if ((m->oflags & VPO_UNMANAGED) == 0) {
2381 new_l3 |= ATTR_SW_MANAGED;
2382 pv = get_pv_entry(pmap, &lock);
2384 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
2385 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2387 if ((new_l3 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
2388 vm_page_aflag_set(m, PGA_WRITEABLE);
2392 * Update the L3 entry.
2396 orig_l3 = pmap_load_store(l3, new_l3);
2398 opa = orig_l3 & ~ATTR_MASK;
2401 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
2402 om = PHYS_TO_VM_PAGE(opa);
2403 if (pmap_page_dirty(orig_l3))
2405 if ((orig_l3 & ATTR_AF) != 0)
2406 vm_page_aflag_set(om, PGA_REFERENCED);
2407 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
2408 pmap_pvh_free(&om->md, pmap, va);
2410 } else if (pmap_page_dirty(orig_l3)) {
2411 if ((orig_l3 & ATTR_SW_MANAGED) != 0)
2415 pmap_load_store(l3, new_l3);
2418 pmap_invalidate_page(pmap, va);
2419 if ((pmap != pmap_kernel()) && (pmap == &curproc->p_vmspace->vm_pmap))
2420 cpu_icache_sync_range(va, PAGE_SIZE);
2424 rw_runlock(&pvh_global_lock);
2426 return (KERN_SUCCESS);
2430 * Maps a sequence of resident pages belonging to the same object.
2431 * The sequence begins with the given page m_start. This page is
2432 * mapped at the given virtual address start. Each subsequent page is
2433 * mapped at a virtual address that is offset from start by the same
2434 * amount as the page is offset from m_start within the object. The
2435 * last page in the sequence is the page with the largest offset from
2436 * m_start that can be mapped at a virtual address less than the given
2437 * virtual address end. Not every virtual page between start and end
2438 * is mapped; only those for which a resident page exists with the
2439 * corresponding offset from m_start are mapped.
2442 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
2443 vm_page_t m_start, vm_prot_t prot)
2445 struct rwlock *lock;
2448 vm_pindex_t diff, psize;
2450 VM_OBJECT_ASSERT_LOCKED(m_start->object);
2452 psize = atop(end - start);
2456 rw_rlock(&pvh_global_lock);
2458 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2459 va = start + ptoa(diff);
2460 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte, &lock);
2461 m = TAILQ_NEXT(m, listq);
2465 rw_runlock(&pvh_global_lock);
2470 * this code makes some *MAJOR* assumptions:
2471 * 1. Current pmap & pmap exists.
2474 * 4. No page table pages.
2475 * but is *MUCH* faster than pmap_enter...
2479 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
2481 struct rwlock *lock;
2484 rw_rlock(&pvh_global_lock);
2486 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
2489 rw_runlock(&pvh_global_lock);
2494 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
2495 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
2497 struct spglist free;
2503 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
2504 (m->oflags & VPO_UNMANAGED) != 0,
2505 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
2506 rw_assert(&pvh_global_lock, RA_LOCKED);
2507 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2509 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
2511 * In the case that a page table page is not
2512 * resident, we are creating it here.
2514 if (va < VM_MAXUSER_ADDRESS) {
2515 vm_pindex_t l2pindex;
2518 * Calculate pagetable page index
2520 l2pindex = pmap_l2_pindex(va);
2521 if (mpte && (mpte->pindex == l2pindex)) {
2527 pde = pmap_pde(pmap, va, &lvl);
2530 * If the page table page is mapped, we just increment
2531 * the hold count, and activate it. Otherwise, we
2532 * attempt to allocate a page table page. If this
2533 * attempt fails, we don't retry. Instead, we give up.
2535 if (lvl == 2 && pmap_load(pde) != 0) {
2537 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
2541 * Pass NULL instead of the PV list lock
2542 * pointer, because we don't intend to sleep.
2544 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
2549 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
2550 l3 = &l3[pmap_l3_index(va)];
2553 pde = pmap_pde(kernel_pmap, va, &lvl);
2554 KASSERT(pde != NULL,
2555 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
2558 ("pmap_enter_quick_locked: Invalid level %d", lvl));
2559 l3 = pmap_l2_to_l3(pde, va);
2562 if (pmap_load(l3) != 0) {
2571 * Enter on the PV list if part of our managed memory.
2573 if ((m->oflags & VPO_UNMANAGED) == 0 &&
2574 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
2577 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
2578 pmap_invalidate_page(pmap, va);
2579 pmap_free_zero_pages(&free);
2587 * Increment counters
2589 pmap_resident_count_inc(pmap, 1);
2591 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
2592 ATTR_AP(ATTR_AP_RW) | L3_PAGE;
2595 * Now validate mapping with RO protection
2597 if ((m->oflags & VPO_UNMANAGED) == 0)
2598 pa |= ATTR_SW_MANAGED;
2599 pmap_load_store(l3, pa);
2601 pmap_invalidate_page(pmap, va);
2606 * This code maps large physical mmap regions into the
2607 * processor address space. Note that some shortcuts
2608 * are taken, but the code works.
2611 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
2612 vm_pindex_t pindex, vm_size_t size)
2615 VM_OBJECT_ASSERT_WLOCKED(object);
2616 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2617 ("pmap_object_init_pt: non-device object"));
2621 * Clear the wired attribute from the mappings for the specified range of
2622 * addresses in the given pmap. Every valid mapping within that range
2623 * must have the wired attribute set. In contrast, invalid mappings
2624 * cannot have the wired attribute set, so they are ignored.
2626 * The wired attribute of the page table entry is not a hardware feature,
2627 * so there is no need to invalidate any TLB entries.
2630 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2632 vm_offset_t va_next;
2633 pd_entry_t *l0, *l1, *l2;
2635 boolean_t pv_lists_locked;
2637 pv_lists_locked = FALSE;
2639 for (; sva < eva; sva = va_next) {
2640 l0 = pmap_l0(pmap, sva);
2641 if (pmap_load(l0) == 0) {
2642 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2648 l1 = pmap_l0_to_l1(l0, sva);
2649 if (pmap_load(l1) == 0) {
2650 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2656 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2660 l2 = pmap_l1_to_l2(l1, sva);
2661 if (pmap_load(l2) == 0)
2666 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2668 if (pmap_load(l3) == 0)
2670 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
2671 panic("pmap_unwire: l3 %#jx is missing "
2672 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
2675 * PG_W must be cleared atomically. Although the pmap
2676 * lock synchronizes access to PG_W, another processor
2677 * could be setting PG_M and/or PG_A concurrently.
2679 atomic_clear_long(l3, ATTR_SW_WIRED);
2680 pmap->pm_stats.wired_count--;
2683 if (pv_lists_locked)
2684 rw_runlock(&pvh_global_lock);
2689 * Copy the range specified by src_addr/len
2690 * from the source map to the range dst_addr/len
2691 * in the destination map.
2693 * This routine is only advisory and need not do anything.
2697 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
2698 vm_offset_t src_addr)
2703 * pmap_zero_page zeros the specified hardware page by mapping
2704 * the page into KVM and using bzero to clear its contents.
2707 pmap_zero_page(vm_page_t m)
2709 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
2711 pagezero((void *)va);
2715 * pmap_zero_page_area zeros the specified hardware page by mapping
2716 * the page into KVM and using bzero to clear its contents.
2718 * off and size may not cover an area beyond a single hardware page.
2721 pmap_zero_page_area(vm_page_t m, int off, int size)
2723 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
2725 if (off == 0 && size == PAGE_SIZE)
2726 pagezero((void *)va);
2728 bzero((char *)va + off, size);
2732 * pmap_zero_page_idle zeros the specified hardware page by mapping
2733 * the page into KVM and using bzero to clear its contents. This
2734 * is intended to be called from the vm_pagezero process only and
2738 pmap_zero_page_idle(vm_page_t m)
2740 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
2742 pagezero((void *)va);
2746 * pmap_copy_page copies the specified (machine independent)
2747 * page by mapping the page into virtual memory and using
2748 * bcopy to copy the page, one machine dependent page at a
2752 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
2754 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
2755 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
2757 pagecopy((void *)src, (void *)dst);
2760 int unmapped_buf_allowed = 1;
2763 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
2764 vm_offset_t b_offset, int xfersize)
2768 vm_paddr_t p_a, p_b;
2769 vm_offset_t a_pg_offset, b_pg_offset;
2772 while (xfersize > 0) {
2773 a_pg_offset = a_offset & PAGE_MASK;
2774 m_a = ma[a_offset >> PAGE_SHIFT];
2775 p_a = m_a->phys_addr;
2776 b_pg_offset = b_offset & PAGE_MASK;
2777 m_b = mb[b_offset >> PAGE_SHIFT];
2778 p_b = m_b->phys_addr;
2779 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2780 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2781 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
2782 panic("!DMAP a %lx", p_a);
2784 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
2786 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
2787 panic("!DMAP b %lx", p_b);
2789 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
2791 bcopy(a_cp, b_cp, cnt);
2799 pmap_quick_enter_page(vm_page_t m)
2802 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
2806 pmap_quick_remove_page(vm_offset_t addr)
2811 * Returns true if the pmap's pv is one of the first
2812 * 16 pvs linked to from this page. This count may
2813 * be changed upwards or downwards in the future; it
2814 * is only necessary that true be returned for a small
2815 * subset of pmaps for proper page aging.
2818 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
2820 struct rwlock *lock;
2825 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2826 ("pmap_page_exists_quick: page %p is not managed", m));
2828 rw_rlock(&pvh_global_lock);
2829 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2831 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
2832 if (PV_PMAP(pv) == pmap) {
2841 rw_runlock(&pvh_global_lock);
2846 * pmap_page_wired_mappings:
2848 * Return the number of managed mappings to the given physical page
2852 pmap_page_wired_mappings(vm_page_t m)
2854 struct rwlock *lock;
2858 int count, lvl, md_gen;
2860 if ((m->oflags & VPO_UNMANAGED) != 0)
2862 rw_rlock(&pvh_global_lock);
2863 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2867 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
2869 if (!PMAP_TRYLOCK(pmap)) {
2870 md_gen = m->md.pv_gen;
2874 if (md_gen != m->md.pv_gen) {
2879 pte = pmap_pte(pmap, pv->pv_va, &lvl);
2880 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
2885 rw_runlock(&pvh_global_lock);
2890 * Destroy all managed, non-wired mappings in the given user-space
2891 * pmap. This pmap cannot be active on any processor besides the
2894 * This function cannot be applied to the kernel pmap. Moreover, it
2895 * is not intended for general use. It is only to be used during
2896 * process termination. Consequently, it can be implemented in ways
2897 * that make it faster than pmap_remove(). First, it can more quickly
2898 * destroy mappings by iterating over the pmap's collection of PV
2899 * entries, rather than searching the page table. Second, it doesn't
2900 * have to test and clear the page table entries atomically, because
2901 * no processor is currently accessing the user address space. In
2902 * particular, a page table entry's dirty bit won't change state once
2903 * this function starts.
2906 pmap_remove_pages(pmap_t pmap)
2909 pt_entry_t *pte, tpte;
2910 struct spglist free;
2913 struct pv_chunk *pc, *npc;
2914 struct rwlock *lock;
2916 uint64_t inuse, bitmask;
2917 int allfree, field, freed, idx, lvl;
2923 rw_rlock(&pvh_global_lock);
2925 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
2928 for (field = 0; field < _NPCM; field++) {
2929 inuse = ~pc->pc_map[field] & pc_freemask[field];
2930 while (inuse != 0) {
2931 bit = ffsl(inuse) - 1;
2932 bitmask = 1UL << bit;
2933 idx = field * 64 + bit;
2934 pv = &pc->pc_pventry[idx];
2937 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2938 KASSERT(pde != NULL,
2939 ("Attempting to remove an unmapped page"));
2941 ("Invalid page directory level: %d", lvl));
2943 pte = pmap_l2_to_l3(pde, pv->pv_va);
2944 KASSERT(pte != NULL,
2945 ("Attempting to remove an unmapped page"));
2947 tpte = pmap_load(pte);
2950 * We cannot remove wired pages from a process' mapping at this time
2952 if (tpte & ATTR_SW_WIRED) {
2957 pa = tpte & ~ATTR_MASK;
2959 m = PHYS_TO_VM_PAGE(pa);
2960 KASSERT(m->phys_addr == pa,
2961 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
2962 m, (uintmax_t)m->phys_addr,
2965 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
2966 m < &vm_page_array[vm_page_array_size],
2967 ("pmap_remove_pages: bad pte %#jx",
2970 /* XXX: assumes tpte is level 3 */
2971 if (pmap_is_current(pmap) &&
2972 pmap_l3_valid_cacheable(tpte))
2973 cpu_dcache_wb_range(pv->pv_va, L3_SIZE);
2974 pmap_load_clear(pte);
2976 pmap_invalidate_page(pmap, pv->pv_va);
2979 * Update the vm_page_t clean/reference bits.
2981 if ((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
2984 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
2987 pc->pc_map[field] |= bitmask;
2989 pmap_resident_count_dec(pmap, 1);
2990 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2993 pmap_unuse_l3(pmap, pv->pv_va, pmap_load(pde),
2998 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2999 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3000 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3002 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3006 pmap_invalidate_all(pmap);
3009 rw_runlock(&pvh_global_lock);
3011 pmap_free_zero_pages(&free);
3015 * This is used to check if a page has been accessed or modified. As we
3016 * don't have a bit to see if it has been modified we have to assume it
3017 * has been if the page is read/write.
3020 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
3022 struct rwlock *lock;
3024 pt_entry_t *pte, mask, value;
3030 rw_rlock(&pvh_global_lock);
3031 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3034 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3036 if (!PMAP_TRYLOCK(pmap)) {
3037 md_gen = m->md.pv_gen;
3041 if (md_gen != m->md.pv_gen) {
3046 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3048 ("pmap_page_test_mappings: Invalid level %d", lvl));
3052 mask |= ATTR_AP_RW_BIT;
3053 value |= ATTR_AP(ATTR_AP_RW);
3056 mask |= ATTR_AF | ATTR_DESCR_MASK;
3057 value |= ATTR_AF | L3_PAGE;
3059 rv = (pmap_load(pte) & mask) == value;
3066 rw_runlock(&pvh_global_lock);
3073 * Return whether or not the specified physical page was modified
3074 * in any physical maps.
3077 pmap_is_modified(vm_page_t m)
3080 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3081 ("pmap_is_modified: page %p is not managed", m));
3084 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3085 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
3086 * is clear, no PTEs can have PG_M set.
3088 VM_OBJECT_ASSERT_WLOCKED(m->object);
3089 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3091 return (pmap_page_test_mappings(m, FALSE, TRUE));
3095 * pmap_is_prefaultable:
3097 * Return whether or not the specified virtual address is eligible
3101 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3109 pte = pmap_pte(pmap, addr, &lvl);
3110 if (pte != NULL && pmap_load(pte) != 0) {
3118 * pmap_is_referenced:
3120 * Return whether or not the specified physical page was referenced
3121 * in any physical maps.
3124 pmap_is_referenced(vm_page_t m)
3127 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3128 ("pmap_is_referenced: page %p is not managed", m));
3129 return (pmap_page_test_mappings(m, TRUE, FALSE));
3133 * Clear the write and modified bits in each of the given page's mappings.
3136 pmap_remove_write(vm_page_t m)
3139 struct rwlock *lock;
3141 pt_entry_t oldpte, *pte;
3144 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3145 ("pmap_remove_write: page %p is not managed", m));
3148 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3149 * set by another thread while the object is locked. Thus,
3150 * if PGA_WRITEABLE is clear, no page table entries need updating.
3152 VM_OBJECT_ASSERT_WLOCKED(m->object);
3153 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3155 rw_rlock(&pvh_global_lock);
3156 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3159 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3161 if (!PMAP_TRYLOCK(pmap)) {
3162 md_gen = m->md.pv_gen;
3166 if (md_gen != m->md.pv_gen) {
3172 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3174 oldpte = pmap_load(pte);
3175 if ((oldpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) {
3176 if (!atomic_cmpset_long(pte, oldpte,
3177 oldpte | ATTR_AP(ATTR_AP_RO)))
3179 if ((oldpte & ATTR_AF) != 0)
3181 pmap_invalidate_page(pmap, pv->pv_va);
3186 vm_page_aflag_clear(m, PGA_WRITEABLE);
3187 rw_runlock(&pvh_global_lock);
3190 static __inline boolean_t
3191 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
3197 #define PMAP_TS_REFERENCED_MAX 5
3200 * pmap_ts_referenced:
3202 * Return a count of reference bits for a page, clearing those bits.
3203 * It is not necessary for every reference bit to be cleared, but it
3204 * is necessary that 0 only be returned when there are truly no
3205 * reference bits set.
3207 * XXX: The exact number of bits to check and clear is a matter that
3208 * should be tested and standardized at some point in the future for
3209 * optimal aging of shared pages.
3212 pmap_ts_referenced(vm_page_t m)
3216 struct rwlock *lock;
3217 pd_entry_t *pde, tpde;
3218 pt_entry_t *pte, tpte;
3220 int cleared, md_gen, not_cleared, lvl;
3221 struct spglist free;
3223 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3224 ("pmap_ts_referenced: page %p is not managed", m));
3227 pa = VM_PAGE_TO_PHYS(m);
3228 lock = PHYS_TO_PV_LIST_LOCK(pa);
3229 rw_rlock(&pvh_global_lock);
3233 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
3240 if (!PMAP_TRYLOCK(pmap)) {
3241 md_gen = m->md.pv_gen;
3245 if (md_gen != m->md.pv_gen) {
3250 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3251 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
3253 ("pmap_ts_referenced: invalid pde level %d", lvl));
3254 tpde = pmap_load(pde);
3255 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
3256 ("pmap_ts_referenced: found an invalid l2 table"));
3257 pte = pmap_l2_to_l3(pde, pv->pv_va);
3258 tpte = pmap_load(pte);
3259 if ((tpte & ATTR_AF) != 0) {
3260 if (safe_to_clear_referenced(pmap, tpte)) {
3262 * TODO: We don't handle the access flag
3263 * at all. We need to be able to set it in
3264 * the exception handler.
3266 panic("ARM64TODO: safe_to_clear_referenced\n");
3267 } else if ((tpte & ATTR_SW_WIRED) == 0) {
3269 * Wired pages cannot be paged out so
3270 * doing accessed bit emulation for
3271 * them is wasted effort. We do the
3272 * hard work for unwired pages only.
3274 pmap_remove_l3(pmap, pte, pv->pv_va, tpde,
3276 pmap_invalidate_page(pmap, pv->pv_va);
3281 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
3282 ("inconsistent pv lock %p %p for page %p",
3283 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
3288 /* Rotate the PV list if it has more than one entry. */
3289 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
3290 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3291 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3294 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
3295 not_cleared < PMAP_TS_REFERENCED_MAX);
3298 rw_runlock(&pvh_global_lock);
3299 pmap_free_zero_pages(&free);
3300 return (cleared + not_cleared);
3304 * Apply the given advice to the specified range of addresses within the
3305 * given pmap. Depending on the advice, clear the referenced and/or
3306 * modified flags in each mapping and set the mapped page's dirty field.
3309 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
3314 * Clear the modify bits on the specified physical page.
3317 pmap_clear_modify(vm_page_t m)
3320 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3321 ("pmap_clear_modify: page %p is not managed", m));
3322 VM_OBJECT_ASSERT_WLOCKED(m->object);
3323 KASSERT(!vm_page_xbusied(m),
3324 ("pmap_clear_modify: page %p is exclusive busied", m));
3327 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
3328 * If the object containing the page is locked and the page is not
3329 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
3331 if ((m->aflags & PGA_WRITEABLE) == 0)
3334 /* ARM64TODO: We lack support for tracking if a page is modified */
3338 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
3341 return ((void *)PHYS_TO_DMAP(pa));
3345 pmap_unmapbios(vm_paddr_t pa, vm_size_t size)
3350 * Sets the memory attribute for the specified page.
3353 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
3356 m->md.pv_memattr = ma;
3359 * ARM64TODO: Implement the below (from the amd64 pmap)
3360 * If "m" is a normal page, update its direct mapping. This update
3361 * can be relied upon to perform any cache operations that are
3362 * required for data coherence.
3364 if ((m->flags & PG_FICTITIOUS) == 0 &&
3365 PHYS_IN_DMAP(VM_PAGE_TO_PHYS(m)))
3366 panic("ARM64TODO: pmap_page_set_memattr");
3370 * perform the pmap work for mincore
3373 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
3375 pd_entry_t *l1p, l1;
3376 pd_entry_t *l2p, l2;
3377 pt_entry_t *l3p, l3;
3388 l1p = pmap_l1(pmap, addr);
3389 if (l1p == NULL) /* No l1 */
3392 l1 = pmap_load(l1p);
3393 if ((l1 & ATTR_DESCR_MASK) == L1_INVAL)
3396 if ((l1 & ATTR_DESCR_MASK) == L1_BLOCK) {
3397 pa = (l1 & ~ATTR_MASK) | (addr & L1_OFFSET);
3398 managed = (l1 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
3399 val = MINCORE_SUPER | MINCORE_INCORE;
3400 if (pmap_page_dirty(l1))
3401 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3402 if ((l1 & ATTR_AF) == ATTR_AF)
3403 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3407 l2p = pmap_l1_to_l2(l1p, addr);
3408 if (l2p == NULL) /* No l2 */
3411 l2 = pmap_load(l2p);
3412 if ((l2 & ATTR_DESCR_MASK) == L2_INVAL)
3415 if ((l2 & ATTR_DESCR_MASK) == L2_BLOCK) {
3416 pa = (l2 & ~ATTR_MASK) | (addr & L2_OFFSET);
3417 managed = (l2 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
3418 val = MINCORE_SUPER | MINCORE_INCORE;
3419 if (pmap_page_dirty(l2))
3420 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3421 if ((l2 & ATTR_AF) == ATTR_AF)
3422 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3426 l3p = pmap_l2_to_l3(l2p, addr);
3427 if (l3p == NULL) /* No l3 */
3430 l3 = pmap_load(l2p);
3431 if ((l3 & ATTR_DESCR_MASK) == L3_INVAL)
3434 if ((l3 & ATTR_DESCR_MASK) == L3_PAGE) {
3435 pa = (l3 & ~ATTR_MASK) | (addr & L3_OFFSET);
3436 managed = (l3 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
3437 val = MINCORE_INCORE;
3438 if (pmap_page_dirty(l3))
3439 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3440 if ((l3 & ATTR_AF) == ATTR_AF)
3441 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3445 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
3446 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
3447 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
3448 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
3451 PA_UNLOCK_COND(*locked_pa);
3458 pmap_activate(struct thread *td)
3463 pmap = vmspace_pmap(td->td_proc->p_vmspace);
3464 td->td_pcb->pcb_l0addr = vtophys(pmap->pm_l0);
3465 __asm __volatile("msr ttbr0_el1, %0" : : "r"(td->td_pcb->pcb_l0addr));
3466 pmap_invalidate_all(pmap);
3471 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
3474 if (va >= VM_MIN_KERNEL_ADDRESS) {
3475 cpu_icache_sync_range(va, sz);
3480 /* Find the length of data in this page to flush */
3481 offset = va & PAGE_MASK;
3482 len = imin(PAGE_SIZE - offset, sz);
3485 /* Extract the physical address & find it in the DMAP */
3486 pa = pmap_extract(pmap, va);
3488 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
3490 /* Move to the next page */
3493 /* Set the length for the next iteration */
3494 len = imin(PAGE_SIZE, sz);
3500 * Increase the starting virtual address of the given mapping if a
3501 * different alignment might result in more superpage mappings.
3504 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
3505 vm_offset_t *addr, vm_size_t size)
3510 * Get the kernel virtual address of a set of physical pages. If there are
3511 * physical addresses not covered by the DMAP perform a transient mapping
3512 * that will be removed when calling pmap_unmap_io_transient.
3514 * \param page The pages the caller wishes to obtain the virtual
3515 * address on the kernel memory map.
3516 * \param vaddr On return contains the kernel virtual memory address
3517 * of the pages passed in the page parameter.
3518 * \param count Number of pages passed in.
3519 * \param can_fault TRUE if the thread using the mapped pages can take
3520 * page faults, FALSE otherwise.
3522 * \returns TRUE if the caller must call pmap_unmap_io_transient when
3523 * finished or FALSE otherwise.
3527 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
3528 boolean_t can_fault)
3531 boolean_t needs_mapping;
3535 * Allocate any KVA space that we need, this is done in a separate
3536 * loop to prevent calling vmem_alloc while pinned.
3538 needs_mapping = FALSE;
3539 for (i = 0; i < count; i++) {
3540 paddr = VM_PAGE_TO_PHYS(page[i]);
3541 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
3542 error = vmem_alloc(kernel_arena, PAGE_SIZE,
3543 M_BESTFIT | M_WAITOK, &vaddr[i]);
3544 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3545 needs_mapping = TRUE;
3547 vaddr[i] = PHYS_TO_DMAP(paddr);
3551 /* Exit early if everything is covered by the DMAP */
3557 for (i = 0; i < count; i++) {
3558 paddr = VM_PAGE_TO_PHYS(page[i]);
3559 if (!PHYS_IN_DMAP(paddr)) {
3561 "pmap_map_io_transient: TODO: Map out of DMAP data");
3565 return (needs_mapping);
3569 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
3570 boolean_t can_fault)
3577 for (i = 0; i < count; i++) {
3578 paddr = VM_PAGE_TO_PHYS(page[i]);
3579 if (!PHYS_IN_DMAP(paddr)) {
3580 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");