2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/limits.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/physmem.h>
123 #include <sys/proc.h>
124 #include <sys/rwlock.h>
125 #include <sys/sbuf.h>
127 #include <sys/vmem.h>
128 #include <sys/vmmeter.h>
129 #include <sys/sched.h>
130 #include <sys/sysctl.h>
131 #include <sys/_unrhdr.h>
135 #include <vm/vm_param.h>
136 #include <vm/vm_kern.h>
137 #include <vm/vm_page.h>
138 #include <vm/vm_map.h>
139 #include <vm/vm_object.h>
140 #include <vm/vm_extern.h>
141 #include <vm/vm_pageout.h>
142 #include <vm/vm_pager.h>
143 #include <vm/vm_phys.h>
144 #include <vm/vm_radix.h>
145 #include <vm/vm_reserv.h>
146 #include <vm/vm_dumpset.h>
149 #include <machine/machdep.h>
150 #include <machine/md_var.h>
151 #include <machine/pcb.h>
153 #define PMAP_ASSERT_STAGE1(pmap) MPASS((pmap)->pm_stage == PM_STAGE1)
154 #define PMAP_ASSERT_STAGE2(pmap) MPASS((pmap)->pm_stage == PM_STAGE2)
156 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
157 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
158 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
159 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
161 #define NUL0E L0_ENTRIES
162 #define NUL1E (NUL0E * NL1PG)
163 #define NUL2E (NUL1E * NL2PG)
165 #if !defined(DIAGNOSTIC)
166 #ifdef __GNUC_GNU_INLINE__
167 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
169 #define PMAP_INLINE extern inline
176 #define PV_STAT(x) do { x ; } while (0)
178 #define PV_STAT(x) do { } while (0)
181 #define pmap_l0_pindex(v) (NUL2E + NUL1E + ((v) >> L0_SHIFT))
182 #define pmap_l1_pindex(v) (NUL2E + ((v) >> L1_SHIFT))
183 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
185 static struct md_page *
186 pa_to_pvh(vm_paddr_t pa)
188 struct vm_phys_seg *seg;
191 for (segind = 0; segind < vm_phys_nsegs; segind++) {
192 seg = &vm_phys_segs[segind];
193 if (pa >= seg->start && pa < seg->end)
194 return ((struct md_page *)seg->md_first +
195 pmap_l2_pindex(pa) - pmap_l2_pindex(seg->start));
197 panic("pa 0x%jx not within vm_phys_segs", (uintmax_t)pa);
200 static struct md_page *
201 page_to_pvh(vm_page_t m)
203 struct vm_phys_seg *seg;
205 seg = &vm_phys_segs[m->segind];
206 return ((struct md_page *)seg->md_first +
207 pmap_l2_pindex(VM_PAGE_TO_PHYS(m)) - pmap_l2_pindex(seg->start));
210 #define NPV_LIST_LOCKS MAXCPU
212 #define PHYS_TO_PV_LIST_LOCK(pa) \
213 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
215 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
216 struct rwlock **_lockp = (lockp); \
217 struct rwlock *_new_lock; \
219 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
220 if (_new_lock != *_lockp) { \
221 if (*_lockp != NULL) \
222 rw_wunlock(*_lockp); \
223 *_lockp = _new_lock; \
228 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
229 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
231 #define RELEASE_PV_LIST_LOCK(lockp) do { \
232 struct rwlock **_lockp = (lockp); \
234 if (*_lockp != NULL) { \
235 rw_wunlock(*_lockp); \
240 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
241 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
244 * The presence of this flag indicates that the mapping is writeable.
245 * If the ATTR_S1_AP_RO bit is also set, then the mapping is clean, otherwise
246 * it is dirty. This flag may only be set on managed mappings.
248 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
249 * as a software managed bit.
251 #define ATTR_SW_DBM ATTR_DBM
253 struct pmap kernel_pmap_store;
255 /* Used for mapping ACPI memory before VM is initialized */
256 #define PMAP_PREINIT_MAPPING_COUNT 32
257 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
258 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
259 static int vm_initialized = 0; /* No need to use pre-init maps when set */
262 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
263 * Always map entire L2 block for simplicity.
264 * VA of L2 block = preinit_map_va + i * L2_SIZE
266 static struct pmap_preinit_mapping {
270 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
272 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
273 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
274 vm_offset_t kernel_vm_end = 0;
277 * Data for the pv entry allocation mechanism.
279 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
280 static struct mtx pv_chunks_mutex;
281 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
282 static struct md_page *pv_table;
283 static struct md_page pv_dummy;
285 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
286 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
287 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
289 /* This code assumes all L1 DMAP entries will be used */
290 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
291 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
293 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
294 extern pt_entry_t pagetable_dmap[];
296 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
297 static vm_paddr_t physmap[PHYSMAP_SIZE];
298 static u_int physmap_idx;
300 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
301 "VM/pmap parameters");
304 * This ASID allocator uses a bit vector ("asid_set") to remember which ASIDs
305 * that it has currently allocated to a pmap, a cursor ("asid_next") to
306 * optimize its search for a free ASID in the bit vector, and an epoch number
307 * ("asid_epoch") to indicate when it has reclaimed all previously allocated
308 * ASIDs that are not currently active on a processor.
310 * The current epoch number is always in the range [0, INT_MAX). Negative
311 * numbers and INT_MAX are reserved for special cases that are described
320 struct mtx asid_set_mutex;
323 static struct asid_set asids;
324 static struct asid_set vmids;
326 static SYSCTL_NODE(_vm_pmap, OID_AUTO, asid, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
328 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, bits, CTLFLAG_RD, &asids.asid_bits, 0,
329 "The number of bits in an ASID");
330 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, next, CTLFLAG_RD, &asids.asid_next, 0,
331 "The last allocated ASID plus one");
332 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, epoch, CTLFLAG_RD, &asids.asid_epoch, 0,
333 "The current epoch number");
335 static SYSCTL_NODE(_vm_pmap, OID_AUTO, vmid, CTLFLAG_RD, 0, "VMID allocator");
336 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, bits, CTLFLAG_RD, &vmids.asid_bits, 0,
337 "The number of bits in an VMID");
338 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, next, CTLFLAG_RD, &vmids.asid_next, 0,
339 "The last allocated VMID plus one");
340 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, epoch, CTLFLAG_RD, &vmids.asid_epoch, 0,
341 "The current epoch number");
343 void (*pmap_clean_stage2_tlbi)(void);
344 void (*pmap_invalidate_vpipt_icache)(void);
347 * A pmap's cookie encodes an ASID and epoch number. Cookies for reserved
348 * ASIDs have a negative epoch number, specifically, INT_MIN. Cookies for
349 * dynamically allocated ASIDs have a non-negative epoch number.
351 * An invalid ASID is represented by -1.
353 * There are two special-case cookie values: (1) COOKIE_FROM(-1, INT_MIN),
354 * which indicates that an ASID should never be allocated to the pmap, and
355 * (2) COOKIE_FROM(-1, INT_MAX), which indicates that an ASID should be
356 * allocated when the pmap is next activated.
358 #define COOKIE_FROM(asid, epoch) ((long)((u_int)(asid) | \
359 ((u_long)(epoch) << 32)))
360 #define COOKIE_TO_ASID(cookie) ((int)(cookie))
361 #define COOKIE_TO_EPOCH(cookie) ((int)((u_long)(cookie) >> 32))
363 static int superpages_enabled = 1;
364 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
365 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
366 "Are large page mappings enabled?");
369 * Internal flags for pmap_enter()'s helper functions.
371 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
372 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
374 static void free_pv_chunk(struct pv_chunk *pc);
375 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
376 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
377 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
378 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
379 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
382 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
383 static bool pmap_activate_int(pmap_t pmap);
384 static void pmap_alloc_asid(pmap_t pmap);
385 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
386 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
387 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
388 vm_offset_t va, struct rwlock **lockp);
389 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
390 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
391 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
392 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
393 u_int flags, vm_page_t m, struct rwlock **lockp);
394 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
395 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
396 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
397 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
398 static void pmap_reset_asid_set(pmap_t pmap);
399 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
400 vm_page_t m, struct rwlock **lockp);
402 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
403 struct rwlock **lockp);
405 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
406 struct spglist *free);
407 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
408 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
411 * These load the old table data and store the new value.
412 * They need to be atomic as the System MMU may write to the table at
413 * the same time as the CPU.
415 #define pmap_clear(table) atomic_store_64(table, 0)
416 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
417 #define pmap_load(table) (*table)
418 #define pmap_load_clear(table) atomic_swap_64(table, 0)
419 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
420 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
421 #define pmap_store(table, entry) atomic_store_64(table, entry)
423 /********************/
424 /* Inline functions */
425 /********************/
428 pagecopy(void *s, void *d)
431 memcpy(d, s, PAGE_SIZE);
434 static __inline pd_entry_t *
435 pmap_l0(pmap_t pmap, vm_offset_t va)
438 return (&pmap->pm_l0[pmap_l0_index(va)]);
441 static __inline pd_entry_t *
442 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
446 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
447 return (&l1[pmap_l1_index(va)]);
450 static __inline pd_entry_t *
451 pmap_l1(pmap_t pmap, vm_offset_t va)
455 l0 = pmap_l0(pmap, va);
456 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
459 return (pmap_l0_to_l1(l0, va));
462 static __inline pd_entry_t *
463 pmap_l1_to_l2(pd_entry_t *l1p, vm_offset_t va)
469 KASSERT(ADDR_IS_CANONICAL(va),
470 ("%s: Address not in canonical form: %lx", __func__, va));
472 * The valid bit may be clear if pmap_update_entry() is concurrently
473 * modifying the entry, so for KVA only the entry type may be checked.
475 KASSERT(ADDR_IS_KERNEL(va) || (l1 & ATTR_DESCR_VALID) != 0,
476 ("%s: L1 entry %#lx for %#lx is invalid", __func__, l1, va));
477 KASSERT((l1 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE,
478 ("%s: L1 entry %#lx for %#lx is a leaf", __func__, l1, va));
479 l2p = (pd_entry_t *)PHYS_TO_DMAP(l1 & ~ATTR_MASK);
480 return (&l2p[pmap_l2_index(va)]);
483 static __inline pd_entry_t *
484 pmap_l2(pmap_t pmap, vm_offset_t va)
488 l1 = pmap_l1(pmap, va);
489 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
492 return (pmap_l1_to_l2(l1, va));
495 static __inline pt_entry_t *
496 pmap_l2_to_l3(pd_entry_t *l2p, vm_offset_t va)
503 KASSERT(ADDR_IS_CANONICAL(va),
504 ("%s: Address not in canonical form: %lx", __func__, va));
506 * The valid bit may be clear if pmap_update_entry() is concurrently
507 * modifying the entry, so for KVA only the entry type may be checked.
509 KASSERT(ADDR_IS_KERNEL(va) || (l2 & ATTR_DESCR_VALID) != 0,
510 ("%s: L2 entry %#lx for %#lx is invalid", __func__, l2, va));
511 KASSERT((l2 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE,
512 ("%s: L2 entry %#lx for %#lx is a leaf", __func__, l2, va));
513 l3p = (pt_entry_t *)PHYS_TO_DMAP(l2 & ~ATTR_MASK);
514 return (&l3p[pmap_l3_index(va)]);
518 * Returns the lowest valid pde for a given virtual address.
519 * The next level may or may not point to a valid page or block.
521 static __inline pd_entry_t *
522 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
524 pd_entry_t *l0, *l1, *l2, desc;
526 l0 = pmap_l0(pmap, va);
527 desc = pmap_load(l0) & ATTR_DESCR_MASK;
528 if (desc != L0_TABLE) {
533 l1 = pmap_l0_to_l1(l0, va);
534 desc = pmap_load(l1) & ATTR_DESCR_MASK;
535 if (desc != L1_TABLE) {
540 l2 = pmap_l1_to_l2(l1, va);
541 desc = pmap_load(l2) & ATTR_DESCR_MASK;
542 if (desc != L2_TABLE) {
552 * Returns the lowest valid pte block or table entry for a given virtual
553 * address. If there are no valid entries return NULL and set the level to
554 * the first invalid level.
556 static __inline pt_entry_t *
557 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
559 pd_entry_t *l1, *l2, desc;
562 l1 = pmap_l1(pmap, va);
567 desc = pmap_load(l1) & ATTR_DESCR_MASK;
568 if (desc == L1_BLOCK) {
573 if (desc != L1_TABLE) {
578 l2 = pmap_l1_to_l2(l1, va);
579 desc = pmap_load(l2) & ATTR_DESCR_MASK;
580 if (desc == L2_BLOCK) {
585 if (desc != L2_TABLE) {
591 l3 = pmap_l2_to_l3(l2, va);
592 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
599 pmap_ps_enabled(pmap_t pmap __unused)
602 return (superpages_enabled != 0);
606 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
607 pd_entry_t **l2, pt_entry_t **l3)
609 pd_entry_t *l0p, *l1p, *l2p;
611 if (pmap->pm_l0 == NULL)
614 l0p = pmap_l0(pmap, va);
617 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
620 l1p = pmap_l0_to_l1(l0p, va);
623 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
629 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
632 l2p = pmap_l1_to_l2(l1p, va);
635 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
640 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
643 *l3 = pmap_l2_to_l3(l2p, va);
649 pmap_l3_valid(pt_entry_t l3)
652 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
655 CTASSERT(L1_BLOCK == L2_BLOCK);
658 pmap_pte_memattr(pmap_t pmap, vm_memattr_t memattr)
662 if (pmap->pm_stage == PM_STAGE1) {
663 val = ATTR_S1_IDX(memattr);
664 if (memattr == VM_MEMATTR_DEVICE)
672 case VM_MEMATTR_DEVICE:
673 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_DEVICE_nGnRnE) |
674 ATTR_S2_XN(ATTR_S2_XN_ALL));
675 case VM_MEMATTR_UNCACHEABLE:
676 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_NC));
677 case VM_MEMATTR_WRITE_BACK:
678 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WB));
679 case VM_MEMATTR_WRITE_THROUGH:
680 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WT));
682 panic("%s: invalid memory attribute %x", __func__, memattr);
687 pmap_pte_prot(pmap_t pmap, vm_prot_t prot)
692 if (pmap->pm_stage == PM_STAGE1) {
693 if ((prot & VM_PROT_EXECUTE) == 0)
695 if ((prot & VM_PROT_WRITE) == 0)
696 val |= ATTR_S1_AP(ATTR_S1_AP_RO);
698 if ((prot & VM_PROT_WRITE) != 0)
699 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
700 if ((prot & VM_PROT_READ) != 0)
701 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_READ);
702 if ((prot & VM_PROT_EXECUTE) == 0)
703 val |= ATTR_S2_XN(ATTR_S2_XN_ALL);
710 * Checks if the PTE is dirty.
713 pmap_pte_dirty(pmap_t pmap, pt_entry_t pte)
716 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
718 if (pmap->pm_stage == PM_STAGE1) {
719 KASSERT((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) != 0,
720 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
722 return ((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
723 (ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_SW_DBM));
726 return ((pte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
727 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE));
731 pmap_resident_count_inc(pmap_t pmap, int count)
734 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
735 pmap->pm_stats.resident_count += count;
739 pmap_resident_count_dec(pmap_t pmap, int count)
742 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
743 KASSERT(pmap->pm_stats.resident_count >= count,
744 ("pmap %p resident count underflow %ld %d", pmap,
745 pmap->pm_stats.resident_count, count));
746 pmap->pm_stats.resident_count -= count;
750 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
754 pa_page = arm64_address_translate_s1e1r(va) & PAR_PA_MASK;
755 return (pa_page | (va & PAR_LOW_MASK));
759 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
760 vm_offset_t freemempos)
764 vm_paddr_t l2_pa, pa;
765 u_int l1_slot, l2_slot, prev_l1_slot;
768 dmap_phys_base = min_pa & ~L1_OFFSET;
774 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
775 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
777 for (i = 0; i < (physmap_idx * 2); i += 2) {
778 pa = physmap[i] & ~L2_OFFSET;
779 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
781 /* Create L2 mappings at the start of the region */
782 if ((pa & L1_OFFSET) != 0) {
783 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
784 if (l1_slot != prev_l1_slot) {
785 prev_l1_slot = l1_slot;
786 l2 = (pt_entry_t *)freemempos;
787 l2_pa = pmap_early_vtophys(kern_l1,
789 freemempos += PAGE_SIZE;
791 pmap_store(&pagetable_dmap[l1_slot],
792 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
794 memset(l2, 0, PAGE_SIZE);
797 ("pmap_bootstrap_dmap: NULL l2 map"));
798 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
799 pa += L2_SIZE, va += L2_SIZE) {
801 * We are on a boundary, stop to
802 * create a level 1 block
804 if ((pa & L1_OFFSET) == 0)
807 l2_slot = pmap_l2_index(va);
808 KASSERT(l2_slot != 0, ("..."));
809 pmap_store(&l2[l2_slot],
810 (pa & ~L2_OFFSET) | ATTR_DEFAULT |
812 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
815 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
819 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
820 (physmap[i + 1] - pa) >= L1_SIZE;
821 pa += L1_SIZE, va += L1_SIZE) {
822 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
823 pmap_store(&pagetable_dmap[l1_slot],
824 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_S1_XN |
825 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L1_BLOCK);
828 /* Create L2 mappings at the end of the region */
829 if (pa < physmap[i + 1]) {
830 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
831 if (l1_slot != prev_l1_slot) {
832 prev_l1_slot = l1_slot;
833 l2 = (pt_entry_t *)freemempos;
834 l2_pa = pmap_early_vtophys(kern_l1,
836 freemempos += PAGE_SIZE;
838 pmap_store(&pagetable_dmap[l1_slot],
839 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
841 memset(l2, 0, PAGE_SIZE);
844 ("pmap_bootstrap_dmap: NULL l2 map"));
845 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
846 pa += L2_SIZE, va += L2_SIZE) {
847 l2_slot = pmap_l2_index(va);
848 pmap_store(&l2[l2_slot],
849 (pa & ~L2_OFFSET) | ATTR_DEFAULT |
851 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
856 if (pa > dmap_phys_max) {
868 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
875 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
877 l1 = (pd_entry_t *)l1pt;
878 l1_slot = pmap_l1_index(va);
881 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
882 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
884 pa = pmap_early_vtophys(l1pt, l2pt);
885 pmap_store(&l1[l1_slot],
886 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
890 /* Clean the L2 page table */
891 memset((void *)l2_start, 0, l2pt - l2_start);
897 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
904 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
906 l2 = pmap_l2(kernel_pmap, va);
907 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
908 l2_slot = pmap_l2_index(va);
911 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
912 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
914 pa = pmap_early_vtophys(l1pt, l3pt);
915 pmap_store(&l2[l2_slot],
916 (pa & ~Ln_TABLE_MASK) | ATTR_S1_UXN | L2_TABLE);
920 /* Clean the L2 page table */
921 memset((void *)l3_start, 0, l3pt - l3_start);
927 * Bootstrap the system enough to run with virtual memory.
930 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
933 vm_offset_t freemempos;
934 vm_offset_t dpcpu, msgbufpv;
935 vm_paddr_t start_pa, pa, min_pa;
939 /* Verify that the ASID is set through TTBR0. */
940 KASSERT((READ_SPECIALREG(tcr_el1) & TCR_A1) == 0,
941 ("pmap_bootstrap: TCR_EL1.A1 != 0"));
943 kern_delta = KERNBASE - kernstart;
945 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
946 printf("%lx\n", l1pt);
947 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
949 /* Set this early so we can use the pagetable walking functions */
950 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
951 PMAP_LOCK_INIT(kernel_pmap);
952 kernel_pmap->pm_l0_paddr = l0pt - kern_delta;
953 kernel_pmap->pm_cookie = COOKIE_FROM(-1, INT_MIN);
954 kernel_pmap->pm_stage = PM_STAGE1;
955 kernel_pmap->pm_levels = 4;
956 kernel_pmap->pm_ttbr = kernel_pmap->pm_l0_paddr;
957 kernel_pmap->pm_asid_set = &asids;
959 /* Assume the address we were loaded to is a valid physical address */
960 min_pa = KERNBASE - kern_delta;
962 physmap_idx = physmem_avail(physmap, nitems(physmap));
966 * Find the minimum physical address. physmap is sorted,
967 * but may contain empty ranges.
969 for (i = 0; i < physmap_idx * 2; i += 2) {
970 if (physmap[i] == physmap[i + 1])
972 if (physmap[i] <= min_pa)
976 freemempos = KERNBASE + kernlen;
977 freemempos = roundup2(freemempos, PAGE_SIZE);
979 /* Create a direct map region early so we can use it for pa -> va */
980 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
982 start_pa = pa = KERNBASE - kern_delta;
985 * Create the l2 tables up to VM_MAX_KERNEL_ADDRESS. We assume that the
986 * loader allocated the first and only l2 page table page used to map
987 * the kernel, preloaded files and module metadata.
989 freemempos = pmap_bootstrap_l2(l1pt, KERNBASE + L1_SIZE, freemempos);
990 /* And the l3 tables for the early devmap */
991 freemempos = pmap_bootstrap_l3(l1pt,
992 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
996 #define alloc_pages(var, np) \
997 (var) = freemempos; \
998 freemempos += (np * PAGE_SIZE); \
999 memset((char *)(var), 0, ((np) * PAGE_SIZE));
1001 /* Allocate dynamic per-cpu area. */
1002 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
1003 dpcpu_init((void *)dpcpu, 0);
1005 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
1006 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
1007 msgbufp = (void *)msgbufpv;
1009 /* Reserve some VA space for early BIOS/ACPI mapping */
1010 preinit_map_va = roundup2(freemempos, L2_SIZE);
1012 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
1013 virtual_avail = roundup2(virtual_avail, L1_SIZE);
1014 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
1015 kernel_vm_end = virtual_avail;
1017 pa = pmap_early_vtophys(l1pt, freemempos);
1019 physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
1025 * Initialize a vm_page's machine-dependent fields.
1028 pmap_page_init(vm_page_t m)
1031 TAILQ_INIT(&m->md.pv_list);
1032 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
1036 pmap_init_asids(struct asid_set *set, int bits)
1040 set->asid_bits = bits;
1043 * We may be too early in the overall initialization process to use
1046 set->asid_set_size = 1 << set->asid_bits;
1047 set->asid_set = (bitstr_t *)kmem_malloc(bitstr_size(set->asid_set_size),
1049 for (i = 0; i < ASID_FIRST_AVAILABLE; i++)
1050 bit_set(set->asid_set, i);
1051 set->asid_next = ASID_FIRST_AVAILABLE;
1052 mtx_init(&set->asid_set_mutex, "asid set", NULL, MTX_SPIN);
1056 * Initialize the pmap module.
1057 * Called by vm_init, to initialize any structures that the pmap
1058 * system needs to map virtual memory.
1063 struct vm_phys_seg *seg, *next_seg;
1064 struct md_page *pvh;
1067 int i, pv_npg, vmid_bits;
1070 * Are large page mappings enabled?
1072 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
1073 if (superpages_enabled) {
1074 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1075 ("pmap_init: can't assign to pagesizes[1]"));
1076 pagesizes[1] = L2_SIZE;
1077 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0,
1078 ("pmap_init: can't assign to pagesizes[2]"));
1079 pagesizes[2] = L1_SIZE;
1083 * Initialize the ASID allocator.
1085 pmap_init_asids(&asids,
1086 (READ_SPECIALREG(tcr_el1) & TCR_ASID_16) != 0 ? 16 : 8);
1089 mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1);
1092 if (ID_AA64MMFR1_VMIDBits_VAL(mmfr1) ==
1093 ID_AA64MMFR1_VMIDBits_16)
1095 pmap_init_asids(&vmids, vmid_bits);
1099 * Initialize the pv chunk list mutex.
1101 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1104 * Initialize the pool of pv list locks.
1106 for (i = 0; i < NPV_LIST_LOCKS; i++)
1107 rw_init(&pv_list_locks[i], "pmap pv list");
1110 * Calculate the size of the pv head table for superpages.
1113 for (i = 0; i < vm_phys_nsegs; i++) {
1114 seg = &vm_phys_segs[i];
1115 pv_npg += pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) -
1116 pmap_l2_pindex(seg->start);
1120 * Allocate memory for the pv head table for superpages.
1122 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1124 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1125 for (i = 0; i < pv_npg; i++)
1126 TAILQ_INIT(&pv_table[i].pv_list);
1127 TAILQ_INIT(&pv_dummy.pv_list);
1130 * Set pointers from vm_phys_segs to pv_table.
1132 for (i = 0, pvh = pv_table; i < vm_phys_nsegs; i++) {
1133 seg = &vm_phys_segs[i];
1134 seg->md_first = pvh;
1135 pvh += pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) -
1136 pmap_l2_pindex(seg->start);
1139 * If there is a following segment, and the final
1140 * superpage of this segment and the initial superpage
1141 * of the next segment are the same then adjust the
1142 * pv_table entry for that next segment down by one so
1143 * that the pv_table entries will be shared.
1145 if (i + 1 < vm_phys_nsegs) {
1146 next_seg = &vm_phys_segs[i + 1];
1147 if (pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) - 1 ==
1148 pmap_l2_pindex(next_seg->start)) {
1157 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1158 "2MB page mapping counters");
1160 static u_long pmap_l2_demotions;
1161 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
1162 &pmap_l2_demotions, 0, "2MB page demotions");
1164 static u_long pmap_l2_mappings;
1165 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
1166 &pmap_l2_mappings, 0, "2MB page mappings");
1168 static u_long pmap_l2_p_failures;
1169 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
1170 &pmap_l2_p_failures, 0, "2MB page promotion failures");
1172 static u_long pmap_l2_promotions;
1173 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
1174 &pmap_l2_promotions, 0, "2MB page promotions");
1177 * Invalidate a single TLB entry.
1179 static __inline void
1180 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1184 PMAP_ASSERT_STAGE1(pmap);
1187 if (pmap == kernel_pmap) {
1189 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1191 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) | atop(va);
1192 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1198 static __inline void
1199 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1201 uint64_t end, r, start;
1203 PMAP_ASSERT_STAGE1(pmap);
1206 if (pmap == kernel_pmap) {
1209 for (r = start; r < end; r++)
1210 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1212 start = end = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1215 for (r = start; r < end; r++)
1216 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1222 static __inline void
1223 pmap_invalidate_all(pmap_t pmap)
1227 PMAP_ASSERT_STAGE1(pmap);
1230 if (pmap == kernel_pmap) {
1231 __asm __volatile("tlbi vmalle1is");
1233 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1234 __asm __volatile("tlbi aside1is, %0" : : "r" (r));
1241 * Routine: pmap_extract
1243 * Extract the physical page address associated
1244 * with the given map/virtual_address pair.
1247 pmap_extract(pmap_t pmap, vm_offset_t va)
1249 pt_entry_t *pte, tpte;
1256 * Find the block or page map for this virtual address. pmap_pte
1257 * will return either a valid block/page entry, or NULL.
1259 pte = pmap_pte(pmap, va, &lvl);
1261 tpte = pmap_load(pte);
1262 pa = tpte & ~ATTR_MASK;
1265 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1266 ("pmap_extract: Invalid L1 pte found: %lx",
1267 tpte & ATTR_DESCR_MASK));
1268 pa |= (va & L1_OFFSET);
1271 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1272 ("pmap_extract: Invalid L2 pte found: %lx",
1273 tpte & ATTR_DESCR_MASK));
1274 pa |= (va & L2_OFFSET);
1277 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1278 ("pmap_extract: Invalid L3 pte found: %lx",
1279 tpte & ATTR_DESCR_MASK));
1280 pa |= (va & L3_OFFSET);
1289 * Routine: pmap_extract_and_hold
1291 * Atomically extract and hold the physical page
1292 * with the given pmap and virtual address pair
1293 * if that mapping permits the given protection.
1296 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1298 pt_entry_t *pte, tpte;
1306 pte = pmap_pte(pmap, va, &lvl);
1308 tpte = pmap_load(pte);
1310 KASSERT(lvl > 0 && lvl <= 3,
1311 ("pmap_extract_and_hold: Invalid level %d", lvl));
1312 CTASSERT(L1_BLOCK == L2_BLOCK);
1313 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1314 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1315 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1316 tpte & ATTR_DESCR_MASK));
1319 if ((prot & VM_PROT_WRITE) == 0)
1321 else if (pmap->pm_stage == PM_STAGE1 &&
1322 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW))
1324 else if (pmap->pm_stage == PM_STAGE2 &&
1325 ((tpte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
1326 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)))
1332 off = va & L1_OFFSET;
1335 off = va & L2_OFFSET;
1341 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1342 if (m != NULL && !vm_page_wire_mapped(m))
1351 * Walks the page tables to translate a kernel virtual address to a
1352 * physical address. Returns true if the kva is valid and stores the
1353 * physical address in pa if it is not NULL.
1356 pmap_klookup(vm_offset_t va, vm_paddr_t *pa)
1358 pt_entry_t *pte, tpte;
1363 * Disable interrupts so we don't get interrupted between asking
1364 * for address translation, and getting the result back.
1366 intr = intr_disable();
1367 par = arm64_address_translate_s1e1r(va);
1370 if (PAR_SUCCESS(par)) {
1372 *pa = (par & PAR_PA_MASK) | (va & PAR_LOW_MASK);
1377 * Fall back to walking the page table. The address translation
1378 * instruction may fail when the page is in a break-before-make
1379 * sequence. As we only clear the valid bit in said sequence we
1380 * can walk the page table to find the physical address.
1383 pte = pmap_l1(kernel_pmap, va);
1388 * A concurrent pmap_update_entry() will clear the entry's valid bit
1389 * but leave the rest of the entry unchanged. Therefore, we treat a
1390 * non-zero entry as being valid, and we ignore the valid bit when
1391 * determining whether the entry maps a block, page, or table.
1393 tpte = pmap_load(pte);
1396 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
1398 *pa = (tpte & ~ATTR_MASK) | (va & L1_OFFSET);
1401 pte = pmap_l1_to_l2(&tpte, va);
1402 tpte = pmap_load(pte);
1405 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
1407 *pa = (tpte & ~ATTR_MASK) | (va & L2_OFFSET);
1410 pte = pmap_l2_to_l3(&tpte, va);
1411 tpte = pmap_load(pte);
1415 *pa = (tpte & ~ATTR_MASK) | (va & L3_OFFSET);
1420 pmap_kextract(vm_offset_t va)
1424 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
1425 return (DMAP_TO_PHYS(va));
1427 if (pmap_klookup(va, &pa) == false)
1432 /***************************************************
1433 * Low level mapping routines.....
1434 ***************************************************/
1437 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1440 pt_entry_t *pte, attr;
1444 KASSERT((pa & L3_OFFSET) == 0,
1445 ("pmap_kenter: Invalid physical address"));
1446 KASSERT((sva & L3_OFFSET) == 0,
1447 ("pmap_kenter: Invalid virtual address"));
1448 KASSERT((size & PAGE_MASK) == 0,
1449 ("pmap_kenter: Mapping is not page-sized"));
1451 attr = ATTR_DEFAULT | ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1452 ATTR_S1_IDX(mode) | L3_PAGE;
1455 pde = pmap_pde(kernel_pmap, va, &lvl);
1456 KASSERT(pde != NULL,
1457 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1458 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1460 pte = pmap_l2_to_l3(pde, va);
1461 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1467 pmap_invalidate_range(kernel_pmap, sva, va);
1471 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1474 pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
1478 * Remove a page from the kernel pagetables.
1481 pmap_kremove(vm_offset_t va)
1486 pte = pmap_pte(kernel_pmap, va, &lvl);
1487 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1488 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1491 pmap_invalidate_page(kernel_pmap, va);
1495 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1501 KASSERT((sva & L3_OFFSET) == 0,
1502 ("pmap_kremove_device: Invalid virtual address"));
1503 KASSERT((size & PAGE_MASK) == 0,
1504 ("pmap_kremove_device: Mapping is not page-sized"));
1508 pte = pmap_pte(kernel_pmap, va, &lvl);
1509 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1511 ("Invalid device pagetable level: %d != 3", lvl));
1517 pmap_invalidate_range(kernel_pmap, sva, va);
1521 * Used to map a range of physical addresses into kernel
1522 * virtual address space.
1524 * The value passed in '*virt' is a suggested virtual address for
1525 * the mapping. Architectures which can support a direct-mapped
1526 * physical to virtual region can return the appropriate address
1527 * within that region, leaving '*virt' unchanged. Other
1528 * architectures should map the pages starting at '*virt' and
1529 * update '*virt' with the first usable address after the mapped
1533 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1535 return PHYS_TO_DMAP(start);
1539 * Add a list of wired pages to the kva
1540 * this routine is only used for temporary
1541 * kernel mappings that do not need to have
1542 * page modification or references recorded.
1543 * Note that old mappings are simply written
1544 * over. The page *must* be wired.
1545 * Note: SMP coherent. Uses a ranged shootdown IPI.
1548 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1551 pt_entry_t *pte, pa;
1557 for (i = 0; i < count; i++) {
1558 pde = pmap_pde(kernel_pmap, va, &lvl);
1559 KASSERT(pde != NULL,
1560 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1562 ("pmap_qenter: Invalid level %d", lvl));
1565 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
1566 ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1567 ATTR_S1_IDX(m->md.pv_memattr) | L3_PAGE;
1568 pte = pmap_l2_to_l3(pde, va);
1569 pmap_load_store(pte, pa);
1573 pmap_invalidate_range(kernel_pmap, sva, va);
1577 * This routine tears out page mappings from the
1578 * kernel -- it is meant only for temporary mappings.
1581 pmap_qremove(vm_offset_t sva, int count)
1587 KASSERT(ADDR_IS_CANONICAL(sva),
1588 ("%s: Address not in canonical form: %lx", __func__, sva));
1589 KASSERT(ADDR_IS_KERNEL(sva), ("usermode va %lx", sva));
1592 while (count-- > 0) {
1593 pte = pmap_pte(kernel_pmap, va, &lvl);
1595 ("Invalid device pagetable level: %d != 3", lvl));
1602 pmap_invalidate_range(kernel_pmap, sva, va);
1605 /***************************************************
1606 * Page table page management routines.....
1607 ***************************************************/
1609 * Schedule the specified unused page table page to be freed. Specifically,
1610 * add the page to the specified list of pages that will be released to the
1611 * physical memory manager after the TLB has been updated.
1613 static __inline void
1614 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1615 boolean_t set_PG_ZERO)
1619 m->flags |= PG_ZERO;
1621 m->flags &= ~PG_ZERO;
1622 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1626 * Decrements a page table page's reference count, which is used to record the
1627 * number of valid page table entries within the page. If the reference count
1628 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1629 * page table page was unmapped and FALSE otherwise.
1631 static inline boolean_t
1632 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1636 if (m->ref_count == 0) {
1637 _pmap_unwire_l3(pmap, va, m, free);
1644 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1647 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1649 * unmap the page table page
1651 if (m->pindex >= (NUL2E + NUL1E)) {
1655 l0 = pmap_l0(pmap, va);
1657 } else if (m->pindex >= NUL2E) {
1661 l1 = pmap_l1(pmap, va);
1667 l2 = pmap_l2(pmap, va);
1670 pmap_resident_count_dec(pmap, 1);
1671 if (m->pindex < NUL2E) {
1672 /* We just released an l3, unhold the matching l2 */
1673 pd_entry_t *l1, tl1;
1676 l1 = pmap_l1(pmap, va);
1677 tl1 = pmap_load(l1);
1678 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1679 pmap_unwire_l3(pmap, va, l2pg, free);
1680 } else if (m->pindex < (NUL2E + NUL1E)) {
1681 /* We just released an l2, unhold the matching l1 */
1682 pd_entry_t *l0, tl0;
1685 l0 = pmap_l0(pmap, va);
1686 tl0 = pmap_load(l0);
1687 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1688 pmap_unwire_l3(pmap, va, l1pg, free);
1690 pmap_invalidate_page(pmap, va);
1693 * Put page on a list so that it is released after
1694 * *ALL* TLB shootdown is done
1696 pmap_add_delayed_free_list(m, free, TRUE);
1700 * After removing a page table entry, this routine is used to
1701 * conditionally free the page, and manage the reference count.
1704 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1705 struct spglist *free)
1709 KASSERT(ADDR_IS_CANONICAL(va),
1710 ("%s: Address not in canonical form: %lx", __func__, va));
1711 if (ADDR_IS_KERNEL(va))
1713 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1714 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1715 return (pmap_unwire_l3(pmap, va, mpte, free));
1719 * Release a page table page reference after a failed attempt to create a
1723 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
1725 struct spglist free;
1728 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
1730 * Although "va" was never mapped, the TLB could nonetheless
1731 * have intermediate entries that refer to the freed page
1732 * table pages. Invalidate those entries.
1734 * XXX redundant invalidation (See _pmap_unwire_l3().)
1736 pmap_invalidate_page(pmap, va);
1737 vm_page_free_pages_toq(&free, true);
1742 pmap_pinit0(pmap_t pmap)
1745 PMAP_LOCK_INIT(pmap);
1746 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1747 pmap->pm_l0_paddr = READ_SPECIALREG(ttbr0_el1);
1748 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1749 pmap->pm_root.rt_root = 0;
1750 pmap->pm_cookie = COOKIE_FROM(ASID_RESERVED_FOR_PID_0, INT_MIN);
1751 pmap->pm_stage = PM_STAGE1;
1752 pmap->pm_levels = 4;
1753 pmap->pm_ttbr = pmap->pm_l0_paddr;
1754 pmap->pm_asid_set = &asids;
1756 PCPU_SET(curpmap, pmap);
1760 pmap_pinit_stage(pmap_t pmap, enum pmap_stage stage, int levels)
1765 * allocate the l0 page
1767 while ((m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1768 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1771 pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(m);
1772 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1774 if ((m->flags & PG_ZERO) == 0)
1775 pagezero(pmap->pm_l0);
1777 pmap->pm_root.rt_root = 0;
1778 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1779 pmap->pm_cookie = COOKIE_FROM(-1, INT_MAX);
1781 MPASS(levels == 3 || levels == 4);
1782 pmap->pm_levels = levels;
1783 pmap->pm_stage = stage;
1786 pmap->pm_asid_set = &asids;
1789 pmap->pm_asid_set = &vmids;
1792 panic("%s: Invalid pmap type %d", __func__, stage);
1796 /* XXX Temporarily disable deferred ASID allocation. */
1797 pmap_alloc_asid(pmap);
1800 * Allocate the level 1 entry to use as the root. This will increase
1801 * the refcount on the level 1 page so it won't be removed until
1802 * pmap_release() is called.
1804 if (pmap->pm_levels == 3) {
1806 m = _pmap_alloc_l3(pmap, NUL2E + NUL1E, NULL);
1809 pmap->pm_ttbr = VM_PAGE_TO_PHYS(m);
1815 pmap_pinit(pmap_t pmap)
1818 return (pmap_pinit_stage(pmap, PM_STAGE1, 4));
1822 * This routine is called if the desired page table page does not exist.
1824 * If page table page allocation fails, this routine may sleep before
1825 * returning NULL. It sleeps only if a lock pointer was given.
1827 * Note: If a page allocation fails at page table level two or three,
1828 * one or two pages may be held during the wait, only to be released
1829 * afterwards. This conservative approach is easily argued to avoid
1833 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1835 vm_page_t m, l1pg, l2pg;
1837 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1840 * Allocate a page table page.
1842 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1843 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1844 if (lockp != NULL) {
1845 RELEASE_PV_LIST_LOCK(lockp);
1852 * Indicate the need to retry. While waiting, the page table
1853 * page may have been allocated.
1857 if ((m->flags & PG_ZERO) == 0)
1861 * Because of AArch64's weak memory consistency model, we must have a
1862 * barrier here to ensure that the stores for zeroing "m", whether by
1863 * pmap_zero_page() or an earlier function, are visible before adding
1864 * "m" to the page table. Otherwise, a page table walk by another
1865 * processor's MMU could see the mapping to "m" and a stale, non-zero
1871 * Map the pagetable page into the process address space, if
1872 * it isn't already there.
1875 if (ptepindex >= (NUL2E + NUL1E)) {
1877 vm_pindex_t l0index;
1879 l0index = ptepindex - (NUL2E + NUL1E);
1880 l0 = &pmap->pm_l0[l0index];
1881 KASSERT((pmap_load(l0) & ATTR_DESCR_VALID) == 0,
1882 ("%s: L0 entry %#lx is valid", __func__, pmap_load(l0)));
1883 pmap_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1884 } else if (ptepindex >= NUL2E) {
1885 vm_pindex_t l0index, l1index;
1886 pd_entry_t *l0, *l1;
1889 l1index = ptepindex - NUL2E;
1890 l0index = l1index >> L0_ENTRIES_SHIFT;
1892 l0 = &pmap->pm_l0[l0index];
1893 tl0 = pmap_load(l0);
1895 /* recurse for allocating page dir */
1896 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1898 vm_page_unwire_noq(m);
1899 vm_page_free_zero(m);
1903 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1907 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1908 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1909 KASSERT((pmap_load(l1) & ATTR_DESCR_VALID) == 0,
1910 ("%s: L1 entry %#lx is valid", __func__, pmap_load(l1)));
1911 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1913 vm_pindex_t l0index, l1index;
1914 pd_entry_t *l0, *l1, *l2;
1915 pd_entry_t tl0, tl1;
1917 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1918 l0index = l1index >> L0_ENTRIES_SHIFT;
1920 l0 = &pmap->pm_l0[l0index];
1921 tl0 = pmap_load(l0);
1923 /* recurse for allocating page dir */
1924 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1926 vm_page_unwire_noq(m);
1927 vm_page_free_zero(m);
1930 tl0 = pmap_load(l0);
1931 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1932 l1 = &l1[l1index & Ln_ADDR_MASK];
1934 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1935 l1 = &l1[l1index & Ln_ADDR_MASK];
1936 tl1 = pmap_load(l1);
1938 /* recurse for allocating page dir */
1939 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1941 vm_page_unwire_noq(m);
1942 vm_page_free_zero(m);
1946 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1951 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1952 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1953 KASSERT((pmap_load(l2) & ATTR_DESCR_VALID) == 0,
1954 ("%s: L2 entry %#lx is valid", __func__, pmap_load(l2)));
1955 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1958 pmap_resident_count_inc(pmap, 1);
1964 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, vm_page_t *l2pgp,
1965 struct rwlock **lockp)
1967 pd_entry_t *l1, *l2;
1969 vm_pindex_t l2pindex;
1971 KASSERT(ADDR_IS_CANONICAL(va),
1972 ("%s: Address not in canonical form: %lx", __func__, va));
1975 l1 = pmap_l1(pmap, va);
1976 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1977 l2 = pmap_l1_to_l2(l1, va);
1978 if (!ADDR_IS_KERNEL(va)) {
1979 /* Add a reference to the L2 page. */
1980 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1984 } else if (!ADDR_IS_KERNEL(va)) {
1985 /* Allocate a L2 page. */
1986 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1987 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1994 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
1995 l2 = &l2[pmap_l2_index(va)];
1997 panic("pmap_alloc_l2: missing page table page for va %#lx",
2004 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2006 vm_pindex_t ptepindex;
2007 pd_entry_t *pde, tpde;
2015 * Calculate pagetable page index
2017 ptepindex = pmap_l2_pindex(va);
2020 * Get the page directory entry
2022 pde = pmap_pde(pmap, va, &lvl);
2025 * If the page table page is mapped, we just increment the hold count,
2026 * and activate it. If we get a level 2 pde it will point to a level 3
2034 pte = pmap_l0_to_l1(pde, va);
2035 KASSERT(pmap_load(pte) == 0,
2036 ("pmap_alloc_l3: TODO: l0 superpages"));
2041 pte = pmap_l1_to_l2(pde, va);
2042 KASSERT(pmap_load(pte) == 0,
2043 ("pmap_alloc_l3: TODO: l1 superpages"));
2047 tpde = pmap_load(pde);
2049 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
2055 panic("pmap_alloc_l3: Invalid level %d", lvl);
2059 * Here if the pte page isn't mapped, or if it has been deallocated.
2061 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
2062 if (m == NULL && lockp != NULL)
2068 /***************************************************
2069 * Pmap allocation/deallocation routines.
2070 ***************************************************/
2073 * Release any resources held by the given physical map.
2074 * Called when a pmap initialized by pmap_pinit is being released.
2075 * Should only be called if the map contains no valid mappings.
2078 pmap_release(pmap_t pmap)
2081 struct spglist free;
2082 struct asid_set *set;
2086 if (pmap->pm_levels != 4) {
2087 PMAP_ASSERT_STAGE2(pmap);
2088 KASSERT(pmap->pm_stats.resident_count == 1,
2089 ("pmap_release: pmap resident count %ld != 0",
2090 pmap->pm_stats.resident_count));
2091 KASSERT((pmap->pm_l0[0] & ATTR_DESCR_VALID) == ATTR_DESCR_VALID,
2092 ("pmap_release: Invalid l0 entry: %lx", pmap->pm_l0[0]));
2095 m = PHYS_TO_VM_PAGE(pmap->pm_ttbr);
2097 rv = pmap_unwire_l3(pmap, 0, m, &free);
2100 vm_page_free_pages_toq(&free, true);
2103 KASSERT(pmap->pm_stats.resident_count == 0,
2104 ("pmap_release: pmap resident count %ld != 0",
2105 pmap->pm_stats.resident_count));
2106 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2107 ("pmap_release: pmap has reserved page table page(s)"));
2109 set = pmap->pm_asid_set;
2110 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
2113 * Allow the ASID to be reused. In stage 2 VMIDs we don't invalidate
2114 * the entries when removing them so rely on a later tlb invalidation.
2115 * this will happen when updating the VMID generation. Because of this
2116 * we don't reuse VMIDs within a generation.
2118 if (pmap->pm_stage == PM_STAGE1) {
2119 mtx_lock_spin(&set->asid_set_mutex);
2120 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch) {
2121 asid = COOKIE_TO_ASID(pmap->pm_cookie);
2122 KASSERT(asid >= ASID_FIRST_AVAILABLE &&
2123 asid < set->asid_set_size,
2124 ("pmap_release: pmap cookie has out-of-range asid"));
2125 bit_clear(set->asid_set, asid);
2127 mtx_unlock_spin(&set->asid_set_mutex);
2130 m = PHYS_TO_VM_PAGE(pmap->pm_l0_paddr);
2131 vm_page_unwire_noq(m);
2132 vm_page_free_zero(m);
2136 kvm_size(SYSCTL_HANDLER_ARGS)
2138 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
2140 return sysctl_handle_long(oidp, &ksize, 0, req);
2142 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
2143 0, 0, kvm_size, "LU",
2147 kvm_free(SYSCTL_HANDLER_ARGS)
2149 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2151 return sysctl_handle_long(oidp, &kfree, 0, req);
2153 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
2154 0, 0, kvm_free, "LU",
2155 "Amount of KVM free");
2158 * grow the number of kernel page table entries, if needed
2161 pmap_growkernel(vm_offset_t addr)
2165 pd_entry_t *l0, *l1, *l2;
2167 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2169 addr = roundup2(addr, L2_SIZE);
2170 if (addr - 1 >= vm_map_max(kernel_map))
2171 addr = vm_map_max(kernel_map);
2172 while (kernel_vm_end < addr) {
2173 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
2174 KASSERT(pmap_load(l0) != 0,
2175 ("pmap_growkernel: No level 0 kernel entry"));
2177 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
2178 if (pmap_load(l1) == 0) {
2179 /* We need a new PDP entry */
2180 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
2181 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2182 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2184 panic("pmap_growkernel: no memory to grow kernel");
2185 if ((nkpg->flags & PG_ZERO) == 0)
2186 pmap_zero_page(nkpg);
2187 /* See the dmb() in _pmap_alloc_l3(). */
2189 paddr = VM_PAGE_TO_PHYS(nkpg);
2190 pmap_store(l1, paddr | L1_TABLE);
2191 continue; /* try again */
2193 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
2194 if (pmap_load(l2) != 0) {
2195 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2196 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2197 kernel_vm_end = vm_map_max(kernel_map);
2203 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
2204 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2207 panic("pmap_growkernel: no memory to grow kernel");
2208 if ((nkpg->flags & PG_ZERO) == 0)
2209 pmap_zero_page(nkpg);
2210 /* See the dmb() in _pmap_alloc_l3(). */
2212 paddr = VM_PAGE_TO_PHYS(nkpg);
2213 pmap_store(l2, paddr | L2_TABLE);
2215 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2216 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2217 kernel_vm_end = vm_map_max(kernel_map);
2223 /***************************************************
2224 * page management routines.
2225 ***************************************************/
2227 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2228 CTASSERT(_NPCM == 3);
2229 CTASSERT(_NPCPV == 168);
2231 static __inline struct pv_chunk *
2232 pv_to_chunk(pv_entry_t pv)
2235 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2238 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2240 #define PC_FREE0 0xfffffffffffffffful
2241 #define PC_FREE1 0xfffffffffffffffful
2242 #define PC_FREE2 0x000000fffffffffful
2244 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2247 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2249 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2250 "Current number of pv entry chunks");
2251 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2252 "Current number of pv entry chunks allocated");
2253 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2254 "Current number of pv entry chunks frees");
2255 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2256 "Number of times tried to get a chunk page but failed.");
2258 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2259 static int pv_entry_spare;
2261 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2262 "Current number of pv entry frees");
2263 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2264 "Current number of pv entry allocs");
2265 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2266 "Current number of pv entries");
2267 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2268 "Current number of spare pv entries");
2272 * We are in a serious low memory condition. Resort to
2273 * drastic measures to free some pages so we can allocate
2274 * another pv entry chunk.
2276 * Returns NULL if PV entries were reclaimed from the specified pmap.
2278 * We do not, however, unmap 2mpages because subsequent accesses will
2279 * allocate per-page pv entries until repromotion occurs, thereby
2280 * exacerbating the shortage of free pv entries.
2283 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2285 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
2286 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
2287 struct md_page *pvh;
2289 pmap_t next_pmap, pmap;
2290 pt_entry_t *pte, tpte;
2294 struct spglist free;
2296 int bit, field, freed, lvl;
2297 static int active_reclaims = 0;
2299 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2300 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2305 bzero(&pc_marker_b, sizeof(pc_marker_b));
2306 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
2307 pc_marker = (struct pv_chunk *)&pc_marker_b;
2308 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
2310 mtx_lock(&pv_chunks_mutex);
2312 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
2313 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
2314 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
2315 SLIST_EMPTY(&free)) {
2316 next_pmap = pc->pc_pmap;
2317 if (next_pmap == NULL) {
2319 * The next chunk is a marker. However, it is
2320 * not our marker, so active_reclaims must be
2321 * > 1. Consequently, the next_chunk code
2322 * will not rotate the pv_chunks list.
2326 mtx_unlock(&pv_chunks_mutex);
2329 * A pv_chunk can only be removed from the pc_lru list
2330 * when both pv_chunks_mutex is owned and the
2331 * corresponding pmap is locked.
2333 if (pmap != next_pmap) {
2334 if (pmap != NULL && pmap != locked_pmap)
2337 /* Avoid deadlock and lock recursion. */
2338 if (pmap > locked_pmap) {
2339 RELEASE_PV_LIST_LOCK(lockp);
2341 mtx_lock(&pv_chunks_mutex);
2343 } else if (pmap != locked_pmap) {
2344 if (PMAP_TRYLOCK(pmap)) {
2345 mtx_lock(&pv_chunks_mutex);
2348 pmap = NULL; /* pmap is not locked */
2349 mtx_lock(&pv_chunks_mutex);
2350 pc = TAILQ_NEXT(pc_marker, pc_lru);
2352 pc->pc_pmap != next_pmap)
2360 * Destroy every non-wired, 4 KB page mapping in the chunk.
2363 for (field = 0; field < _NPCM; field++) {
2364 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2365 inuse != 0; inuse &= ~(1UL << bit)) {
2366 bit = ffsl(inuse) - 1;
2367 pv = &pc->pc_pventry[field * 64 + bit];
2369 pde = pmap_pde(pmap, va, &lvl);
2372 pte = pmap_l2_to_l3(pde, va);
2373 tpte = pmap_load(pte);
2374 if ((tpte & ATTR_SW_WIRED) != 0)
2376 tpte = pmap_load_clear(pte);
2377 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
2378 if (pmap_pte_dirty(pmap, tpte))
2380 if ((tpte & ATTR_AF) != 0) {
2381 pmap_invalidate_page(pmap, va);
2382 vm_page_aflag_set(m, PGA_REFERENCED);
2384 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2385 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2387 if (TAILQ_EMPTY(&m->md.pv_list) &&
2388 (m->flags & PG_FICTITIOUS) == 0) {
2389 pvh = page_to_pvh(m);
2390 if (TAILQ_EMPTY(&pvh->pv_list)) {
2391 vm_page_aflag_clear(m,
2395 pc->pc_map[field] |= 1UL << bit;
2396 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
2401 mtx_lock(&pv_chunks_mutex);
2404 /* Every freed mapping is for a 4 KB page. */
2405 pmap_resident_count_dec(pmap, freed);
2406 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2407 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2408 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2409 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2410 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2411 pc->pc_map[2] == PC_FREE2) {
2412 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2413 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2414 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2415 /* Entire chunk is free; return it. */
2416 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2417 dump_drop_page(m_pc->phys_addr);
2418 mtx_lock(&pv_chunks_mutex);
2419 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2422 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2423 mtx_lock(&pv_chunks_mutex);
2424 /* One freed pv entry in locked_pmap is sufficient. */
2425 if (pmap == locked_pmap)
2429 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2430 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2431 if (active_reclaims == 1 && pmap != NULL) {
2433 * Rotate the pv chunks list so that we do not
2434 * scan the same pv chunks that could not be
2435 * freed (because they contained a wired
2436 * and/or superpage mapping) on every
2437 * invocation of reclaim_pv_chunk().
2439 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2440 MPASS(pc->pc_pmap != NULL);
2441 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2442 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2446 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2447 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2449 mtx_unlock(&pv_chunks_mutex);
2450 if (pmap != NULL && pmap != locked_pmap)
2452 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2453 m_pc = SLIST_FIRST(&free);
2454 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2455 /* Recycle a freed page table page. */
2456 m_pc->ref_count = 1;
2458 vm_page_free_pages_toq(&free, true);
2463 * free the pv_entry back to the free list
2466 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2468 struct pv_chunk *pc;
2469 int idx, field, bit;
2471 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2472 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2473 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2474 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2475 pc = pv_to_chunk(pv);
2476 idx = pv - &pc->pc_pventry[0];
2479 pc->pc_map[field] |= 1ul << bit;
2480 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2481 pc->pc_map[2] != PC_FREE2) {
2482 /* 98% of the time, pc is already at the head of the list. */
2483 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2484 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2485 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2489 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2494 free_pv_chunk(struct pv_chunk *pc)
2498 mtx_lock(&pv_chunks_mutex);
2499 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2500 mtx_unlock(&pv_chunks_mutex);
2501 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2502 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2503 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2504 /* entire chunk is free, return it */
2505 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2506 dump_drop_page(m->phys_addr);
2507 vm_page_unwire_noq(m);
2512 * Returns a new PV entry, allocating a new PV chunk from the system when
2513 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2514 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2517 * The given PV list lock may be released.
2520 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2524 struct pv_chunk *pc;
2527 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2528 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2530 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2532 for (field = 0; field < _NPCM; field++) {
2533 if (pc->pc_map[field]) {
2534 bit = ffsl(pc->pc_map[field]) - 1;
2538 if (field < _NPCM) {
2539 pv = &pc->pc_pventry[field * 64 + bit];
2540 pc->pc_map[field] &= ~(1ul << bit);
2541 /* If this was the last item, move it to tail */
2542 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2543 pc->pc_map[2] == 0) {
2544 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2545 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2548 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2549 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2553 /* No free items, allocate another chunk */
2554 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2557 if (lockp == NULL) {
2558 PV_STAT(pc_chunk_tryfail++);
2561 m = reclaim_pv_chunk(pmap, lockp);
2565 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2566 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2567 dump_add_page(m->phys_addr);
2568 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2570 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2571 pc->pc_map[1] = PC_FREE1;
2572 pc->pc_map[2] = PC_FREE2;
2573 mtx_lock(&pv_chunks_mutex);
2574 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2575 mtx_unlock(&pv_chunks_mutex);
2576 pv = &pc->pc_pventry[0];
2577 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2578 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2579 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2584 * Ensure that the number of spare PV entries in the specified pmap meets or
2585 * exceeds the given count, "needed".
2587 * The given PV list lock may be released.
2590 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2592 struct pch new_tail;
2593 struct pv_chunk *pc;
2598 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2599 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2602 * Newly allocated PV chunks must be stored in a private list until
2603 * the required number of PV chunks have been allocated. Otherwise,
2604 * reclaim_pv_chunk() could recycle one of these chunks. In
2605 * contrast, these chunks must be added to the pmap upon allocation.
2607 TAILQ_INIT(&new_tail);
2610 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2611 bit_count((bitstr_t *)pc->pc_map, 0,
2612 sizeof(pc->pc_map) * NBBY, &free);
2616 if (avail >= needed)
2619 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2620 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2623 m = reclaim_pv_chunk(pmap, lockp);
2628 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2629 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2630 dump_add_page(m->phys_addr);
2631 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2633 pc->pc_map[0] = PC_FREE0;
2634 pc->pc_map[1] = PC_FREE1;
2635 pc->pc_map[2] = PC_FREE2;
2636 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2637 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2638 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2641 * The reclaim might have freed a chunk from the current pmap.
2642 * If that chunk contained available entries, we need to
2643 * re-count the number of available entries.
2648 if (!TAILQ_EMPTY(&new_tail)) {
2649 mtx_lock(&pv_chunks_mutex);
2650 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2651 mtx_unlock(&pv_chunks_mutex);
2656 * First find and then remove the pv entry for the specified pmap and virtual
2657 * address from the specified pv list. Returns the pv entry if found and NULL
2658 * otherwise. This operation can be performed on pv lists for either 4KB or
2659 * 2MB page mappings.
2661 static __inline pv_entry_t
2662 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2666 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2667 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2668 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2677 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2678 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2679 * entries for each of the 4KB page mappings.
2682 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2683 struct rwlock **lockp)
2685 struct md_page *pvh;
2686 struct pv_chunk *pc;
2688 vm_offset_t va_last;
2692 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2693 KASSERT((va & L2_OFFSET) == 0,
2694 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
2695 KASSERT((pa & L2_OFFSET) == 0,
2696 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2697 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2700 * Transfer the 2mpage's pv entry for this mapping to the first
2701 * page's pv list. Once this transfer begins, the pv list lock
2702 * must not be released until the last pv entry is reinstantiated.
2704 pvh = pa_to_pvh(pa);
2705 pv = pmap_pvh_remove(pvh, pmap, va);
2706 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2707 m = PHYS_TO_VM_PAGE(pa);
2708 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2710 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2711 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2712 va_last = va + L2_SIZE - PAGE_SIZE;
2714 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2715 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2716 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2717 for (field = 0; field < _NPCM; field++) {
2718 while (pc->pc_map[field]) {
2719 bit = ffsl(pc->pc_map[field]) - 1;
2720 pc->pc_map[field] &= ~(1ul << bit);
2721 pv = &pc->pc_pventry[field * 64 + bit];
2725 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2726 ("pmap_pv_demote_l2: page %p is not managed", m));
2727 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2733 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2734 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2737 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2738 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2739 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2741 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2742 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2746 * First find and then destroy the pv entry for the specified pmap and virtual
2747 * address. This operation can be performed on pv lists for either 4KB or 2MB
2751 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2755 pv = pmap_pvh_remove(pvh, pmap, va);
2756 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2757 free_pv_entry(pmap, pv);
2761 * Conditionally create the PV entry for a 4KB page mapping if the required
2762 * memory can be allocated without resorting to reclamation.
2765 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2766 struct rwlock **lockp)
2770 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2771 /* Pass NULL instead of the lock pointer to disable reclamation. */
2772 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2774 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2775 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2783 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2784 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2785 * false if the PV entry cannot be allocated without resorting to reclamation.
2788 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2789 struct rwlock **lockp)
2791 struct md_page *pvh;
2795 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2796 /* Pass NULL instead of the lock pointer to disable reclamation. */
2797 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2798 NULL : lockp)) == NULL)
2801 pa = l2e & ~ATTR_MASK;
2802 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2803 pvh = pa_to_pvh(pa);
2804 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2810 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2812 pt_entry_t newl2, oldl2;
2816 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2817 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2818 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2820 ml3 = pmap_remove_pt_page(pmap, va);
2822 panic("pmap_remove_kernel_l2: Missing pt page");
2824 ml3pa = VM_PAGE_TO_PHYS(ml3);
2825 newl2 = ml3pa | L2_TABLE;
2828 * If this page table page was unmapped by a promotion, then it
2829 * contains valid mappings. Zero it to invalidate those mappings.
2831 if (ml3->valid != 0)
2832 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2835 * Demote the mapping. The caller must have already invalidated the
2836 * mapping (i.e., the "break" in break-before-make).
2838 oldl2 = pmap_load_store(l2, newl2);
2839 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
2840 __func__, l2, oldl2));
2844 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
2847 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2848 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2850 struct md_page *pvh;
2852 vm_page_t m, ml3, mt;
2854 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2855 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2856 old_l2 = pmap_load_clear(l2);
2857 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2858 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2861 * Since a promotion must break the 4KB page mappings before making
2862 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2864 pmap_invalidate_page(pmap, sva);
2866 if (old_l2 & ATTR_SW_WIRED)
2867 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2868 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2869 if (old_l2 & ATTR_SW_MANAGED) {
2870 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2871 pvh = page_to_pvh(m);
2872 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2873 pmap_pvh_free(pvh, pmap, sva);
2874 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) {
2875 if (pmap_pte_dirty(pmap, old_l2))
2877 if (old_l2 & ATTR_AF)
2878 vm_page_aflag_set(mt, PGA_REFERENCED);
2879 if (TAILQ_EMPTY(&mt->md.pv_list) &&
2880 TAILQ_EMPTY(&pvh->pv_list))
2881 vm_page_aflag_clear(mt, PGA_WRITEABLE);
2884 if (pmap == kernel_pmap) {
2885 pmap_remove_kernel_l2(pmap, l2, sva);
2887 ml3 = pmap_remove_pt_page(pmap, sva);
2889 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
2890 ("pmap_remove_l2: l3 page not promoted"));
2891 pmap_resident_count_dec(pmap, 1);
2892 KASSERT(ml3->ref_count == NL3PG,
2893 ("pmap_remove_l2: l3 page ref count error"));
2895 pmap_add_delayed_free_list(ml3, free, FALSE);
2898 return (pmap_unuse_pt(pmap, sva, l1e, free));
2902 * pmap_remove_l3: do the things to unmap a page in a process
2905 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2906 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2908 struct md_page *pvh;
2912 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2913 old_l3 = pmap_load_clear(l3);
2914 pmap_invalidate_page(pmap, va);
2915 if (old_l3 & ATTR_SW_WIRED)
2916 pmap->pm_stats.wired_count -= 1;
2917 pmap_resident_count_dec(pmap, 1);
2918 if (old_l3 & ATTR_SW_MANAGED) {
2919 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2920 if (pmap_pte_dirty(pmap, old_l3))
2922 if (old_l3 & ATTR_AF)
2923 vm_page_aflag_set(m, PGA_REFERENCED);
2924 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2925 pmap_pvh_free(&m->md, pmap, va);
2926 if (TAILQ_EMPTY(&m->md.pv_list) &&
2927 (m->flags & PG_FICTITIOUS) == 0) {
2928 pvh = page_to_pvh(m);
2929 if (TAILQ_EMPTY(&pvh->pv_list))
2930 vm_page_aflag_clear(m, PGA_WRITEABLE);
2933 return (pmap_unuse_pt(pmap, va, l2e, free));
2937 * Remove the specified range of addresses from the L3 page table that is
2938 * identified by the given L2 entry.
2941 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
2942 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
2944 struct md_page *pvh;
2945 struct rwlock *new_lock;
2946 pt_entry_t *l3, old_l3;
2950 KASSERT(ADDR_IS_CANONICAL(sva),
2951 ("%s: Start address not in canonical form: %lx", __func__, sva));
2952 KASSERT(ADDR_IS_CANONICAL(eva) || eva == VM_MAX_USER_ADDRESS,
2953 ("%s: End address not in canonical form: %lx", __func__, eva));
2955 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2956 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
2957 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
2958 l3pg = !ADDR_IS_KERNEL(sva) ? PHYS_TO_VM_PAGE(l2e & ~ATTR_MASK) : NULL;
2960 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
2961 if (!pmap_l3_valid(pmap_load(l3))) {
2963 pmap_invalidate_range(pmap, va, sva);
2968 old_l3 = pmap_load_clear(l3);
2969 if ((old_l3 & ATTR_SW_WIRED) != 0)
2970 pmap->pm_stats.wired_count--;
2971 pmap_resident_count_dec(pmap, 1);
2972 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
2973 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2974 if (pmap_pte_dirty(pmap, old_l3))
2976 if ((old_l3 & ATTR_AF) != 0)
2977 vm_page_aflag_set(m, PGA_REFERENCED);
2978 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
2979 if (new_lock != *lockp) {
2980 if (*lockp != NULL) {
2982 * Pending TLB invalidations must be
2983 * performed before the PV list lock is
2984 * released. Otherwise, a concurrent
2985 * pmap_remove_all() on a physical page
2986 * could return while a stale TLB entry
2987 * still provides access to that page.
2990 pmap_invalidate_range(pmap, va,
2999 pmap_pvh_free(&m->md, pmap, sva);
3000 if (TAILQ_EMPTY(&m->md.pv_list) &&
3001 (m->flags & PG_FICTITIOUS) == 0) {
3002 pvh = page_to_pvh(m);
3003 if (TAILQ_EMPTY(&pvh->pv_list))
3004 vm_page_aflag_clear(m, PGA_WRITEABLE);
3009 if (l3pg != NULL && pmap_unwire_l3(pmap, sva, l3pg, free)) {
3015 pmap_invalidate_range(pmap, va, sva);
3019 * Remove the given range of addresses from the specified map.
3021 * It is assumed that the start and end are properly
3022 * rounded to the page size.
3025 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3027 struct rwlock *lock;
3028 vm_offset_t va_next;
3029 pd_entry_t *l0, *l1, *l2;
3030 pt_entry_t l3_paddr;
3031 struct spglist free;
3034 * Perform an unsynchronized read. This is, however, safe.
3036 if (pmap->pm_stats.resident_count == 0)
3044 for (; sva < eva; sva = va_next) {
3045 if (pmap->pm_stats.resident_count == 0)
3048 l0 = pmap_l0(pmap, sva);
3049 if (pmap_load(l0) == 0) {
3050 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3056 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3059 l1 = pmap_l0_to_l1(l0, sva);
3060 if (pmap_load(l1) == 0)
3062 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
3063 KASSERT(va_next <= eva,
3064 ("partial update of non-transparent 1G page "
3065 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
3066 pmap_load(l1), sva, eva, va_next));
3067 MPASS(pmap != kernel_pmap);
3068 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0);
3070 pmap_invalidate_page(pmap, sva);
3071 pmap_resident_count_dec(pmap, L1_SIZE / PAGE_SIZE);
3072 pmap_unuse_pt(pmap, sva, pmap_load(l0), &free);
3077 * Calculate index for next page table.
3079 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3083 l2 = pmap_l1_to_l2(l1, sva);
3087 l3_paddr = pmap_load(l2);
3089 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
3090 if (sva + L2_SIZE == va_next && eva >= va_next) {
3091 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
3094 } else if (pmap_demote_l2_locked(pmap, l2, sva,
3097 l3_paddr = pmap_load(l2);
3101 * Weed out invalid mappings.
3103 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
3107 * Limit our scan to either the end of the va represented
3108 * by the current page table page, or to the end of the
3109 * range being removed.
3114 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
3120 vm_page_free_pages_toq(&free, true);
3124 * Routine: pmap_remove_all
3126 * Removes this physical page from
3127 * all physical maps in which it resides.
3128 * Reflects back modify bits to the pager.
3131 * Original versions of this routine were very
3132 * inefficient because they iteratively called
3133 * pmap_remove (slow...)
3137 pmap_remove_all(vm_page_t m)
3139 struct md_page *pvh;
3142 struct rwlock *lock;
3143 pd_entry_t *pde, tpde;
3144 pt_entry_t *pte, tpte;
3146 struct spglist free;
3147 int lvl, pvh_gen, md_gen;
3149 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3150 ("pmap_remove_all: page %p is not managed", m));
3152 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3153 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
3156 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3158 if (!PMAP_TRYLOCK(pmap)) {
3159 pvh_gen = pvh->pv_gen;
3163 if (pvh_gen != pvh->pv_gen) {
3169 pte = pmap_pte(pmap, va, &lvl);
3170 KASSERT(pte != NULL,
3171 ("pmap_remove_all: no page table entry found"));
3173 ("pmap_remove_all: invalid pte level %d", lvl));
3174 pmap_demote_l2_locked(pmap, pte, va, &lock);
3177 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3179 PMAP_ASSERT_STAGE1(pmap);
3180 if (!PMAP_TRYLOCK(pmap)) {
3181 pvh_gen = pvh->pv_gen;
3182 md_gen = m->md.pv_gen;
3186 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
3191 pmap_resident_count_dec(pmap, 1);
3193 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3194 KASSERT(pde != NULL,
3195 ("pmap_remove_all: no page directory entry found"));
3197 ("pmap_remove_all: invalid pde level %d", lvl));
3198 tpde = pmap_load(pde);
3200 pte = pmap_l2_to_l3(pde, pv->pv_va);
3201 tpte = pmap_load_clear(pte);
3202 if (tpte & ATTR_SW_WIRED)
3203 pmap->pm_stats.wired_count--;
3204 if ((tpte & ATTR_AF) != 0) {
3205 pmap_invalidate_page(pmap, pv->pv_va);
3206 vm_page_aflag_set(m, PGA_REFERENCED);
3210 * Update the vm_page_t clean and reference bits.
3212 if (pmap_pte_dirty(pmap, tpte))
3214 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
3215 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3217 free_pv_entry(pmap, pv);
3220 vm_page_aflag_clear(m, PGA_WRITEABLE);
3222 vm_page_free_pages_toq(&free, true);
3226 * pmap_protect_l2: do the things to protect a 2MB page in a pmap
3229 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
3235 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3236 PMAP_ASSERT_STAGE1(pmap);
3237 KASSERT((sva & L2_OFFSET) == 0,
3238 ("pmap_protect_l2: sva is not 2mpage aligned"));
3239 old_l2 = pmap_load(l2);
3240 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
3241 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
3244 * Return if the L2 entry already has the desired access restrictions
3248 if ((old_l2 & mask) == nbits)
3252 * When a dirty read/write superpage mapping is write protected,
3253 * update the dirty field of each of the superpage's constituent 4KB
3256 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
3257 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3258 pmap_pte_dirty(pmap, old_l2)) {
3259 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
3260 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3264 if (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
3268 * Since a promotion must break the 4KB page mappings before making
3269 * the 2MB page mapping, a pmap_invalidate_page() suffices.
3271 pmap_invalidate_page(pmap, sva);
3275 * Set the physical protection on the
3276 * specified range of this map as requested.
3279 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3281 vm_offset_t va, va_next;
3282 pd_entry_t *l0, *l1, *l2;
3283 pt_entry_t *l3p, l3, mask, nbits;
3285 PMAP_ASSERT_STAGE1(pmap);
3286 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3287 if (prot == VM_PROT_NONE) {
3288 pmap_remove(pmap, sva, eva);
3293 if ((prot & VM_PROT_WRITE) == 0) {
3294 mask |= ATTR_S1_AP_RW_BIT | ATTR_SW_DBM;
3295 nbits |= ATTR_S1_AP(ATTR_S1_AP_RO);
3297 if ((prot & VM_PROT_EXECUTE) == 0) {
3299 nbits |= ATTR_S1_XN;
3305 for (; sva < eva; sva = va_next) {
3306 l0 = pmap_l0(pmap, sva);
3307 if (pmap_load(l0) == 0) {
3308 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3314 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3317 l1 = pmap_l0_to_l1(l0, sva);
3318 if (pmap_load(l1) == 0)
3320 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
3321 KASSERT(va_next <= eva,
3322 ("partial update of non-transparent 1G page "
3323 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
3324 pmap_load(l1), sva, eva, va_next));
3325 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0);
3326 if ((pmap_load(l1) & mask) != nbits) {
3327 pmap_store(l1, (pmap_load(l1) & ~mask) | nbits);
3328 pmap_invalidate_page(pmap, sva);
3333 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3337 l2 = pmap_l1_to_l2(l1, sva);
3338 if (pmap_load(l2) == 0)
3341 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3342 if (sva + L2_SIZE == va_next && eva >= va_next) {
3343 pmap_protect_l2(pmap, l2, sva, mask, nbits);
3345 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3348 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3349 ("pmap_protect: Invalid L2 entry after demotion"));
3355 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
3357 l3 = pmap_load(l3p);
3360 * Go to the next L3 entry if the current one is
3361 * invalid or already has the desired access
3362 * restrictions in place. (The latter case occurs
3363 * frequently. For example, in a "buildworld"
3364 * workload, almost 1 out of 4 L3 entries already
3365 * have the desired restrictions.)
3367 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
3368 if (va != va_next) {
3369 pmap_invalidate_range(pmap, va, sva);
3376 * When a dirty read/write mapping is write protected,
3377 * update the page's dirty field.
3379 if ((l3 & ATTR_SW_MANAGED) != 0 &&
3380 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3381 pmap_pte_dirty(pmap, l3))
3382 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK));
3384 if (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) | nbits))
3390 pmap_invalidate_range(pmap, va, sva);
3396 * Inserts the specified page table page into the specified pmap's collection
3397 * of idle page table pages. Each of a pmap's page table pages is responsible
3398 * for mapping a distinct range of virtual addresses. The pmap's collection is
3399 * ordered by this virtual address range.
3401 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3404 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3407 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3408 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3409 return (vm_radix_insert(&pmap->pm_root, mpte));
3413 * Removes the page table page mapping the specified virtual address from the
3414 * specified pmap's collection of idle page table pages, and returns it.
3415 * Otherwise, returns NULL if there is no page table page corresponding to the
3416 * specified virtual address.
3418 static __inline vm_page_t
3419 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3422 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3423 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
3427 * Performs a break-before-make update of a pmap entry. This is needed when
3428 * either promoting or demoting pages to ensure the TLB doesn't get into an
3429 * inconsistent state.
3432 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
3433 vm_offset_t va, vm_size_t size)
3437 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3440 * Ensure we don't get switched out with the page table in an
3441 * inconsistent state. We also need to ensure no interrupts fire
3442 * as they may make use of an address we are about to invalidate.
3444 intr = intr_disable();
3447 * Clear the old mapping's valid bit, but leave the rest of the entry
3448 * unchanged, so that a lockless, concurrent pmap_kextract() can still
3449 * lookup the physical address.
3451 pmap_clear_bits(pte, ATTR_DESCR_VALID);
3452 pmap_invalidate_range(pmap, va, va + size);
3454 /* Create the new mapping */
3455 pmap_store(pte, newpte);
3461 #if VM_NRESERVLEVEL > 0
3463 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3464 * replace the many pv entries for the 4KB page mappings by a single pv entry
3465 * for the 2MB page mapping.
3468 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3469 struct rwlock **lockp)
3471 struct md_page *pvh;
3473 vm_offset_t va_last;
3476 KASSERT((pa & L2_OFFSET) == 0,
3477 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
3478 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3481 * Transfer the first page's pv entry for this mapping to the 2mpage's
3482 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3483 * a transfer avoids the possibility that get_pv_entry() calls
3484 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3485 * mappings that is being promoted.
3487 m = PHYS_TO_VM_PAGE(pa);
3488 va = va & ~L2_OFFSET;
3489 pv = pmap_pvh_remove(&m->md, pmap, va);
3490 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
3491 pvh = page_to_pvh(m);
3492 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3494 /* Free the remaining NPTEPG - 1 pv entries. */
3495 va_last = va + L2_SIZE - PAGE_SIZE;
3499 pmap_pvh_free(&m->md, pmap, va);
3500 } while (va < va_last);
3504 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3505 * single level 2 table entry to a single 2MB page mapping. For promotion
3506 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3507 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3508 * identical characteristics.
3511 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
3512 struct rwlock **lockp)
3514 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
3518 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3519 PMAP_ASSERT_STAGE1(pmap);
3521 sva = va & ~L2_OFFSET;
3522 firstl3 = pmap_l2_to_l3(l2, sva);
3523 newl2 = pmap_load(firstl3);
3526 if (((newl2 & (~ATTR_MASK | ATTR_AF)) & L2_OFFSET) != ATTR_AF) {
3527 atomic_add_long(&pmap_l2_p_failures, 1);
3528 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3529 " in pmap %p", va, pmap);
3533 if ((newl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3534 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3536 * When the mapping is clean, i.e., ATTR_S1_AP_RO is set,
3537 * ATTR_SW_DBM can be cleared without a TLB invalidation.
3539 if (!atomic_fcmpset_64(firstl3, &newl2, newl2 & ~ATTR_SW_DBM))
3541 newl2 &= ~ATTR_SW_DBM;
3544 pa = newl2 + L2_SIZE - PAGE_SIZE;
3545 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
3546 oldl3 = pmap_load(l3);
3548 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3549 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3551 * When the mapping is clean, i.e., ATTR_S1_AP_RO is
3552 * set, ATTR_SW_DBM can be cleared without a TLB
3555 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
3558 oldl3 &= ~ATTR_SW_DBM;
3561 atomic_add_long(&pmap_l2_p_failures, 1);
3562 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3563 " in pmap %p", va, pmap);
3570 * Save the page table page in its current state until the L2
3571 * mapping the superpage is demoted by pmap_demote_l2() or
3572 * destroyed by pmap_remove_l3().
3574 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3575 KASSERT(mpte >= vm_page_array &&
3576 mpte < &vm_page_array[vm_page_array_size],
3577 ("pmap_promote_l2: page table page is out of range"));
3578 KASSERT(mpte->pindex == pmap_l2_pindex(va),
3579 ("pmap_promote_l2: page table page's pindex is wrong"));
3580 if (pmap_insert_pt_page(pmap, mpte, true)) {
3581 atomic_add_long(&pmap_l2_p_failures, 1);
3583 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
3588 if ((newl2 & ATTR_SW_MANAGED) != 0)
3589 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
3591 newl2 &= ~ATTR_DESCR_MASK;
3594 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
3596 atomic_add_long(&pmap_l2_promotions, 1);
3597 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
3600 #endif /* VM_NRESERVLEVEL > 0 */
3603 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags,
3606 pd_entry_t *l0p, *l1p, *l2p, origpte;
3609 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3610 KASSERT(psind > 0 && psind < MAXPAGESIZES,
3611 ("psind %d unexpected", psind));
3612 KASSERT(((newpte & ~ATTR_MASK) & (pagesizes[psind] - 1)) == 0,
3613 ("unaligned phys address %#lx newpte %#lx psind %d",
3614 (newpte & ~ATTR_MASK), newpte, psind));
3618 l0p = pmap_l0(pmap, va);
3619 if ((pmap_load(l0p) & ATTR_DESCR_VALID) == 0) {
3620 mp = _pmap_alloc_l3(pmap, pmap_l0_pindex(va), NULL);
3622 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
3623 return (KERN_RESOURCE_SHORTAGE);
3629 l1p = pmap_l0_to_l1(l0p, va);
3630 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va));
3631 origpte = pmap_load(l1p);
3633 l1p = pmap_l0_to_l1(l0p, va);
3634 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va));
3635 origpte = pmap_load(l1p);
3636 if ((origpte & ATTR_DESCR_VALID) == 0) {
3637 mp = PHYS_TO_VM_PAGE(pmap_load(l0p) &
3642 KASSERT((origpte & ATTR_DESCR_VALID) == 0 ||
3643 ((origpte & ATTR_DESCR_MASK) == L1_BLOCK &&
3644 (origpte & ~ATTR_MASK) == (newpte & ~ATTR_MASK)),
3645 ("va %#lx changing 1G phys page l1 %#lx newpte %#lx",
3646 va, origpte, newpte));
3647 pmap_store(l1p, newpte);
3648 } else /* (psind == 1) */ {
3649 l2p = pmap_l2(pmap, va);
3651 mp = _pmap_alloc_l3(pmap, pmap_l1_pindex(va), NULL);
3653 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
3654 return (KERN_RESOURCE_SHORTAGE);
3660 l2p = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
3661 l2p = &l2p[pmap_l2_index(va)];
3662 origpte = pmap_load(l2p);
3664 l1p = pmap_l1(pmap, va);
3665 origpte = pmap_load(l2p);
3666 if ((origpte & ATTR_DESCR_VALID) == 0) {
3667 mp = PHYS_TO_VM_PAGE(pmap_load(l1p) &
3672 KASSERT((origpte & ATTR_DESCR_VALID) == 0 ||
3673 ((origpte & ATTR_DESCR_MASK) == L2_BLOCK &&
3674 (origpte & ~ATTR_MASK) == (newpte & ~ATTR_MASK)),
3675 ("va %#lx changing 2M phys page l2 %#lx newpte %#lx",
3676 va, origpte, newpte));
3677 pmap_store(l2p, newpte);
3681 if ((origpte & ATTR_DESCR_VALID) == 0)
3682 pmap_resident_count_inc(pmap, pagesizes[psind] / PAGE_SIZE);
3683 if ((newpte & ATTR_SW_WIRED) != 0 && (origpte & ATTR_SW_WIRED) == 0)
3684 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE;
3685 else if ((newpte & ATTR_SW_WIRED) == 0 &&
3686 (origpte & ATTR_SW_WIRED) != 0)
3687 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE;
3689 return (KERN_SUCCESS);
3693 * Add a single SMMU entry. This function does not sleep.
3696 pmap_senter(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3697 vm_prot_t prot, u_int flags)
3700 pt_entry_t new_l3, orig_l3;
3706 PMAP_ASSERT_STAGE1(pmap);
3707 KASSERT(va < VM_MAXUSER_ADDRESS, ("wrong address space"));
3709 va = trunc_page(va);
3710 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT |
3711 ATTR_S1_IDX(VM_MEMATTR_DEVICE) | L3_PAGE);
3712 if ((prot & VM_PROT_WRITE) == 0)
3713 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
3714 new_l3 |= ATTR_S1_XN; /* Execute never. */
3715 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER);
3716 new_l3 |= ATTR_S1_nG; /* Non global. */
3718 CTR2(KTR_PMAP, "pmap_senter: %.16lx -> %.16lx", va, pa);
3723 * In the case that a page table page is not
3724 * resident, we are creating it here.
3727 pde = pmap_pde(pmap, va, &lvl);
3728 if (pde != NULL && lvl == 2) {
3729 l3 = pmap_l2_to_l3(pde, va);
3731 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va), NULL);
3733 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3734 rv = KERN_RESOURCE_SHORTAGE;
3740 orig_l3 = pmap_load(l3);
3741 KASSERT(!pmap_l3_valid(orig_l3), ("l3 is valid"));
3744 pmap_store(l3, new_l3);
3745 pmap_resident_count_inc(pmap, 1);
3756 * Remove a single SMMU entry.
3759 pmap_sremove(pmap_t pmap, vm_offset_t va)
3767 pte = pmap_pte(pmap, va, &lvl);
3769 ("Invalid SMMU pagetable level: %d != 3", lvl));
3772 pmap_resident_count_dec(pmap, 1);
3784 * Remove all the allocated L1, L2 pages from SMMU pmap.
3785 * All the L3 entires must be cleared in advance, otherwise
3786 * this function panics.
3789 pmap_sremove_pages(pmap_t pmap)
3791 pd_entry_t l0e, *l1, l1e, *l2, l2e;
3792 pt_entry_t *l3, l3e;
3793 vm_page_t m, m0, m1;
3802 for (sva = VM_MINUSER_ADDRESS, i = pmap_l0_index(sva);
3803 (i < Ln_ENTRIES && sva < VM_MAXUSER_ADDRESS); i++) {
3804 l0e = pmap->pm_l0[i];
3805 if ((l0e & ATTR_DESCR_VALID) == 0) {
3809 pa0 = l0e & ~ATTR_MASK;
3810 m0 = PHYS_TO_VM_PAGE(pa0);
3811 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa0);
3813 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
3815 if ((l1e & ATTR_DESCR_VALID) == 0) {
3819 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
3823 pa1 = l1e & ~ATTR_MASK;
3824 m1 = PHYS_TO_VM_PAGE(pa1);
3825 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa1);
3827 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
3829 if ((l2e & ATTR_DESCR_VALID) == 0) {
3833 pa = l2e & ~ATTR_MASK;
3834 m = PHYS_TO_VM_PAGE(pa);
3835 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
3837 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
3838 l++, sva += L3_SIZE) {
3840 if ((l3e & ATTR_DESCR_VALID) == 0)
3842 panic("%s: l3e found for va %jx\n",
3846 vm_page_unwire_noq(m1);
3847 vm_page_unwire_noq(m);
3848 pmap_resident_count_dec(pmap, 1);
3853 vm_page_unwire_noq(m0);
3854 pmap_resident_count_dec(pmap, 1);
3859 pmap_resident_count_dec(pmap, 1);
3861 pmap_clear(&pmap->pm_l0[i]);
3864 KASSERT(pmap->pm_stats.resident_count == 0,
3865 ("Invalid resident count %jd", pmap->pm_stats.resident_count));
3871 * Insert the given physical page (p) at
3872 * the specified virtual address (v) in the
3873 * target physical map with the protection requested.
3875 * If specified, the page will be wired down, meaning
3876 * that the related pte can not be reclaimed.
3878 * NB: This is the only routine which MAY NOT lazy-evaluate
3879 * or lose information. That is, this routine must actually
3880 * insert this page into the given map NOW.
3883 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3884 u_int flags, int8_t psind)
3886 struct rwlock *lock;
3888 pt_entry_t new_l3, orig_l3;
3889 pt_entry_t *l2, *l3;
3896 KASSERT(ADDR_IS_CANONICAL(va),
3897 ("%s: Address not in canonical form: %lx", __func__, va));
3899 va = trunc_page(va);
3900 if ((m->oflags & VPO_UNMANAGED) == 0)
3901 VM_PAGE_OBJECT_BUSY_ASSERT(m);
3902 pa = VM_PAGE_TO_PHYS(m);
3903 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | L3_PAGE);
3904 new_l3 |= pmap_pte_memattr(pmap, m->md.pv_memattr);
3905 new_l3 |= pmap_pte_prot(pmap, prot);
3907 if ((flags & PMAP_ENTER_WIRED) != 0)
3908 new_l3 |= ATTR_SW_WIRED;
3909 if (pmap->pm_stage == PM_STAGE1) {
3910 if (!ADDR_IS_KERNEL(va))
3911 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
3913 new_l3 |= ATTR_S1_UXN;
3914 if (pmap != kernel_pmap)
3915 new_l3 |= ATTR_S1_nG;
3918 * Clear the access flag on executable mappings, this will be
3919 * set later when the page is accessed. The fault handler is
3920 * required to invalidate the I-cache.
3922 * TODO: Switch to the valid flag to allow hardware management
3923 * of the access flag. Much of the pmap code assumes the
3924 * valid flag is set and fails to destroy the old page tables
3925 * correctly if it is clear.
3927 if (prot & VM_PROT_EXECUTE)
3930 if ((m->oflags & VPO_UNMANAGED) == 0) {
3931 new_l3 |= ATTR_SW_MANAGED;
3932 if ((prot & VM_PROT_WRITE) != 0) {
3933 new_l3 |= ATTR_SW_DBM;
3934 if ((flags & VM_PROT_WRITE) == 0) {
3935 if (pmap->pm_stage == PM_STAGE1)
3936 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
3939 ~ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
3944 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3948 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) {
3949 KASSERT((m->oflags & VPO_UNMANAGED) != 0,
3950 ("managed largepage va %#lx flags %#x", va, flags));
3954 else /* (psind == 1) */
3956 rv = pmap_enter_largepage(pmap, va, new_l3, flags, psind);
3960 /* Assert the required virtual and physical alignment. */
3961 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3962 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3963 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3970 * In the case that a page table page is not
3971 * resident, we are creating it here.
3974 pde = pmap_pde(pmap, va, &lvl);
3975 if (pde != NULL && lvl == 2) {
3976 l3 = pmap_l2_to_l3(pde, va);
3977 if (!ADDR_IS_KERNEL(va) && mpte == NULL) {
3978 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3982 } else if (pde != NULL && lvl == 1) {
3983 l2 = pmap_l1_to_l2(pde, va);
3984 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3985 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
3986 l3 = &l3[pmap_l3_index(va)];
3987 if (!ADDR_IS_KERNEL(va)) {
3988 mpte = PHYS_TO_VM_PAGE(
3989 pmap_load(l2) & ~ATTR_MASK);
3994 /* We need to allocate an L3 table. */
3996 if (!ADDR_IS_KERNEL(va)) {
3997 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
4000 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
4001 * to handle the possibility that a superpage mapping for "va"
4002 * was created while we slept.
4004 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
4005 nosleep ? NULL : &lock);
4006 if (mpte == NULL && nosleep) {
4007 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
4008 rv = KERN_RESOURCE_SHORTAGE;
4013 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
4016 orig_l3 = pmap_load(l3);
4017 opa = orig_l3 & ~ATTR_MASK;
4021 * Is the specified virtual address already mapped?
4023 if (pmap_l3_valid(orig_l3)) {
4025 * Only allow adding new entries on stage 2 tables for now.
4026 * This simplifies cache invalidation as we may need to call
4027 * into EL2 to perform such actions.
4029 PMAP_ASSERT_STAGE1(pmap);
4031 * Wiring change, just update stats. We don't worry about
4032 * wiring PT pages as they remain resident as long as there
4033 * are valid mappings in them. Hence, if a user page is wired,
4034 * the PT page will be also.
4036 if ((flags & PMAP_ENTER_WIRED) != 0 &&
4037 (orig_l3 & ATTR_SW_WIRED) == 0)
4038 pmap->pm_stats.wired_count++;
4039 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
4040 (orig_l3 & ATTR_SW_WIRED) != 0)
4041 pmap->pm_stats.wired_count--;
4044 * Remove the extra PT page reference.
4048 KASSERT(mpte->ref_count > 0,
4049 ("pmap_enter: missing reference to page table page,"
4054 * Has the physical page changed?
4058 * No, might be a protection or wiring change.
4060 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
4061 (new_l3 & ATTR_SW_DBM) != 0)
4062 vm_page_aflag_set(m, PGA_WRITEABLE);
4067 * The physical page has changed. Temporarily invalidate
4070 orig_l3 = pmap_load_clear(l3);
4071 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
4072 ("pmap_enter: unexpected pa update for %#lx", va));
4073 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
4074 om = PHYS_TO_VM_PAGE(opa);
4077 * The pmap lock is sufficient to synchronize with
4078 * concurrent calls to pmap_page_test_mappings() and
4079 * pmap_ts_referenced().
4081 if (pmap_pte_dirty(pmap, orig_l3))
4083 if ((orig_l3 & ATTR_AF) != 0) {
4084 pmap_invalidate_page(pmap, va);
4085 vm_page_aflag_set(om, PGA_REFERENCED);
4087 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4088 pv = pmap_pvh_remove(&om->md, pmap, va);
4089 if ((m->oflags & VPO_UNMANAGED) != 0)
4090 free_pv_entry(pmap, pv);
4091 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
4092 TAILQ_EMPTY(&om->md.pv_list) &&
4093 ((om->flags & PG_FICTITIOUS) != 0 ||
4094 TAILQ_EMPTY(&page_to_pvh(om)->pv_list)))
4095 vm_page_aflag_clear(om, PGA_WRITEABLE);
4097 KASSERT((orig_l3 & ATTR_AF) != 0,
4098 ("pmap_enter: unmanaged mapping lacks ATTR_AF"));
4099 pmap_invalidate_page(pmap, va);
4104 * Increment the counters.
4106 if ((new_l3 & ATTR_SW_WIRED) != 0)
4107 pmap->pm_stats.wired_count++;
4108 pmap_resident_count_inc(pmap, 1);
4111 * Enter on the PV list if part of our managed memory.
4113 if ((m->oflags & VPO_UNMANAGED) == 0) {
4115 pv = get_pv_entry(pmap, &lock);
4118 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4119 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4121 if ((new_l3 & ATTR_SW_DBM) != 0)
4122 vm_page_aflag_set(m, PGA_WRITEABLE);
4126 if (pmap->pm_stage == PM_STAGE1) {
4128 * Sync icache if exec permission and attribute
4129 * VM_MEMATTR_WRITE_BACK is set. Do it now, before the mapping
4130 * is stored and made valid for hardware table walk. If done
4131 * later, then other can access this page before caches are
4132 * properly synced. Don't do it for kernel memory which is
4133 * mapped with exec permission even if the memory isn't going
4134 * to hold executable code. The only time when icache sync is
4135 * needed is after kernel module is loaded and the relocation
4136 * info is processed. And it's done in elf_cpu_load_file().
4138 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4139 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
4140 (opa != pa || (orig_l3 & ATTR_S1_XN))) {
4141 PMAP_ASSERT_STAGE1(pmap);
4142 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4145 cpu_dcache_wb_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4149 * Update the L3 entry
4151 if (pmap_l3_valid(orig_l3)) {
4152 PMAP_ASSERT_STAGE1(pmap);
4153 KASSERT(opa == pa, ("pmap_enter: invalid update"));
4154 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
4155 /* same PA, different attributes */
4156 orig_l3 = pmap_load_store(l3, new_l3);
4157 pmap_invalidate_page(pmap, va);
4158 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
4159 pmap_pte_dirty(pmap, orig_l3))
4164 * This can happens if multiple threads simultaneously
4165 * access not yet mapped page. This bad for performance
4166 * since this can cause full demotion-NOP-promotion
4168 * Another possible reasons are:
4169 * - VM and pmap memory layout are diverged
4170 * - tlb flush is missing somewhere and CPU doesn't see
4173 CTR4(KTR_PMAP, "%s: already mapped page - "
4174 "pmap %p va 0x%#lx pte 0x%lx",
4175 __func__, pmap, va, new_l3);
4179 pmap_store(l3, new_l3);
4183 #if VM_NRESERVLEVEL > 0
4185 * Try to promote from level 3 pages to a level 2 superpage. This
4186 * currently only works on stage 1 pmaps as pmap_promote_l2 looks at
4187 * stage 1 specific fields and performs a break-before-make sequence
4188 * that is incorrect a stage 2 pmap.
4190 if ((mpte == NULL || mpte->ref_count == NL3PG) &&
4191 pmap_ps_enabled(pmap) && pmap->pm_stage == PM_STAGE1 &&
4192 (m->flags & PG_FICTITIOUS) == 0 &&
4193 vm_reserv_level_iffullpop(m) == 0) {
4194 pmap_promote_l2(pmap, pde, va, &lock);
4207 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
4208 * if successful. Returns false if (1) a page table page cannot be allocated
4209 * without sleeping, (2) a mapping already exists at the specified virtual
4210 * address, or (3) a PV entry cannot be allocated without reclaiming another
4214 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4215 struct rwlock **lockp)
4219 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4220 PMAP_ASSERT_STAGE1(pmap);
4221 KASSERT(ADDR_IS_CANONICAL(va),
4222 ("%s: Address not in canonical form: %lx", __func__, va));
4224 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
4225 ATTR_S1_IDX(m->md.pv_memattr) | ATTR_S1_AP(ATTR_S1_AP_RO) |
4227 if ((m->oflags & VPO_UNMANAGED) == 0) {
4228 new_l2 |= ATTR_SW_MANAGED;
4231 if ((prot & VM_PROT_EXECUTE) == 0 ||
4232 m->md.pv_memattr == VM_MEMATTR_DEVICE)
4233 new_l2 |= ATTR_S1_XN;
4234 if (!ADDR_IS_KERNEL(va))
4235 new_l2 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4237 new_l2 |= ATTR_S1_UXN;
4238 if (pmap != kernel_pmap)
4239 new_l2 |= ATTR_S1_nG;
4240 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
4241 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
4246 * Returns true if every page table entry in the specified page table is
4250 pmap_every_pte_zero(vm_paddr_t pa)
4252 pt_entry_t *pt_end, *pte;
4254 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
4255 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
4256 for (pt_end = pte + Ln_ENTRIES; pte < pt_end; pte++) {
4264 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
4265 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
4266 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
4267 * a mapping already exists at the specified virtual address. Returns
4268 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
4269 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
4270 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
4272 * The parameter "m" is only used when creating a managed, writeable mapping.
4275 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
4276 vm_page_t m, struct rwlock **lockp)
4278 struct spglist free;
4279 pd_entry_t *l2, old_l2;
4282 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4283 KASSERT(ADDR_IS_CANONICAL(va),
4284 ("%s: Address not in canonical form: %lx", __func__, va));
4286 if ((l2 = pmap_alloc_l2(pmap, va, &l2pg, (flags &
4287 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
4288 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
4290 return (KERN_RESOURCE_SHORTAGE);
4294 * If there are existing mappings, either abort or remove them.
4296 if ((old_l2 = pmap_load(l2)) != 0) {
4297 KASSERT(l2pg == NULL || l2pg->ref_count > 1,
4298 ("pmap_enter_l2: l2pg's ref count is too low"));
4299 if ((flags & PMAP_ENTER_NOREPLACE) != 0 &&
4300 (!ADDR_IS_KERNEL(va) ||
4301 (old_l2 & ATTR_DESCR_MASK) == L2_BLOCK ||
4302 !pmap_every_pte_zero(old_l2 & ~ATTR_MASK))) {
4305 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx"
4306 " in pmap %p", va, pmap);
4307 return (KERN_FAILURE);
4310 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
4311 (void)pmap_remove_l2(pmap, l2, va,
4312 pmap_load(pmap_l1(pmap, va)), &free, lockp);
4314 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
4316 if (!ADDR_IS_KERNEL(va)) {
4317 vm_page_free_pages_toq(&free, true);
4318 KASSERT(pmap_load(l2) == 0,
4319 ("pmap_enter_l2: non-zero L2 entry %p", l2));
4321 KASSERT(SLIST_EMPTY(&free),
4322 ("pmap_enter_l2: freed kernel page table page"));
4325 * Both pmap_remove_l2() and pmap_remove_l3_range()
4326 * will leave the kernel page table page zero filled.
4327 * Nonetheless, the TLB could have an intermediate
4328 * entry for the kernel page table page.
4330 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
4331 if (pmap_insert_pt_page(pmap, mt, false))
4332 panic("pmap_enter_l2: trie insert failed");
4334 pmap_invalidate_page(pmap, va);
4338 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
4340 * Abort this mapping if its PV entry could not be created.
4342 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
4344 pmap_abort_ptp(pmap, va, l2pg);
4346 "pmap_enter_l2: failure for va %#lx in pmap %p",
4348 return (KERN_RESOURCE_SHORTAGE);
4350 if ((new_l2 & ATTR_SW_DBM) != 0)
4351 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4352 vm_page_aflag_set(mt, PGA_WRITEABLE);
4356 * Increment counters.
4358 if ((new_l2 & ATTR_SW_WIRED) != 0)
4359 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
4360 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
4363 * Map the superpage.
4365 pmap_store(l2, new_l2);
4368 atomic_add_long(&pmap_l2_mappings, 1);
4369 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
4372 return (KERN_SUCCESS);
4376 * Maps a sequence of resident pages belonging to the same object.
4377 * The sequence begins with the given page m_start. This page is
4378 * mapped at the given virtual address start. Each subsequent page is
4379 * mapped at a virtual address that is offset from start by the same
4380 * amount as the page is offset from m_start within the object. The
4381 * last page in the sequence is the page with the largest offset from
4382 * m_start that can be mapped at a virtual address less than the given
4383 * virtual address end. Not every virtual page between start and end
4384 * is mapped; only those for which a resident page exists with the
4385 * corresponding offset from m_start are mapped.
4388 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4389 vm_page_t m_start, vm_prot_t prot)
4391 struct rwlock *lock;
4394 vm_pindex_t diff, psize;
4396 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4398 psize = atop(end - start);
4403 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4404 va = start + ptoa(diff);
4405 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
4406 m->psind == 1 && pmap_ps_enabled(pmap) &&
4407 pmap_enter_2mpage(pmap, va, m, prot, &lock))
4408 m = &m[L2_SIZE / PAGE_SIZE - 1];
4410 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
4412 m = TAILQ_NEXT(m, listq);
4420 * this code makes some *MAJOR* assumptions:
4421 * 1. Current pmap & pmap exists.
4424 * 4. No page table pages.
4425 * but is *MUCH* faster than pmap_enter...
4429 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4431 struct rwlock *lock;
4435 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
4442 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4443 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
4446 pt_entry_t *l2, *l3, l3_val;
4450 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4451 (m->oflags & VPO_UNMANAGED) != 0,
4452 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4453 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4454 PMAP_ASSERT_STAGE1(pmap);
4455 KASSERT(ADDR_IS_CANONICAL(va),
4456 ("%s: Address not in canonical form: %lx", __func__, va));
4458 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
4460 * In the case that a page table page is not
4461 * resident, we are creating it here.
4463 if (!ADDR_IS_KERNEL(va)) {
4464 vm_pindex_t l2pindex;
4467 * Calculate pagetable page index
4469 l2pindex = pmap_l2_pindex(va);
4470 if (mpte && (mpte->pindex == l2pindex)) {
4476 pde = pmap_pde(pmap, va, &lvl);
4479 * If the page table page is mapped, we just increment
4480 * the hold count, and activate it. Otherwise, we
4481 * attempt to allocate a page table page. If this
4482 * attempt fails, we don't retry. Instead, we give up.
4485 l2 = pmap_l1_to_l2(pde, va);
4486 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
4490 if (lvl == 2 && pmap_load(pde) != 0) {
4492 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
4496 * Pass NULL instead of the PV list lock
4497 * pointer, because we don't intend to sleep.
4499 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
4504 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4505 l3 = &l3[pmap_l3_index(va)];
4508 pde = pmap_pde(kernel_pmap, va, &lvl);
4509 KASSERT(pde != NULL,
4510 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
4513 ("pmap_enter_quick_locked: Invalid level %d", lvl));
4514 l3 = pmap_l2_to_l3(pde, va);
4518 * Abort if a mapping already exists.
4520 if (pmap_load(l3) != 0) {
4527 * Enter on the PV list if part of our managed memory.
4529 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4530 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4532 pmap_abort_ptp(pmap, va, mpte);
4537 * Increment counters
4539 pmap_resident_count_inc(pmap, 1);
4541 pa = VM_PAGE_TO_PHYS(m);
4542 l3_val = pa | ATTR_DEFAULT | ATTR_S1_IDX(m->md.pv_memattr) |
4543 ATTR_S1_AP(ATTR_S1_AP_RO) | L3_PAGE;
4544 if ((prot & VM_PROT_EXECUTE) == 0 ||
4545 m->md.pv_memattr == VM_MEMATTR_DEVICE)
4546 l3_val |= ATTR_S1_XN;
4547 if (!ADDR_IS_KERNEL(va))
4548 l3_val |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4550 l3_val |= ATTR_S1_UXN;
4551 if (pmap != kernel_pmap)
4552 l3_val |= ATTR_S1_nG;
4555 * Now validate mapping with RO protection
4557 if ((m->oflags & VPO_UNMANAGED) == 0) {
4558 l3_val |= ATTR_SW_MANAGED;
4562 /* Sync icache before the mapping is stored to PTE */
4563 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4564 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
4565 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4567 pmap_store(l3, l3_val);
4574 * This code maps large physical mmap regions into the
4575 * processor address space. Note that some shortcuts
4576 * are taken, but the code works.
4579 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4580 vm_pindex_t pindex, vm_size_t size)
4583 VM_OBJECT_ASSERT_WLOCKED(object);
4584 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4585 ("pmap_object_init_pt: non-device object"));
4589 * Clear the wired attribute from the mappings for the specified range of
4590 * addresses in the given pmap. Every valid mapping within that range
4591 * must have the wired attribute set. In contrast, invalid mappings
4592 * cannot have the wired attribute set, so they are ignored.
4594 * The wired attribute of the page table entry is not a hardware feature,
4595 * so there is no need to invalidate any TLB entries.
4598 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4600 vm_offset_t va_next;
4601 pd_entry_t *l0, *l1, *l2;
4605 for (; sva < eva; sva = va_next) {
4606 l0 = pmap_l0(pmap, sva);
4607 if (pmap_load(l0) == 0) {
4608 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
4614 l1 = pmap_l0_to_l1(l0, sva);
4615 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
4618 if (pmap_load(l1) == 0)
4621 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
4622 KASSERT(va_next <= eva,
4623 ("partial update of non-transparent 1G page "
4624 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
4625 pmap_load(l1), sva, eva, va_next));
4626 MPASS(pmap != kernel_pmap);
4627 MPASS((pmap_load(l1) & (ATTR_SW_MANAGED |
4628 ATTR_SW_WIRED)) == ATTR_SW_WIRED);
4629 pmap_clear_bits(l1, ATTR_SW_WIRED);
4630 pmap->pm_stats.wired_count -= L1_SIZE / PAGE_SIZE;
4634 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
4638 l2 = pmap_l1_to_l2(l1, sva);
4639 if (pmap_load(l2) == 0)
4642 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
4643 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
4644 panic("pmap_unwire: l2 %#jx is missing "
4645 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
4648 * Are we unwiring the entire large page? If not,
4649 * demote the mapping and fall through.
4651 if (sva + L2_SIZE == va_next && eva >= va_next) {
4652 pmap_clear_bits(l2, ATTR_SW_WIRED);
4653 pmap->pm_stats.wired_count -= L2_SIZE /
4656 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
4657 panic("pmap_unwire: demotion failed");
4659 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
4660 ("pmap_unwire: Invalid l2 entry after demotion"));
4664 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
4666 if (pmap_load(l3) == 0)
4668 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
4669 panic("pmap_unwire: l3 %#jx is missing "
4670 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
4673 * ATTR_SW_WIRED must be cleared atomically. Although
4674 * the pmap lock synchronizes access to ATTR_SW_WIRED,
4675 * the System MMU may write to the entry concurrently.
4677 pmap_clear_bits(l3, ATTR_SW_WIRED);
4678 pmap->pm_stats.wired_count--;
4685 * Copy the range specified by src_addr/len
4686 * from the source map to the range dst_addr/len
4687 * in the destination map.
4689 * This routine is only advisory and need not do anything.
4691 * Because the executable mappings created by this routine are copied,
4692 * it should not have to flush the instruction cache.
4695 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4696 vm_offset_t src_addr)
4698 struct rwlock *lock;
4699 pd_entry_t *l0, *l1, *l2, srcptepaddr;
4700 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
4701 vm_offset_t addr, end_addr, va_next;
4702 vm_page_t dst_m, dstmpte, srcmpte;
4704 PMAP_ASSERT_STAGE1(dst_pmap);
4705 PMAP_ASSERT_STAGE1(src_pmap);
4707 if (dst_addr != src_addr)
4709 end_addr = src_addr + len;
4711 if (dst_pmap < src_pmap) {
4712 PMAP_LOCK(dst_pmap);
4713 PMAP_LOCK(src_pmap);
4715 PMAP_LOCK(src_pmap);
4716 PMAP_LOCK(dst_pmap);
4718 for (addr = src_addr; addr < end_addr; addr = va_next) {
4719 l0 = pmap_l0(src_pmap, addr);
4720 if (pmap_load(l0) == 0) {
4721 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
4727 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
4730 l1 = pmap_l0_to_l1(l0, addr);
4731 if (pmap_load(l1) == 0)
4733 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
4734 KASSERT(va_next <= end_addr,
4735 ("partial update of non-transparent 1G page "
4736 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx",
4737 pmap_load(l1), addr, end_addr, va_next));
4738 srcptepaddr = pmap_load(l1);
4739 l1 = pmap_l1(dst_pmap, addr);
4741 if (_pmap_alloc_l3(dst_pmap,
4742 pmap_l0_pindex(addr), NULL) == NULL)
4744 l1 = pmap_l1(dst_pmap, addr);
4746 l0 = pmap_l0(dst_pmap, addr);
4747 dst_m = PHYS_TO_VM_PAGE(pmap_load(l0) &
4751 KASSERT(pmap_load(l1) == 0,
4752 ("1G mapping present in dst pmap "
4753 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx",
4754 pmap_load(l1), addr, end_addr, va_next));
4755 pmap_store(l1, srcptepaddr & ~ATTR_SW_WIRED);
4756 pmap_resident_count_inc(dst_pmap, L1_SIZE / PAGE_SIZE);
4760 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
4763 l2 = pmap_l1_to_l2(l1, addr);
4764 srcptepaddr = pmap_load(l2);
4765 if (srcptepaddr == 0)
4767 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
4768 if ((addr & L2_OFFSET) != 0 ||
4769 addr + L2_SIZE > end_addr)
4771 l2 = pmap_alloc_l2(dst_pmap, addr, &dst_m, NULL);
4774 if (pmap_load(l2) == 0 &&
4775 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
4776 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
4777 PMAP_ENTER_NORECLAIM, &lock))) {
4778 mask = ATTR_SW_WIRED;
4779 pmap_store(l2, srcptepaddr & ~mask);
4780 pmap_resident_count_inc(dst_pmap, L2_SIZE /
4782 atomic_add_long(&pmap_l2_mappings, 1);
4784 pmap_abort_ptp(dst_pmap, addr, dst_m);
4787 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
4788 ("pmap_copy: invalid L2 entry"));
4789 srcptepaddr &= ~ATTR_MASK;
4790 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4791 KASSERT(srcmpte->ref_count > 0,
4792 ("pmap_copy: source page table page is unused"));
4793 if (va_next > end_addr)
4795 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4796 src_pte = &src_pte[pmap_l3_index(addr)];
4798 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
4799 ptetemp = pmap_load(src_pte);
4802 * We only virtual copy managed pages.
4804 if ((ptetemp & ATTR_SW_MANAGED) == 0)
4807 if (dstmpte != NULL) {
4808 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
4809 ("dstmpte pindex/addr mismatch"));
4810 dstmpte->ref_count++;
4811 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
4814 dst_pte = (pt_entry_t *)
4815 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4816 dst_pte = &dst_pte[pmap_l3_index(addr)];
4817 if (pmap_load(dst_pte) == 0 &&
4818 pmap_try_insert_pv_entry(dst_pmap, addr,
4819 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
4821 * Clear the wired, modified, and accessed
4822 * (referenced) bits during the copy.
4824 mask = ATTR_AF | ATTR_SW_WIRED;
4826 if ((ptetemp & ATTR_SW_DBM) != 0)
4827 nbits |= ATTR_S1_AP_RW_BIT;
4828 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
4829 pmap_resident_count_inc(dst_pmap, 1);
4831 pmap_abort_ptp(dst_pmap, addr, dstmpte);
4834 /* Have we copied all of the valid mappings? */
4835 if (dstmpte->ref_count >= srcmpte->ref_count)
4841 * XXX This barrier may not be needed because the destination pmap is
4848 PMAP_UNLOCK(src_pmap);
4849 PMAP_UNLOCK(dst_pmap);
4853 * pmap_zero_page zeros the specified hardware page by mapping
4854 * the page into KVM and using bzero to clear its contents.
4857 pmap_zero_page(vm_page_t m)
4859 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4861 pagezero((void *)va);
4865 * pmap_zero_page_area zeros the specified hardware page by mapping
4866 * the page into KVM and using bzero to clear its contents.
4868 * off and size may not cover an area beyond a single hardware page.
4871 pmap_zero_page_area(vm_page_t m, int off, int size)
4873 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4875 if (off == 0 && size == PAGE_SIZE)
4876 pagezero((void *)va);
4878 bzero((char *)va + off, size);
4882 * pmap_copy_page copies the specified (machine independent)
4883 * page by mapping the page into virtual memory and using
4884 * bcopy to copy the page, one machine dependent page at a
4888 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4890 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4891 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4893 pagecopy((void *)src, (void *)dst);
4896 int unmapped_buf_allowed = 1;
4899 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4900 vm_offset_t b_offset, int xfersize)
4904 vm_paddr_t p_a, p_b;
4905 vm_offset_t a_pg_offset, b_pg_offset;
4908 while (xfersize > 0) {
4909 a_pg_offset = a_offset & PAGE_MASK;
4910 m_a = ma[a_offset >> PAGE_SHIFT];
4911 p_a = m_a->phys_addr;
4912 b_pg_offset = b_offset & PAGE_MASK;
4913 m_b = mb[b_offset >> PAGE_SHIFT];
4914 p_b = m_b->phys_addr;
4915 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4916 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4917 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
4918 panic("!DMAP a %lx", p_a);
4920 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
4922 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
4923 panic("!DMAP b %lx", p_b);
4925 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
4927 bcopy(a_cp, b_cp, cnt);
4935 pmap_quick_enter_page(vm_page_t m)
4938 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
4942 pmap_quick_remove_page(vm_offset_t addr)
4947 * Returns true if the pmap's pv is one of the first
4948 * 16 pvs linked to from this page. This count may
4949 * be changed upwards or downwards in the future; it
4950 * is only necessary that true be returned for a small
4951 * subset of pmaps for proper page aging.
4954 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4956 struct md_page *pvh;
4957 struct rwlock *lock;
4962 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4963 ("pmap_page_exists_quick: page %p is not managed", m));
4965 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4967 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4968 if (PV_PMAP(pv) == pmap) {
4976 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4977 pvh = page_to_pvh(m);
4978 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4979 if (PV_PMAP(pv) == pmap) {
4993 * pmap_page_wired_mappings:
4995 * Return the number of managed mappings to the given physical page
4999 pmap_page_wired_mappings(vm_page_t m)
5001 struct rwlock *lock;
5002 struct md_page *pvh;
5006 int count, lvl, md_gen, pvh_gen;
5008 if ((m->oflags & VPO_UNMANAGED) != 0)
5010 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5014 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5016 if (!PMAP_TRYLOCK(pmap)) {
5017 md_gen = m->md.pv_gen;
5021 if (md_gen != m->md.pv_gen) {
5026 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5027 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
5031 if ((m->flags & PG_FICTITIOUS) == 0) {
5032 pvh = page_to_pvh(m);
5033 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5035 if (!PMAP_TRYLOCK(pmap)) {
5036 md_gen = m->md.pv_gen;
5037 pvh_gen = pvh->pv_gen;
5041 if (md_gen != m->md.pv_gen ||
5042 pvh_gen != pvh->pv_gen) {
5047 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5049 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
5059 * Returns true if the given page is mapped individually or as part of
5060 * a 2mpage. Otherwise, returns false.
5063 pmap_page_is_mapped(vm_page_t m)
5065 struct rwlock *lock;
5068 if ((m->oflags & VPO_UNMANAGED) != 0)
5070 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5072 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5073 ((m->flags & PG_FICTITIOUS) == 0 &&
5074 !TAILQ_EMPTY(&page_to_pvh(m)->pv_list));
5080 * Destroy all managed, non-wired mappings in the given user-space
5081 * pmap. This pmap cannot be active on any processor besides the
5084 * This function cannot be applied to the kernel pmap. Moreover, it
5085 * is not intended for general use. It is only to be used during
5086 * process termination. Consequently, it can be implemented in ways
5087 * that make it faster than pmap_remove(). First, it can more quickly
5088 * destroy mappings by iterating over the pmap's collection of PV
5089 * entries, rather than searching the page table. Second, it doesn't
5090 * have to test and clear the page table entries atomically, because
5091 * no processor is currently accessing the user address space. In
5092 * particular, a page table entry's dirty bit won't change state once
5093 * this function starts.
5096 pmap_remove_pages(pmap_t pmap)
5099 pt_entry_t *pte, tpte;
5100 struct spglist free;
5101 vm_page_t m, ml3, mt;
5103 struct md_page *pvh;
5104 struct pv_chunk *pc, *npc;
5105 struct rwlock *lock;
5107 uint64_t inuse, bitmask;
5108 int allfree, field, freed, idx, lvl;
5115 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5118 for (field = 0; field < _NPCM; field++) {
5119 inuse = ~pc->pc_map[field] & pc_freemask[field];
5120 while (inuse != 0) {
5121 bit = ffsl(inuse) - 1;
5122 bitmask = 1UL << bit;
5123 idx = field * 64 + bit;
5124 pv = &pc->pc_pventry[idx];
5127 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5128 KASSERT(pde != NULL,
5129 ("Attempting to remove an unmapped page"));
5133 pte = pmap_l1_to_l2(pde, pv->pv_va);
5134 tpte = pmap_load(pte);
5135 KASSERT((tpte & ATTR_DESCR_MASK) ==
5137 ("Attempting to remove an invalid "
5138 "block: %lx", tpte));
5141 pte = pmap_l2_to_l3(pde, pv->pv_va);
5142 tpte = pmap_load(pte);
5143 KASSERT((tpte & ATTR_DESCR_MASK) ==
5145 ("Attempting to remove an invalid "
5146 "page: %lx", tpte));
5150 "Invalid page directory level: %d",
5155 * We cannot remove wired pages from a process' mapping at this time
5157 if (tpte & ATTR_SW_WIRED) {
5162 pa = tpte & ~ATTR_MASK;
5164 m = PHYS_TO_VM_PAGE(pa);
5165 KASSERT(m->phys_addr == pa,
5166 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
5167 m, (uintmax_t)m->phys_addr,
5170 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
5171 m < &vm_page_array[vm_page_array_size],
5172 ("pmap_remove_pages: bad pte %#jx",
5176 * Because this pmap is not active on other
5177 * processors, the dirty bit cannot have
5178 * changed state since we last loaded pte.
5183 * Update the vm_page_t clean/reference bits.
5185 if (pmap_pte_dirty(pmap, tpte)) {
5188 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
5197 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
5200 pc->pc_map[field] |= bitmask;
5203 pmap_resident_count_dec(pmap,
5204 L2_SIZE / PAGE_SIZE);
5205 pvh = page_to_pvh(m);
5206 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
5208 if (TAILQ_EMPTY(&pvh->pv_list)) {
5209 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
5210 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
5211 TAILQ_EMPTY(&mt->md.pv_list))
5212 vm_page_aflag_clear(mt, PGA_WRITEABLE);
5214 ml3 = pmap_remove_pt_page(pmap,
5217 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
5218 ("pmap_remove_pages: l3 page not promoted"));
5219 pmap_resident_count_dec(pmap,1);
5220 KASSERT(ml3->ref_count == NL3PG,
5221 ("pmap_remove_pages: l3 page ref count error"));
5223 pmap_add_delayed_free_list(ml3,
5228 pmap_resident_count_dec(pmap, 1);
5229 TAILQ_REMOVE(&m->md.pv_list, pv,
5232 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
5233 TAILQ_EMPTY(&m->md.pv_list) &&
5234 (m->flags & PG_FICTITIOUS) == 0) {
5235 pvh = page_to_pvh(m);
5236 if (TAILQ_EMPTY(&pvh->pv_list))
5237 vm_page_aflag_clear(m,
5242 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
5247 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
5248 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
5249 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
5251 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5257 pmap_invalidate_all(pmap);
5259 vm_page_free_pages_toq(&free, true);
5263 * This is used to check if a page has been accessed or modified.
5266 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
5268 struct rwlock *lock;
5270 struct md_page *pvh;
5271 pt_entry_t *pte, mask, value;
5273 int lvl, md_gen, pvh_gen;
5277 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5280 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5282 PMAP_ASSERT_STAGE1(pmap);
5283 if (!PMAP_TRYLOCK(pmap)) {
5284 md_gen = m->md.pv_gen;
5288 if (md_gen != m->md.pv_gen) {
5293 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5295 ("pmap_page_test_mappings: Invalid level %d", lvl));
5299 mask |= ATTR_S1_AP_RW_BIT;
5300 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
5303 mask |= ATTR_AF | ATTR_DESCR_MASK;
5304 value |= ATTR_AF | L3_PAGE;
5306 rv = (pmap_load(pte) & mask) == value;
5311 if ((m->flags & PG_FICTITIOUS) == 0) {
5312 pvh = page_to_pvh(m);
5313 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5315 PMAP_ASSERT_STAGE1(pmap);
5316 if (!PMAP_TRYLOCK(pmap)) {
5317 md_gen = m->md.pv_gen;
5318 pvh_gen = pvh->pv_gen;
5322 if (md_gen != m->md.pv_gen ||
5323 pvh_gen != pvh->pv_gen) {
5328 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5330 ("pmap_page_test_mappings: Invalid level %d", lvl));
5334 mask |= ATTR_S1_AP_RW_BIT;
5335 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
5338 mask |= ATTR_AF | ATTR_DESCR_MASK;
5339 value |= ATTR_AF | L2_BLOCK;
5341 rv = (pmap_load(pte) & mask) == value;
5355 * Return whether or not the specified physical page was modified
5356 * in any physical maps.
5359 pmap_is_modified(vm_page_t m)
5362 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5363 ("pmap_is_modified: page %p is not managed", m));
5366 * If the page is not busied then this check is racy.
5368 if (!pmap_page_is_write_mapped(m))
5370 return (pmap_page_test_mappings(m, FALSE, TRUE));
5374 * pmap_is_prefaultable:
5376 * Return whether or not the specified virtual address is eligible
5380 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5388 pte = pmap_pte(pmap, addr, &lvl);
5389 if (pte != NULL && pmap_load(pte) != 0) {
5397 * pmap_is_referenced:
5399 * Return whether or not the specified physical page was referenced
5400 * in any physical maps.
5403 pmap_is_referenced(vm_page_t m)
5406 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5407 ("pmap_is_referenced: page %p is not managed", m));
5408 return (pmap_page_test_mappings(m, TRUE, FALSE));
5412 * Clear the write and modified bits in each of the given page's mappings.
5415 pmap_remove_write(vm_page_t m)
5417 struct md_page *pvh;
5419 struct rwlock *lock;
5420 pv_entry_t next_pv, pv;
5421 pt_entry_t oldpte, *pte;
5423 int lvl, md_gen, pvh_gen;
5425 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5426 ("pmap_remove_write: page %p is not managed", m));
5427 vm_page_assert_busied(m);
5429 if (!pmap_page_is_write_mapped(m))
5431 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5432 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
5435 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5437 PMAP_ASSERT_STAGE1(pmap);
5438 if (!PMAP_TRYLOCK(pmap)) {
5439 pvh_gen = pvh->pv_gen;
5443 if (pvh_gen != pvh->pv_gen) {
5449 pte = pmap_pte(pmap, va, &lvl);
5450 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
5451 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
5452 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5453 ("inconsistent pv lock %p %p for page %p",
5454 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5457 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5459 PMAP_ASSERT_STAGE1(pmap);
5460 if (!PMAP_TRYLOCK(pmap)) {
5461 pvh_gen = pvh->pv_gen;
5462 md_gen = m->md.pv_gen;
5466 if (pvh_gen != pvh->pv_gen ||
5467 md_gen != m->md.pv_gen) {
5472 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5473 oldpte = pmap_load(pte);
5474 if ((oldpte & ATTR_SW_DBM) != 0) {
5475 while (!atomic_fcmpset_64(pte, &oldpte,
5476 (oldpte | ATTR_S1_AP_RW_BIT) & ~ATTR_SW_DBM))
5478 if ((oldpte & ATTR_S1_AP_RW_BIT) ==
5479 ATTR_S1_AP(ATTR_S1_AP_RW))
5481 pmap_invalidate_page(pmap, pv->pv_va);
5486 vm_page_aflag_clear(m, PGA_WRITEABLE);
5490 * pmap_ts_referenced:
5492 * Return a count of reference bits for a page, clearing those bits.
5493 * It is not necessary for every reference bit to be cleared, but it
5494 * is necessary that 0 only be returned when there are truly no
5495 * reference bits set.
5497 * As an optimization, update the page's dirty field if a modified bit is
5498 * found while counting reference bits. This opportunistic update can be
5499 * performed at low cost and can eliminate the need for some future calls
5500 * to pmap_is_modified(). However, since this function stops after
5501 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5502 * dirty pages. Those dirty pages will only be detected by a future call
5503 * to pmap_is_modified().
5506 pmap_ts_referenced(vm_page_t m)
5508 struct md_page *pvh;
5511 struct rwlock *lock;
5512 pd_entry_t *pde, tpde;
5513 pt_entry_t *pte, tpte;
5516 int cleared, lvl, md_gen, not_cleared, pvh_gen;
5517 struct spglist free;
5519 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5520 ("pmap_ts_referenced: page %p is not managed", m));
5523 pa = VM_PAGE_TO_PHYS(m);
5524 lock = PHYS_TO_PV_LIST_LOCK(pa);
5525 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
5529 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5530 goto small_mappings;
5536 if (!PMAP_TRYLOCK(pmap)) {
5537 pvh_gen = pvh->pv_gen;
5541 if (pvh_gen != pvh->pv_gen) {
5547 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5548 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
5550 ("pmap_ts_referenced: invalid pde level %d", lvl));
5551 tpde = pmap_load(pde);
5552 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
5553 ("pmap_ts_referenced: found an invalid l1 table"));
5554 pte = pmap_l1_to_l2(pde, pv->pv_va);
5555 tpte = pmap_load(pte);
5556 if (pmap_pte_dirty(pmap, tpte)) {
5558 * Although "tpte" is mapping a 2MB page, because
5559 * this function is called at a 4KB page granularity,
5560 * we only update the 4KB page under test.
5565 if ((tpte & ATTR_AF) != 0) {
5567 * Since this reference bit is shared by 512 4KB pages,
5568 * it should not be cleared every time it is tested.
5569 * Apply a simple "hash" function on the physical page
5570 * number, the virtual superpage number, and the pmap
5571 * address to select one 4KB page out of the 512 on
5572 * which testing the reference bit will result in
5573 * clearing that reference bit. This function is
5574 * designed to avoid the selection of the same 4KB page
5575 * for every 2MB page mapping.
5577 * On demotion, a mapping that hasn't been referenced
5578 * is simply destroyed. To avoid the possibility of a
5579 * subsequent page fault on a demoted wired mapping,
5580 * always leave its reference bit set. Moreover,
5581 * since the superpage is wired, the current state of
5582 * its reference bit won't affect page replacement.
5584 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
5585 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
5586 (tpte & ATTR_SW_WIRED) == 0) {
5587 pmap_clear_bits(pte, ATTR_AF);
5588 pmap_invalidate_page(pmap, pv->pv_va);
5594 /* Rotate the PV list if it has more than one entry. */
5595 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5596 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5597 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5600 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5602 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5604 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5611 if (!PMAP_TRYLOCK(pmap)) {
5612 pvh_gen = pvh->pv_gen;
5613 md_gen = m->md.pv_gen;
5617 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5622 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5623 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
5625 ("pmap_ts_referenced: invalid pde level %d", lvl));
5626 tpde = pmap_load(pde);
5627 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
5628 ("pmap_ts_referenced: found an invalid l2 table"));
5629 pte = pmap_l2_to_l3(pde, pv->pv_va);
5630 tpte = pmap_load(pte);
5631 if (pmap_pte_dirty(pmap, tpte))
5633 if ((tpte & ATTR_AF) != 0) {
5634 if ((tpte & ATTR_SW_WIRED) == 0) {
5635 pmap_clear_bits(pte, ATTR_AF);
5636 pmap_invalidate_page(pmap, pv->pv_va);
5642 /* Rotate the PV list if it has more than one entry. */
5643 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5644 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5645 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5648 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
5649 not_cleared < PMAP_TS_REFERENCED_MAX);
5652 vm_page_free_pages_toq(&free, true);
5653 return (cleared + not_cleared);
5657 * Apply the given advice to the specified range of addresses within the
5658 * given pmap. Depending on the advice, clear the referenced and/or
5659 * modified flags in each mapping and set the mapped page's dirty field.
5662 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5664 struct rwlock *lock;
5665 vm_offset_t va, va_next;
5667 pd_entry_t *l0, *l1, *l2, oldl2;
5668 pt_entry_t *l3, oldl3;
5670 PMAP_ASSERT_STAGE1(pmap);
5672 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5676 for (; sva < eva; sva = va_next) {
5677 l0 = pmap_l0(pmap, sva);
5678 if (pmap_load(l0) == 0) {
5679 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
5685 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
5688 l1 = pmap_l0_to_l1(l0, sva);
5689 if (pmap_load(l1) == 0)
5691 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
5692 KASSERT(va_next <= eva,
5693 ("partial update of non-transparent 1G page "
5694 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
5695 pmap_load(l1), sva, eva, va_next));
5699 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
5702 l2 = pmap_l1_to_l2(l1, sva);
5703 oldl2 = pmap_load(l2);
5706 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
5707 if ((oldl2 & ATTR_SW_MANAGED) == 0)
5710 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
5715 * The 2MB page mapping was destroyed.
5721 * Unless the page mappings are wired, remove the
5722 * mapping to a single page so that a subsequent
5723 * access may repromote. Choosing the last page
5724 * within the address range [sva, min(va_next, eva))
5725 * generally results in more repromotions. Since the
5726 * underlying page table page is fully populated, this
5727 * removal never frees a page table page.
5729 if ((oldl2 & ATTR_SW_WIRED) == 0) {
5735 ("pmap_advise: no address gap"));
5736 l3 = pmap_l2_to_l3(l2, va);
5737 KASSERT(pmap_load(l3) != 0,
5738 ("pmap_advise: invalid PTE"));
5739 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
5745 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
5746 ("pmap_advise: invalid L2 entry after demotion"));
5750 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
5752 oldl3 = pmap_load(l3);
5753 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
5754 (ATTR_SW_MANAGED | L3_PAGE))
5756 else if (pmap_pte_dirty(pmap, oldl3)) {
5757 if (advice == MADV_DONTNEED) {
5759 * Future calls to pmap_is_modified()
5760 * can be avoided by making the page
5763 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK);
5766 while (!atomic_fcmpset_long(l3, &oldl3,
5767 (oldl3 & ~ATTR_AF) |
5768 ATTR_S1_AP(ATTR_S1_AP_RO)))
5770 } else if ((oldl3 & ATTR_AF) != 0)
5771 pmap_clear_bits(l3, ATTR_AF);
5778 if (va != va_next) {
5779 pmap_invalidate_range(pmap, va, sva);
5784 pmap_invalidate_range(pmap, va, sva);
5790 * Clear the modify bits on the specified physical page.
5793 pmap_clear_modify(vm_page_t m)
5795 struct md_page *pvh;
5796 struct rwlock *lock;
5798 pv_entry_t next_pv, pv;
5799 pd_entry_t *l2, oldl2;
5800 pt_entry_t *l3, oldl3;
5802 int md_gen, pvh_gen;
5804 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5805 ("pmap_clear_modify: page %p is not managed", m));
5806 vm_page_assert_busied(m);
5808 if (!pmap_page_is_write_mapped(m))
5810 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
5811 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5814 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5816 PMAP_ASSERT_STAGE1(pmap);
5817 if (!PMAP_TRYLOCK(pmap)) {
5818 pvh_gen = pvh->pv_gen;
5822 if (pvh_gen != pvh->pv_gen) {
5828 l2 = pmap_l2(pmap, va);
5829 oldl2 = pmap_load(l2);
5830 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */
5831 if ((oldl2 & ATTR_SW_DBM) != 0 &&
5832 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
5833 (oldl2 & ATTR_SW_WIRED) == 0) {
5835 * Write protect the mapping to a single page so that
5836 * a subsequent write access may repromote.
5838 va += VM_PAGE_TO_PHYS(m) - (oldl2 & ~ATTR_MASK);
5839 l3 = pmap_l2_to_l3(l2, va);
5840 oldl3 = pmap_load(l3);
5841 while (!atomic_fcmpset_long(l3, &oldl3,
5842 (oldl3 & ~ATTR_SW_DBM) | ATTR_S1_AP(ATTR_S1_AP_RO)))
5845 pmap_invalidate_page(pmap, va);
5849 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5851 PMAP_ASSERT_STAGE1(pmap);
5852 if (!PMAP_TRYLOCK(pmap)) {
5853 md_gen = m->md.pv_gen;
5854 pvh_gen = pvh->pv_gen;
5858 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5863 l2 = pmap_l2(pmap, pv->pv_va);
5864 l3 = pmap_l2_to_l3(l2, pv->pv_va);
5865 oldl3 = pmap_load(l3);
5866 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM){
5867 pmap_set_bits(l3, ATTR_S1_AP(ATTR_S1_AP_RO));
5868 pmap_invalidate_page(pmap, pv->pv_va);
5876 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5878 struct pmap_preinit_mapping *ppim;
5879 vm_offset_t va, offset;
5882 int i, lvl, l2_blocks, free_l2_count, start_idx;
5884 if (!vm_initialized) {
5886 * No L3 ptables so map entire L2 blocks where start VA is:
5887 * preinit_map_va + start_idx * L2_SIZE
5888 * There may be duplicate mappings (multiple VA -> same PA) but
5889 * ARM64 dcache is always PIPT so that's acceptable.
5894 /* Calculate how many L2 blocks are needed for the mapping */
5895 l2_blocks = (roundup2(pa + size, L2_SIZE) -
5896 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
5898 offset = pa & L2_OFFSET;
5900 if (preinit_map_va == 0)
5903 /* Map 2MiB L2 blocks from reserved VA space */
5907 /* Find enough free contiguous VA space */
5908 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5909 ppim = pmap_preinit_mapping + i;
5910 if (free_l2_count > 0 && ppim->pa != 0) {
5911 /* Not enough space here */
5917 if (ppim->pa == 0) {
5919 if (start_idx == -1)
5922 if (free_l2_count == l2_blocks)
5926 if (free_l2_count != l2_blocks)
5927 panic("%s: too many preinit mappings", __func__);
5929 va = preinit_map_va + (start_idx * L2_SIZE);
5930 for (i = start_idx; i < start_idx + l2_blocks; i++) {
5931 /* Mark entries as allocated */
5932 ppim = pmap_preinit_mapping + i;
5934 ppim->va = va + offset;
5939 pa = rounddown2(pa, L2_SIZE);
5940 for (i = 0; i < l2_blocks; i++) {
5941 pde = pmap_pde(kernel_pmap, va, &lvl);
5942 KASSERT(pde != NULL,
5943 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
5946 ("pmap_mapbios: Invalid level %d", lvl));
5948 /* Insert L2_BLOCK */
5949 l2 = pmap_l1_to_l2(pde, va);
5951 pa | ATTR_DEFAULT | ATTR_S1_XN |
5952 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
5957 pmap_invalidate_all(kernel_pmap);
5959 va = preinit_map_va + (start_idx * L2_SIZE);
5962 /* kva_alloc may be used to map the pages */
5963 offset = pa & PAGE_MASK;
5964 size = round_page(offset + size);
5966 va = kva_alloc(size);
5968 panic("%s: Couldn't allocate KVA", __func__);
5970 pde = pmap_pde(kernel_pmap, va, &lvl);
5971 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
5973 /* L3 table is linked */
5974 va = trunc_page(va);
5975 pa = trunc_page(pa);
5976 pmap_kenter(va, size, pa, memory_mapping_mode(pa));
5979 return ((void *)(va + offset));
5983 pmap_unmapbios(vm_offset_t va, vm_size_t size)
5985 struct pmap_preinit_mapping *ppim;
5986 vm_offset_t offset, tmpsize, va_trunc;
5989 int i, lvl, l2_blocks, block;
5993 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
5994 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
5996 /* Remove preinit mapping */
5997 preinit_map = false;
5999 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6000 ppim = pmap_preinit_mapping + i;
6001 if (ppim->va == va) {
6002 KASSERT(ppim->size == size,
6003 ("pmap_unmapbios: size mismatch"));
6008 offset = block * L2_SIZE;
6009 va_trunc = rounddown2(va, L2_SIZE) + offset;
6011 /* Remove L2_BLOCK */
6012 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
6013 KASSERT(pde != NULL,
6014 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
6016 l2 = pmap_l1_to_l2(pde, va_trunc);
6019 if (block == (l2_blocks - 1))
6025 pmap_invalidate_all(kernel_pmap);
6029 /* Unmap the pages reserved with kva_alloc. */
6030 if (vm_initialized) {
6031 offset = va & PAGE_MASK;
6032 size = round_page(offset + size);
6033 va = trunc_page(va);
6035 pde = pmap_pde(kernel_pmap, va, &lvl);
6036 KASSERT(pde != NULL,
6037 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
6038 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
6040 /* Unmap and invalidate the pages */
6041 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6042 pmap_kremove(va + tmpsize);
6049 * Sets the memory attribute for the specified page.
6052 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
6055 m->md.pv_memattr = ma;
6058 * If "m" is a normal page, update its direct mapping. This update
6059 * can be relied upon to perform any cache operations that are
6060 * required for data coherence.
6062 if ((m->flags & PG_FICTITIOUS) == 0 &&
6063 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
6064 m->md.pv_memattr) != 0)
6065 panic("memory attribute change on the direct map failed");
6069 * Changes the specified virtual address range's memory type to that given by
6070 * the parameter "mode". The specified virtual address range must be
6071 * completely contained within either the direct map or the kernel map. If
6072 * the virtual address range is contained within the kernel map, then the
6073 * memory type for each of the corresponding ranges of the direct map is also
6074 * changed. (The corresponding ranges of the direct map are those ranges that
6075 * map the same physical pages as the specified virtual address range.) These
6076 * changes to the direct map are necessary because Intel describes the
6077 * behavior of their processors as "undefined" if two or more mappings to the
6078 * same physical page have different memory types.
6080 * Returns zero if the change completed successfully, and either EINVAL or
6081 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
6082 * of the virtual address range was not mapped, and ENOMEM is returned if
6083 * there was insufficient memory available to complete the change. In the
6084 * latter case, the memory type may have been changed on some part of the
6085 * virtual address range or the direct map.
6088 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
6092 PMAP_LOCK(kernel_pmap);
6093 error = pmap_change_attr_locked(va, size, mode);
6094 PMAP_UNLOCK(kernel_pmap);
6099 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
6101 vm_offset_t base, offset, tmpva;
6102 pt_entry_t l3, *pte, *newpte;
6105 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
6106 base = trunc_page(va);
6107 offset = va & PAGE_MASK;
6108 size = round_page(offset + size);
6110 if (!VIRT_IN_DMAP(base) &&
6111 !(base >= VM_MIN_KERNEL_ADDRESS && base < VM_MAX_KERNEL_ADDRESS))
6114 for (tmpva = base; tmpva < base + size; ) {
6115 pte = pmap_pte(kernel_pmap, tmpva, &lvl);
6119 if ((pmap_load(pte) & ATTR_S1_IDX_MASK) == ATTR_S1_IDX(mode)) {
6121 * We already have the correct attribute,
6122 * ignore this entry.
6126 panic("Invalid DMAP table level: %d\n", lvl);
6128 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
6131 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
6139 * Split the entry to an level 3 table, then
6140 * set the new attribute.
6144 panic("Invalid DMAP table level: %d\n", lvl);
6146 newpte = pmap_demote_l1(kernel_pmap, pte,
6147 tmpva & ~L1_OFFSET);
6150 pte = pmap_l1_to_l2(pte, tmpva);
6152 newpte = pmap_demote_l2(kernel_pmap, pte,
6156 pte = pmap_l2_to_l3(pte, tmpva);
6158 /* Update the entry */
6159 l3 = pmap_load(pte);
6160 l3 &= ~ATTR_S1_IDX_MASK;
6161 l3 |= ATTR_S1_IDX(mode);
6162 if (mode == VM_MEMATTR_DEVICE)
6165 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
6169 * If moving to a non-cacheable entry flush
6172 if (mode == VM_MEMATTR_UNCACHEABLE)
6173 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
6185 * Create an L2 table to map all addresses within an L1 mapping.
6188 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
6190 pt_entry_t *l2, newl2, oldl1;
6192 vm_paddr_t l2phys, phys;
6196 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6197 oldl1 = pmap_load(l1);
6198 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
6199 ("pmap_demote_l1: Demoting a non-block entry"));
6200 KASSERT((va & L1_OFFSET) == 0,
6201 ("pmap_demote_l1: Invalid virtual address %#lx", va));
6202 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
6203 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
6206 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
6207 tmpl1 = kva_alloc(PAGE_SIZE);
6212 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
6213 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
6214 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
6215 " in pmap %p", va, pmap);
6220 l2phys = VM_PAGE_TO_PHYS(ml2);
6221 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
6223 /* Address the range points at */
6224 phys = oldl1 & ~ATTR_MASK;
6225 /* The attributed from the old l1 table to be copied */
6226 newl2 = oldl1 & ATTR_MASK;
6228 /* Create the new entries */
6229 for (i = 0; i < Ln_ENTRIES; i++) {
6230 l2[i] = newl2 | phys;
6233 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
6234 ("Invalid l2 page (%lx != %lx)", l2[0],
6235 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
6238 pmap_kenter(tmpl1, PAGE_SIZE,
6239 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET,
6240 VM_MEMATTR_WRITE_BACK);
6241 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
6244 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
6248 pmap_kremove(tmpl1);
6249 kva_free(tmpl1, PAGE_SIZE);
6256 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
6260 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
6267 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
6268 struct rwlock **lockp)
6270 struct spglist free;
6273 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
6275 vm_page_free_pages_toq(&free, true);
6279 * Create an L3 table to map all addresses within an L2 mapping.
6282 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
6283 struct rwlock **lockp)
6285 pt_entry_t *l3, newl3, oldl2;
6290 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6291 PMAP_ASSERT_STAGE1(pmap);
6292 KASSERT(ADDR_IS_CANONICAL(va),
6293 ("%s: Address not in canonical form: %lx", __func__, va));
6296 oldl2 = pmap_load(l2);
6297 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
6298 ("pmap_demote_l2: Demoting a non-block entry"));
6302 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
6303 tmpl2 = kva_alloc(PAGE_SIZE);
6309 * Invalidate the 2MB page mapping and return "failure" if the
6310 * mapping was never accessed.
6312 if ((oldl2 & ATTR_AF) == 0) {
6313 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
6314 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
6315 pmap_demote_l2_abort(pmap, va, l2, lockp);
6316 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
6321 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
6322 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
6323 ("pmap_demote_l2: page table page for a wired mapping"
6327 * If the page table page is missing and the mapping
6328 * is for a kernel address, the mapping must belong to
6329 * the direct map. Page table pages are preallocated
6330 * for every other part of the kernel address space,
6331 * so the direct map region is the only part of the
6332 * kernel address space that must be handled here.
6334 KASSERT(!ADDR_IS_KERNEL(va) || VIRT_IN_DMAP(va),
6335 ("pmap_demote_l2: No saved mpte for va %#lx", va));
6338 * If the 2MB page mapping belongs to the direct map
6339 * region of the kernel's address space, then the page
6340 * allocation request specifies the highest possible
6341 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
6342 * priority is normal.
6344 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
6345 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
6346 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
6349 * If the allocation of the new page table page fails,
6350 * invalidate the 2MB page mapping and return "failure".
6353 pmap_demote_l2_abort(pmap, va, l2, lockp);
6354 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
6355 " in pmap %p", va, pmap);
6359 if (!ADDR_IS_KERNEL(va)) {
6360 ml3->ref_count = NL3PG;
6361 pmap_resident_count_inc(pmap, 1);
6364 l3phys = VM_PAGE_TO_PHYS(ml3);
6365 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
6366 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
6367 KASSERT((oldl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) !=
6368 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM),
6369 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
6372 * If the page table page is not leftover from an earlier promotion,
6373 * or the mapping attributes have changed, (re)initialize the L3 table.
6375 * When pmap_update_entry() clears the old L2 mapping, it (indirectly)
6376 * performs a dsb(). That dsb() ensures that the stores for filling
6377 * "l3" are visible before "l3" is added to the page table.
6379 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK))
6380 pmap_fill_l3(l3, newl3);
6383 * Map the temporary page so we don't lose access to the l2 table.
6386 pmap_kenter(tmpl2, PAGE_SIZE,
6387 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET,
6388 VM_MEMATTR_WRITE_BACK);
6389 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
6393 * The spare PV entries must be reserved prior to demoting the
6394 * mapping, that is, prior to changing the PDE. Otherwise, the state
6395 * of the L2 and the PV lists will be inconsistent, which can result
6396 * in reclaim_pv_chunk() attempting to remove a PV entry from the
6397 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
6398 * PV entry for the 2MB page mapping that is being demoted.
6400 if ((oldl2 & ATTR_SW_MANAGED) != 0)
6401 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
6404 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
6405 * the 2MB page mapping.
6407 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
6410 * Demote the PV entry.
6412 if ((oldl2 & ATTR_SW_MANAGED) != 0)
6413 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
6415 atomic_add_long(&pmap_l2_demotions, 1);
6416 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
6417 " in pmap %p %lx", va, pmap, l3[0]);
6421 pmap_kremove(tmpl2);
6422 kva_free(tmpl2, PAGE_SIZE);
6430 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
6432 struct rwlock *lock;
6436 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
6443 * Perform the pmap work for mincore(2). If the page is not both referenced and
6444 * modified by this pmap, returns its physical address so that the caller can
6445 * find other mappings.
6448 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
6450 pt_entry_t *pte, tpte;
6451 vm_paddr_t mask, pa;
6455 PMAP_ASSERT_STAGE1(pmap);
6457 pte = pmap_pte(pmap, addr, &lvl);
6459 tpte = pmap_load(pte);
6472 panic("pmap_mincore: invalid level %d", lvl);
6475 managed = (tpte & ATTR_SW_MANAGED) != 0;
6476 val = MINCORE_INCORE;
6478 val |= MINCORE_PSIND(3 - lvl);
6479 if ((managed && pmap_pte_dirty(pmap, tpte)) || (!managed &&
6480 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW)))
6481 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6482 if ((tpte & ATTR_AF) == ATTR_AF)
6483 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6485 pa = (tpte & ~ATTR_MASK) | (addr & mask);
6491 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6492 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
6500 * Garbage collect every ASID that is neither active on a processor nor
6504 pmap_reset_asid_set(pmap_t pmap)
6507 int asid, cpuid, epoch;
6508 struct asid_set *set;
6509 enum pmap_stage stage;
6511 set = pmap->pm_asid_set;
6512 stage = pmap->pm_stage;
6514 set = pmap->pm_asid_set;
6515 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6516 mtx_assert(&set->asid_set_mutex, MA_OWNED);
6519 * Ensure that the store to asid_epoch is globally visible before the
6520 * loads from pc_curpmap are performed.
6522 epoch = set->asid_epoch + 1;
6523 if (epoch == INT_MAX)
6525 set->asid_epoch = epoch;
6527 if (stage == PM_STAGE1) {
6528 __asm __volatile("tlbi vmalle1is");
6530 KASSERT(pmap_clean_stage2_tlbi != NULL,
6531 ("%s: Unset stage 2 tlb invalidation callback\n",
6533 pmap_clean_stage2_tlbi();
6536 bit_nclear(set->asid_set, ASID_FIRST_AVAILABLE,
6537 set->asid_set_size - 1);
6538 CPU_FOREACH(cpuid) {
6539 if (cpuid == curcpu)
6541 if (stage == PM_STAGE1) {
6542 curpmap = pcpu_find(cpuid)->pc_curpmap;
6543 PMAP_ASSERT_STAGE1(pmap);
6545 curpmap = pcpu_find(cpuid)->pc_curvmpmap;
6546 if (curpmap == NULL)
6548 PMAP_ASSERT_STAGE2(pmap);
6550 KASSERT(curpmap->pm_asid_set == set, ("Incorrect set"));
6551 asid = COOKIE_TO_ASID(curpmap->pm_cookie);
6554 bit_set(set->asid_set, asid);
6555 curpmap->pm_cookie = COOKIE_FROM(asid, epoch);
6560 * Allocate a new ASID for the specified pmap.
6563 pmap_alloc_asid(pmap_t pmap)
6565 struct asid_set *set;
6568 set = pmap->pm_asid_set;
6569 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6571 mtx_lock_spin(&set->asid_set_mutex);
6574 * While this processor was waiting to acquire the asid set mutex,
6575 * pmap_reset_asid_set() running on another processor might have
6576 * updated this pmap's cookie to the current epoch. In which case, we
6577 * don't need to allocate a new ASID.
6579 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch)
6582 bit_ffc_at(set->asid_set, set->asid_next, set->asid_set_size,
6584 if (new_asid == -1) {
6585 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
6586 set->asid_next, &new_asid);
6587 if (new_asid == -1) {
6588 pmap_reset_asid_set(pmap);
6589 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
6590 set->asid_set_size, &new_asid);
6591 KASSERT(new_asid != -1, ("ASID allocation failure"));
6594 bit_set(set->asid_set, new_asid);
6595 set->asid_next = new_asid + 1;
6596 pmap->pm_cookie = COOKIE_FROM(new_asid, set->asid_epoch);
6598 mtx_unlock_spin(&set->asid_set_mutex);
6602 * Compute the value that should be stored in ttbr0 to activate the specified
6603 * pmap. This value may change from time to time.
6606 pmap_to_ttbr0(pmap_t pmap)
6609 return (ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) |
6614 pmap_activate_int(pmap_t pmap)
6616 struct asid_set *set;
6619 KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap"));
6620 KASSERT(pmap != kernel_pmap, ("kernel pmap activation"));
6622 if ((pmap->pm_stage == PM_STAGE1 && pmap == PCPU_GET(curpmap)) ||
6623 (pmap->pm_stage == PM_STAGE2 && pmap == PCPU_GET(curvmpmap))) {
6625 * Handle the possibility that the old thread was preempted
6626 * after an "ic" or "tlbi" instruction but before it performed
6627 * a "dsb" instruction. If the old thread migrates to a new
6628 * processor, its completion of a "dsb" instruction on that
6629 * new processor does not guarantee that the "ic" or "tlbi"
6630 * instructions performed on the old processor have completed.
6636 set = pmap->pm_asid_set;
6637 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6640 * Ensure that the store to curpmap is globally visible before the
6641 * load from asid_epoch is performed.
6643 if (pmap->pm_stage == PM_STAGE1)
6644 PCPU_SET(curpmap, pmap);
6646 PCPU_SET(curvmpmap, pmap);
6648 epoch = COOKIE_TO_EPOCH(pmap->pm_cookie);
6649 if (epoch >= 0 && epoch != set->asid_epoch)
6650 pmap_alloc_asid(pmap);
6652 if (pmap->pm_stage == PM_STAGE1) {
6653 set_ttbr0(pmap_to_ttbr0(pmap));
6654 if (PCPU_GET(bcast_tlbi_workaround) != 0)
6655 invalidate_local_icache();
6661 pmap_activate_vm(pmap_t pmap)
6664 PMAP_ASSERT_STAGE2(pmap);
6666 (void)pmap_activate_int(pmap);
6670 pmap_activate(struct thread *td)
6674 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6675 PMAP_ASSERT_STAGE1(pmap);
6677 (void)pmap_activate_int(pmap);
6682 * To eliminate the unused parameter "old", we would have to add an instruction
6686 pmap_switch(struct thread *old __unused, struct thread *new)
6688 pcpu_bp_harden bp_harden;
6691 /* Store the new curthread */
6692 PCPU_SET(curthread, new);
6694 /* And the new pcb */
6696 PCPU_SET(curpcb, pcb);
6699 * TODO: We may need to flush the cache here if switching
6700 * to a user process.
6703 if (pmap_activate_int(vmspace_pmap(new->td_proc->p_vmspace))) {
6705 * Stop userspace from training the branch predictor against
6706 * other processes. This will call into a CPU specific
6707 * function that clears the branch predictor state.
6709 bp_harden = PCPU_GET(bp_harden);
6710 if (bp_harden != NULL)
6718 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
6721 PMAP_ASSERT_STAGE1(pmap);
6722 KASSERT(ADDR_IS_CANONICAL(va),
6723 ("%s: Address not in canonical form: %lx", __func__, va));
6725 if (ADDR_IS_KERNEL(va)) {
6726 cpu_icache_sync_range(va, sz);
6731 /* Find the length of data in this page to flush */
6732 offset = va & PAGE_MASK;
6733 len = imin(PAGE_SIZE - offset, sz);
6736 /* Extract the physical address & find it in the DMAP */
6737 pa = pmap_extract(pmap, va);
6739 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
6741 /* Move to the next page */
6744 /* Set the length for the next iteration */
6745 len = imin(PAGE_SIZE, sz);
6751 pmap_stage2_fault(pmap_t pmap, uint64_t esr, uint64_t far)
6754 pt_entry_t *ptep, pte;
6757 PMAP_ASSERT_STAGE2(pmap);
6760 /* Data and insn aborts use same encoding for FSC field. */
6761 dfsc = esr & ISS_DATA_DFSC_MASK;
6763 case ISS_DATA_DFSC_TF_L0:
6764 case ISS_DATA_DFSC_TF_L1:
6765 case ISS_DATA_DFSC_TF_L2:
6766 case ISS_DATA_DFSC_TF_L3:
6768 pdep = pmap_pde(pmap, far, &lvl);
6769 if (pdep == NULL || lvl != (dfsc - ISS_DATA_DFSC_TF_L1)) {
6776 ptep = pmap_l0_to_l1(pdep, far);
6779 ptep = pmap_l1_to_l2(pdep, far);
6782 ptep = pmap_l2_to_l3(pdep, far);
6785 panic("%s: Invalid pde level %d", __func__,lvl);
6789 case ISS_DATA_DFSC_AFF_L1:
6790 case ISS_DATA_DFSC_AFF_L2:
6791 case ISS_DATA_DFSC_AFF_L3:
6793 ptep = pmap_pte(pmap, far, &lvl);
6795 if (ptep != NULL && (pte = pmap_load(ptep)) != 0) {
6797 pmap_invalidate_vpipt_icache();
6800 * If accessing an executable page invalidate
6801 * the I-cache so it will be valid when we
6802 * continue execution in the guest. The D-cache
6803 * is assumed to already be clean to the Point
6806 if ((pte & ATTR_S2_XN_MASK) !=
6807 ATTR_S2_XN(ATTR_S2_XN_NONE)) {
6808 invalidate_icache();
6811 pmap_set_bits(ptep, ATTR_AF | ATTR_DESCR_VALID);
6822 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
6824 pt_entry_t pte, *ptep;
6831 ec = ESR_ELx_EXCEPTION(esr);
6833 case EXCP_INSN_ABORT_L:
6834 case EXCP_INSN_ABORT:
6835 case EXCP_DATA_ABORT_L:
6836 case EXCP_DATA_ABORT:
6842 if (pmap->pm_stage == PM_STAGE2)
6843 return (pmap_stage2_fault(pmap, esr, far));
6845 /* Data and insn aborts use same encoding for FSC field. */
6846 switch (esr & ISS_DATA_DFSC_MASK) {
6847 case ISS_DATA_DFSC_AFF_L1:
6848 case ISS_DATA_DFSC_AFF_L2:
6849 case ISS_DATA_DFSC_AFF_L3:
6851 ptep = pmap_pte(pmap, far, &lvl);
6853 pmap_set_bits(ptep, ATTR_AF);
6856 * XXXMJ as an optimization we could mark the entry
6857 * dirty if this is a write fault.
6862 case ISS_DATA_DFSC_PF_L1:
6863 case ISS_DATA_DFSC_PF_L2:
6864 case ISS_DATA_DFSC_PF_L3:
6865 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
6866 (esr & ISS_DATA_WnR) == 0)
6869 ptep = pmap_pte(pmap, far, &lvl);
6871 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
6872 if ((pte & ATTR_S1_AP_RW_BIT) ==
6873 ATTR_S1_AP(ATTR_S1_AP_RO)) {
6874 pmap_clear_bits(ptep, ATTR_S1_AP_RW_BIT);
6875 pmap_invalidate_page(pmap, far);
6881 case ISS_DATA_DFSC_TF_L0:
6882 case ISS_DATA_DFSC_TF_L1:
6883 case ISS_DATA_DFSC_TF_L2:
6884 case ISS_DATA_DFSC_TF_L3:
6886 * Retry the translation. A break-before-make sequence can
6887 * produce a transient fault.
6889 if (pmap == kernel_pmap) {
6891 * The translation fault may have occurred within a
6892 * critical section. Therefore, we must check the
6893 * address without acquiring the kernel pmap's lock.
6895 if (pmap_klookup(far, NULL))
6899 /* Ask the MMU to check the address. */
6900 intr = intr_disable();
6901 par = arm64_address_translate_s1e0r(far);
6906 * If the translation was successful, then we can
6907 * return success to the trap handler.
6909 if (PAR_SUCCESS(par))
6919 * Increase the starting virtual address of the given mapping if a
6920 * different alignment might result in more superpage mappings.
6923 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6924 vm_offset_t *addr, vm_size_t size)
6926 vm_offset_t superpage_offset;
6930 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6931 offset += ptoa(object->pg_color);
6932 superpage_offset = offset & L2_OFFSET;
6933 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
6934 (*addr & L2_OFFSET) == superpage_offset)
6936 if ((*addr & L2_OFFSET) < superpage_offset)
6937 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
6939 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
6943 * Get the kernel virtual address of a set of physical pages. If there are
6944 * physical addresses not covered by the DMAP perform a transient mapping
6945 * that will be removed when calling pmap_unmap_io_transient.
6947 * \param page The pages the caller wishes to obtain the virtual
6948 * address on the kernel memory map.
6949 * \param vaddr On return contains the kernel virtual memory address
6950 * of the pages passed in the page parameter.
6951 * \param count Number of pages passed in.
6952 * \param can_fault TRUE if the thread using the mapped pages can take
6953 * page faults, FALSE otherwise.
6955 * \returns TRUE if the caller must call pmap_unmap_io_transient when
6956 * finished or FALSE otherwise.
6960 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6961 boolean_t can_fault)
6964 boolean_t needs_mapping;
6968 * Allocate any KVA space that we need, this is done in a separate
6969 * loop to prevent calling vmem_alloc while pinned.
6971 needs_mapping = FALSE;
6972 for (i = 0; i < count; i++) {
6973 paddr = VM_PAGE_TO_PHYS(page[i]);
6974 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
6975 error = vmem_alloc(kernel_arena, PAGE_SIZE,
6976 M_BESTFIT | M_WAITOK, &vaddr[i]);
6977 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
6978 needs_mapping = TRUE;
6980 vaddr[i] = PHYS_TO_DMAP(paddr);
6984 /* Exit early if everything is covered by the DMAP */
6990 for (i = 0; i < count; i++) {
6991 paddr = VM_PAGE_TO_PHYS(page[i]);
6992 if (!PHYS_IN_DMAP(paddr)) {
6994 "pmap_map_io_transient: TODO: Map out of DMAP data");
6998 return (needs_mapping);
7002 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7003 boolean_t can_fault)
7010 for (i = 0; i < count; i++) {
7011 paddr = VM_PAGE_TO_PHYS(page[i]);
7012 if (!PHYS_IN_DMAP(paddr)) {
7013 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
7019 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
7022 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);
7026 * Track a range of the kernel's virtual address space that is contiguous
7027 * in various mapping attributes.
7029 struct pmap_kernel_map_range {
7039 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
7045 if (eva <= range->sva)
7048 index = range->attrs & ATTR_S1_IDX_MASK;
7050 case ATTR_S1_IDX(VM_MEMATTR_DEVICE):
7053 case ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE):
7056 case ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK):
7059 case ATTR_S1_IDX(VM_MEMATTR_WRITE_THROUGH):
7064 "%s: unknown memory type %x for range 0x%016lx-0x%016lx\n",
7065 __func__, index, range->sva, eva);
7070 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c %3s %d %d %d %d\n",
7072 (range->attrs & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP_RW ? 'w' : '-',
7073 (range->attrs & ATTR_S1_PXN) != 0 ? '-' : 'x',
7074 (range->attrs & ATTR_S1_AP_USER) != 0 ? 'u' : 's',
7075 mode, range->l1blocks, range->l2blocks, range->l3contig,
7078 /* Reset to sentinel value. */
7079 range->sva = 0xfffffffffffffffful;
7083 * Determine whether the attributes specified by a page table entry match those
7084 * being tracked by the current range.
7087 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
7090 return (range->attrs == attrs);
7094 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
7098 memset(range, 0, sizeof(*range));
7100 range->attrs = attrs;
7104 * Given a leaf PTE, derive the mapping's attributes. If they do not match
7105 * those of the current run, dump the address range and its attributes, and
7109 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
7110 vm_offset_t va, pd_entry_t l0e, pd_entry_t l1e, pd_entry_t l2e,
7115 attrs = l0e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
7116 attrs |= l1e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
7117 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK)
7118 attrs |= l1e & ATTR_S1_IDX_MASK;
7119 attrs |= l2e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
7120 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK)
7121 attrs |= l2e & ATTR_S1_IDX_MASK;
7122 attrs |= l3e & (ATTR_S1_AP_MASK | ATTR_S1_XN | ATTR_S1_IDX_MASK);
7124 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
7125 sysctl_kmaps_dump(sb, range, va);
7126 sysctl_kmaps_reinit(range, va, attrs);
7131 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
7133 struct pmap_kernel_map_range range;
7134 struct sbuf sbuf, *sb;
7135 pd_entry_t l0e, *l1, l1e, *l2, l2e;
7136 pt_entry_t *l3, l3e;
7139 int error, i, j, k, l;
7141 error = sysctl_wire_old_buffer(req, 0);
7145 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
7147 /* Sentinel value. */
7148 range.sva = 0xfffffffffffffffful;
7151 * Iterate over the kernel page tables without holding the kernel pmap
7152 * lock. Kernel page table pages are never freed, so at worst we will
7153 * observe inconsistencies in the output.
7155 for (sva = 0xffff000000000000ul, i = pmap_l0_index(sva); i < Ln_ENTRIES;
7157 if (i == pmap_l0_index(DMAP_MIN_ADDRESS))
7158 sbuf_printf(sb, "\nDirect map:\n");
7159 else if (i == pmap_l0_index(VM_MIN_KERNEL_ADDRESS))
7160 sbuf_printf(sb, "\nKernel map:\n");
7162 l0e = kernel_pmap->pm_l0[i];
7163 if ((l0e & ATTR_DESCR_VALID) == 0) {
7164 sysctl_kmaps_dump(sb, &range, sva);
7168 pa = l0e & ~ATTR_MASK;
7169 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa);
7171 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
7173 if ((l1e & ATTR_DESCR_VALID) == 0) {
7174 sysctl_kmaps_dump(sb, &range, sva);
7178 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
7179 sysctl_kmaps_check(sb, &range, sva, l0e, l1e,
7185 pa = l1e & ~ATTR_MASK;
7186 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa);
7188 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
7190 if ((l2e & ATTR_DESCR_VALID) == 0) {
7191 sysctl_kmaps_dump(sb, &range, sva);
7195 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK) {
7196 sysctl_kmaps_check(sb, &range, sva,
7202 pa = l2e & ~ATTR_MASK;
7203 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
7205 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
7206 l++, sva += L3_SIZE) {
7208 if ((l3e & ATTR_DESCR_VALID) == 0) {
7209 sysctl_kmaps_dump(sb, &range,
7213 sysctl_kmaps_check(sb, &range, sva,
7214 l0e, l1e, l2e, l3e);
7215 if ((l3e & ATTR_CONTIGUOUS) != 0)
7216 range.l3contig += l % 16 == 0 ?
7225 error = sbuf_finish(sb);
7229 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
7230 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP,
7231 NULL, 0, sysctl_kmaps, "A",
7232 "Dump kernel address layout");