2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
108 #include <sys/param.h>
110 #include <sys/systm.h>
111 #include <sys/kernel.h>
113 #include <sys/lock.h>
114 #include <sys/malloc.h>
115 #include <sys/mman.h>
116 #include <sys/msgbuf.h>
117 #include <sys/mutex.h>
118 #include <sys/proc.h>
119 #include <sys/rwlock.h>
121 #include <sys/vmem.h>
122 #include <sys/vmmeter.h>
123 #include <sys/sched.h>
124 #include <sys/sysctl.h>
125 #include <sys/_unrhdr.h>
129 #include <vm/vm_param.h>
130 #include <vm/vm_kern.h>
131 #include <vm/vm_page.h>
132 #include <vm/vm_map.h>
133 #include <vm/vm_object.h>
134 #include <vm/vm_extern.h>
135 #include <vm/vm_pageout.h>
136 #include <vm/vm_pager.h>
137 #include <vm/vm_radix.h>
138 #include <vm/vm_reserv.h>
141 #include <machine/machdep.h>
142 #include <machine/md_var.h>
143 #include <machine/pcb.h>
145 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
146 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
147 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
148 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
150 #define NUL0E L0_ENTRIES
151 #define NUL1E (NUL0E * NL1PG)
152 #define NUL2E (NUL1E * NL2PG)
154 #if !defined(DIAGNOSTIC)
155 #ifdef __GNUC_GNU_INLINE__
156 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
158 #define PMAP_INLINE extern inline
165 * These are configured by the mair_el1 register. This is set up in locore.S
167 #define DEVICE_MEMORY 0
168 #define UNCACHED_MEMORY 1
169 #define CACHED_MEMORY 2
173 #define PV_STAT(x) do { x ; } while (0)
175 #define PV_STAT(x) do { } while (0)
178 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
180 #define NPV_LIST_LOCKS MAXCPU
182 #define PHYS_TO_PV_LIST_LOCK(pa) \
183 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
185 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
186 struct rwlock **_lockp = (lockp); \
187 struct rwlock *_new_lock; \
189 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
190 if (_new_lock != *_lockp) { \
191 if (*_lockp != NULL) \
192 rw_wunlock(*_lockp); \
193 *_lockp = _new_lock; \
198 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
199 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
201 #define RELEASE_PV_LIST_LOCK(lockp) do { \
202 struct rwlock **_lockp = (lockp); \
204 if (*_lockp != NULL) { \
205 rw_wunlock(*_lockp); \
210 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
211 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
213 struct pmap kernel_pmap_store;
215 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
216 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
217 vm_offset_t kernel_vm_end = 0;
219 struct msgbuf *msgbufp = NULL;
221 static struct rwlock_padalign pvh_global_lock;
223 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
226 * Data for the pv entry allocation mechanism
228 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
229 static struct mtx pv_chunks_mutex;
230 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
232 static void free_pv_chunk(struct pv_chunk *pc);
233 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
234 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
235 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
236 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
237 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
239 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
240 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
241 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
242 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
243 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
244 vm_page_t m, struct rwlock **lockp);
246 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
247 struct rwlock **lockp);
249 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
250 struct spglist *free);
251 static int pmap_unuse_l3(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
254 * These load the old table data and store the new value.
255 * They need to be atomic as the System MMU may write to the table at
256 * the same time as the CPU.
258 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
259 #define pmap_set(table, mask) atomic_set_64(table, mask)
260 #define pmap_load_clear(table) atomic_swap_64(table, 0)
261 #define pmap_load(table) (*table)
263 /********************/
264 /* Inline functions */
265 /********************/
268 pagecopy(void *s, void *d)
271 memcpy(d, s, PAGE_SIZE);
281 #define pmap_l0_index(va) (((va) >> L0_SHIFT) & L0_ADDR_MASK)
282 #define pmap_l1_index(va) (((va) >> L1_SHIFT) & Ln_ADDR_MASK)
283 #define pmap_l2_index(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK)
284 #define pmap_l3_index(va) (((va) >> L3_SHIFT) & Ln_ADDR_MASK)
286 static __inline pd_entry_t *
287 pmap_l0(pmap_t pmap, vm_offset_t va)
290 return (&pmap->pm_l0[pmap_l0_index(va)]);
293 static __inline pd_entry_t *
294 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
298 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
299 return (&l1[pmap_l1_index(va)]);
302 static __inline pd_entry_t *
303 pmap_l1(pmap_t pmap, vm_offset_t va)
307 l0 = pmap_l0(pmap, va);
308 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
311 return (pmap_l0_to_l1(l0, va));
314 static __inline pd_entry_t *
315 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
319 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
320 return (&l2[pmap_l2_index(va)]);
323 static __inline pd_entry_t *
324 pmap_l2(pmap_t pmap, vm_offset_t va)
328 l1 = pmap_l1(pmap, va);
329 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
332 return (pmap_l1_to_l2(l1, va));
335 static __inline pt_entry_t *
336 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
340 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
341 return (&l3[pmap_l3_index(va)]);
345 * Returns the lowest valid pde for a given virtual address.
346 * The next level may or may not point to a valid page or block.
348 static __inline pd_entry_t *
349 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
351 pd_entry_t *l0, *l1, *l2, desc;
353 l0 = pmap_l0(pmap, va);
354 desc = pmap_load(l0) & ATTR_DESCR_MASK;
355 if (desc != L0_TABLE) {
360 l1 = pmap_l0_to_l1(l0, va);
361 desc = pmap_load(l1) & ATTR_DESCR_MASK;
362 if (desc != L1_TABLE) {
367 l2 = pmap_l1_to_l2(l1, va);
368 desc = pmap_load(l2) & ATTR_DESCR_MASK;
369 if (desc != L2_TABLE) {
379 * Returns the lowest valid pte block or table entry for a given virtual
380 * address. If there are no valid entries return NULL and set the level to
381 * the first invalid level.
383 static __inline pt_entry_t *
384 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
386 pd_entry_t *l1, *l2, desc;
389 l1 = pmap_l1(pmap, va);
394 desc = pmap_load(l1) & ATTR_DESCR_MASK;
395 if (desc == L1_BLOCK) {
400 if (desc != L1_TABLE) {
405 l2 = pmap_l1_to_l2(l1, va);
406 desc = pmap_load(l2) & ATTR_DESCR_MASK;
407 if (desc == L2_BLOCK) {
412 if (desc != L2_TABLE) {
418 l3 = pmap_l2_to_l3(l2, va);
419 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
426 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
427 pd_entry_t **l2, pt_entry_t **l3)
429 pd_entry_t *l0p, *l1p, *l2p;
431 if (pmap->pm_l0 == NULL)
434 l0p = pmap_l0(pmap, va);
437 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
440 l1p = pmap_l0_to_l1(l0p, va);
443 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
449 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
452 l2p = pmap_l1_to_l2(l1p, va);
455 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
460 *l3 = pmap_l2_to_l3(l2p, va);
466 pmap_is_current(pmap_t pmap)
469 return ((pmap == pmap_kernel()) ||
470 (pmap == curthread->td_proc->p_vmspace->vm_map.pmap));
474 pmap_l3_valid(pt_entry_t l3)
477 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
481 pmap_l3_valid_cacheable(pt_entry_t l3)
484 return (((l3 & ATTR_DESCR_MASK) == L3_PAGE) &&
485 ((l3 & ATTR_IDX_MASK) == ATTR_IDX(CACHED_MEMORY)));
488 #define PTE_SYNC(pte) cpu_dcache_wb_range((vm_offset_t)pte, sizeof(*pte))
491 * Checks if the page is dirty. We currently lack proper tracking of this on
492 * arm64 so for now assume is a page mapped as rw was accessed it is.
495 pmap_page_dirty(pt_entry_t pte)
498 return ((pte & (ATTR_AF | ATTR_AP_RW_BIT)) ==
499 (ATTR_AF | ATTR_AP(ATTR_AP_RW)));
503 pmap_resident_count_inc(pmap_t pmap, int count)
506 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
507 pmap->pm_stats.resident_count += count;
511 pmap_resident_count_dec(pmap_t pmap, int count)
514 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
515 KASSERT(pmap->pm_stats.resident_count >= count,
516 ("pmap %p resident count underflow %ld %d", pmap,
517 pmap->pm_stats.resident_count, count));
518 pmap->pm_stats.resident_count -= count;
522 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
528 l1 = (pd_entry_t *)l1pt;
529 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
531 /* Check locore has used a table L1 map */
532 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
533 ("Invalid bootstrap L1 table"));
534 /* Find the address of the L2 table */
535 l2 = (pt_entry_t *)init_pt_va;
536 *l2_slot = pmap_l2_index(va);
542 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
544 u_int l1_slot, l2_slot;
547 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
549 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
553 pmap_bootstrap_dmap(vm_offset_t l1pt, vm_paddr_t kernstart)
560 pa = dmap_phys_base = kernstart & ~L1_OFFSET;
561 va = DMAP_MIN_ADDRESS;
562 l1 = (pd_entry_t *)l1pt;
563 l1_slot = pmap_l1_index(DMAP_MIN_ADDRESS);
565 for (; va < DMAP_MAX_ADDRESS;
566 pa += L1_SIZE, va += L1_SIZE, l1_slot++) {
567 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
569 pmap_load_store(&l1[l1_slot],
570 (pa & ~L1_OFFSET) | ATTR_DEFAULT |
571 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
574 cpu_dcache_wb_range((vm_offset_t)l1, PAGE_SIZE);
579 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
586 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
588 l1 = (pd_entry_t *)l1pt;
589 l1_slot = pmap_l1_index(va);
592 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
593 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
595 pa = pmap_early_vtophys(l1pt, l2pt);
596 pmap_load_store(&l1[l1_slot],
597 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
601 /* Clean the L2 page table */
602 memset((void *)l2_start, 0, l2pt - l2_start);
603 cpu_dcache_wb_range(l2_start, l2pt - l2_start);
605 /* Flush the l1 table to ram */
606 cpu_dcache_wb_range((vm_offset_t)l1, PAGE_SIZE);
612 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
614 vm_offset_t l2pt, l3pt;
619 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
621 l2 = pmap_l2(kernel_pmap, va);
622 l2 = (pd_entry_t *)((uintptr_t)l2 & ~(PAGE_SIZE - 1));
623 l2pt = (vm_offset_t)l2;
624 l2_slot = pmap_l2_index(va);
627 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
628 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
630 pa = pmap_early_vtophys(l1pt, l3pt);
631 pmap_load_store(&l2[l2_slot],
632 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
636 /* Clean the L2 page table */
637 memset((void *)l3_start, 0, l3pt - l3_start);
638 cpu_dcache_wb_range(l3_start, l3pt - l3_start);
640 cpu_dcache_wb_range((vm_offset_t)l2, PAGE_SIZE);
646 * Bootstrap the system enough to run with virtual memory.
649 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
652 u_int l1_slot, l2_slot, avail_slot, map_slot, used_map_slot;
655 vm_offset_t va, freemempos;
656 vm_offset_t dpcpu, msgbufpv;
657 vm_paddr_t pa, min_pa;
660 kern_delta = KERNBASE - kernstart;
663 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
664 printf("%lx\n", l1pt);
665 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
667 /* Set this early so we can use the pagetable walking functions */
668 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
669 PMAP_LOCK_INIT(kernel_pmap);
672 * Initialize the global pv list lock.
674 rw_init(&pvh_global_lock, "pmap pv global");
676 /* Assume the address we were loaded to is a valid physical address */
677 min_pa = KERNBASE - kern_delta;
680 * Find the minimum physical address. physmap is sorted,
681 * but may contain empty ranges.
683 for (i = 0; i < (physmap_idx * 2); i += 2) {
684 if (physmap[i] == physmap[i + 1])
686 if (physmap[i] <= min_pa)
691 /* Create a direct map region early so we can use it for pa -> va */
692 pmap_bootstrap_dmap(l1pt, min_pa);
695 pa = KERNBASE - kern_delta;
698 * Start to initialise phys_avail by copying from physmap
699 * up to the physical address KERNBASE points at.
701 map_slot = avail_slot = 0;
702 for (; map_slot < (physmap_idx * 2) &&
703 avail_slot < (PHYS_AVAIL_SIZE - 2); map_slot += 2) {
704 if (physmap[map_slot] == physmap[map_slot + 1])
707 if (physmap[map_slot] <= pa &&
708 physmap[map_slot + 1] > pa)
711 phys_avail[avail_slot] = physmap[map_slot];
712 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
713 physmem += (phys_avail[avail_slot + 1] -
714 phys_avail[avail_slot]) >> PAGE_SHIFT;
718 /* Add the memory before the kernel */
719 if (physmap[avail_slot] < pa && avail_slot < (PHYS_AVAIL_SIZE - 2)) {
720 phys_avail[avail_slot] = physmap[map_slot];
721 phys_avail[avail_slot + 1] = pa;
722 physmem += (phys_avail[avail_slot + 1] -
723 phys_avail[avail_slot]) >> PAGE_SHIFT;
726 used_map_slot = map_slot;
729 * Read the page table to find out what is already mapped.
730 * This assumes we have mapped a block of memory from KERNBASE
731 * using a single L1 entry.
733 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
735 /* Sanity check the index, KERNBASE should be the first VA */
736 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
738 /* Find how many pages we have mapped */
739 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
740 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
743 /* Check locore used L2 blocks */
744 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
745 ("Invalid bootstrap L2 table"));
746 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
747 ("Incorrect PA in L2 table"));
753 va = roundup2(va, L1_SIZE);
755 freemempos = KERNBASE + kernlen;
756 freemempos = roundup2(freemempos, PAGE_SIZE);
757 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
758 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
759 /* And the l3 tables for the early devmap */
760 freemempos = pmap_bootstrap_l3(l1pt,
761 VM_MAX_KERNEL_ADDRESS - L2_SIZE, freemempos);
765 #define alloc_pages(var, np) \
766 (var) = freemempos; \
767 freemempos += (np * PAGE_SIZE); \
768 memset((char *)(var), 0, ((np) * PAGE_SIZE));
770 /* Allocate dynamic per-cpu area. */
771 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
772 dpcpu_init((void *)dpcpu, 0);
774 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
775 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
776 msgbufp = (void *)msgbufpv;
778 virtual_avail = roundup2(freemempos, L1_SIZE);
779 virtual_end = VM_MAX_KERNEL_ADDRESS - L2_SIZE;
780 kernel_vm_end = virtual_avail;
782 pa = pmap_early_vtophys(l1pt, freemempos);
784 /* Finish initialising physmap */
785 map_slot = used_map_slot;
786 for (; avail_slot < (PHYS_AVAIL_SIZE - 2) &&
787 map_slot < (physmap_idx * 2); map_slot += 2) {
788 if (physmap[map_slot] == physmap[map_slot + 1])
791 /* Have we used the current range? */
792 if (physmap[map_slot + 1] <= pa)
795 /* Do we need to split the entry? */
796 if (physmap[map_slot] < pa) {
797 phys_avail[avail_slot] = pa;
798 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
800 phys_avail[avail_slot] = physmap[map_slot];
801 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
803 physmem += (phys_avail[avail_slot + 1] -
804 phys_avail[avail_slot]) >> PAGE_SHIFT;
808 phys_avail[avail_slot] = 0;
809 phys_avail[avail_slot + 1] = 0;
812 * Maxmem isn't the "maximum memory", it's one larger than the
813 * highest page of the physical address space. It should be
814 * called something like "Maxphyspage".
816 Maxmem = atop(phys_avail[avail_slot - 1]);
822 * Initialize a vm_page's machine-dependent fields.
825 pmap_page_init(vm_page_t m)
828 TAILQ_INIT(&m->md.pv_list);
829 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
833 * Initialize the pmap module.
834 * Called by vm_init, to initialize any structures that the pmap
835 * system needs to map virtual memory.
843 * Initialize the pv chunk list mutex.
845 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
848 * Initialize the pool of pv list locks.
850 for (i = 0; i < NPV_LIST_LOCKS; i++)
851 rw_init(&pv_list_locks[i], "pmap pv list");
855 * Normal, non-SMP, invalidation functions.
856 * We inline these within pmap.c for speed.
859 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
865 "tlbi vaae1is, %0 \n"
868 : : "r"(va >> PAGE_SHIFT));
873 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
878 __asm __volatile("dsb sy");
879 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
881 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
890 pmap_invalidate_all(pmap_t pmap)
903 * Routine: pmap_extract
905 * Extract the physical page address associated
906 * with the given map/virtual_address pair.
909 pmap_extract(pmap_t pmap, vm_offset_t va)
911 pt_entry_t *pte, tpte;
918 * Find the block or page map for this virtual address. pmap_pte
919 * will return either a valid block/page entry, or NULL.
921 pte = pmap_pte(pmap, va, &lvl);
923 tpte = pmap_load(pte);
924 pa = tpte & ~ATTR_MASK;
927 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
928 ("pmap_extract: Invalid L1 pte found: %lx",
929 tpte & ATTR_DESCR_MASK));
930 pa |= (va & L1_OFFSET);
933 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
934 ("pmap_extract: Invalid L2 pte found: %lx",
935 tpte & ATTR_DESCR_MASK));
936 pa |= (va & L2_OFFSET);
939 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
940 ("pmap_extract: Invalid L3 pte found: %lx",
941 tpte & ATTR_DESCR_MASK));
942 pa |= (va & L3_OFFSET);
951 * Routine: pmap_extract_and_hold
953 * Atomically extract and hold the physical page
954 * with the given pmap and virtual address pair
955 * if that mapping permits the given protection.
958 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
960 pt_entry_t *pte, tpte;
969 pte = pmap_pte(pmap, va, &lvl);
971 tpte = pmap_load(pte);
973 KASSERT(lvl > 0 && lvl <= 3,
974 ("pmap_extract_and_hold: Invalid level %d", lvl));
975 CTASSERT(L1_BLOCK == L2_BLOCK);
976 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
977 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
978 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
979 tpte & ATTR_DESCR_MASK));
980 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
981 ((prot & VM_PROT_WRITE) == 0)) {
982 if (vm_page_pa_tryrelock(pmap, tpte & ~ATTR_MASK, &pa))
984 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
994 pmap_kextract(vm_offset_t va)
996 pt_entry_t *pte, tpte;
1000 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1001 pa = DMAP_TO_PHYS(va);
1004 pte = pmap_pte(kernel_pmap, va, &lvl);
1006 tpte = pmap_load(pte);
1007 pa = tpte & ~ATTR_MASK;
1010 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1011 ("pmap_kextract: Invalid L1 pte found: %lx",
1012 tpte & ATTR_DESCR_MASK));
1013 pa |= (va & L1_OFFSET);
1016 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1017 ("pmap_kextract: Invalid L2 pte found: %lx",
1018 tpte & ATTR_DESCR_MASK));
1019 pa |= (va & L2_OFFSET);
1022 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1023 ("pmap_kextract: Invalid L3 pte found: %lx",
1024 tpte & ATTR_DESCR_MASK));
1025 pa |= (va & L3_OFFSET);
1033 /***************************************************
1034 * Low level mapping routines.....
1035 ***************************************************/
1038 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1045 KASSERT((pa & L3_OFFSET) == 0,
1046 ("pmap_kenter_device: Invalid physical address"));
1047 KASSERT((sva & L3_OFFSET) == 0,
1048 ("pmap_kenter_device: Invalid virtual address"));
1049 KASSERT((size & PAGE_MASK) == 0,
1050 ("pmap_kenter_device: Mapping is not page-sized"));
1054 pde = pmap_pde(kernel_pmap, va, &lvl);
1055 KASSERT(pde != NULL,
1056 ("pmap_kenter_device: Invalid page entry, va: 0x%lx", va));
1058 ("pmap_kenter_device: Invalid level %d", lvl));
1060 pte = pmap_l2_to_l3(pde, va);
1061 pmap_load_store(pte, (pa & ~L3_OFFSET) | ATTR_DEFAULT |
1062 ATTR_IDX(DEVICE_MEMORY) | L3_PAGE);
1069 pmap_invalidate_range(kernel_pmap, sva, va);
1073 * Remove a page from the kernel pagetables.
1076 pmap_kremove(vm_offset_t va)
1081 pte = pmap_pte(kernel_pmap, va, &lvl);
1082 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1083 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1085 if (pmap_l3_valid_cacheable(pmap_load(pte)))
1086 cpu_dcache_wb_range(va, L3_SIZE);
1087 pmap_load_clear(pte);
1089 pmap_invalidate_page(kernel_pmap, va);
1093 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1099 KASSERT((sva & L3_OFFSET) == 0,
1100 ("pmap_kremove_device: Invalid virtual address"));
1101 KASSERT((size & PAGE_MASK) == 0,
1102 ("pmap_kremove_device: Mapping is not page-sized"));
1106 pte = pmap_pte(kernel_pmap, va, &lvl);
1107 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1109 ("Invalid device pagetable level: %d != 3", lvl));
1110 pmap_load_clear(pte);
1116 pmap_invalidate_range(kernel_pmap, sva, va);
1120 * Used to map a range of physical addresses into kernel
1121 * virtual address space.
1123 * The value passed in '*virt' is a suggested virtual address for
1124 * the mapping. Architectures which can support a direct-mapped
1125 * physical to virtual region can return the appropriate address
1126 * within that region, leaving '*virt' unchanged. Other
1127 * architectures should map the pages starting at '*virt' and
1128 * update '*virt' with the first usable address after the mapped
1132 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1134 return PHYS_TO_DMAP(start);
1139 * Add a list of wired pages to the kva
1140 * this routine is only used for temporary
1141 * kernel mappings that do not need to have
1142 * page modification or references recorded.
1143 * Note that old mappings are simply written
1144 * over. The page *must* be wired.
1145 * Note: SMP coherent. Uses a ranged shootdown IPI.
1148 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1151 pt_entry_t *pte, pa;
1157 for (i = 0; i < count; i++) {
1158 pde = pmap_pde(kernel_pmap, va, &lvl);
1159 KASSERT(pde != NULL,
1160 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1162 ("pmap_qenter: Invalid level %d", lvl));
1165 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1166 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1167 pte = pmap_l2_to_l3(pde, va);
1168 pmap_load_store(pte, pa);
1173 pmap_invalidate_range(kernel_pmap, sva, va);
1177 * This routine tears out page mappings from the
1178 * kernel -- it is meant only for temporary mappings.
1181 pmap_qremove(vm_offset_t sva, int count)
1187 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1190 while (count-- > 0) {
1191 pte = pmap_pte(kernel_pmap, va, &lvl);
1193 ("Invalid device pagetable level: %d != 3", lvl));
1195 if (pmap_l3_valid_cacheable(pmap_load(pte)))
1196 cpu_dcache_wb_range(va, L3_SIZE);
1197 pmap_load_clear(pte);
1203 pmap_invalidate_range(kernel_pmap, sva, va);
1206 /***************************************************
1207 * Page table page management routines.....
1208 ***************************************************/
1209 static __inline void
1210 pmap_free_zero_pages(struct spglist *free)
1214 while ((m = SLIST_FIRST(free)) != NULL) {
1215 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1216 /* Preserve the page's PG_ZERO setting. */
1217 vm_page_free_toq(m);
1222 * Schedule the specified unused page table page to be freed. Specifically,
1223 * add the page to the specified list of pages that will be released to the
1224 * physical memory manager after the TLB has been updated.
1226 static __inline void
1227 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1228 boolean_t set_PG_ZERO)
1232 m->flags |= PG_ZERO;
1234 m->flags &= ~PG_ZERO;
1235 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1239 * Decrements a page table page's wire count, which is used to record the
1240 * number of valid page table entries within the page. If the wire count
1241 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1242 * page table page was unmapped and FALSE otherwise.
1244 static inline boolean_t
1245 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1249 if (m->wire_count == 0) {
1250 _pmap_unwire_l3(pmap, va, m, free);
1257 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1260 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1262 * unmap the page table page
1264 if (m->pindex >= (NUL2E + NUL1E)) {
1268 l0 = pmap_l0(pmap, va);
1269 pmap_load_clear(l0);
1271 } else if (m->pindex >= NUL2E) {
1275 l1 = pmap_l1(pmap, va);
1276 pmap_load_clear(l1);
1282 l2 = pmap_l2(pmap, va);
1283 pmap_load_clear(l2);
1286 pmap_resident_count_dec(pmap, 1);
1287 if (m->pindex < NUL2E) {
1288 /* We just released an l3, unhold the matching l2 */
1289 pd_entry_t *l1, tl1;
1292 l1 = pmap_l1(pmap, va);
1293 tl1 = pmap_load(l1);
1294 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1295 pmap_unwire_l3(pmap, va, l2pg, free);
1296 } else if (m->pindex < (NUL2E + NUL1E)) {
1297 /* We just released an l2, unhold the matching l1 */
1298 pd_entry_t *l0, tl0;
1301 l0 = pmap_l0(pmap, va);
1302 tl0 = pmap_load(l0);
1303 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1304 pmap_unwire_l3(pmap, va, l1pg, free);
1306 pmap_invalidate_page(pmap, va);
1309 * This is a release store so that the ordinary store unmapping
1310 * the page table page is globally performed before TLB shoot-
1313 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
1316 * Put page on a list so that it is released after
1317 * *ALL* TLB shootdown is done
1319 pmap_add_delayed_free_list(m, free, TRUE);
1323 * After removing an l3 entry, this routine is used to
1324 * conditionally free the page, and manage the hold/wire counts.
1327 pmap_unuse_l3(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1328 struct spglist *free)
1332 if (va >= VM_MAXUSER_ADDRESS)
1334 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1335 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1336 return (pmap_unwire_l3(pmap, va, mpte, free));
1340 pmap_pinit0(pmap_t pmap)
1343 PMAP_LOCK_INIT(pmap);
1344 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1345 pmap->pm_l0 = kernel_pmap->pm_l0;
1349 pmap_pinit(pmap_t pmap)
1355 * allocate the l0 page
1357 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1358 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1361 l0phys = VM_PAGE_TO_PHYS(l0pt);
1362 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1364 if ((l0pt->flags & PG_ZERO) == 0)
1365 pagezero(pmap->pm_l0);
1367 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1373 * This routine is called if the desired page table page does not exist.
1375 * If page table page allocation fails, this routine may sleep before
1376 * returning NULL. It sleeps only if a lock pointer was given.
1378 * Note: If a page allocation fails at page table level two or three,
1379 * one or two pages may be held during the wait, only to be released
1380 * afterwards. This conservative approach is easily argued to avoid
1384 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1386 vm_page_t m, l1pg, l2pg;
1388 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1391 * Allocate a page table page.
1393 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1394 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1395 if (lockp != NULL) {
1396 RELEASE_PV_LIST_LOCK(lockp);
1398 rw_runlock(&pvh_global_lock);
1400 rw_rlock(&pvh_global_lock);
1405 * Indicate the need to retry. While waiting, the page table
1406 * page may have been allocated.
1410 if ((m->flags & PG_ZERO) == 0)
1414 * Map the pagetable page into the process address space, if
1415 * it isn't already there.
1418 if (ptepindex >= (NUL2E + NUL1E)) {
1420 vm_pindex_t l0index;
1422 l0index = ptepindex - (NUL2E + NUL1E);
1423 l0 = &pmap->pm_l0[l0index];
1424 pmap_load_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1426 } else if (ptepindex >= NUL2E) {
1427 vm_pindex_t l0index, l1index;
1428 pd_entry_t *l0, *l1;
1431 l1index = ptepindex - NUL2E;
1432 l0index = l1index >> L0_ENTRIES_SHIFT;
1434 l0 = &pmap->pm_l0[l0index];
1435 tl0 = pmap_load(l0);
1437 /* recurse for allocating page dir */
1438 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1441 /* XXX: release mem barrier? */
1442 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1443 vm_page_free_zero(m);
1447 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1451 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1452 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1453 pmap_load_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1456 vm_pindex_t l0index, l1index;
1457 pd_entry_t *l0, *l1, *l2;
1458 pd_entry_t tl0, tl1;
1460 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1461 l0index = l1index >> L0_ENTRIES_SHIFT;
1463 l0 = &pmap->pm_l0[l0index];
1464 tl0 = pmap_load(l0);
1466 /* recurse for allocating page dir */
1467 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1470 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1471 vm_page_free_zero(m);
1474 tl0 = pmap_load(l0);
1475 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1476 l1 = &l1[l1index & Ln_ADDR_MASK];
1478 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1479 l1 = &l1[l1index & Ln_ADDR_MASK];
1480 tl1 = pmap_load(l1);
1482 /* recurse for allocating page dir */
1483 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1486 /* XXX: release mem barrier? */
1487 atomic_subtract_int(
1488 &vm_cnt.v_wire_count, 1);
1489 vm_page_free_zero(m);
1493 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1498 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1499 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1500 pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1504 pmap_resident_count_inc(pmap, 1);
1510 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1512 vm_pindex_t ptepindex;
1513 pd_entry_t *pde, tpde;
1518 * Calculate pagetable page index
1520 ptepindex = pmap_l2_pindex(va);
1523 * Get the page directory entry
1525 pde = pmap_pde(pmap, va, &lvl);
1528 * If the page table page is mapped, we just increment the hold count,
1529 * and activate it. If we get a level 2 pde it will point to a level 3
1533 tpde = pmap_load(pde);
1535 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1542 * Here if the pte page isn't mapped, or if it has been deallocated.
1544 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1545 if (m == NULL && lockp != NULL)
1552 /***************************************************
1553 * Pmap allocation/deallocation routines.
1554 ***************************************************/
1557 * Release any resources held by the given physical map.
1558 * Called when a pmap initialized by pmap_pinit is being released.
1559 * Should only be called if the map contains no valid mappings.
1562 pmap_release(pmap_t pmap)
1566 KASSERT(pmap->pm_stats.resident_count == 0,
1567 ("pmap_release: pmap resident count %ld != 0",
1568 pmap->pm_stats.resident_count));
1570 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1573 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1574 vm_page_free_zero(m);
1579 kvm_size(SYSCTL_HANDLER_ARGS)
1581 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1583 return sysctl_handle_long(oidp, &ksize, 0, req);
1585 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1586 0, 0, kvm_size, "LU", "Size of KVM");
1589 kvm_free(SYSCTL_HANDLER_ARGS)
1591 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1593 return sysctl_handle_long(oidp, &kfree, 0, req);
1595 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1596 0, 0, kvm_free, "LU", "Amount of KVM free");
1600 * grow the number of kernel page table entries, if needed
1603 pmap_growkernel(vm_offset_t addr)
1607 pd_entry_t *l0, *l1, *l2;
1609 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1611 addr = roundup2(addr, L2_SIZE);
1612 if (addr - 1 >= kernel_map->max_offset)
1613 addr = kernel_map->max_offset;
1614 while (kernel_vm_end < addr) {
1615 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1616 KASSERT(pmap_load(l0) != 0,
1617 ("pmap_growkernel: No level 0 kernel entry"));
1619 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1620 if (pmap_load(l1) == 0) {
1621 /* We need a new PDP entry */
1622 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1623 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1624 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1626 panic("pmap_growkernel: no memory to grow kernel");
1627 if ((nkpg->flags & PG_ZERO) == 0)
1628 pmap_zero_page(nkpg);
1629 paddr = VM_PAGE_TO_PHYS(nkpg);
1630 pmap_load_store(l1, paddr | L1_TABLE);
1632 continue; /* try again */
1634 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1635 if ((pmap_load(l2) & ATTR_AF) != 0) {
1636 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1637 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1638 kernel_vm_end = kernel_map->max_offset;
1644 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1645 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1648 panic("pmap_growkernel: no memory to grow kernel");
1649 if ((nkpg->flags & PG_ZERO) == 0)
1650 pmap_zero_page(nkpg);
1651 paddr = VM_PAGE_TO_PHYS(nkpg);
1652 pmap_load_store(l2, paddr | L2_TABLE);
1654 pmap_invalidate_page(kernel_pmap, kernel_vm_end);
1656 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1657 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1658 kernel_vm_end = kernel_map->max_offset;
1665 /***************************************************
1666 * page management routines.
1667 ***************************************************/
1669 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1670 CTASSERT(_NPCM == 3);
1671 CTASSERT(_NPCPV == 168);
1673 static __inline struct pv_chunk *
1674 pv_to_chunk(pv_entry_t pv)
1677 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1680 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1682 #define PC_FREE0 0xfffffffffffffffful
1683 #define PC_FREE1 0xfffffffffffffffful
1684 #define PC_FREE2 0x000000fffffffffful
1686 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1690 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1692 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1693 "Current number of pv entry chunks");
1694 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1695 "Current number of pv entry chunks allocated");
1696 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1697 "Current number of pv entry chunks frees");
1698 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1699 "Number of times tried to get a chunk page but failed.");
1701 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1702 static int pv_entry_spare;
1704 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1705 "Current number of pv entry frees");
1706 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1707 "Current number of pv entry allocs");
1708 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1709 "Current number of pv entries");
1710 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1711 "Current number of spare pv entries");
1716 * We are in a serious low memory condition. Resort to
1717 * drastic measures to free some pages so we can allocate
1718 * another pv entry chunk.
1720 * Returns NULL if PV entries were reclaimed from the specified pmap.
1722 * We do not, however, unmap 2mpages because subsequent accesses will
1723 * allocate per-page pv entries until repromotion occurs, thereby
1724 * exacerbating the shortage of free pv entries.
1727 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1730 panic("ARM64TODO: reclaim_pv_chunk");
1734 * free the pv_entry back to the free list
1737 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1739 struct pv_chunk *pc;
1740 int idx, field, bit;
1742 rw_assert(&pvh_global_lock, RA_LOCKED);
1743 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1744 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
1745 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
1746 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
1747 pc = pv_to_chunk(pv);
1748 idx = pv - &pc->pc_pventry[0];
1751 pc->pc_map[field] |= 1ul << bit;
1752 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
1753 pc->pc_map[2] != PC_FREE2) {
1754 /* 98% of the time, pc is already at the head of the list. */
1755 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
1756 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1757 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1761 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1766 free_pv_chunk(struct pv_chunk *pc)
1770 mtx_lock(&pv_chunks_mutex);
1771 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1772 mtx_unlock(&pv_chunks_mutex);
1773 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1774 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1775 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1776 /* entire chunk is free, return it */
1777 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1778 dump_drop_page(m->phys_addr);
1779 vm_page_unwire(m, PQ_NONE);
1784 * Returns a new PV entry, allocating a new PV chunk from the system when
1785 * needed. If this PV chunk allocation fails and a PV list lock pointer was
1786 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
1789 * The given PV list lock may be released.
1792 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
1796 struct pv_chunk *pc;
1799 rw_assert(&pvh_global_lock, RA_LOCKED);
1800 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1801 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
1803 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1805 for (field = 0; field < _NPCM; field++) {
1806 if (pc->pc_map[field]) {
1807 bit = ffsl(pc->pc_map[field]) - 1;
1811 if (field < _NPCM) {
1812 pv = &pc->pc_pventry[field * 64 + bit];
1813 pc->pc_map[field] &= ~(1ul << bit);
1814 /* If this was the last item, move it to tail */
1815 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
1816 pc->pc_map[2] == 0) {
1817 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1818 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
1821 PV_STAT(atomic_add_long(&pv_entry_count, 1));
1822 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
1826 /* No free items, allocate another chunk */
1827 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1830 if (lockp == NULL) {
1831 PV_STAT(pc_chunk_tryfail++);
1834 m = reclaim_pv_chunk(pmap, lockp);
1838 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
1839 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
1840 dump_add_page(m->phys_addr);
1841 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
1843 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
1844 pc->pc_map[1] = PC_FREE1;
1845 pc->pc_map[2] = PC_FREE2;
1846 mtx_lock(&pv_chunks_mutex);
1847 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
1848 mtx_unlock(&pv_chunks_mutex);
1849 pv = &pc->pc_pventry[0];
1850 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1851 PV_STAT(atomic_add_long(&pv_entry_count, 1));
1852 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
1857 * First find and then remove the pv entry for the specified pmap and virtual
1858 * address from the specified pv list. Returns the pv entry if found and NULL
1859 * otherwise. This operation can be performed on pv lists for either 4KB or
1860 * 2MB page mappings.
1862 static __inline pv_entry_t
1863 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1867 rw_assert(&pvh_global_lock, RA_LOCKED);
1868 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
1869 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
1870 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
1879 * First find and then destroy the pv entry for the specified pmap and virtual
1880 * address. This operation can be performed on pv lists for either 4KB or 2MB
1884 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1888 pv = pmap_pvh_remove(pvh, pmap, va);
1889 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
1890 free_pv_entry(pmap, pv);
1894 * Conditionally create the PV entry for a 4KB page mapping if the required
1895 * memory can be allocated without resorting to reclamation.
1898 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
1899 struct rwlock **lockp)
1903 rw_assert(&pvh_global_lock, RA_LOCKED);
1904 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1905 /* Pass NULL instead of the lock pointer to disable reclamation. */
1906 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
1908 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1909 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
1917 * pmap_remove_l3: do the things to unmap a page in a process
1920 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
1921 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
1926 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1927 if (pmap_is_current(pmap) && pmap_l3_valid_cacheable(pmap_load(l3)))
1928 cpu_dcache_wb_range(va, L3_SIZE);
1929 old_l3 = pmap_load_clear(l3);
1931 pmap_invalidate_page(pmap, va);
1932 if (old_l3 & ATTR_SW_WIRED)
1933 pmap->pm_stats.wired_count -= 1;
1934 pmap_resident_count_dec(pmap, 1);
1935 if (old_l3 & ATTR_SW_MANAGED) {
1936 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
1937 if (pmap_page_dirty(old_l3))
1939 if (old_l3 & ATTR_AF)
1940 vm_page_aflag_set(m, PGA_REFERENCED);
1941 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1942 pmap_pvh_free(&m->md, pmap, va);
1944 return (pmap_unuse_l3(pmap, va, l2e, free));
1948 * Remove the given range of addresses from the specified map.
1950 * It is assumed that the start and end are properly
1951 * rounded to the page size.
1954 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1956 struct rwlock *lock;
1957 vm_offset_t va, va_next;
1958 pd_entry_t *l0, *l1, *l2;
1959 pt_entry_t l3_paddr, *l3;
1960 struct spglist free;
1964 * Perform an unsynchronized read. This is, however, safe.
1966 if (pmap->pm_stats.resident_count == 0)
1972 rw_rlock(&pvh_global_lock);
1976 for (; sva < eva; sva = va_next) {
1978 if (pmap->pm_stats.resident_count == 0)
1981 l0 = pmap_l0(pmap, sva);
1982 if (pmap_load(l0) == 0) {
1983 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
1989 l1 = pmap_l0_to_l1(l0, sva);
1990 if (pmap_load(l1) == 0) {
1991 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
1998 * Calculate index for next page table.
2000 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2004 l2 = pmap_l1_to_l2(l1, sva);
2008 l3_paddr = pmap_load(l2);
2011 * Weed out invalid mappings.
2013 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2017 * Limit our scan to either the end of the va represented
2018 * by the current page table page, or to the end of the
2019 * range being removed.
2025 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2028 panic("l3 == NULL");
2029 if (pmap_load(l3) == 0) {
2030 if (va != va_next) {
2031 pmap_invalidate_range(pmap, va, sva);
2038 if (pmap_remove_l3(pmap, l3, sva, l3_paddr, &free,
2045 pmap_invalidate_range(pmap, va, sva);
2050 pmap_invalidate_all(pmap);
2051 rw_runlock(&pvh_global_lock);
2053 pmap_free_zero_pages(&free);
2057 * Routine: pmap_remove_all
2059 * Removes this physical page from
2060 * all physical maps in which it resides.
2061 * Reflects back modify bits to the pager.
2064 * Original versions of this routine were very
2065 * inefficient because they iteratively called
2066 * pmap_remove (slow...)
2070 pmap_remove_all(vm_page_t m)
2074 pd_entry_t *pde, tpde;
2075 pt_entry_t *pte, tpte;
2076 struct spglist free;
2079 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2080 ("pmap_remove_all: page %p is not managed", m));
2082 rw_wlock(&pvh_global_lock);
2083 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2086 pmap_resident_count_dec(pmap, 1);
2088 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2089 KASSERT(pde != NULL,
2090 ("pmap_remove_all: no page directory entry found"));
2092 ("pmap_remove_all: invalid pde level %d", lvl));
2093 tpde = pmap_load(pde);
2095 pte = pmap_l2_to_l3(pde, pv->pv_va);
2096 tpte = pmap_load(pte);
2097 if (pmap_is_current(pmap) &&
2098 pmap_l3_valid_cacheable(tpte))
2099 cpu_dcache_wb_range(pv->pv_va, L3_SIZE);
2100 pmap_load_clear(pte);
2102 pmap_invalidate_page(pmap, pv->pv_va);
2103 if (tpte & ATTR_SW_WIRED)
2104 pmap->pm_stats.wired_count--;
2105 if ((tpte & ATTR_AF) != 0)
2106 vm_page_aflag_set(m, PGA_REFERENCED);
2109 * Update the vm_page_t clean and reference bits.
2111 if (pmap_page_dirty(tpte))
2113 pmap_unuse_l3(pmap, pv->pv_va, tpde, &free);
2114 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2116 free_pv_entry(pmap, pv);
2119 vm_page_aflag_clear(m, PGA_WRITEABLE);
2120 rw_wunlock(&pvh_global_lock);
2121 pmap_free_zero_pages(&free);
2125 * Set the physical protection on the
2126 * specified range of this map as requested.
2129 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2131 vm_offset_t va, va_next;
2132 pd_entry_t *l0, *l1, *l2;
2133 pt_entry_t *l3p, l3;
2135 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2136 pmap_remove(pmap, sva, eva);
2140 if ((prot & VM_PROT_WRITE) == VM_PROT_WRITE)
2144 for (; sva < eva; sva = va_next) {
2146 l0 = pmap_l0(pmap, sva);
2147 if (pmap_load(l0) == 0) {
2148 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2154 l1 = pmap_l0_to_l1(l0, sva);
2155 if (pmap_load(l1) == 0) {
2156 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2162 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2166 l2 = pmap_l1_to_l2(l1, sva);
2167 if (l2 == NULL || (pmap_load(l2) & ATTR_DESCR_MASK) != L2_TABLE)
2174 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2176 l3 = pmap_load(l3p);
2177 if (pmap_l3_valid(l3)) {
2178 pmap_set(l3p, ATTR_AP(ATTR_AP_RO));
2180 /* XXX: Use pmap_invalidate_range */
2181 pmap_invalidate_page(pmap, va);
2187 /* TODO: Only invalidate entries we are touching */
2188 pmap_invalidate_all(pmap);
2192 * Insert the given physical page (p) at
2193 * the specified virtual address (v) in the
2194 * target physical map with the protection requested.
2196 * If specified, the page will be wired down, meaning
2197 * that the related pte can not be reclaimed.
2199 * NB: This is the only routine which MAY NOT lazy-evaluate
2200 * or lose information. That is, this routine must actually
2201 * insert this page into the given map NOW.
2204 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2205 u_int flags, int8_t psind __unused)
2207 struct rwlock *lock;
2209 pt_entry_t new_l3, orig_l3;
2212 vm_paddr_t opa, pa, l1_pa, l2_pa, l3_pa;
2213 vm_page_t mpte, om, l1_m, l2_m, l3_m;
2217 va = trunc_page(va);
2218 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2219 VM_OBJECT_ASSERT_LOCKED(m->object);
2220 pa = VM_PAGE_TO_PHYS(m);
2221 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
2223 if ((prot & VM_PROT_WRITE) == 0)
2224 new_l3 |= ATTR_AP(ATTR_AP_RO);
2225 if ((flags & PMAP_ENTER_WIRED) != 0)
2226 new_l3 |= ATTR_SW_WIRED;
2227 if ((va >> 63) == 0)
2228 new_l3 |= ATTR_AP(ATTR_AP_USER);
2230 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
2235 rw_rlock(&pvh_global_lock);
2238 if (va < VM_MAXUSER_ADDRESS) {
2239 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
2240 mpte = pmap_alloc_l3(pmap, va, nosleep ? NULL : &lock);
2241 if (mpte == NULL && nosleep) {
2242 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
2245 rw_runlock(&pvh_global_lock);
2247 return (KERN_RESOURCE_SHORTAGE);
2249 pde = pmap_pde(pmap, va, &lvl);
2250 KASSERT(pde != NULL,
2251 ("pmap_enter: Invalid page entry, va: 0x%lx", va));
2253 ("pmap_enter: Invalid level %d", lvl));
2255 l3 = pmap_l2_to_l3(pde, va);
2257 pde = pmap_pde(pmap, va, &lvl);
2259 * If we get a level 2 pde it must point to a level 3 entry
2260 * otherwise we will need to create the intermediate tables
2266 /* Get the l0 pde to update */
2267 pde = pmap_l0(pmap, va);
2268 KASSERT(pde != NULL, ("..."));
2270 l1_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2271 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2274 panic("pmap_enter: l1 pte_m == NULL");
2275 if ((l1_m->flags & PG_ZERO) == 0)
2276 pmap_zero_page(l1_m);
2278 l1_pa = VM_PAGE_TO_PHYS(l1_m);
2279 pmap_load_store(pde, l1_pa | L0_TABLE);
2283 /* Get the l1 pde to update */
2284 pde = pmap_l1_to_l2(pde, va);
2285 KASSERT(pde != NULL, ("..."));
2287 l2_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2288 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2291 panic("pmap_enter: l2 pte_m == NULL");
2292 if ((l2_m->flags & PG_ZERO) == 0)
2293 pmap_zero_page(l2_m);
2295 l2_pa = VM_PAGE_TO_PHYS(l2_m);
2296 pmap_load_store(pde, l2_pa | L1_TABLE);
2300 /* Get the l2 pde to update */
2301 pde = pmap_l1_to_l2(pde, va);
2303 l3_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2304 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2307 panic("pmap_enter: l3 pte_m == NULL");
2308 if ((l3_m->flags & PG_ZERO) == 0)
2309 pmap_zero_page(l3_m);
2311 l3_pa = VM_PAGE_TO_PHYS(l3_m);
2312 pmap_load_store(pde, l3_pa | L2_TABLE);
2317 l3 = pmap_l2_to_l3(pde, va);
2318 pmap_invalidate_page(pmap, va);
2322 orig_l3 = pmap_load(l3);
2323 opa = orig_l3 & ~ATTR_MASK;
2326 * Is the specified virtual address already mapped?
2328 if (pmap_l3_valid(orig_l3)) {
2330 * Wiring change, just update stats. We don't worry about
2331 * wiring PT pages as they remain resident as long as there
2332 * are valid mappings in them. Hence, if a user page is wired,
2333 * the PT page will be also.
2335 if ((flags & PMAP_ENTER_WIRED) != 0 &&
2336 (orig_l3 & ATTR_SW_WIRED) == 0)
2337 pmap->pm_stats.wired_count++;
2338 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
2339 (orig_l3 & ATTR_SW_WIRED) != 0)
2340 pmap->pm_stats.wired_count--;
2343 * Remove the extra PT page reference.
2347 KASSERT(mpte->wire_count > 0,
2348 ("pmap_enter: missing reference to page table page,"
2353 * Has the physical page changed?
2357 * No, might be a protection or wiring change.
2359 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
2360 new_l3 |= ATTR_SW_MANAGED;
2361 if ((new_l3 & ATTR_AP(ATTR_AP_RW)) ==
2362 ATTR_AP(ATTR_AP_RW)) {
2363 vm_page_aflag_set(m, PGA_WRITEABLE);
2369 /* Flush the cache, there might be uncommitted data in it */
2370 if (pmap_is_current(pmap) && pmap_l3_valid_cacheable(orig_l3))
2371 cpu_dcache_wb_range(va, L3_SIZE);
2374 * Increment the counters.
2376 if ((new_l3 & ATTR_SW_WIRED) != 0)
2377 pmap->pm_stats.wired_count++;
2378 pmap_resident_count_inc(pmap, 1);
2381 * Enter on the PV list if part of our managed memory.
2383 if ((m->oflags & VPO_UNMANAGED) == 0) {
2384 new_l3 |= ATTR_SW_MANAGED;
2385 pv = get_pv_entry(pmap, &lock);
2387 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
2388 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2390 if ((new_l3 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
2391 vm_page_aflag_set(m, PGA_WRITEABLE);
2395 * Update the L3 entry.
2399 orig_l3 = pmap_load_store(l3, new_l3);
2401 opa = orig_l3 & ~ATTR_MASK;
2404 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
2405 om = PHYS_TO_VM_PAGE(opa);
2406 if (pmap_page_dirty(orig_l3))
2408 if ((orig_l3 & ATTR_AF) != 0)
2409 vm_page_aflag_set(om, PGA_REFERENCED);
2410 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
2411 pmap_pvh_free(&om->md, pmap, va);
2413 } else if (pmap_page_dirty(orig_l3)) {
2414 if ((orig_l3 & ATTR_SW_MANAGED) != 0)
2418 pmap_load_store(l3, new_l3);
2421 pmap_invalidate_page(pmap, va);
2422 if ((pmap != pmap_kernel()) && (pmap == &curproc->p_vmspace->vm_pmap))
2423 cpu_icache_sync_range(va, PAGE_SIZE);
2427 rw_runlock(&pvh_global_lock);
2429 return (KERN_SUCCESS);
2433 * Maps a sequence of resident pages belonging to the same object.
2434 * The sequence begins with the given page m_start. This page is
2435 * mapped at the given virtual address start. Each subsequent page is
2436 * mapped at a virtual address that is offset from start by the same
2437 * amount as the page is offset from m_start within the object. The
2438 * last page in the sequence is the page with the largest offset from
2439 * m_start that can be mapped at a virtual address less than the given
2440 * virtual address end. Not every virtual page between start and end
2441 * is mapped; only those for which a resident page exists with the
2442 * corresponding offset from m_start are mapped.
2445 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
2446 vm_page_t m_start, vm_prot_t prot)
2448 struct rwlock *lock;
2451 vm_pindex_t diff, psize;
2453 VM_OBJECT_ASSERT_LOCKED(m_start->object);
2455 psize = atop(end - start);
2459 rw_rlock(&pvh_global_lock);
2461 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2462 va = start + ptoa(diff);
2463 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte, &lock);
2464 m = TAILQ_NEXT(m, listq);
2468 rw_runlock(&pvh_global_lock);
2473 * this code makes some *MAJOR* assumptions:
2474 * 1. Current pmap & pmap exists.
2477 * 4. No page table pages.
2478 * but is *MUCH* faster than pmap_enter...
2482 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
2484 struct rwlock *lock;
2487 rw_rlock(&pvh_global_lock);
2489 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
2492 rw_runlock(&pvh_global_lock);
2497 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
2498 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
2500 struct spglist free;
2506 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
2507 (m->oflags & VPO_UNMANAGED) != 0,
2508 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
2509 rw_assert(&pvh_global_lock, RA_LOCKED);
2510 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2512 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
2514 * In the case that a page table page is not
2515 * resident, we are creating it here.
2517 if (va < VM_MAXUSER_ADDRESS) {
2518 vm_pindex_t l2pindex;
2521 * Calculate pagetable page index
2523 l2pindex = pmap_l2_pindex(va);
2524 if (mpte && (mpte->pindex == l2pindex)) {
2530 pde = pmap_pde(pmap, va, &lvl);
2533 * If the page table page is mapped, we just increment
2534 * the hold count, and activate it. Otherwise, we
2535 * attempt to allocate a page table page. If this
2536 * attempt fails, we don't retry. Instead, we give up.
2538 if (lvl == 2 && pmap_load(pde) != 0) {
2540 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
2544 * Pass NULL instead of the PV list lock
2545 * pointer, because we don't intend to sleep.
2547 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
2552 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
2553 l3 = &l3[pmap_l3_index(va)];
2556 pde = pmap_pde(kernel_pmap, va, &lvl);
2557 KASSERT(pde != NULL,
2558 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
2561 ("pmap_enter_quick_locked: Invalid level %d", lvl));
2562 l3 = pmap_l2_to_l3(pde, va);
2565 if (pmap_load(l3) != 0) {
2574 * Enter on the PV list if part of our managed memory.
2576 if ((m->oflags & VPO_UNMANAGED) == 0 &&
2577 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
2580 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
2581 pmap_invalidate_page(pmap, va);
2582 pmap_free_zero_pages(&free);
2590 * Increment counters
2592 pmap_resident_count_inc(pmap, 1);
2594 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
2595 ATTR_AP(ATTR_AP_RW) | L3_PAGE;
2598 * Now validate mapping with RO protection
2600 if ((m->oflags & VPO_UNMANAGED) == 0)
2601 pa |= ATTR_SW_MANAGED;
2602 pmap_load_store(l3, pa);
2604 pmap_invalidate_page(pmap, va);
2609 * This code maps large physical mmap regions into the
2610 * processor address space. Note that some shortcuts
2611 * are taken, but the code works.
2614 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
2615 vm_pindex_t pindex, vm_size_t size)
2618 VM_OBJECT_ASSERT_WLOCKED(object);
2619 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2620 ("pmap_object_init_pt: non-device object"));
2624 * Clear the wired attribute from the mappings for the specified range of
2625 * addresses in the given pmap. Every valid mapping within that range
2626 * must have the wired attribute set. In contrast, invalid mappings
2627 * cannot have the wired attribute set, so they are ignored.
2629 * The wired attribute of the page table entry is not a hardware feature,
2630 * so there is no need to invalidate any TLB entries.
2633 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2635 vm_offset_t va_next;
2636 pd_entry_t *l0, *l1, *l2;
2638 boolean_t pv_lists_locked;
2640 pv_lists_locked = FALSE;
2642 for (; sva < eva; sva = va_next) {
2643 l0 = pmap_l0(pmap, sva);
2644 if (pmap_load(l0) == 0) {
2645 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2651 l1 = pmap_l0_to_l1(l0, sva);
2652 if (pmap_load(l1) == 0) {
2653 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2659 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2663 l2 = pmap_l1_to_l2(l1, sva);
2664 if (pmap_load(l2) == 0)
2669 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2671 if (pmap_load(l3) == 0)
2673 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
2674 panic("pmap_unwire: l3 %#jx is missing "
2675 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
2678 * PG_W must be cleared atomically. Although the pmap
2679 * lock synchronizes access to PG_W, another processor
2680 * could be setting PG_M and/or PG_A concurrently.
2682 atomic_clear_long(l3, ATTR_SW_WIRED);
2683 pmap->pm_stats.wired_count--;
2686 if (pv_lists_locked)
2687 rw_runlock(&pvh_global_lock);
2692 * Copy the range specified by src_addr/len
2693 * from the source map to the range dst_addr/len
2694 * in the destination map.
2696 * This routine is only advisory and need not do anything.
2700 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
2701 vm_offset_t src_addr)
2706 * pmap_zero_page zeros the specified hardware page by mapping
2707 * the page into KVM and using bzero to clear its contents.
2710 pmap_zero_page(vm_page_t m)
2712 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
2714 pagezero((void *)va);
2718 * pmap_zero_page_area zeros the specified hardware page by mapping
2719 * the page into KVM and using bzero to clear its contents.
2721 * off and size may not cover an area beyond a single hardware page.
2724 pmap_zero_page_area(vm_page_t m, int off, int size)
2726 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
2728 if (off == 0 && size == PAGE_SIZE)
2729 pagezero((void *)va);
2731 bzero((char *)va + off, size);
2735 * pmap_zero_page_idle zeros the specified hardware page by mapping
2736 * the page into KVM and using bzero to clear its contents. This
2737 * is intended to be called from the vm_pagezero process only and
2741 pmap_zero_page_idle(vm_page_t m)
2743 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
2745 pagezero((void *)va);
2749 * pmap_copy_page copies the specified (machine independent)
2750 * page by mapping the page into virtual memory and using
2751 * bcopy to copy the page, one machine dependent page at a
2755 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
2757 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
2758 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
2760 pagecopy((void *)src, (void *)dst);
2763 int unmapped_buf_allowed = 1;
2766 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
2767 vm_offset_t b_offset, int xfersize)
2771 vm_paddr_t p_a, p_b;
2772 vm_offset_t a_pg_offset, b_pg_offset;
2775 while (xfersize > 0) {
2776 a_pg_offset = a_offset & PAGE_MASK;
2777 m_a = ma[a_offset >> PAGE_SHIFT];
2778 p_a = m_a->phys_addr;
2779 b_pg_offset = b_offset & PAGE_MASK;
2780 m_b = mb[b_offset >> PAGE_SHIFT];
2781 p_b = m_b->phys_addr;
2782 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2783 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2784 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
2785 panic("!DMAP a %lx", p_a);
2787 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
2789 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
2790 panic("!DMAP b %lx", p_b);
2792 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
2794 bcopy(a_cp, b_cp, cnt);
2802 pmap_quick_enter_page(vm_page_t m)
2805 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
2809 pmap_quick_remove_page(vm_offset_t addr)
2814 * Returns true if the pmap's pv is one of the first
2815 * 16 pvs linked to from this page. This count may
2816 * be changed upwards or downwards in the future; it
2817 * is only necessary that true be returned for a small
2818 * subset of pmaps for proper page aging.
2821 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
2823 struct rwlock *lock;
2828 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2829 ("pmap_page_exists_quick: page %p is not managed", m));
2831 rw_rlock(&pvh_global_lock);
2832 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2834 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
2835 if (PV_PMAP(pv) == pmap) {
2844 rw_runlock(&pvh_global_lock);
2849 * pmap_page_wired_mappings:
2851 * Return the number of managed mappings to the given physical page
2855 pmap_page_wired_mappings(vm_page_t m)
2857 struct rwlock *lock;
2861 int count, lvl, md_gen;
2863 if ((m->oflags & VPO_UNMANAGED) != 0)
2865 rw_rlock(&pvh_global_lock);
2866 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2870 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
2872 if (!PMAP_TRYLOCK(pmap)) {
2873 md_gen = m->md.pv_gen;
2877 if (md_gen != m->md.pv_gen) {
2882 pte = pmap_pte(pmap, pv->pv_va, &lvl);
2883 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
2888 rw_runlock(&pvh_global_lock);
2893 * Destroy all managed, non-wired mappings in the given user-space
2894 * pmap. This pmap cannot be active on any processor besides the
2897 * This function cannot be applied to the kernel pmap. Moreover, it
2898 * is not intended for general use. It is only to be used during
2899 * process termination. Consequently, it can be implemented in ways
2900 * that make it faster than pmap_remove(). First, it can more quickly
2901 * destroy mappings by iterating over the pmap's collection of PV
2902 * entries, rather than searching the page table. Second, it doesn't
2903 * have to test and clear the page table entries atomically, because
2904 * no processor is currently accessing the user address space. In
2905 * particular, a page table entry's dirty bit won't change state once
2906 * this function starts.
2909 pmap_remove_pages(pmap_t pmap)
2912 pt_entry_t *pte, tpte;
2913 struct spglist free;
2916 struct pv_chunk *pc, *npc;
2917 struct rwlock *lock;
2919 uint64_t inuse, bitmask;
2920 int allfree, field, freed, idx, lvl;
2926 rw_rlock(&pvh_global_lock);
2928 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
2931 for (field = 0; field < _NPCM; field++) {
2932 inuse = ~pc->pc_map[field] & pc_freemask[field];
2933 while (inuse != 0) {
2934 bit = ffsl(inuse) - 1;
2935 bitmask = 1UL << bit;
2936 idx = field * 64 + bit;
2937 pv = &pc->pc_pventry[idx];
2940 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2941 KASSERT(pde != NULL,
2942 ("Attempting to remove an unmapped page"));
2944 ("Invalid page directory level: %d", lvl));
2946 pte = pmap_l2_to_l3(pde, pv->pv_va);
2947 KASSERT(pte != NULL,
2948 ("Attempting to remove an unmapped page"));
2950 tpte = pmap_load(pte);
2953 * We cannot remove wired pages from a process' mapping at this time
2955 if (tpte & ATTR_SW_WIRED) {
2960 pa = tpte & ~ATTR_MASK;
2962 m = PHYS_TO_VM_PAGE(pa);
2963 KASSERT(m->phys_addr == pa,
2964 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
2965 m, (uintmax_t)m->phys_addr,
2968 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
2969 m < &vm_page_array[vm_page_array_size],
2970 ("pmap_remove_pages: bad pte %#jx",
2973 /* XXX: assumes tpte is level 3 */
2974 if (pmap_is_current(pmap) &&
2975 pmap_l3_valid_cacheable(tpte))
2976 cpu_dcache_wb_range(pv->pv_va, L3_SIZE);
2977 pmap_load_clear(pte);
2979 pmap_invalidate_page(pmap, pv->pv_va);
2982 * Update the vm_page_t clean/reference bits.
2984 if ((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
2987 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
2990 pc->pc_map[field] |= bitmask;
2992 pmap_resident_count_dec(pmap, 1);
2993 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2996 pmap_unuse_l3(pmap, pv->pv_va, pmap_load(pde),
3001 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3002 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3003 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3005 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3009 pmap_invalidate_all(pmap);
3012 rw_runlock(&pvh_global_lock);
3014 pmap_free_zero_pages(&free);
3018 * This is used to check if a page has been accessed or modified. As we
3019 * don't have a bit to see if it has been modified we have to assume it
3020 * has been if the page is read/write.
3023 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
3025 struct rwlock *lock;
3027 pt_entry_t *pte, mask, value;
3033 rw_rlock(&pvh_global_lock);
3034 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3037 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3039 if (!PMAP_TRYLOCK(pmap)) {
3040 md_gen = m->md.pv_gen;
3044 if (md_gen != m->md.pv_gen) {
3049 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3051 ("pmap_page_test_mappings: Invalid level %d", lvl));
3055 mask |= ATTR_AP_RW_BIT;
3056 value |= ATTR_AP(ATTR_AP_RW);
3059 mask |= ATTR_AF | ATTR_DESCR_MASK;
3060 value |= ATTR_AF | L3_PAGE;
3062 rv = (pmap_load(pte) & mask) == value;
3069 rw_runlock(&pvh_global_lock);
3076 * Return whether or not the specified physical page was modified
3077 * in any physical maps.
3080 pmap_is_modified(vm_page_t m)
3083 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3084 ("pmap_is_modified: page %p is not managed", m));
3087 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3088 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
3089 * is clear, no PTEs can have PG_M set.
3091 VM_OBJECT_ASSERT_WLOCKED(m->object);
3092 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3094 return (pmap_page_test_mappings(m, FALSE, TRUE));
3098 * pmap_is_prefaultable:
3100 * Return whether or not the specified virtual address is eligible
3104 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3112 pte = pmap_pte(pmap, addr, &lvl);
3113 if (pte != NULL && pmap_load(pte) != 0) {
3121 * pmap_is_referenced:
3123 * Return whether or not the specified physical page was referenced
3124 * in any physical maps.
3127 pmap_is_referenced(vm_page_t m)
3130 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3131 ("pmap_is_referenced: page %p is not managed", m));
3132 return (pmap_page_test_mappings(m, TRUE, FALSE));
3136 * Clear the write and modified bits in each of the given page's mappings.
3139 pmap_remove_write(vm_page_t m)
3142 struct rwlock *lock;
3144 pt_entry_t oldpte, *pte;
3147 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3148 ("pmap_remove_write: page %p is not managed", m));
3151 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3152 * set by another thread while the object is locked. Thus,
3153 * if PGA_WRITEABLE is clear, no page table entries need updating.
3155 VM_OBJECT_ASSERT_WLOCKED(m->object);
3156 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3158 rw_rlock(&pvh_global_lock);
3159 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3162 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3164 if (!PMAP_TRYLOCK(pmap)) {
3165 md_gen = m->md.pv_gen;
3169 if (md_gen != m->md.pv_gen) {
3175 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3177 oldpte = pmap_load(pte);
3178 if ((oldpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) {
3179 if (!atomic_cmpset_long(pte, oldpte,
3180 oldpte | ATTR_AP(ATTR_AP_RO)))
3182 if ((oldpte & ATTR_AF) != 0)
3184 pmap_invalidate_page(pmap, pv->pv_va);
3189 vm_page_aflag_clear(m, PGA_WRITEABLE);
3190 rw_runlock(&pvh_global_lock);
3193 static __inline boolean_t
3194 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
3200 #define PMAP_TS_REFERENCED_MAX 5
3203 * pmap_ts_referenced:
3205 * Return a count of reference bits for a page, clearing those bits.
3206 * It is not necessary for every reference bit to be cleared, but it
3207 * is necessary that 0 only be returned when there are truly no
3208 * reference bits set.
3210 * XXX: The exact number of bits to check and clear is a matter that
3211 * should be tested and standardized at some point in the future for
3212 * optimal aging of shared pages.
3215 pmap_ts_referenced(vm_page_t m)
3219 struct rwlock *lock;
3220 pd_entry_t *pde, tpde;
3221 pt_entry_t *pte, tpte;
3223 int cleared, md_gen, not_cleared, lvl;
3224 struct spglist free;
3226 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3227 ("pmap_ts_referenced: page %p is not managed", m));
3230 pa = VM_PAGE_TO_PHYS(m);
3231 lock = PHYS_TO_PV_LIST_LOCK(pa);
3232 rw_rlock(&pvh_global_lock);
3236 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
3243 if (!PMAP_TRYLOCK(pmap)) {
3244 md_gen = m->md.pv_gen;
3248 if (md_gen != m->md.pv_gen) {
3253 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3254 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
3256 ("pmap_ts_referenced: invalid pde level %d", lvl));
3257 tpde = pmap_load(pde);
3258 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
3259 ("pmap_ts_referenced: found an invalid l2 table"));
3260 pte = pmap_l2_to_l3(pde, pv->pv_va);
3261 tpte = pmap_load(pte);
3262 if ((tpte & ATTR_AF) != 0) {
3263 if (safe_to_clear_referenced(pmap, tpte)) {
3265 * TODO: We don't handle the access flag
3266 * at all. We need to be able to set it in
3267 * the exception handler.
3269 panic("ARM64TODO: safe_to_clear_referenced\n");
3270 } else if ((tpte & ATTR_SW_WIRED) == 0) {
3272 * Wired pages cannot be paged out so
3273 * doing accessed bit emulation for
3274 * them is wasted effort. We do the
3275 * hard work for unwired pages only.
3277 pmap_remove_l3(pmap, pte, pv->pv_va, tpde,
3279 pmap_invalidate_page(pmap, pv->pv_va);
3284 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
3285 ("inconsistent pv lock %p %p for page %p",
3286 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
3291 /* Rotate the PV list if it has more than one entry. */
3292 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
3293 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3294 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3297 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
3298 not_cleared < PMAP_TS_REFERENCED_MAX);
3301 rw_runlock(&pvh_global_lock);
3302 pmap_free_zero_pages(&free);
3303 return (cleared + not_cleared);
3307 * Apply the given advice to the specified range of addresses within the
3308 * given pmap. Depending on the advice, clear the referenced and/or
3309 * modified flags in each mapping and set the mapped page's dirty field.
3312 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
3317 * Clear the modify bits on the specified physical page.
3320 pmap_clear_modify(vm_page_t m)
3323 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3324 ("pmap_clear_modify: page %p is not managed", m));
3325 VM_OBJECT_ASSERT_WLOCKED(m->object);
3326 KASSERT(!vm_page_xbusied(m),
3327 ("pmap_clear_modify: page %p is exclusive busied", m));
3330 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
3331 * If the object containing the page is locked and the page is not
3332 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
3334 if ((m->aflags & PGA_WRITEABLE) == 0)
3337 /* ARM64TODO: We lack support for tracking if a page is modified */
3341 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
3344 return ((void *)PHYS_TO_DMAP(pa));
3348 pmap_unmapbios(vm_paddr_t pa, vm_size_t size)
3353 * Sets the memory attribute for the specified page.
3356 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
3359 m->md.pv_memattr = ma;
3362 * ARM64TODO: Implement the below (from the amd64 pmap)
3363 * If "m" is a normal page, update its direct mapping. This update
3364 * can be relied upon to perform any cache operations that are
3365 * required for data coherence.
3367 if ((m->flags & PG_FICTITIOUS) == 0 &&
3368 PHYS_IN_DMAP(VM_PAGE_TO_PHYS(m)))
3369 panic("ARM64TODO: pmap_page_set_memattr");
3373 * perform the pmap work for mincore
3376 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
3378 pd_entry_t *l1p, l1;
3379 pd_entry_t *l2p, l2;
3380 pt_entry_t *l3p, l3;
3391 l1p = pmap_l1(pmap, addr);
3392 if (l1p == NULL) /* No l1 */
3395 l1 = pmap_load(l1p);
3396 if ((l1 & ATTR_DESCR_MASK) == L1_INVAL)
3399 if ((l1 & ATTR_DESCR_MASK) == L1_BLOCK) {
3400 pa = (l1 & ~ATTR_MASK) | (addr & L1_OFFSET);
3401 managed = (l1 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
3402 val = MINCORE_SUPER | MINCORE_INCORE;
3403 if (pmap_page_dirty(l1))
3404 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3405 if ((l1 & ATTR_AF) == ATTR_AF)
3406 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3410 l2p = pmap_l1_to_l2(l1p, addr);
3411 if (l2p == NULL) /* No l2 */
3414 l2 = pmap_load(l2p);
3415 if ((l2 & ATTR_DESCR_MASK) == L2_INVAL)
3418 if ((l2 & ATTR_DESCR_MASK) == L2_BLOCK) {
3419 pa = (l2 & ~ATTR_MASK) | (addr & L2_OFFSET);
3420 managed = (l2 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
3421 val = MINCORE_SUPER | MINCORE_INCORE;
3422 if (pmap_page_dirty(l2))
3423 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3424 if ((l2 & ATTR_AF) == ATTR_AF)
3425 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3429 l3p = pmap_l2_to_l3(l2p, addr);
3430 if (l3p == NULL) /* No l3 */
3433 l3 = pmap_load(l2p);
3434 if ((l3 & ATTR_DESCR_MASK) == L3_INVAL)
3437 if ((l3 & ATTR_DESCR_MASK) == L3_PAGE) {
3438 pa = (l3 & ~ATTR_MASK) | (addr & L3_OFFSET);
3439 managed = (l3 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
3440 val = MINCORE_INCORE;
3441 if (pmap_page_dirty(l3))
3442 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3443 if ((l3 & ATTR_AF) == ATTR_AF)
3444 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3448 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
3449 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
3450 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
3451 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
3454 PA_UNLOCK_COND(*locked_pa);
3461 pmap_activate(struct thread *td)
3466 pmap = vmspace_pmap(td->td_proc->p_vmspace);
3467 td->td_pcb->pcb_l0addr = vtophys(pmap->pm_l0);
3468 __asm __volatile("msr ttbr0_el1, %0" : : "r"(td->td_pcb->pcb_l0addr));
3469 pmap_invalidate_all(pmap);
3474 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
3477 if (va >= VM_MIN_KERNEL_ADDRESS) {
3478 cpu_icache_sync_range(va, sz);
3483 /* Find the length of data in this page to flush */
3484 offset = va & PAGE_MASK;
3485 len = imin(PAGE_SIZE - offset, sz);
3488 /* Extract the physical address & find it in the DMAP */
3489 pa = pmap_extract(pmap, va);
3491 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
3493 /* Move to the next page */
3496 /* Set the length for the next iteration */
3497 len = imin(PAGE_SIZE, sz);
3503 * Increase the starting virtual address of the given mapping if a
3504 * different alignment might result in more superpage mappings.
3507 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
3508 vm_offset_t *addr, vm_size_t size)
3513 * Get the kernel virtual address of a set of physical pages. If there are
3514 * physical addresses not covered by the DMAP perform a transient mapping
3515 * that will be removed when calling pmap_unmap_io_transient.
3517 * \param page The pages the caller wishes to obtain the virtual
3518 * address on the kernel memory map.
3519 * \param vaddr On return contains the kernel virtual memory address
3520 * of the pages passed in the page parameter.
3521 * \param count Number of pages passed in.
3522 * \param can_fault TRUE if the thread using the mapped pages can take
3523 * page faults, FALSE otherwise.
3525 * \returns TRUE if the caller must call pmap_unmap_io_transient when
3526 * finished or FALSE otherwise.
3530 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
3531 boolean_t can_fault)
3534 boolean_t needs_mapping;
3538 * Allocate any KVA space that we need, this is done in a separate
3539 * loop to prevent calling vmem_alloc while pinned.
3541 needs_mapping = FALSE;
3542 for (i = 0; i < count; i++) {
3543 paddr = VM_PAGE_TO_PHYS(page[i]);
3544 if (__predict_false(paddr >= DMAP_MAX_PHYSADDR)) {
3545 error = vmem_alloc(kernel_arena, PAGE_SIZE,
3546 M_BESTFIT | M_WAITOK, &vaddr[i]);
3547 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3548 needs_mapping = TRUE;
3550 vaddr[i] = PHYS_TO_DMAP(paddr);
3554 /* Exit early if everything is covered by the DMAP */
3560 for (i = 0; i < count; i++) {
3561 paddr = VM_PAGE_TO_PHYS(page[i]);
3562 if (paddr >= DMAP_MAX_PHYSADDR) {
3564 "pmap_map_io_transient: TODO: Map out of DMAP data");
3568 return (needs_mapping);
3572 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
3573 boolean_t can_fault)
3580 for (i = 0; i < count; i++) {
3581 paddr = VM_PAGE_TO_PHYS(page[i]);
3582 if (paddr >= DMAP_MAX_PHYSADDR) {
3583 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");