2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
53 * Copyright (c) 2003 Networks Associates Technology, Inc.
54 * All rights reserved.
56 * This software was developed for the FreeBSD Project by Jake Burkholder,
57 * Safeport Network Services, and Network Associates Laboratories, the
58 * Security Research Division of Network Associates, Inc. under
59 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
60 * CHATS research program.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions
65 * 1. Redistributions of source code must retain the above copyright
66 * notice, this list of conditions and the following disclaimer.
67 * 2. Redistributions in binary form must reproduce the above copyright
68 * notice, this list of conditions and the following disclaimer in the
69 * documentation and/or other materials provided with the distribution.
71 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
72 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
74 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
77 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
78 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
79 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
80 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
84 #include <sys/cdefs.h>
86 * Manages physical address maps.
88 * Since the information managed by this module is
89 * also stored by the logical address mapping module,
90 * this module may throw away valid virtual-to-physical
91 * mappings at almost any time. However, invalidations
92 * of virtual-to-physical mappings must be done as
95 * In order to cope with hardware architectures which
96 * make virtual-to-physical map invalidates expensive,
97 * this module may delay invalidate or reduced protection
98 * operations until such time as they are actually
99 * necessary. This module is given full information as
100 * to which processors are currently using which maps,
101 * and to when physical maps must be made correct.
106 #include <sys/param.h>
107 #include <sys/asan.h>
108 #include <sys/bitstring.h>
110 #include <sys/systm.h>
111 #include <sys/kernel.h>
113 #include <sys/limits.h>
114 #include <sys/lock.h>
115 #include <sys/malloc.h>
116 #include <sys/mman.h>
117 #include <sys/msgbuf.h>
118 #include <sys/mutex.h>
119 #include <sys/physmem.h>
120 #include <sys/proc.h>
121 #include <sys/rwlock.h>
122 #include <sys/sbuf.h>
124 #include <sys/vmem.h>
125 #include <sys/vmmeter.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/_unrhdr.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/vm_pager.h>
140 #include <vm/vm_phys.h>
141 #include <vm/vm_radix.h>
142 #include <vm/vm_reserv.h>
143 #include <vm/vm_dumpset.h>
146 #include <machine/asan.h>
147 #include <machine/machdep.h>
148 #include <machine/md_var.h>
149 #include <machine/pcb.h>
152 #define PMAP_MEMDOM MAXMEMDOM
154 #define PMAP_MEMDOM 1
157 #define PMAP_ASSERT_STAGE1(pmap) MPASS((pmap)->pm_stage == PM_STAGE1)
158 #define PMAP_ASSERT_STAGE2(pmap) MPASS((pmap)->pm_stage == PM_STAGE2)
160 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
161 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
162 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
163 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
165 #define NUL0E L0_ENTRIES
166 #define NUL1E (NUL0E * NL1PG)
167 #define NUL2E (NUL1E * NL2PG)
170 #define PV_STAT(x) do { x ; } while (0)
173 #define PV_STAT(x) do { } while (0)
174 #define __pvused __unused
177 #define pmap_l0_pindex(v) (NUL2E + NUL1E + ((v) >> L0_SHIFT))
178 #define pmap_l1_pindex(v) (NUL2E + ((v) >> L1_SHIFT))
179 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
181 #ifdef __ARM_FEATURE_BTI_DEFAULT
182 #define ATTR_KERN_GP ATTR_S1_GP
184 #define ATTR_KERN_GP 0
186 #define PMAP_SAN_PTE_BITS (ATTR_DEFAULT | ATTR_S1_XN | ATTR_KERN_GP | \
187 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | ATTR_S1_AP(ATTR_S1_AP_RW))
189 struct pmap_large_md_page {
190 struct rwlock pv_lock;
191 struct md_page pv_page;
192 /* Pad to a power of 2, see pmap_init_pv_table(). */
196 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
197 #define pv_dummy pv_dummy_large.pv_page
198 __read_mostly static struct pmap_large_md_page *pv_table;
200 static struct pmap_large_md_page *
201 _pa_to_pmdp(vm_paddr_t pa)
203 struct vm_phys_seg *seg;
205 if ((seg = vm_phys_paddr_to_seg(pa)) != NULL)
206 return ((struct pmap_large_md_page *)seg->md_first +
207 pmap_l2_pindex(pa) - pmap_l2_pindex(seg->start));
211 static struct pmap_large_md_page *
212 pa_to_pmdp(vm_paddr_t pa)
214 struct pmap_large_md_page *pvd;
216 pvd = _pa_to_pmdp(pa);
218 panic("pa 0x%jx not within vm_phys_segs", (uintmax_t)pa);
222 static struct pmap_large_md_page *
223 page_to_pmdp(vm_page_t m)
225 struct vm_phys_seg *seg;
227 seg = &vm_phys_segs[m->segind];
228 return ((struct pmap_large_md_page *)seg->md_first +
229 pmap_l2_pindex(VM_PAGE_TO_PHYS(m)) - pmap_l2_pindex(seg->start));
232 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
233 #define page_to_pvh(m) (&(page_to_pmdp(m)->pv_page))
235 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
236 struct pmap_large_md_page *_pvd; \
237 struct rwlock *_lock; \
238 _pvd = _pa_to_pmdp(pa); \
239 if (__predict_false(_pvd == NULL)) \
240 _lock = &pv_dummy_large.pv_lock; \
242 _lock = &(_pvd->pv_lock); \
246 static struct rwlock *
247 VM_PAGE_TO_PV_LIST_LOCK(vm_page_t m)
249 if ((m->flags & PG_FICTITIOUS) == 0)
250 return (&page_to_pmdp(m)->pv_lock);
252 return (&pv_dummy_large.pv_lock);
255 #define CHANGE_PV_LIST_LOCK(lockp, new_lock) do { \
256 struct rwlock **_lockp = (lockp); \
257 struct rwlock *_new_lock = (new_lock); \
259 if (_new_lock != *_lockp) { \
260 if (*_lockp != NULL) \
261 rw_wunlock(*_lockp); \
262 *_lockp = _new_lock; \
267 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) \
268 CHANGE_PV_LIST_LOCK(lockp, PHYS_TO_PV_LIST_LOCK(pa))
270 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
271 CHANGE_PV_LIST_LOCK(lockp, VM_PAGE_TO_PV_LIST_LOCK(m))
273 #define RELEASE_PV_LIST_LOCK(lockp) do { \
274 struct rwlock **_lockp = (lockp); \
276 if (*_lockp != NULL) { \
277 rw_wunlock(*_lockp); \
283 * The presence of this flag indicates that the mapping is writeable.
284 * If the ATTR_S1_AP_RO bit is also set, then the mapping is clean, otherwise
285 * it is dirty. This flag may only be set on managed mappings.
287 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
288 * as a software managed bit.
290 #define ATTR_SW_DBM ATTR_DBM
292 struct pmap kernel_pmap_store;
294 /* Used for mapping ACPI memory before VM is initialized */
295 #define PMAP_PREINIT_MAPPING_COUNT 32
296 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
297 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
298 static int vm_initialized = 0; /* No need to use pre-init maps when set */
301 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
302 * Always map entire L2 block for simplicity.
303 * VA of L2 block = preinit_map_va + i * L2_SIZE
305 static struct pmap_preinit_mapping {
309 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
311 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
312 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
313 vm_offset_t kernel_vm_end = 0;
316 * Data for the pv entry allocation mechanism.
320 pc_to_domain(struct pv_chunk *pc)
322 return (vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
326 pc_to_domain(struct pv_chunk *pc __unused)
332 struct pv_chunks_list {
334 TAILQ_HEAD(pch, pv_chunk) pvc_list;
336 } __aligned(CACHE_LINE_SIZE);
338 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
340 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
341 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
342 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
344 extern pt_entry_t pagetable_l0_ttbr1[];
346 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
347 static vm_paddr_t physmap[PHYSMAP_SIZE];
348 static u_int physmap_idx;
350 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
351 "VM/pmap parameters");
353 #if PAGE_SIZE == PAGE_SIZE_4K
354 #define L1_BLOCKS_SUPPORTED 1
356 /* TODO: Make this dynamic when we support FEAT_LPA2 (TCR_EL1.DS == 1) */
357 #define L1_BLOCKS_SUPPORTED 0
360 #define PMAP_ASSERT_L1_BLOCKS_SUPPORTED MPASS(L1_BLOCKS_SUPPORTED)
363 * This ASID allocator uses a bit vector ("asid_set") to remember which ASIDs
364 * that it has currently allocated to a pmap, a cursor ("asid_next") to
365 * optimize its search for a free ASID in the bit vector, and an epoch number
366 * ("asid_epoch") to indicate when it has reclaimed all previously allocated
367 * ASIDs that are not currently active on a processor.
369 * The current epoch number is always in the range [0, INT_MAX). Negative
370 * numbers and INT_MAX are reserved for special cases that are described
379 struct mtx asid_set_mutex;
382 static struct asid_set asids;
383 static struct asid_set vmids;
385 static SYSCTL_NODE(_vm_pmap, OID_AUTO, asid, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
387 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, bits, CTLFLAG_RD, &asids.asid_bits, 0,
388 "The number of bits in an ASID");
389 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, next, CTLFLAG_RD, &asids.asid_next, 0,
390 "The last allocated ASID plus one");
391 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, epoch, CTLFLAG_RD, &asids.asid_epoch, 0,
392 "The current epoch number");
394 static SYSCTL_NODE(_vm_pmap, OID_AUTO, vmid, CTLFLAG_RD, 0, "VMID allocator");
395 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, bits, CTLFLAG_RD, &vmids.asid_bits, 0,
396 "The number of bits in an VMID");
397 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, next, CTLFLAG_RD, &vmids.asid_next, 0,
398 "The last allocated VMID plus one");
399 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, epoch, CTLFLAG_RD, &vmids.asid_epoch, 0,
400 "The current epoch number");
402 void (*pmap_clean_stage2_tlbi)(void);
403 void (*pmap_invalidate_vpipt_icache)(void);
404 void (*pmap_stage2_invalidate_range)(uint64_t, vm_offset_t, vm_offset_t, bool);
405 void (*pmap_stage2_invalidate_all)(uint64_t);
408 * A pmap's cookie encodes an ASID and epoch number. Cookies for reserved
409 * ASIDs have a negative epoch number, specifically, INT_MIN. Cookies for
410 * dynamically allocated ASIDs have a non-negative epoch number.
412 * An invalid ASID is represented by -1.
414 * There are two special-case cookie values: (1) COOKIE_FROM(-1, INT_MIN),
415 * which indicates that an ASID should never be allocated to the pmap, and
416 * (2) COOKIE_FROM(-1, INT_MAX), which indicates that an ASID should be
417 * allocated when the pmap is next activated.
419 #define COOKIE_FROM(asid, epoch) ((long)((u_int)(asid) | \
420 ((u_long)(epoch) << 32)))
421 #define COOKIE_TO_ASID(cookie) ((int)(cookie))
422 #define COOKIE_TO_EPOCH(cookie) ((int)((u_long)(cookie) >> 32))
424 #define TLBI_VA_SHIFT 12
425 #define TLBI_VA_MASK ((1ul << 44) - 1)
426 #define TLBI_VA(addr) (((addr) >> TLBI_VA_SHIFT) & TLBI_VA_MASK)
427 #define TLBI_VA_L3_INCR (L3_SIZE >> TLBI_VA_SHIFT)
429 static int __read_frequently superpages_enabled = 1;
430 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
431 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
432 "Are large page mappings enabled?");
435 * Internal flags for pmap_enter()'s helper functions.
437 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
438 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
440 TAILQ_HEAD(pv_chunklist, pv_chunk);
442 static void free_pv_chunk(struct pv_chunk *pc);
443 static void free_pv_chunk_batch(struct pv_chunklist *batch);
444 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
445 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
446 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
447 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
448 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
451 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
452 static bool pmap_activate_int(pmap_t pmap);
453 static void pmap_alloc_asid(pmap_t pmap);
454 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
455 vm_prot_t prot, int mode, bool skip_unmapped);
456 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
457 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
458 vm_offset_t va, struct rwlock **lockp);
459 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
460 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
461 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
462 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
463 u_int flags, vm_page_t m, struct rwlock **lockp);
464 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
465 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
466 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
467 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
468 static void pmap_reset_asid_set(pmap_t pmap);
469 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
470 vm_page_t m, struct rwlock **lockp);
472 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
473 struct rwlock **lockp);
475 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
476 struct spglist *free);
477 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
478 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
480 static pt_entry_t pmap_pte_bti(pmap_t pmap, vm_offset_t va);
483 * These load the old table data and store the new value.
484 * They need to be atomic as the System MMU may write to the table at
485 * the same time as the CPU.
487 #define pmap_clear(table) atomic_store_64(table, 0)
488 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
489 #define pmap_load(table) (*table)
490 #define pmap_load_clear(table) atomic_swap_64(table, 0)
491 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
492 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
493 #define pmap_store(table, entry) atomic_store_64(table, entry)
495 /********************/
496 /* Inline functions */
497 /********************/
500 pagecopy(void *s, void *d)
503 memcpy(d, s, PAGE_SIZE);
506 static __inline pd_entry_t *
507 pmap_l0(pmap_t pmap, vm_offset_t va)
510 return (&pmap->pm_l0[pmap_l0_index(va)]);
513 static __inline pd_entry_t *
514 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
518 l1 = (pd_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(pmap_load(l0)));
519 return (&l1[pmap_l1_index(va)]);
522 static __inline pd_entry_t *
523 pmap_l1(pmap_t pmap, vm_offset_t va)
527 l0 = pmap_l0(pmap, va);
528 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
531 return (pmap_l0_to_l1(l0, va));
534 static __inline pd_entry_t *
535 pmap_l1_to_l2(pd_entry_t *l1p, vm_offset_t va)
541 KASSERT(ADDR_IS_CANONICAL(va),
542 ("%s: Address not in canonical form: %lx", __func__, va));
544 * The valid bit may be clear if pmap_update_entry() is concurrently
545 * modifying the entry, so for KVA only the entry type may be checked.
547 KASSERT(ADDR_IS_KERNEL(va) || (l1 & ATTR_DESCR_VALID) != 0,
548 ("%s: L1 entry %#lx for %#lx is invalid", __func__, l1, va));
549 KASSERT((l1 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE,
550 ("%s: L1 entry %#lx for %#lx is a leaf", __func__, l1, va));
551 l2p = (pd_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(l1));
552 return (&l2p[pmap_l2_index(va)]);
555 static __inline pd_entry_t *
556 pmap_l2(pmap_t pmap, vm_offset_t va)
560 l1 = pmap_l1(pmap, va);
561 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
564 return (pmap_l1_to_l2(l1, va));
567 static __inline pt_entry_t *
568 pmap_l2_to_l3(pd_entry_t *l2p, vm_offset_t va)
575 KASSERT(ADDR_IS_CANONICAL(va),
576 ("%s: Address not in canonical form: %lx", __func__, va));
578 * The valid bit may be clear if pmap_update_entry() is concurrently
579 * modifying the entry, so for KVA only the entry type may be checked.
581 KASSERT(ADDR_IS_KERNEL(va) || (l2 & ATTR_DESCR_VALID) != 0,
582 ("%s: L2 entry %#lx for %#lx is invalid", __func__, l2, va));
583 KASSERT((l2 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE,
584 ("%s: L2 entry %#lx for %#lx is a leaf", __func__, l2, va));
585 l3p = (pt_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(l2));
586 return (&l3p[pmap_l3_index(va)]);
590 * Returns the lowest valid pde for a given virtual address.
591 * The next level may or may not point to a valid page or block.
593 static __inline pd_entry_t *
594 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
596 pd_entry_t *l0, *l1, *l2, desc;
598 l0 = pmap_l0(pmap, va);
599 desc = pmap_load(l0) & ATTR_DESCR_MASK;
600 if (desc != L0_TABLE) {
605 l1 = pmap_l0_to_l1(l0, va);
606 desc = pmap_load(l1) & ATTR_DESCR_MASK;
607 if (desc != L1_TABLE) {
612 l2 = pmap_l1_to_l2(l1, va);
613 desc = pmap_load(l2) & ATTR_DESCR_MASK;
614 if (desc != L2_TABLE) {
624 * Returns the lowest valid pte block or table entry for a given virtual
625 * address. If there are no valid entries return NULL and set the level to
626 * the first invalid level.
628 static __inline pt_entry_t *
629 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
631 pd_entry_t *l1, *l2, desc;
634 l1 = pmap_l1(pmap, va);
639 desc = pmap_load(l1) & ATTR_DESCR_MASK;
640 if (desc == L1_BLOCK) {
641 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
646 if (desc != L1_TABLE) {
651 l2 = pmap_l1_to_l2(l1, va);
652 desc = pmap_load(l2) & ATTR_DESCR_MASK;
653 if (desc == L2_BLOCK) {
658 if (desc != L2_TABLE) {
664 l3 = pmap_l2_to_l3(l2, va);
665 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
672 * If the given pmap has an L{1,2}_BLOCK or L3_PAGE entry at the specified
673 * level that maps the specified virtual address, then a pointer to that entry
674 * is returned. Otherwise, NULL is returned, unless INVARIANTS are enabled
675 * and a diagnostic message is provided, in which case this function panics.
677 static __always_inline pt_entry_t *
678 pmap_pte_exists(pmap_t pmap, vm_offset_t va, int level, const char *diag)
680 pd_entry_t *l0p, *l1p, *l2p;
681 pt_entry_t desc, *l3p;
682 int walk_level __diagused;
684 KASSERT(level >= 0 && level < 4,
685 ("%s: %s passed an out-of-range level (%d)", __func__, diag,
687 l0p = pmap_l0(pmap, va);
688 desc = pmap_load(l0p) & ATTR_DESCR_MASK;
689 if (desc == L0_TABLE && level > 0) {
690 l1p = pmap_l0_to_l1(l0p, va);
691 desc = pmap_load(l1p) & ATTR_DESCR_MASK;
692 if (desc == L1_BLOCK && level == 1) {
693 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
696 if (desc == L1_TABLE && level > 1) {
697 l2p = pmap_l1_to_l2(l1p, va);
698 desc = pmap_load(l2p) & ATTR_DESCR_MASK;
699 if (desc == L2_BLOCK && level == 2)
701 else if (desc == L2_TABLE && level > 2) {
702 l3p = pmap_l2_to_l3(l2p, va);
703 desc = pmap_load(l3p) & ATTR_DESCR_MASK;
704 if (desc == L3_PAGE && level == 3)
714 KASSERT(diag == NULL,
715 ("%s: va %#lx not mapped at level %d, desc %ld at level %d",
716 diag, va, level, desc, walk_level));
721 pmap_ps_enabled(pmap_t pmap)
724 * Promotion requires a hypervisor call when the kernel is running
725 * in EL1. To stop this disable superpage support on non-stage 1
728 if (pmap->pm_stage != PM_STAGE1)
731 return (superpages_enabled != 0);
735 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
736 pd_entry_t **l2, pt_entry_t **l3)
738 pd_entry_t *l0p, *l1p, *l2p;
740 if (pmap->pm_l0 == NULL)
743 l0p = pmap_l0(pmap, va);
746 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
749 l1p = pmap_l0_to_l1(l0p, va);
752 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
753 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
759 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
762 l2p = pmap_l1_to_l2(l1p, va);
765 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
770 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
773 *l3 = pmap_l2_to_l3(l2p, va);
779 pmap_l3_valid(pt_entry_t l3)
782 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
785 CTASSERT(L1_BLOCK == L2_BLOCK);
788 pmap_pte_memattr(pmap_t pmap, vm_memattr_t memattr)
792 if (pmap->pm_stage == PM_STAGE1) {
793 val = ATTR_S1_IDX(memattr);
794 if (memattr == VM_MEMATTR_DEVICE)
802 case VM_MEMATTR_DEVICE:
803 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_DEVICE_nGnRnE) |
804 ATTR_S2_XN(ATTR_S2_XN_ALL));
805 case VM_MEMATTR_UNCACHEABLE:
806 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_NC));
807 case VM_MEMATTR_WRITE_BACK:
808 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WB));
809 case VM_MEMATTR_WRITE_THROUGH:
810 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WT));
812 panic("%s: invalid memory attribute %x", __func__, memattr);
817 pmap_pte_prot(pmap_t pmap, vm_prot_t prot)
822 if (pmap->pm_stage == PM_STAGE1) {
823 if ((prot & VM_PROT_EXECUTE) == 0)
825 if ((prot & VM_PROT_WRITE) == 0)
826 val |= ATTR_S1_AP(ATTR_S1_AP_RO);
828 if ((prot & VM_PROT_WRITE) != 0)
829 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
830 if ((prot & VM_PROT_READ) != 0)
831 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_READ);
832 if ((prot & VM_PROT_EXECUTE) == 0)
833 val |= ATTR_S2_XN(ATTR_S2_XN_ALL);
840 * Checks if the PTE is dirty.
843 pmap_pte_dirty(pmap_t pmap, pt_entry_t pte)
846 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
848 if (pmap->pm_stage == PM_STAGE1) {
849 KASSERT((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) != 0,
850 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
852 return ((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
853 (ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_SW_DBM));
856 return ((pte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
857 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE));
861 pmap_resident_count_inc(pmap_t pmap, int count)
864 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
865 pmap->pm_stats.resident_count += count;
869 pmap_resident_count_dec(pmap_t pmap, int count)
872 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
873 KASSERT(pmap->pm_stats.resident_count >= count,
874 ("pmap %p resident count underflow %ld %d", pmap,
875 pmap->pm_stats.resident_count, count));
876 pmap->pm_stats.resident_count -= count;
880 pmap_early_vtophys(vm_offset_t va)
884 pa_page = arm64_address_translate_s1e1r(va) & PAR_PA_MASK;
885 return (pa_page | (va & PAR_LOW_MASK));
888 /* State of the bootstrapped DMAP page tables */
889 struct pmap_bootstrap_state {
893 vm_offset_t freemempos;
896 pt_entry_t table_attrs;
903 /* The bootstrap state */
904 static struct pmap_bootstrap_state bs_state = {
908 .table_attrs = TATTR_PXN_TABLE,
909 .l0_slot = L0_ENTRIES,
910 .l1_slot = Ln_ENTRIES,
911 .l2_slot = Ln_ENTRIES,
916 pmap_bootstrap_l0_table(struct pmap_bootstrap_state *state)
922 /* Link the level 0 table to a level 1 table */
923 l0_slot = pmap_l0_index(state->va);
924 if (l0_slot != state->l0_slot) {
926 * Make sure we move from a low address to high address
927 * before the DMAP region is ready. This ensures we never
928 * modify an existing mapping until we can map from a
929 * physical address to a virtual address.
931 MPASS(state->l0_slot < l0_slot ||
932 state->l0_slot == L0_ENTRIES ||
935 /* Reset lower levels */
938 state->l1_slot = Ln_ENTRIES;
939 state->l2_slot = Ln_ENTRIES;
941 /* Check the existing L0 entry */
942 state->l0_slot = l0_slot;
943 if (state->dmap_valid) {
944 l0e = pagetable_l0_ttbr1[l0_slot];
945 if ((l0e & ATTR_DESCR_VALID) != 0) {
946 MPASS((l0e & ATTR_DESCR_MASK) == L0_TABLE);
947 l1_pa = PTE_TO_PHYS(l0e);
948 state->l1 = (pt_entry_t *)PHYS_TO_DMAP(l1_pa);
953 /* Create a new L0 table entry */
954 state->l1 = (pt_entry_t *)state->freemempos;
955 memset(state->l1, 0, PAGE_SIZE);
956 state->freemempos += PAGE_SIZE;
958 l1_pa = pmap_early_vtophys((vm_offset_t)state->l1);
959 MPASS((l1_pa & Ln_TABLE_MASK) == 0);
960 MPASS(pagetable_l0_ttbr1[l0_slot] == 0);
961 pmap_store(&pagetable_l0_ttbr1[l0_slot], PHYS_TO_PTE(l1_pa) |
962 TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0 | L0_TABLE);
964 KASSERT(state->l1 != NULL, ("%s: NULL l1", __func__));
968 pmap_bootstrap_l1_table(struct pmap_bootstrap_state *state)
974 /* Make sure there is a valid L0 -> L1 table */
975 pmap_bootstrap_l0_table(state);
977 /* Link the level 1 table to a level 2 table */
978 l1_slot = pmap_l1_index(state->va);
979 if (l1_slot != state->l1_slot) {
980 /* See pmap_bootstrap_l0_table for a description */
981 MPASS(state->l1_slot < l1_slot ||
982 state->l1_slot == Ln_ENTRIES ||
985 /* Reset lower levels */
987 state->l2_slot = Ln_ENTRIES;
989 /* Check the existing L1 entry */
990 state->l1_slot = l1_slot;
991 if (state->dmap_valid) {
992 l1e = state->l1[l1_slot];
993 if ((l1e & ATTR_DESCR_VALID) != 0) {
994 MPASS((l1e & ATTR_DESCR_MASK) == L1_TABLE);
995 l2_pa = PTE_TO_PHYS(l1e);
996 state->l2 = (pt_entry_t *)PHYS_TO_DMAP(l2_pa);
1001 /* Create a new L1 table entry */
1002 state->l2 = (pt_entry_t *)state->freemempos;
1003 memset(state->l2, 0, PAGE_SIZE);
1004 state->freemempos += PAGE_SIZE;
1006 l2_pa = pmap_early_vtophys((vm_offset_t)state->l2);
1007 MPASS((l2_pa & Ln_TABLE_MASK) == 0);
1008 MPASS(state->l1[l1_slot] == 0);
1009 pmap_store(&state->l1[l1_slot], PHYS_TO_PTE(l2_pa) |
1010 state->table_attrs | L1_TABLE);
1012 KASSERT(state->l2 != NULL, ("%s: NULL l2", __func__));
1016 pmap_bootstrap_l2_table(struct pmap_bootstrap_state *state)
1022 /* Make sure there is a valid L1 -> L2 table */
1023 pmap_bootstrap_l1_table(state);
1025 /* Link the level 2 table to a level 3 table */
1026 l2_slot = pmap_l2_index(state->va);
1027 if (l2_slot != state->l2_slot) {
1028 /* See pmap_bootstrap_l0_table for a description */
1029 MPASS(state->l2_slot < l2_slot ||
1030 state->l2_slot == Ln_ENTRIES ||
1033 /* Check the existing L2 entry */
1034 state->l2_slot = l2_slot;
1035 if (state->dmap_valid) {
1036 l2e = state->l2[l2_slot];
1037 if ((l2e & ATTR_DESCR_VALID) != 0) {
1038 MPASS((l2e & ATTR_DESCR_MASK) == L2_TABLE);
1039 l3_pa = PTE_TO_PHYS(l2e);
1040 state->l3 = (pt_entry_t *)PHYS_TO_DMAP(l3_pa);
1045 /* Create a new L2 table entry */
1046 state->l3 = (pt_entry_t *)state->freemempos;
1047 memset(state->l3, 0, PAGE_SIZE);
1048 state->freemempos += PAGE_SIZE;
1050 l3_pa = pmap_early_vtophys((vm_offset_t)state->l3);
1051 MPASS((l3_pa & Ln_TABLE_MASK) == 0);
1052 MPASS(state->l2[l2_slot] == 0);
1053 pmap_store(&state->l2[l2_slot], PHYS_TO_PTE(l3_pa) |
1054 state->table_attrs | L2_TABLE);
1056 KASSERT(state->l3 != NULL, ("%s: NULL l3", __func__));
1060 pmap_bootstrap_l2_block(struct pmap_bootstrap_state *state, int i)
1065 if ((physmap[i + 1] - state->pa) < L2_SIZE)
1068 /* Make sure there is a valid L1 table */
1069 pmap_bootstrap_l1_table(state);
1071 MPASS((state->va & L2_OFFSET) == 0);
1073 state->va < DMAP_MAX_ADDRESS &&
1074 (physmap[i + 1] - state->pa) >= L2_SIZE;
1075 state->va += L2_SIZE, state->pa += L2_SIZE) {
1077 * Stop if we are about to walk off the end of what the
1078 * current L1 slot can address.
1080 if (!first && (state->pa & L1_OFFSET) == 0)
1084 l2_slot = pmap_l2_index(state->va);
1085 MPASS((state->pa & L2_OFFSET) == 0);
1086 MPASS(state->l2[l2_slot] == 0);
1087 pmap_store(&state->l2[l2_slot], PHYS_TO_PTE(state->pa) |
1088 ATTR_DEFAULT | ATTR_S1_XN | ATTR_KERN_GP |
1089 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
1091 MPASS(state->va == (state->pa - dmap_phys_base + DMAP_MIN_ADDRESS));
1095 pmap_bootstrap_l3_page(struct pmap_bootstrap_state *state, int i)
1100 if ((physmap[i + 1] - state->pa) < L3_SIZE)
1103 /* Make sure there is a valid L2 table */
1104 pmap_bootstrap_l2_table(state);
1106 MPASS((state->va & L3_OFFSET) == 0);
1108 state->va < DMAP_MAX_ADDRESS &&
1109 (physmap[i + 1] - state->pa) >= L3_SIZE;
1110 state->va += L3_SIZE, state->pa += L3_SIZE) {
1112 * Stop if we are about to walk off the end of what the
1113 * current L2 slot can address.
1115 if (!first && (state->pa & L2_OFFSET) == 0)
1119 l3_slot = pmap_l3_index(state->va);
1120 MPASS((state->pa & L3_OFFSET) == 0);
1121 MPASS(state->l3[l3_slot] == 0);
1122 pmap_store(&state->l3[l3_slot], PHYS_TO_PTE(state->pa) |
1123 ATTR_DEFAULT | ATTR_S1_XN | ATTR_KERN_GP |
1124 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L3_PAGE);
1126 MPASS(state->va == (state->pa - dmap_phys_base + DMAP_MIN_ADDRESS));
1130 pmap_bootstrap_dmap(vm_paddr_t min_pa)
1134 dmap_phys_base = min_pa & ~L1_OFFSET;
1138 for (i = 0; i < (physmap_idx * 2); i += 2) {
1139 bs_state.pa = physmap[i] & ~L3_OFFSET;
1140 bs_state.va = bs_state.pa - dmap_phys_base + DMAP_MIN_ADDRESS;
1142 /* Create L3 mappings at the start of the region */
1143 if ((bs_state.pa & L2_OFFSET) != 0)
1144 pmap_bootstrap_l3_page(&bs_state, i);
1145 MPASS(bs_state.pa <= physmap[i + 1]);
1147 if (L1_BLOCKS_SUPPORTED) {
1148 /* Create L2 mappings at the start of the region */
1149 if ((bs_state.pa & L1_OFFSET) != 0)
1150 pmap_bootstrap_l2_block(&bs_state, i);
1151 MPASS(bs_state.pa <= physmap[i + 1]);
1153 /* Create the main L1 block mappings */
1154 for (; bs_state.va < DMAP_MAX_ADDRESS &&
1155 (physmap[i + 1] - bs_state.pa) >= L1_SIZE;
1156 bs_state.va += L1_SIZE, bs_state.pa += L1_SIZE) {
1157 /* Make sure there is a valid L1 table */
1158 pmap_bootstrap_l0_table(&bs_state);
1159 MPASS((bs_state.pa & L1_OFFSET) == 0);
1161 &bs_state.l1[pmap_l1_index(bs_state.va)],
1162 PHYS_TO_PTE(bs_state.pa) | ATTR_DEFAULT |
1163 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
1164 ATTR_S1_XN | ATTR_KERN_GP | L1_BLOCK);
1166 MPASS(bs_state.pa <= physmap[i + 1]);
1168 /* Create L2 mappings at the end of the region */
1169 pmap_bootstrap_l2_block(&bs_state, i);
1171 while (bs_state.va < DMAP_MAX_ADDRESS &&
1172 (physmap[i + 1] - bs_state.pa) >= L2_SIZE) {
1173 pmap_bootstrap_l2_block(&bs_state, i);
1176 MPASS(bs_state.pa <= physmap[i + 1]);
1178 /* Create L3 mappings at the end of the region */
1179 pmap_bootstrap_l3_page(&bs_state, i);
1180 MPASS(bs_state.pa == physmap[i + 1]);
1182 if (bs_state.pa > dmap_phys_max) {
1183 dmap_phys_max = bs_state.pa;
1184 dmap_max_addr = bs_state.va;
1192 pmap_bootstrap_l2(vm_offset_t va)
1194 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
1196 /* Leave bs_state.pa as it's only needed to bootstrap blocks and pages*/
1199 for (; bs_state.va < VM_MAX_KERNEL_ADDRESS; bs_state.va += L1_SIZE)
1200 pmap_bootstrap_l1_table(&bs_state);
1204 pmap_bootstrap_l3(vm_offset_t va)
1206 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
1208 /* Leave bs_state.pa as it's only needed to bootstrap blocks and pages*/
1211 for (; bs_state.va < VM_MAX_KERNEL_ADDRESS; bs_state.va += L2_SIZE)
1212 pmap_bootstrap_l2_table(&bs_state);
1217 pmap_bootstrap_allocate_kasan_l2(vm_paddr_t start_pa, vm_paddr_t end_pa,
1218 vm_offset_t *start_va, int *nkasan_l2)
1226 pa = rounddown2(end_pa - L2_SIZE, L2_SIZE);
1227 l2 = pmap_l2(kernel_pmap, va);
1229 for (i = 0; pa >= start_pa && i < *nkasan_l2;
1230 i++, va += L2_SIZE, pa -= L2_SIZE, l2++) {
1232 * KASAN stack checking results in us having already allocated
1233 * part of our shadow map, so we can just skip those segments.
1235 if ((pmap_load(l2) & ATTR_DESCR_VALID) != 0) {
1240 pmap_store(l2, PHYS_TO_PTE(pa) | PMAP_SAN_PTE_BITS | L2_BLOCK);
1244 * Ended the allocation due to start_pa constraint, rather than because
1245 * we allocated everything. Adjust back up to the start_pa and remove
1246 * the invalid L2 block from our accounting.
1248 if (pa < start_pa) {
1254 bzero((void *)PHYS_TO_DMAP(pa), i * L2_SIZE);
1255 physmem_exclude_region(pa, i * L2_SIZE, EXFLAG_NOALLOC);
1263 * Bootstrap the system enough to run with virtual memory.
1266 pmap_bootstrap(vm_size_t kernlen)
1268 vm_offset_t dpcpu, msgbufpv;
1269 vm_paddr_t start_pa, pa, min_pa;
1272 /* Verify that the ASID is set through TTBR0. */
1273 KASSERT((READ_SPECIALREG(tcr_el1) & TCR_A1) == 0,
1274 ("pmap_bootstrap: TCR_EL1.A1 != 0"));
1276 /* Set this early so we can use the pagetable walking functions */
1277 kernel_pmap_store.pm_l0 = pagetable_l0_ttbr1;
1278 PMAP_LOCK_INIT(kernel_pmap);
1279 kernel_pmap->pm_l0_paddr =
1280 pmap_early_vtophys((vm_offset_t)kernel_pmap_store.pm_l0);
1281 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1282 vm_radix_init(&kernel_pmap->pm_root);
1283 kernel_pmap->pm_cookie = COOKIE_FROM(-1, INT_MIN);
1284 kernel_pmap->pm_stage = PM_STAGE1;
1285 kernel_pmap->pm_levels = 4;
1286 kernel_pmap->pm_ttbr = kernel_pmap->pm_l0_paddr;
1287 kernel_pmap->pm_asid_set = &asids;
1289 /* Assume the address we were loaded to is a valid physical address */
1290 min_pa = pmap_early_vtophys(KERNBASE);
1292 physmap_idx = physmem_avail(physmap, nitems(physmap));
1296 * Find the minimum physical address. physmap is sorted,
1297 * but may contain empty ranges.
1299 for (i = 0; i < physmap_idx * 2; i += 2) {
1300 if (physmap[i] == physmap[i + 1])
1302 if (physmap[i] <= min_pa)
1303 min_pa = physmap[i];
1306 bs_state.freemempos = KERNBASE + kernlen;
1307 bs_state.freemempos = roundup2(bs_state.freemempos, PAGE_SIZE);
1309 /* Create a direct map region early so we can use it for pa -> va */
1310 pmap_bootstrap_dmap(min_pa);
1311 bs_state.dmap_valid = true;
1313 * We only use PXN when we know nothing will be executed from it, e.g.
1316 bs_state.table_attrs &= ~TATTR_PXN_TABLE;
1318 start_pa = pa = pmap_early_vtophys(KERNBASE);
1321 * Create the l2 tables up to VM_MAX_KERNEL_ADDRESS. We assume that the
1322 * loader allocated the first and only l2 page table page used to map
1323 * the kernel, preloaded files and module metadata.
1325 pmap_bootstrap_l2(KERNBASE + L1_SIZE);
1326 /* And the l3 tables for the early devmap */
1327 pmap_bootstrap_l3(VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE));
1331 #define alloc_pages(var, np) \
1332 (var) = bs_state.freemempos; \
1333 bs_state.freemempos += (np * PAGE_SIZE); \
1334 memset((char *)(var), 0, ((np) * PAGE_SIZE));
1336 /* Allocate dynamic per-cpu area. */
1337 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
1338 dpcpu_init((void *)dpcpu, 0);
1340 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
1341 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
1342 msgbufp = (void *)msgbufpv;
1344 /* Reserve some VA space for early BIOS/ACPI mapping */
1345 preinit_map_va = roundup2(bs_state.freemempos, L2_SIZE);
1347 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
1348 virtual_avail = roundup2(virtual_avail, L1_SIZE);
1349 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
1350 kernel_vm_end = virtual_avail;
1352 pa = pmap_early_vtophys(bs_state.freemempos);
1354 physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
1361 * Finish constructing the initial shadow map:
1362 * - Count how many pages from KERNBASE to virtual_avail (scaled for
1364 * - Map that entire range using L2 superpages.
1367 pmap_bootstrap_san(void)
1370 vm_paddr_t kernstart;
1371 int i, shadow_npages, nkasan_l2;
1373 kernstart = pmap_early_vtophys(KERNBASE);
1376 * Rebuild physmap one more time, we may have excluded more regions from
1377 * allocation since pmap_bootstrap().
1379 bzero(physmap, sizeof(physmap));
1380 physmap_idx = physmem_avail(physmap, nitems(physmap));
1383 shadow_npages = (virtual_avail - VM_MIN_KERNEL_ADDRESS) / PAGE_SIZE;
1384 shadow_npages = howmany(shadow_npages, KASAN_SHADOW_SCALE);
1385 nkasan_l2 = howmany(shadow_npages, Ln_ENTRIES);
1387 /* Map the valid KVA up to this point. */
1388 va = KASAN_MIN_ADDRESS;
1391 * Find a slot in the physmap large enough for what we needed. We try to put
1392 * the shadow map as high up as we can to avoid depleting the lower 4GB in case
1393 * it's needed for, e.g., an xhci controller that can only do 32-bit DMA.
1395 for (i = (physmap_idx * 2) - 2; i >= 0 && nkasan_l2 > 0; i -= 2) {
1396 vm_paddr_t plow, phigh;
1398 /* L2 mappings must be backed by memory that is L2-aligned */
1399 plow = roundup2(physmap[i], L2_SIZE);
1400 phigh = physmap[i + 1];
1403 if (kernstart >= plow && kernstart < phigh)
1405 if (phigh - plow >= L2_SIZE)
1406 pmap_bootstrap_allocate_kasan_l2(plow, phigh, &va,
1411 panic("Could not find phys region for shadow map");
1414 * Done. We should now have a valid shadow address mapped for all KVA
1415 * that has been mapped so far, i.e., KERNBASE to virtual_avail. Thus,
1416 * shadow accesses by the kasan(9) runtime will succeed for this range.
1417 * When the kernel virtual address range is later expanded, as will
1418 * happen in vm_mem_init(), the shadow map will be grown as well. This
1419 * is handled by pmap_san_enter().
1425 * Initialize a vm_page's machine-dependent fields.
1428 pmap_page_init(vm_page_t m)
1431 TAILQ_INIT(&m->md.pv_list);
1432 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
1436 pmap_init_asids(struct asid_set *set, int bits)
1440 set->asid_bits = bits;
1443 * We may be too early in the overall initialization process to use
1446 set->asid_set_size = 1 << set->asid_bits;
1447 set->asid_set = kmem_malloc(bitstr_size(set->asid_set_size),
1449 for (i = 0; i < ASID_FIRST_AVAILABLE; i++)
1450 bit_set(set->asid_set, i);
1451 set->asid_next = ASID_FIRST_AVAILABLE;
1452 mtx_init(&set->asid_set_mutex, "asid set", NULL, MTX_SPIN);
1456 pmap_init_pv_table(void)
1458 struct vm_phys_seg *seg, *next_seg;
1459 struct pmap_large_md_page *pvd;
1461 int domain, i, j, pages;
1464 * We strongly depend on the size being a power of two, so the assert
1465 * is overzealous. However, should the struct be resized to a
1466 * different power of two, the code below needs to be revisited.
1468 CTASSERT((sizeof(*pvd) == 64));
1471 * Calculate the size of the array.
1474 for (i = 0; i < vm_phys_nsegs; i++) {
1475 seg = &vm_phys_segs[i];
1476 pages = pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) -
1477 pmap_l2_pindex(seg->start);
1478 s += round_page(pages * sizeof(*pvd));
1480 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
1481 if (pv_table == NULL)
1482 panic("%s: kva_alloc failed\n", __func__);
1485 * Iterate physical segments to allocate domain-local memory for PV
1489 for (i = 0; i < vm_phys_nsegs; i++) {
1490 seg = &vm_phys_segs[i];
1491 pages = pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) -
1492 pmap_l2_pindex(seg->start);
1493 domain = seg->domain;
1495 s = round_page(pages * sizeof(*pvd));
1497 for (j = 0; j < s; j += PAGE_SIZE) {
1498 vm_page_t m = vm_page_alloc_noobj_domain(domain,
1501 panic("failed to allocate PV table page");
1502 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
1505 for (j = 0; j < s / sizeof(*pvd); j++) {
1506 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
1507 TAILQ_INIT(&pvd->pv_page.pv_list);
1511 pvd = &pv_dummy_large;
1512 memset(pvd, 0, sizeof(*pvd));
1513 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
1514 TAILQ_INIT(&pvd->pv_page.pv_list);
1517 * Set pointers from vm_phys_segs to pv_table.
1519 for (i = 0, pvd = pv_table; i < vm_phys_nsegs; i++) {
1520 seg = &vm_phys_segs[i];
1521 seg->md_first = pvd;
1522 pvd += pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) -
1523 pmap_l2_pindex(seg->start);
1526 * If there is a following segment, and the final
1527 * superpage of this segment and the initial superpage
1528 * of the next segment are the same then adjust the
1529 * pv_table entry for that next segment down by one so
1530 * that the pv_table entries will be shared.
1532 if (i + 1 < vm_phys_nsegs) {
1533 next_seg = &vm_phys_segs[i + 1];
1534 if (pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) - 1 ==
1535 pmap_l2_pindex(next_seg->start)) {
1543 * Initialize the pmap module.
1544 * Called by vm_init, to initialize any structures that the pmap
1545 * system needs to map virtual memory.
1554 * Are large page mappings enabled?
1556 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
1557 if (superpages_enabled) {
1558 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1559 ("pmap_init: can't assign to pagesizes[1]"));
1560 pagesizes[1] = L2_SIZE;
1561 if (L1_BLOCKS_SUPPORTED) {
1562 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0,
1563 ("pmap_init: can't assign to pagesizes[2]"));
1564 pagesizes[2] = L1_SIZE;
1569 * Initialize the ASID allocator.
1571 pmap_init_asids(&asids,
1572 (READ_SPECIALREG(tcr_el1) & TCR_ASID_16) != 0 ? 16 : 8);
1575 mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1);
1578 if (ID_AA64MMFR1_VMIDBits_VAL(mmfr1) ==
1579 ID_AA64MMFR1_VMIDBits_16)
1581 pmap_init_asids(&vmids, vmid_bits);
1585 * Initialize pv chunk lists.
1587 for (i = 0; i < PMAP_MEMDOM; i++) {
1588 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL,
1590 TAILQ_INIT(&pv_chunks[i].pvc_list);
1592 pmap_init_pv_table();
1597 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1598 "2MB page mapping counters");
1600 static u_long pmap_l2_demotions;
1601 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
1602 &pmap_l2_demotions, 0, "2MB page demotions");
1604 static u_long pmap_l2_mappings;
1605 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
1606 &pmap_l2_mappings, 0, "2MB page mappings");
1608 static u_long pmap_l2_p_failures;
1609 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
1610 &pmap_l2_p_failures, 0, "2MB page promotion failures");
1612 static u_long pmap_l2_promotions;
1613 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
1614 &pmap_l2_promotions, 0, "2MB page promotions");
1617 * If the given value for "final_only" is false, then any cached intermediate-
1618 * level entries, i.e., L{0,1,2}_TABLE entries, are invalidated in addition to
1619 * any cached final-level entry, i.e., either an L{1,2}_BLOCK or L3_PAGE entry.
1620 * Otherwise, just the cached final-level entry is invalidated.
1622 static __inline void
1623 pmap_s1_invalidate_kernel(uint64_t r, bool final_only)
1626 __asm __volatile("tlbi vaale1is, %0" : : "r" (r));
1628 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1631 static __inline void
1632 pmap_s1_invalidate_user(uint64_t r, bool final_only)
1635 __asm __volatile("tlbi vale1is, %0" : : "r" (r));
1637 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1641 * Invalidates any cached final- and optionally intermediate-level TLB entries
1642 * for the specified virtual address in the given virtual address space.
1644 static __inline void
1645 pmap_s1_invalidate_page(pmap_t pmap, vm_offset_t va, bool final_only)
1649 PMAP_ASSERT_STAGE1(pmap);
1653 if (pmap == kernel_pmap) {
1654 pmap_s1_invalidate_kernel(r, final_only);
1656 r |= ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1657 pmap_s1_invalidate_user(r, final_only);
1663 static __inline void
1664 pmap_s2_invalidate_page(pmap_t pmap, vm_offset_t va, bool final_only)
1666 PMAP_ASSERT_STAGE2(pmap);
1667 MPASS(pmap_stage2_invalidate_range != NULL);
1668 pmap_stage2_invalidate_range(pmap_to_ttbr0(pmap), va, va + PAGE_SIZE,
1672 static __inline void
1673 pmap_invalidate_page(pmap_t pmap, vm_offset_t va, bool final_only)
1675 if (pmap->pm_stage == PM_STAGE1)
1676 pmap_s1_invalidate_page(pmap, va, final_only);
1678 pmap_s2_invalidate_page(pmap, va, final_only);
1682 * Invalidates any cached final- and optionally intermediate-level TLB entries
1683 * for the specified virtual address range in the given virtual address space.
1685 static __inline void
1686 pmap_s1_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1689 uint64_t end, r, start;
1691 PMAP_ASSERT_STAGE1(pmap);
1694 if (pmap == kernel_pmap) {
1695 start = TLBI_VA(sva);
1697 for (r = start; r < end; r += TLBI_VA_L3_INCR)
1698 pmap_s1_invalidate_kernel(r, final_only);
1700 start = end = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1701 start |= TLBI_VA(sva);
1702 end |= TLBI_VA(eva);
1703 for (r = start; r < end; r += TLBI_VA_L3_INCR)
1704 pmap_s1_invalidate_user(r, final_only);
1710 static __inline void
1711 pmap_s2_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1714 PMAP_ASSERT_STAGE2(pmap);
1715 MPASS(pmap_stage2_invalidate_range != NULL);
1716 pmap_stage2_invalidate_range(pmap_to_ttbr0(pmap), sva, eva, final_only);
1719 static __inline void
1720 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1723 if (pmap->pm_stage == PM_STAGE1)
1724 pmap_s1_invalidate_range(pmap, sva, eva, final_only);
1726 pmap_s2_invalidate_range(pmap, sva, eva, final_only);
1730 * Invalidates all cached intermediate- and final-level TLB entries for the
1731 * given virtual address space.
1733 static __inline void
1734 pmap_s1_invalidate_all(pmap_t pmap)
1738 PMAP_ASSERT_STAGE1(pmap);
1741 if (pmap == kernel_pmap) {
1742 __asm __volatile("tlbi vmalle1is");
1744 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1745 __asm __volatile("tlbi aside1is, %0" : : "r" (r));
1751 static __inline void
1752 pmap_s2_invalidate_all(pmap_t pmap)
1754 PMAP_ASSERT_STAGE2(pmap);
1755 MPASS(pmap_stage2_invalidate_all != NULL);
1756 pmap_stage2_invalidate_all(pmap_to_ttbr0(pmap));
1759 static __inline void
1760 pmap_invalidate_all(pmap_t pmap)
1762 if (pmap->pm_stage == PM_STAGE1)
1763 pmap_s1_invalidate_all(pmap);
1765 pmap_s2_invalidate_all(pmap);
1769 * Routine: pmap_extract
1771 * Extract the physical page address associated
1772 * with the given map/virtual_address pair.
1775 pmap_extract(pmap_t pmap, vm_offset_t va)
1777 pt_entry_t *pte, tpte;
1784 * Find the block or page map for this virtual address. pmap_pte
1785 * will return either a valid block/page entry, or NULL.
1787 pte = pmap_pte(pmap, va, &lvl);
1789 tpte = pmap_load(pte);
1790 pa = PTE_TO_PHYS(tpte);
1793 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
1794 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1795 ("pmap_extract: Invalid L1 pte found: %lx",
1796 tpte & ATTR_DESCR_MASK));
1797 pa |= (va & L1_OFFSET);
1800 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1801 ("pmap_extract: Invalid L2 pte found: %lx",
1802 tpte & ATTR_DESCR_MASK));
1803 pa |= (va & L2_OFFSET);
1806 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1807 ("pmap_extract: Invalid L3 pte found: %lx",
1808 tpte & ATTR_DESCR_MASK));
1809 pa |= (va & L3_OFFSET);
1818 * Routine: pmap_extract_and_hold
1820 * Atomically extract and hold the physical page
1821 * with the given pmap and virtual address pair
1822 * if that mapping permits the given protection.
1825 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1827 pt_entry_t *pte, tpte;
1835 pte = pmap_pte(pmap, va, &lvl);
1837 tpte = pmap_load(pte);
1839 KASSERT(lvl > 0 && lvl <= 3,
1840 ("pmap_extract_and_hold: Invalid level %d", lvl));
1842 * Check that the pte is either a L3 page, or a L1 or L2 block
1843 * entry. We can assume L1_BLOCK == L2_BLOCK.
1845 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1846 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1847 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1848 tpte & ATTR_DESCR_MASK));
1851 if ((prot & VM_PROT_WRITE) == 0)
1853 else if (pmap->pm_stage == PM_STAGE1 &&
1854 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW))
1856 else if (pmap->pm_stage == PM_STAGE2 &&
1857 ((tpte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
1858 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)))
1864 off = va & L1_OFFSET;
1867 off = va & L2_OFFSET;
1873 m = PHYS_TO_VM_PAGE(PTE_TO_PHYS(tpte) | off);
1874 if (m != NULL && !vm_page_wire_mapped(m))
1883 * Walks the page tables to translate a kernel virtual address to a
1884 * physical address. Returns true if the kva is valid and stores the
1885 * physical address in pa if it is not NULL.
1887 * See the comment above data_abort() for the rationale for specifying
1888 * NO_PERTHREAD_SSP here.
1890 bool NO_PERTHREAD_SSP
1891 pmap_klookup(vm_offset_t va, vm_paddr_t *pa)
1893 pt_entry_t *pte, tpte;
1898 * Disable interrupts so we don't get interrupted between asking
1899 * for address translation, and getting the result back.
1901 intr = intr_disable();
1902 par = arm64_address_translate_s1e1r(va);
1905 if (PAR_SUCCESS(par)) {
1907 *pa = (par & PAR_PA_MASK) | (va & PAR_LOW_MASK);
1912 * Fall back to walking the page table. The address translation
1913 * instruction may fail when the page is in a break-before-make
1914 * sequence. As we only clear the valid bit in said sequence we
1915 * can walk the page table to find the physical address.
1918 pte = pmap_l1(kernel_pmap, va);
1923 * A concurrent pmap_update_entry() will clear the entry's valid bit
1924 * but leave the rest of the entry unchanged. Therefore, we treat a
1925 * non-zero entry as being valid, and we ignore the valid bit when
1926 * determining whether the entry maps a block, page, or table.
1928 tpte = pmap_load(pte);
1931 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
1933 *pa = PTE_TO_PHYS(tpte) | (va & L1_OFFSET);
1936 pte = pmap_l1_to_l2(&tpte, va);
1937 tpte = pmap_load(pte);
1940 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
1942 *pa = PTE_TO_PHYS(tpte) | (va & L2_OFFSET);
1945 pte = pmap_l2_to_l3(&tpte, va);
1946 tpte = pmap_load(pte);
1950 *pa = PTE_TO_PHYS(tpte) | (va & L3_OFFSET);
1955 * Routine: pmap_kextract
1957 * Extract the physical page address associated with the given kernel
1961 pmap_kextract(vm_offset_t va)
1965 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
1966 return (DMAP_TO_PHYS(va));
1968 if (pmap_klookup(va, &pa) == false)
1973 /***************************************************
1974 * Low level mapping routines.....
1975 ***************************************************/
1978 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1981 pt_entry_t attr, old_l3e, *pte;
1985 KASSERT((pa & L3_OFFSET) == 0,
1986 ("pmap_kenter: Invalid physical address"));
1987 KASSERT((sva & L3_OFFSET) == 0,
1988 ("pmap_kenter: Invalid virtual address"));
1989 KASSERT((size & PAGE_MASK) == 0,
1990 ("pmap_kenter: Mapping is not page-sized"));
1992 attr = ATTR_DEFAULT | ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1993 ATTR_KERN_GP | ATTR_S1_IDX(mode) | L3_PAGE;
1997 pde = pmap_pde(kernel_pmap, va, &lvl);
1998 KASSERT(pde != NULL,
1999 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
2000 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
2002 pte = pmap_l2_to_l3(pde, va);
2003 old_l3e |= pmap_load_store(pte, PHYS_TO_PTE(pa) | attr);
2009 if ((old_l3e & ATTR_DESCR_VALID) != 0)
2010 pmap_s1_invalidate_range(kernel_pmap, sva, va, true);
2013 * Because the old entries were invalid and the new mappings
2014 * are not executable, an isb is not required.
2021 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
2024 pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
2028 * Remove a page from the kernel pagetables.
2031 pmap_kremove(vm_offset_t va)
2035 pte = pmap_pte_exists(kernel_pmap, va, 3, __func__);
2037 pmap_s1_invalidate_page(kernel_pmap, va, true);
2041 * Remove the specified range of mappings from the kernel address space.
2043 * Should only be applied to mappings that were created by pmap_kenter() or
2044 * pmap_kenter_device(). Nothing about this function is actually specific
2045 * to device mappings.
2048 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
2053 KASSERT((sva & L3_OFFSET) == 0,
2054 ("pmap_kremove_device: Invalid virtual address"));
2055 KASSERT((size & PAGE_MASK) == 0,
2056 ("pmap_kremove_device: Mapping is not page-sized"));
2060 pte = pmap_pte_exists(kernel_pmap, va, 3, __func__);
2066 pmap_s1_invalidate_range(kernel_pmap, sva, va, true);
2070 * Used to map a range of physical addresses into kernel
2071 * virtual address space.
2073 * The value passed in '*virt' is a suggested virtual address for
2074 * the mapping. Architectures which can support a direct-mapped
2075 * physical to virtual region can return the appropriate address
2076 * within that region, leaving '*virt' unchanged. Other
2077 * architectures should map the pages starting at '*virt' and
2078 * update '*virt' with the first usable address after the mapped
2082 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
2084 return PHYS_TO_DMAP(start);
2088 * Add a list of wired pages to the kva
2089 * this routine is only used for temporary
2090 * kernel mappings that do not need to have
2091 * page modification or references recorded.
2092 * Note that old mappings are simply written
2093 * over. The page *must* be wired.
2094 * Note: SMP coherent. Uses a ranged shootdown IPI.
2097 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
2100 pt_entry_t attr, old_l3e, pa, *pte;
2107 for (i = 0; i < count; i++) {
2108 pde = pmap_pde(kernel_pmap, va, &lvl);
2109 KASSERT(pde != NULL,
2110 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
2112 ("pmap_qenter: Invalid level %d", lvl));
2115 pa = VM_PAGE_TO_PHYS(m);
2116 attr = ATTR_DEFAULT | ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
2117 ATTR_KERN_GP | ATTR_S1_IDX(m->md.pv_memattr) | L3_PAGE;
2118 pte = pmap_l2_to_l3(pde, va);
2119 old_l3e |= pmap_load_store(pte, PHYS_TO_PTE(pa) | attr);
2123 if ((old_l3e & ATTR_DESCR_VALID) != 0)
2124 pmap_s1_invalidate_range(kernel_pmap, sva, va, true);
2127 * Because the old entries were invalid and the new mappings
2128 * are not executable, an isb is not required.
2135 * This routine tears out page mappings from the
2136 * kernel -- it is meant only for temporary mappings.
2139 pmap_qremove(vm_offset_t sva, int count)
2144 KASSERT(ADDR_IS_CANONICAL(sva),
2145 ("%s: Address not in canonical form: %lx", __func__, sva));
2146 KASSERT(ADDR_IS_KERNEL(sva), ("usermode va %lx", sva));
2149 while (count-- > 0) {
2150 pte = pmap_pte_exists(kernel_pmap, va, 3, NULL);
2157 pmap_s1_invalidate_range(kernel_pmap, sva, va, true);
2160 /***************************************************
2161 * Page table page management routines.....
2162 ***************************************************/
2164 * Schedule the specified unused page table page to be freed. Specifically,
2165 * add the page to the specified list of pages that will be released to the
2166 * physical memory manager after the TLB has been updated.
2168 static __inline void
2169 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2170 boolean_t set_PG_ZERO)
2174 m->flags |= PG_ZERO;
2176 m->flags &= ~PG_ZERO;
2177 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2181 * Decrements a page table page's reference count, which is used to record the
2182 * number of valid page table entries within the page. If the reference count
2183 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2184 * page table page was unmapped and FALSE otherwise.
2186 static inline boolean_t
2187 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2191 if (m->ref_count == 0) {
2192 _pmap_unwire_l3(pmap, va, m, free);
2199 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2202 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2204 * unmap the page table page
2206 if (m->pindex >= (NUL2E + NUL1E)) {
2210 l0 = pmap_l0(pmap, va);
2212 } else if (m->pindex >= NUL2E) {
2216 l1 = pmap_l1(pmap, va);
2222 l2 = pmap_l2(pmap, va);
2225 pmap_resident_count_dec(pmap, 1);
2226 if (m->pindex < NUL2E) {
2227 /* We just released an l3, unhold the matching l2 */
2228 pd_entry_t *l1, tl1;
2231 l1 = pmap_l1(pmap, va);
2232 tl1 = pmap_load(l1);
2233 l2pg = PHYS_TO_VM_PAGE(PTE_TO_PHYS(tl1));
2234 pmap_unwire_l3(pmap, va, l2pg, free);
2235 } else if (m->pindex < (NUL2E + NUL1E)) {
2236 /* We just released an l2, unhold the matching l1 */
2237 pd_entry_t *l0, tl0;
2240 l0 = pmap_l0(pmap, va);
2241 tl0 = pmap_load(l0);
2242 l1pg = PHYS_TO_VM_PAGE(PTE_TO_PHYS(tl0));
2243 pmap_unwire_l3(pmap, va, l1pg, free);
2245 pmap_invalidate_page(pmap, va, false);
2248 * Put page on a list so that it is released after
2249 * *ALL* TLB shootdown is done
2251 pmap_add_delayed_free_list(m, free, TRUE);
2255 * After removing a page table entry, this routine is used to
2256 * conditionally free the page, and manage the reference count.
2259 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2260 struct spglist *free)
2264 KASSERT(ADDR_IS_CANONICAL(va),
2265 ("%s: Address not in canonical form: %lx", __func__, va));
2266 if (ADDR_IS_KERNEL(va))
2268 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2269 mpte = PHYS_TO_VM_PAGE(PTE_TO_PHYS(ptepde));
2270 return (pmap_unwire_l3(pmap, va, mpte, free));
2274 * Release a page table page reference after a failed attempt to create a
2278 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
2280 struct spglist free;
2283 if (pmap_unwire_l3(pmap, va, mpte, &free))
2284 vm_page_free_pages_toq(&free, true);
2288 pmap_pinit0(pmap_t pmap)
2291 PMAP_LOCK_INIT(pmap);
2292 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
2293 pmap->pm_l0_paddr = READ_SPECIALREG(ttbr0_el1);
2294 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
2295 TAILQ_INIT(&pmap->pm_pvchunk);
2296 vm_radix_init(&pmap->pm_root);
2297 pmap->pm_cookie = COOKIE_FROM(ASID_RESERVED_FOR_PID_0, INT_MIN);
2298 pmap->pm_stage = PM_STAGE1;
2299 pmap->pm_levels = 4;
2300 pmap->pm_ttbr = pmap->pm_l0_paddr;
2301 pmap->pm_asid_set = &asids;
2303 PCPU_SET(curpmap, pmap);
2307 pmap_pinit_stage(pmap_t pmap, enum pmap_stage stage, int levels)
2312 * allocate the l0 page
2314 m = vm_page_alloc_noobj(VM_ALLOC_WAITOK | VM_ALLOC_WIRED |
2316 pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(m);
2317 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
2319 TAILQ_INIT(&pmap->pm_pvchunk);
2320 vm_radix_init(&pmap->pm_root);
2321 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
2322 pmap->pm_cookie = COOKIE_FROM(-1, INT_MAX);
2324 MPASS(levels == 3 || levels == 4);
2325 pmap->pm_levels = levels;
2326 pmap->pm_stage = stage;
2329 pmap->pm_asid_set = &asids;
2332 pmap->pm_asid_set = &vmids;
2335 panic("%s: Invalid pmap type %d", __func__, stage);
2339 /* XXX Temporarily disable deferred ASID allocation. */
2340 pmap_alloc_asid(pmap);
2343 * Allocate the level 1 entry to use as the root. This will increase
2344 * the refcount on the level 1 page so it won't be removed until
2345 * pmap_release() is called.
2347 if (pmap->pm_levels == 3) {
2349 m = _pmap_alloc_l3(pmap, NUL2E + NUL1E, NULL);
2352 pmap->pm_ttbr = VM_PAGE_TO_PHYS(m);
2358 pmap_pinit(pmap_t pmap)
2361 return (pmap_pinit_stage(pmap, PM_STAGE1, 4));
2365 * This routine is called if the desired page table page does not exist.
2367 * If page table page allocation fails, this routine may sleep before
2368 * returning NULL. It sleeps only if a lock pointer was given.
2370 * Note: If a page allocation fails at page table level two or three,
2371 * one or two pages may be held during the wait, only to be released
2372 * afterwards. This conservative approach is easily argued to avoid
2376 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
2378 vm_page_t m, l1pg, l2pg;
2380 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2383 * Allocate a page table page.
2385 if ((m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2386 if (lockp != NULL) {
2387 RELEASE_PV_LIST_LOCK(lockp);
2394 * Indicate the need to retry. While waiting, the page table
2395 * page may have been allocated.
2399 m->pindex = ptepindex;
2402 * Because of AArch64's weak memory consistency model, we must have a
2403 * barrier here to ensure that the stores for zeroing "m", whether by
2404 * pmap_zero_page() or an earlier function, are visible before adding
2405 * "m" to the page table. Otherwise, a page table walk by another
2406 * processor's MMU could see the mapping to "m" and a stale, non-zero
2412 * Map the pagetable page into the process address space, if
2413 * it isn't already there.
2416 if (ptepindex >= (NUL2E + NUL1E)) {
2417 pd_entry_t *l0p, l0e;
2418 vm_pindex_t l0index;
2420 l0index = ptepindex - (NUL2E + NUL1E);
2421 l0p = &pmap->pm_l0[l0index];
2422 KASSERT((pmap_load(l0p) & ATTR_DESCR_VALID) == 0,
2423 ("%s: L0 entry %#lx is valid", __func__, pmap_load(l0p)));
2424 l0e = PHYS_TO_PTE(VM_PAGE_TO_PHYS(m)) | L0_TABLE;
2427 * Mark all kernel memory as not accessible from userspace
2428 * and userspace memory as not executable from the kernel.
2429 * This has been done for the bootstrap L0 entries in
2432 if (pmap == kernel_pmap)
2433 l0e |= TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0;
2435 l0e |= TATTR_PXN_TABLE;
2436 pmap_store(l0p, l0e);
2437 } else if (ptepindex >= NUL2E) {
2438 vm_pindex_t l0index, l1index;
2439 pd_entry_t *l0, *l1;
2442 l1index = ptepindex - NUL2E;
2443 l0index = l1index >> Ln_ENTRIES_SHIFT;
2445 l0 = &pmap->pm_l0[l0index];
2446 tl0 = pmap_load(l0);
2448 /* recurse for allocating page dir */
2449 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
2451 vm_page_unwire_noq(m);
2452 vm_page_free_zero(m);
2456 l1pg = PHYS_TO_VM_PAGE(PTE_TO_PHYS(tl0));
2460 l1 = (pd_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(pmap_load(l0)));
2461 l1 = &l1[ptepindex & Ln_ADDR_MASK];
2462 KASSERT((pmap_load(l1) & ATTR_DESCR_VALID) == 0,
2463 ("%s: L1 entry %#lx is valid", __func__, pmap_load(l1)));
2464 pmap_store(l1, PHYS_TO_PTE(VM_PAGE_TO_PHYS(m)) | L1_TABLE);
2466 vm_pindex_t l0index, l1index;
2467 pd_entry_t *l0, *l1, *l2;
2468 pd_entry_t tl0, tl1;
2470 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
2471 l0index = l1index >> Ln_ENTRIES_SHIFT;
2473 l0 = &pmap->pm_l0[l0index];
2474 tl0 = pmap_load(l0);
2476 /* recurse for allocating page dir */
2477 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
2479 vm_page_unwire_noq(m);
2480 vm_page_free_zero(m);
2483 tl0 = pmap_load(l0);
2484 l1 = (pd_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(tl0));
2485 l1 = &l1[l1index & Ln_ADDR_MASK];
2487 l1 = (pd_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(tl0));
2488 l1 = &l1[l1index & Ln_ADDR_MASK];
2489 tl1 = pmap_load(l1);
2491 /* recurse for allocating page dir */
2492 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
2494 vm_page_unwire_noq(m);
2495 vm_page_free_zero(m);
2499 l2pg = PHYS_TO_VM_PAGE(PTE_TO_PHYS(tl1));
2504 l2 = (pd_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(pmap_load(l1)));
2505 l2 = &l2[ptepindex & Ln_ADDR_MASK];
2506 KASSERT((pmap_load(l2) & ATTR_DESCR_VALID) == 0,
2507 ("%s: L2 entry %#lx is valid", __func__, pmap_load(l2)));
2508 pmap_store(l2, PHYS_TO_PTE(VM_PAGE_TO_PHYS(m)) | L2_TABLE);
2511 pmap_resident_count_inc(pmap, 1);
2517 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, vm_page_t *l2pgp,
2518 struct rwlock **lockp)
2520 pd_entry_t *l1, *l2;
2522 vm_pindex_t l2pindex;
2524 KASSERT(ADDR_IS_CANONICAL(va),
2525 ("%s: Address not in canonical form: %lx", __func__, va));
2528 l1 = pmap_l1(pmap, va);
2529 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
2530 l2 = pmap_l1_to_l2(l1, va);
2531 if (!ADDR_IS_KERNEL(va)) {
2532 /* Add a reference to the L2 page. */
2533 l2pg = PHYS_TO_VM_PAGE(PTE_TO_PHYS(pmap_load(l1)));
2537 } else if (!ADDR_IS_KERNEL(va)) {
2538 /* Allocate a L2 page. */
2539 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
2540 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
2547 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
2548 l2 = &l2[pmap_l2_index(va)];
2550 panic("pmap_alloc_l2: missing page table page for va %#lx",
2557 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2559 vm_pindex_t ptepindex;
2560 pd_entry_t *pde, tpde;
2568 * Calculate pagetable page index
2570 ptepindex = pmap_l2_pindex(va);
2573 * Get the page directory entry
2575 pde = pmap_pde(pmap, va, &lvl);
2578 * If the page table page is mapped, we just increment the hold count,
2579 * and activate it. If we get a level 2 pde it will point to a level 3
2587 pte = pmap_l0_to_l1(pde, va);
2588 KASSERT(pmap_load(pte) == 0,
2589 ("pmap_alloc_l3: TODO: l0 superpages"));
2594 pte = pmap_l1_to_l2(pde, va);
2595 KASSERT(pmap_load(pte) == 0,
2596 ("pmap_alloc_l3: TODO: l1 superpages"));
2600 tpde = pmap_load(pde);
2602 m = PHYS_TO_VM_PAGE(PTE_TO_PHYS(tpde));
2608 panic("pmap_alloc_l3: Invalid level %d", lvl);
2612 * Here if the pte page isn't mapped, or if it has been deallocated.
2614 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
2615 if (m == NULL && lockp != NULL)
2621 /***************************************************
2622 * Pmap allocation/deallocation routines.
2623 ***************************************************/
2626 * Release any resources held by the given physical map.
2627 * Called when a pmap initialized by pmap_pinit is being released.
2628 * Should only be called if the map contains no valid mappings.
2631 pmap_release(pmap_t pmap)
2633 boolean_t rv __diagused;
2634 struct spglist free;
2635 struct asid_set *set;
2639 if (pmap->pm_levels != 4) {
2640 PMAP_ASSERT_STAGE2(pmap);
2641 KASSERT(pmap->pm_stats.resident_count == 1,
2642 ("pmap_release: pmap resident count %ld != 0",
2643 pmap->pm_stats.resident_count));
2644 KASSERT((pmap->pm_l0[0] & ATTR_DESCR_VALID) == ATTR_DESCR_VALID,
2645 ("pmap_release: Invalid l0 entry: %lx", pmap->pm_l0[0]));
2648 m = PHYS_TO_VM_PAGE(pmap->pm_ttbr);
2650 rv = pmap_unwire_l3(pmap, 0, m, &free);
2653 vm_page_free_pages_toq(&free, true);
2656 KASSERT(pmap->pm_stats.resident_count == 0,
2657 ("pmap_release: pmap resident count %ld != 0",
2658 pmap->pm_stats.resident_count));
2659 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2660 ("pmap_release: pmap has reserved page table page(s)"));
2662 set = pmap->pm_asid_set;
2663 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
2666 * Allow the ASID to be reused. In stage 2 VMIDs we don't invalidate
2667 * the entries when removing them so rely on a later tlb invalidation.
2668 * this will happen when updating the VMID generation. Because of this
2669 * we don't reuse VMIDs within a generation.
2671 if (pmap->pm_stage == PM_STAGE1) {
2672 mtx_lock_spin(&set->asid_set_mutex);
2673 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch) {
2674 asid = COOKIE_TO_ASID(pmap->pm_cookie);
2675 KASSERT(asid >= ASID_FIRST_AVAILABLE &&
2676 asid < set->asid_set_size,
2677 ("pmap_release: pmap cookie has out-of-range asid"));
2678 bit_clear(set->asid_set, asid);
2680 mtx_unlock_spin(&set->asid_set_mutex);
2683 m = PHYS_TO_VM_PAGE(pmap->pm_l0_paddr);
2684 vm_page_unwire_noq(m);
2685 vm_page_free_zero(m);
2689 kvm_size(SYSCTL_HANDLER_ARGS)
2691 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
2693 return sysctl_handle_long(oidp, &ksize, 0, req);
2695 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
2696 0, 0, kvm_size, "LU",
2700 kvm_free(SYSCTL_HANDLER_ARGS)
2702 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2704 return sysctl_handle_long(oidp, &kfree, 0, req);
2706 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
2707 0, 0, kvm_free, "LU",
2708 "Amount of KVM free");
2711 * grow the number of kernel page table entries, if needed
2714 pmap_growkernel(vm_offset_t addr)
2718 pd_entry_t *l0, *l1, *l2;
2720 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2722 addr = roundup2(addr, L2_SIZE);
2723 if (addr - 1 >= vm_map_max(kernel_map))
2724 addr = vm_map_max(kernel_map);
2725 if (kernel_vm_end < addr)
2726 kasan_shadow_map(kernel_vm_end, addr - kernel_vm_end);
2727 while (kernel_vm_end < addr) {
2728 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
2729 KASSERT(pmap_load(l0) != 0,
2730 ("pmap_growkernel: No level 0 kernel entry"));
2732 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
2733 if (pmap_load(l1) == 0) {
2734 /* We need a new PDP entry */
2735 nkpg = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT |
2736 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2738 panic("pmap_growkernel: no memory to grow kernel");
2739 nkpg->pindex = kernel_vm_end >> L1_SHIFT;
2740 /* See the dmb() in _pmap_alloc_l3(). */
2742 paddr = VM_PAGE_TO_PHYS(nkpg);
2743 pmap_store(l1, PHYS_TO_PTE(paddr) | L1_TABLE);
2744 continue; /* try again */
2746 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
2747 if (pmap_load(l2) != 0) {
2748 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2749 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2750 kernel_vm_end = vm_map_max(kernel_map);
2756 nkpg = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED |
2759 panic("pmap_growkernel: no memory to grow kernel");
2760 nkpg->pindex = kernel_vm_end >> L2_SHIFT;
2761 /* See the dmb() in _pmap_alloc_l3(). */
2763 paddr = VM_PAGE_TO_PHYS(nkpg);
2764 pmap_store(l2, PHYS_TO_PTE(paddr) | L2_TABLE);
2766 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2767 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2768 kernel_vm_end = vm_map_max(kernel_map);
2774 /***************************************************
2775 * page management routines.
2776 ***************************************************/
2778 static const uint64_t pc_freemask[_NPCM] = {
2779 [0 ... _NPCM - 2] = PC_FREEN,
2780 [_NPCM - 1] = PC_FREEL
2784 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2786 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2787 "Current number of pv entry chunks");
2788 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2789 "Current number of pv entry chunks allocated");
2790 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2791 "Current number of pv entry chunks frees");
2792 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2793 "Number of times tried to get a chunk page but failed.");
2795 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2796 static int pv_entry_spare;
2798 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2799 "Current number of pv entry frees");
2800 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2801 "Current number of pv entry allocs");
2802 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2803 "Current number of pv entries");
2804 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2805 "Current number of spare pv entries");
2809 * We are in a serious low memory condition. Resort to
2810 * drastic measures to free some pages so we can allocate
2811 * another pv entry chunk.
2813 * Returns NULL if PV entries were reclaimed from the specified pmap.
2815 * We do not, however, unmap 2mpages because subsequent accesses will
2816 * allocate per-page pv entries until repromotion occurs, thereby
2817 * exacerbating the shortage of free pv entries.
2820 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
2822 struct pv_chunks_list *pvc;
2823 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
2824 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
2825 struct md_page *pvh;
2827 pmap_t next_pmap, pmap;
2828 pt_entry_t *pte, tpte;
2832 struct spglist free;
2834 int bit, field, freed, lvl;
2836 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2837 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2842 bzero(&pc_marker_b, sizeof(pc_marker_b));
2843 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
2844 pc_marker = (struct pv_chunk *)&pc_marker_b;
2845 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
2847 pvc = &pv_chunks[domain];
2848 mtx_lock(&pvc->pvc_lock);
2849 pvc->active_reclaims++;
2850 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
2851 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
2852 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
2853 SLIST_EMPTY(&free)) {
2854 next_pmap = pc->pc_pmap;
2855 if (next_pmap == NULL) {
2857 * The next chunk is a marker. However, it is
2858 * not our marker, so active_reclaims must be
2859 * > 1. Consequently, the next_chunk code
2860 * will not rotate the pv_chunks list.
2864 mtx_unlock(&pvc->pvc_lock);
2867 * A pv_chunk can only be removed from the pc_lru list
2868 * when both pvc->pvc_lock is owned and the
2869 * corresponding pmap is locked.
2871 if (pmap != next_pmap) {
2872 if (pmap != NULL && pmap != locked_pmap)
2875 /* Avoid deadlock and lock recursion. */
2876 if (pmap > locked_pmap) {
2877 RELEASE_PV_LIST_LOCK(lockp);
2879 mtx_lock(&pvc->pvc_lock);
2881 } else if (pmap != locked_pmap) {
2882 if (PMAP_TRYLOCK(pmap)) {
2883 mtx_lock(&pvc->pvc_lock);
2886 pmap = NULL; /* pmap is not locked */
2887 mtx_lock(&pvc->pvc_lock);
2888 pc = TAILQ_NEXT(pc_marker, pc_lru);
2890 pc->pc_pmap != next_pmap)
2898 * Destroy every non-wired, 4 KB page mapping in the chunk.
2901 for (field = 0; field < _NPCM; field++) {
2902 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2903 inuse != 0; inuse &= ~(1UL << bit)) {
2904 bit = ffsl(inuse) - 1;
2905 pv = &pc->pc_pventry[field * 64 + bit];
2907 pde = pmap_pde(pmap, va, &lvl);
2910 pte = pmap_l2_to_l3(pde, va);
2911 tpte = pmap_load(pte);
2912 if ((tpte & ATTR_SW_WIRED) != 0)
2914 tpte = pmap_load_clear(pte);
2915 m = PHYS_TO_VM_PAGE(PTE_TO_PHYS(tpte));
2916 if (pmap_pte_dirty(pmap, tpte))
2918 if ((tpte & ATTR_AF) != 0) {
2919 pmap_s1_invalidate_page(pmap, va, true);
2920 vm_page_aflag_set(m, PGA_REFERENCED);
2922 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2923 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2925 if (TAILQ_EMPTY(&m->md.pv_list) &&
2926 (m->flags & PG_FICTITIOUS) == 0) {
2927 pvh = page_to_pvh(m);
2928 if (TAILQ_EMPTY(&pvh->pv_list)) {
2929 vm_page_aflag_clear(m,
2933 pc->pc_map[field] |= 1UL << bit;
2934 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
2939 mtx_lock(&pvc->pvc_lock);
2942 /* Every freed mapping is for a 4 KB page. */
2943 pmap_resident_count_dec(pmap, freed);
2944 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2945 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2946 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2947 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2948 if (pc_is_free(pc)) {
2949 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2950 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2951 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2952 /* Entire chunk is free; return it. */
2953 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2954 dump_drop_page(m_pc->phys_addr);
2955 mtx_lock(&pvc->pvc_lock);
2956 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
2959 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2960 mtx_lock(&pvc->pvc_lock);
2961 /* One freed pv entry in locked_pmap is sufficient. */
2962 if (pmap == locked_pmap)
2966 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
2967 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
2968 if (pvc->active_reclaims == 1 && pmap != NULL) {
2970 * Rotate the pv chunks list so that we do not
2971 * scan the same pv chunks that could not be
2972 * freed (because they contained a wired
2973 * and/or superpage mapping) on every
2974 * invocation of reclaim_pv_chunk().
2976 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker){
2977 MPASS(pc->pc_pmap != NULL);
2978 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
2979 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
2983 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
2984 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
2985 pvc->active_reclaims--;
2986 mtx_unlock(&pvc->pvc_lock);
2987 if (pmap != NULL && pmap != locked_pmap)
2989 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2990 m_pc = SLIST_FIRST(&free);
2991 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2992 /* Recycle a freed page table page. */
2993 m_pc->ref_count = 1;
2995 vm_page_free_pages_toq(&free, true);
3000 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
3005 domain = PCPU_GET(domain);
3006 for (i = 0; i < vm_ndomains; i++) {
3007 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
3010 domain = (domain + 1) % vm_ndomains;
3017 * free the pv_entry back to the free list
3020 free_pv_entry(pmap_t pmap, pv_entry_t pv)
3022 struct pv_chunk *pc;
3023 int idx, field, bit;
3025 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3026 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
3027 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
3028 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
3029 pc = pv_to_chunk(pv);
3030 idx = pv - &pc->pc_pventry[0];
3033 pc->pc_map[field] |= 1ul << bit;
3034 if (!pc_is_free(pc)) {
3035 /* 98% of the time, pc is already at the head of the list. */
3036 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
3037 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3038 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3042 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3047 free_pv_chunk_dequeued(struct pv_chunk *pc)
3051 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3052 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3053 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3054 /* entire chunk is free, return it */
3055 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3056 dump_drop_page(m->phys_addr);
3057 vm_page_unwire_noq(m);
3062 free_pv_chunk(struct pv_chunk *pc)
3064 struct pv_chunks_list *pvc;
3066 pvc = &pv_chunks[pc_to_domain(pc)];
3067 mtx_lock(&pvc->pvc_lock);
3068 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
3069 mtx_unlock(&pvc->pvc_lock);
3070 free_pv_chunk_dequeued(pc);
3074 free_pv_chunk_batch(struct pv_chunklist *batch)
3076 struct pv_chunks_list *pvc;
3077 struct pv_chunk *pc, *npc;
3080 for (i = 0; i < vm_ndomains; i++) {
3081 if (TAILQ_EMPTY(&batch[i]))
3083 pvc = &pv_chunks[i];
3084 mtx_lock(&pvc->pvc_lock);
3085 TAILQ_FOREACH(pc, &batch[i], pc_list) {
3086 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
3088 mtx_unlock(&pvc->pvc_lock);
3091 for (i = 0; i < vm_ndomains; i++) {
3092 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
3093 free_pv_chunk_dequeued(pc);
3099 * Returns a new PV entry, allocating a new PV chunk from the system when
3100 * needed. If this PV chunk allocation fails and a PV list lock pointer was
3101 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
3104 * The given PV list lock may be released.
3107 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
3109 struct pv_chunks_list *pvc;
3112 struct pv_chunk *pc;
3115 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3116 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
3118 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3120 for (field = 0; field < _NPCM; field++) {
3121 if (pc->pc_map[field]) {
3122 bit = ffsl(pc->pc_map[field]) - 1;
3126 if (field < _NPCM) {
3127 pv = &pc->pc_pventry[field * 64 + bit];
3128 pc->pc_map[field] &= ~(1ul << bit);
3129 /* If this was the last item, move it to tail */
3130 if (pc_is_full(pc)) {
3131 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3132 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
3135 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3136 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
3140 /* No free items, allocate another chunk */
3141 m = vm_page_alloc_noobj(VM_ALLOC_WIRED);
3143 if (lockp == NULL) {
3144 PV_STAT(pc_chunk_tryfail++);
3147 m = reclaim_pv_chunk(pmap, lockp);
3151 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3152 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3153 dump_add_page(m->phys_addr);
3154 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3156 memcpy(pc->pc_map, pc_freemask, sizeof(pc_freemask));
3157 pc->pc_map[0] &= ~1ul; /* preallocated bit 0 */
3158 pvc = &pv_chunks[vm_page_domain(m)];
3159 mtx_lock(&pvc->pvc_lock);
3160 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
3161 mtx_unlock(&pvc->pvc_lock);
3162 pv = &pc->pc_pventry[0];
3163 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3164 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3165 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
3170 * Ensure that the number of spare PV entries in the specified pmap meets or
3171 * exceeds the given count, "needed".
3173 * The given PV list lock may be released.
3176 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
3178 struct pv_chunks_list *pvc;
3179 struct pch new_tail[PMAP_MEMDOM];
3180 struct pv_chunk *pc;
3185 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3186 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
3189 * Newly allocated PV chunks must be stored in a private list until
3190 * the required number of PV chunks have been allocated. Otherwise,
3191 * reclaim_pv_chunk() could recycle one of these chunks. In
3192 * contrast, these chunks must be added to the pmap upon allocation.
3194 for (i = 0; i < PMAP_MEMDOM; i++)
3195 TAILQ_INIT(&new_tail[i]);
3198 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
3199 bit_count((bitstr_t *)pc->pc_map, 0,
3200 sizeof(pc->pc_map) * NBBY, &free);
3204 if (avail >= needed)
3207 for (reclaimed = false; avail < needed; avail += _NPCPV) {
3208 m = vm_page_alloc_noobj(VM_ALLOC_WIRED);
3210 m = reclaim_pv_chunk(pmap, lockp);
3215 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3216 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3217 dump_add_page(m->phys_addr);
3218 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3220 memcpy(pc->pc_map, pc_freemask, sizeof(pc_freemask));
3221 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3222 TAILQ_INSERT_TAIL(&new_tail[vm_page_domain(m)], pc, pc_lru);
3223 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3226 * The reclaim might have freed a chunk from the current pmap.
3227 * If that chunk contained available entries, we need to
3228 * re-count the number of available entries.
3233 for (i = 0; i < vm_ndomains; i++) {
3234 if (TAILQ_EMPTY(&new_tail[i]))
3236 pvc = &pv_chunks[i];
3237 mtx_lock(&pvc->pvc_lock);
3238 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
3239 mtx_unlock(&pvc->pvc_lock);
3244 * First find and then remove the pv entry for the specified pmap and virtual
3245 * address from the specified pv list. Returns the pv entry if found and NULL
3246 * otherwise. This operation can be performed on pv lists for either 4KB or
3247 * 2MB page mappings.
3249 static __inline pv_entry_t
3250 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3254 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3255 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3256 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3265 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3266 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3267 * entries for each of the 4KB page mappings.
3270 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3271 struct rwlock **lockp)
3273 struct md_page *pvh;
3274 struct pv_chunk *pc;
3276 vm_offset_t va_last;
3280 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3281 KASSERT((va & L2_OFFSET) == 0,
3282 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
3283 KASSERT((pa & L2_OFFSET) == 0,
3284 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
3285 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3288 * Transfer the 2mpage's pv entry for this mapping to the first
3289 * page's pv list. Once this transfer begins, the pv list lock
3290 * must not be released until the last pv entry is reinstantiated.
3292 pvh = pa_to_pvh(pa);
3293 pv = pmap_pvh_remove(pvh, pmap, va);
3294 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
3295 m = PHYS_TO_VM_PAGE(pa);
3296 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3298 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
3299 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
3300 va_last = va + L2_SIZE - PAGE_SIZE;
3302 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3303 KASSERT(!pc_is_full(pc), ("pmap_pv_demote_l2: missing spare"));
3304 for (field = 0; field < _NPCM; field++) {
3305 while (pc->pc_map[field]) {
3306 bit = ffsl(pc->pc_map[field]) - 1;
3307 pc->pc_map[field] &= ~(1ul << bit);
3308 pv = &pc->pc_pventry[field * 64 + bit];
3312 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3313 ("pmap_pv_demote_l2: page %p is not managed", m));
3314 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3320 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3321 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3324 if (pc_is_full(pc)) {
3325 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3326 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3328 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
3329 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
3333 * First find and then destroy the pv entry for the specified pmap and virtual
3334 * address. This operation can be performed on pv lists for either 4KB or 2MB
3338 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3342 pv = pmap_pvh_remove(pvh, pmap, va);
3343 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3344 free_pv_entry(pmap, pv);
3348 * Conditionally create the PV entry for a 4KB page mapping if the required
3349 * memory can be allocated without resorting to reclamation.
3352 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
3353 struct rwlock **lockp)
3357 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3358 /* Pass NULL instead of the lock pointer to disable reclamation. */
3359 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3361 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3362 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3370 * Create the PV entry for a 2MB page mapping. Always returns true unless the
3371 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
3372 * false if the PV entry cannot be allocated without resorting to reclamation.
3375 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
3376 struct rwlock **lockp)
3378 struct md_page *pvh;
3382 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3383 /* Pass NULL instead of the lock pointer to disable reclamation. */
3384 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
3385 NULL : lockp)) == NULL)
3388 pa = PTE_TO_PHYS(l2e);
3389 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3390 pvh = pa_to_pvh(pa);
3391 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3397 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
3399 pt_entry_t newl2, oldl2 __diagused;
3403 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
3404 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
3405 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3407 ml3 = pmap_remove_pt_page(pmap, va);
3409 panic("pmap_remove_kernel_l2: Missing pt page");
3411 ml3pa = VM_PAGE_TO_PHYS(ml3);
3412 newl2 = PHYS_TO_PTE(ml3pa) | L2_TABLE;
3415 * If this page table page was unmapped by a promotion, then it
3416 * contains valid mappings. Zero it to invalidate those mappings.
3418 if (vm_page_any_valid(ml3))
3419 pagezero((void *)PHYS_TO_DMAP(ml3pa));
3422 * Demote the mapping. The caller must have already invalidated the
3423 * mapping (i.e., the "break" in break-before-make).
3425 oldl2 = pmap_load_store(l2, newl2);
3426 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
3427 __func__, l2, oldl2));
3431 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
3434 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
3435 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
3437 struct md_page *pvh;
3439 vm_page_t m, ml3, mt;
3441 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3442 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
3443 old_l2 = pmap_load_clear(l2);
3444 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
3445 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
3448 * Since a promotion must break the 4KB page mappings before making
3449 * the 2MB page mapping, a pmap_s1_invalidate_page() suffices.
3451 pmap_s1_invalidate_page(pmap, sva, true);
3453 if (old_l2 & ATTR_SW_WIRED)
3454 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
3455 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
3456 if (old_l2 & ATTR_SW_MANAGED) {
3457 m = PHYS_TO_VM_PAGE(PTE_TO_PHYS(old_l2));
3458 pvh = page_to_pvh(m);
3459 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3460 pmap_pvh_free(pvh, pmap, sva);
3461 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) {
3462 if (pmap_pte_dirty(pmap, old_l2))
3464 if (old_l2 & ATTR_AF)
3465 vm_page_aflag_set(mt, PGA_REFERENCED);
3466 if (TAILQ_EMPTY(&mt->md.pv_list) &&
3467 TAILQ_EMPTY(&pvh->pv_list))
3468 vm_page_aflag_clear(mt, PGA_WRITEABLE);
3471 if (pmap == kernel_pmap) {
3472 pmap_remove_kernel_l2(pmap, l2, sva);
3474 ml3 = pmap_remove_pt_page(pmap, sva);
3476 KASSERT(vm_page_any_valid(ml3),
3477 ("pmap_remove_l2: l3 page not promoted"));
3478 pmap_resident_count_dec(pmap, 1);
3479 KASSERT(ml3->ref_count == NL3PG,
3480 ("pmap_remove_l2: l3 page ref count error"));
3482 pmap_add_delayed_free_list(ml3, free, FALSE);
3485 return (pmap_unuse_pt(pmap, sva, l1e, free));
3489 * pmap_remove_l3: do the things to unmap a page in a process
3492 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
3493 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
3495 struct md_page *pvh;
3499 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3500 old_l3 = pmap_load_clear(l3);
3501 pmap_s1_invalidate_page(pmap, va, true);
3502 if (old_l3 & ATTR_SW_WIRED)
3503 pmap->pm_stats.wired_count -= 1;
3504 pmap_resident_count_dec(pmap, 1);
3505 if (old_l3 & ATTR_SW_MANAGED) {
3506 m = PHYS_TO_VM_PAGE(PTE_TO_PHYS(old_l3));
3507 if (pmap_pte_dirty(pmap, old_l3))
3509 if (old_l3 & ATTR_AF)
3510 vm_page_aflag_set(m, PGA_REFERENCED);
3511 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3512 pmap_pvh_free(&m->md, pmap, va);
3513 if (TAILQ_EMPTY(&m->md.pv_list) &&
3514 (m->flags & PG_FICTITIOUS) == 0) {
3515 pvh = page_to_pvh(m);
3516 if (TAILQ_EMPTY(&pvh->pv_list))
3517 vm_page_aflag_clear(m, PGA_WRITEABLE);
3520 return (pmap_unuse_pt(pmap, va, l2e, free));
3524 * Remove the specified range of addresses from the L3 page table that is
3525 * identified by the given L2 entry.
3528 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
3529 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
3531 struct md_page *pvh;
3532 struct rwlock *new_lock;
3533 pt_entry_t *l3, old_l3;
3537 KASSERT(ADDR_IS_CANONICAL(sva),
3538 ("%s: Start address not in canonical form: %lx", __func__, sva));
3539 KASSERT(ADDR_IS_CANONICAL(eva) || eva == VM_MAX_USER_ADDRESS,
3540 ("%s: End address not in canonical form: %lx", __func__, eva));
3542 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3543 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
3544 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
3545 l3pg = !ADDR_IS_KERNEL(sva) ? PHYS_TO_VM_PAGE(PTE_TO_PHYS(l2e)) : NULL;
3547 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
3548 if (!pmap_l3_valid(pmap_load(l3))) {
3550 pmap_invalidate_range(pmap, va, sva, true);
3555 old_l3 = pmap_load_clear(l3);
3556 if ((old_l3 & ATTR_SW_WIRED) != 0)
3557 pmap->pm_stats.wired_count--;
3558 pmap_resident_count_dec(pmap, 1);
3559 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
3560 m = PHYS_TO_VM_PAGE(PTE_TO_PHYS(old_l3));
3561 if (pmap_pte_dirty(pmap, old_l3))
3563 if ((old_l3 & ATTR_AF) != 0)
3564 vm_page_aflag_set(m, PGA_REFERENCED);
3565 new_lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3566 if (new_lock != *lockp) {
3567 if (*lockp != NULL) {
3569 * Pending TLB invalidations must be
3570 * performed before the PV list lock is
3571 * released. Otherwise, a concurrent
3572 * pmap_remove_all() on a physical page
3573 * could return while a stale TLB entry
3574 * still provides access to that page.
3577 pmap_invalidate_range(pmap, va,
3586 pmap_pvh_free(&m->md, pmap, sva);
3587 if (TAILQ_EMPTY(&m->md.pv_list) &&
3588 (m->flags & PG_FICTITIOUS) == 0) {
3589 pvh = page_to_pvh(m);
3590 if (TAILQ_EMPTY(&pvh->pv_list))
3591 vm_page_aflag_clear(m, PGA_WRITEABLE);
3594 if (l3pg != NULL && pmap_unwire_l3(pmap, sva, l3pg, free)) {
3596 * _pmap_unwire_l3() has already invalidated the TLB
3597 * entries at all levels for "sva". So, we need not
3598 * perform "sva += L3_SIZE;" here. Moreover, we need
3599 * not perform "va = sva;" if "sva" is at the start
3600 * of a new valid range consisting of a single page.
3608 pmap_invalidate_range(pmap, va, sva, true);
3612 * Remove the given range of addresses from the specified map.
3614 * It is assumed that the start and end are properly
3615 * rounded to the page size.
3618 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3620 struct rwlock *lock;
3621 vm_offset_t va_next;
3622 pd_entry_t *l0, *l1, *l2;
3623 pt_entry_t l3_paddr;
3624 struct spglist free;
3627 * Perform an unsynchronized read. This is, however, safe.
3629 if (pmap->pm_stats.resident_count == 0)
3637 for (; sva < eva; sva = va_next) {
3638 if (pmap->pm_stats.resident_count == 0)
3641 l0 = pmap_l0(pmap, sva);
3642 if (pmap_load(l0) == 0) {
3643 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3649 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3652 l1 = pmap_l0_to_l1(l0, sva);
3653 if (pmap_load(l1) == 0)
3655 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
3656 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
3657 KASSERT(va_next <= eva,
3658 ("partial update of non-transparent 1G page "
3659 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
3660 pmap_load(l1), sva, eva, va_next));
3661 MPASS(pmap != kernel_pmap);
3662 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0);
3664 pmap_s1_invalidate_page(pmap, sva, true);
3665 pmap_resident_count_dec(pmap, L1_SIZE / PAGE_SIZE);
3666 pmap_unuse_pt(pmap, sva, pmap_load(l0), &free);
3671 * Calculate index for next page table.
3673 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3677 l2 = pmap_l1_to_l2(l1, sva);
3681 l3_paddr = pmap_load(l2);
3683 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
3684 if (sva + L2_SIZE == va_next && eva >= va_next) {
3685 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
3688 } else if (pmap_demote_l2_locked(pmap, l2, sva,
3691 l3_paddr = pmap_load(l2);
3695 * Weed out invalid mappings.
3697 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
3701 * Limit our scan to either the end of the va represented
3702 * by the current page table page, or to the end of the
3703 * range being removed.
3708 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
3714 vm_page_free_pages_toq(&free, true);
3718 * Remove the given range of addresses as part of a logical unmap
3719 * operation. This has the effect of calling pmap_remove(), but
3720 * also clears any metadata that should persist for the lifetime
3721 * of a logical mapping.
3724 pmap_map_delete(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3726 pmap_remove(pmap, sva, eva);
3730 * Routine: pmap_remove_all
3732 * Removes this physical page from
3733 * all physical maps in which it resides.
3734 * Reflects back modify bits to the pager.
3737 * Original versions of this routine were very
3738 * inefficient because they iteratively called
3739 * pmap_remove (slow...)
3743 pmap_remove_all(vm_page_t m)
3745 struct md_page *pvh;
3748 struct rwlock *lock;
3749 pd_entry_t *pde, tpde;
3750 pt_entry_t *pte, tpte;
3752 struct spglist free;
3753 int lvl, pvh_gen, md_gen;
3755 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3756 ("pmap_remove_all: page %p is not managed", m));
3758 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3759 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
3762 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3764 if (!PMAP_TRYLOCK(pmap)) {
3765 pvh_gen = pvh->pv_gen;
3769 if (pvh_gen != pvh->pv_gen) {
3775 pte = pmap_pte_exists(pmap, va, 2, __func__);
3776 pmap_demote_l2_locked(pmap, pte, va, &lock);
3779 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3781 if (!PMAP_TRYLOCK(pmap)) {
3782 pvh_gen = pvh->pv_gen;
3783 md_gen = m->md.pv_gen;
3787 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
3792 pmap_resident_count_dec(pmap, 1);
3794 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3795 KASSERT(pde != NULL,
3796 ("pmap_remove_all: no page directory entry found"));
3798 ("pmap_remove_all: invalid pde level %d", lvl));
3799 tpde = pmap_load(pde);
3801 pte = pmap_l2_to_l3(pde, pv->pv_va);
3802 tpte = pmap_load_clear(pte);
3803 if (tpte & ATTR_SW_WIRED)
3804 pmap->pm_stats.wired_count--;
3805 if ((tpte & ATTR_AF) != 0) {
3806 pmap_invalidate_page(pmap, pv->pv_va, true);
3807 vm_page_aflag_set(m, PGA_REFERENCED);
3811 * Update the vm_page_t clean and reference bits.
3813 if (pmap_pte_dirty(pmap, tpte))
3815 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
3816 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3818 free_pv_entry(pmap, pv);
3821 vm_page_aflag_clear(m, PGA_WRITEABLE);
3823 vm_page_free_pages_toq(&free, true);
3827 * Masks and sets bits in a level 2 page table entries in the specified pmap
3830 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
3836 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3837 PMAP_ASSERT_STAGE1(pmap);
3838 KASSERT((sva & L2_OFFSET) == 0,
3839 ("pmap_protect_l2: sva is not 2mpage aligned"));
3840 old_l2 = pmap_load(l2);
3841 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
3842 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
3845 * Return if the L2 entry already has the desired access restrictions
3848 if ((old_l2 & mask) == nbits)
3851 while (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
3855 * When a dirty read/write superpage mapping is write protected,
3856 * update the dirty field of each of the superpage's constituent 4KB
3859 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
3860 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3861 pmap_pte_dirty(pmap, old_l2)) {
3862 m = PHYS_TO_VM_PAGE(PTE_TO_PHYS(old_l2));
3863 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3868 * Since a promotion must break the 4KB page mappings before making
3869 * the 2MB page mapping, a pmap_s1_invalidate_page() suffices.
3871 pmap_s1_invalidate_page(pmap, sva, true);
3875 * Masks and sets bits in last level page table entries in the specified
3879 pmap_mask_set_locked(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, pt_entry_t mask,
3880 pt_entry_t nbits, bool invalidate)
3882 vm_offset_t va, va_next;
3883 pd_entry_t *l0, *l1, *l2;
3884 pt_entry_t *l3p, l3;
3886 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3887 for (; sva < eva; sva = va_next) {
3888 l0 = pmap_l0(pmap, sva);
3889 if (pmap_load(l0) == 0) {
3890 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3896 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3899 l1 = pmap_l0_to_l1(l0, sva);
3900 if (pmap_load(l1) == 0)
3902 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
3903 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
3904 KASSERT(va_next <= eva,
3905 ("partial update of non-transparent 1G page "
3906 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
3907 pmap_load(l1), sva, eva, va_next));
3908 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0);
3909 if ((pmap_load(l1) & mask) != nbits) {
3910 pmap_store(l1, (pmap_load(l1) & ~mask) | nbits);
3912 pmap_s1_invalidate_page(pmap, sva, true);
3917 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3921 l2 = pmap_l1_to_l2(l1, sva);
3922 if (pmap_load(l2) == 0)
3925 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3926 if (sva + L2_SIZE == va_next && eva >= va_next) {
3927 pmap_protect_l2(pmap, l2, sva, mask, nbits);
3929 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3932 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3933 ("pmap_protect: Invalid L2 entry after demotion"));
3939 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
3941 l3 = pmap_load(l3p);
3944 * Go to the next L3 entry if the current one is
3945 * invalid or already has the desired access
3946 * restrictions in place. (The latter case occurs
3947 * frequently. For example, in a "buildworld"
3948 * workload, almost 1 out of 4 L3 entries already
3949 * have the desired restrictions.)
3951 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
3952 if (va != va_next) {
3954 pmap_s1_invalidate_range(pmap,
3961 while (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) |
3966 * When a dirty read/write mapping is write protected,
3967 * update the page's dirty field.
3969 if ((l3 & ATTR_SW_MANAGED) != 0 &&
3970 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3971 pmap_pte_dirty(pmap, l3))
3972 vm_page_dirty(PHYS_TO_VM_PAGE(PTE_TO_PHYS(l3)));
3977 if (va != va_next && invalidate)
3978 pmap_s1_invalidate_range(pmap, va, sva, true);
3983 pmap_mask_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, pt_entry_t mask,
3984 pt_entry_t nbits, bool invalidate)
3987 pmap_mask_set_locked(pmap, sva, eva, mask, nbits, invalidate);
3992 * Set the physical protection on the
3993 * specified range of this map as requested.
3996 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3998 pt_entry_t mask, nbits;
4000 PMAP_ASSERT_STAGE1(pmap);
4001 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4002 if (prot == VM_PROT_NONE) {
4003 pmap_remove(pmap, sva, eva);
4008 if ((prot & VM_PROT_WRITE) == 0) {
4009 mask |= ATTR_S1_AP_RW_BIT | ATTR_SW_DBM;
4010 nbits |= ATTR_S1_AP(ATTR_S1_AP_RO);
4012 if ((prot & VM_PROT_EXECUTE) == 0) {
4014 nbits |= ATTR_S1_XN;
4016 if (pmap == kernel_pmap) {
4017 mask |= ATTR_KERN_GP;
4018 nbits |= ATTR_KERN_GP;
4023 pmap_mask_set(pmap, sva, eva, mask, nbits, true);
4027 pmap_disable_promotion(vm_offset_t sva, vm_size_t size)
4030 MPASS((sva & L3_OFFSET) == 0);
4031 MPASS(((sva + size) & L3_OFFSET) == 0);
4033 pmap_mask_set(kernel_pmap, sva, sva + size, ATTR_SW_NO_PROMOTE,
4034 ATTR_SW_NO_PROMOTE, false);
4038 * Inserts the specified page table page into the specified pmap's collection
4039 * of idle page table pages. Each of a pmap's page table pages is responsible
4040 * for mapping a distinct range of virtual addresses. The pmap's collection is
4041 * ordered by this virtual address range.
4043 * If "promoted" is false, then the page table page "mpte" must be zero filled;
4044 * "mpte"'s valid field will be set to 0.
4046 * If "promoted" is true and "all_l3e_AF_set" is false, then "mpte" must
4047 * contain valid mappings with identical attributes except for ATTR_AF;
4048 * "mpte"'s valid field will be set to 1.
4050 * If "promoted" and "all_l3e_AF_set" are both true, then "mpte" must contain
4051 * valid mappings with identical attributes including ATTR_AF; "mpte"'s valid
4052 * field will be set to VM_PAGE_BITS_ALL.
4055 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted,
4056 bool all_l3e_AF_set)
4059 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4060 KASSERT(promoted || !all_l3e_AF_set,
4061 ("a zero-filled PTP can't have ATTR_AF set in every PTE"));
4062 mpte->valid = promoted ? (all_l3e_AF_set ? VM_PAGE_BITS_ALL : 1) : 0;
4063 return (vm_radix_insert(&pmap->pm_root, mpte));
4067 * Removes the page table page mapping the specified virtual address from the
4068 * specified pmap's collection of idle page table pages, and returns it.
4069 * Otherwise, returns NULL if there is no page table page corresponding to the
4070 * specified virtual address.
4072 static __inline vm_page_t
4073 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
4076 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4077 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
4081 * Performs a break-before-make update of a pmap entry. This is needed when
4082 * either promoting or demoting pages to ensure the TLB doesn't get into an
4083 * inconsistent state.
4086 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
4087 vm_offset_t va, vm_size_t size)
4091 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4093 if ((newpte & ATTR_SW_NO_PROMOTE) != 0)
4094 panic("%s: Updating non-promote pte", __func__);
4097 * Ensure we don't get switched out with the page table in an
4098 * inconsistent state. We also need to ensure no interrupts fire
4099 * as they may make use of an address we are about to invalidate.
4101 intr = intr_disable();
4104 * Clear the old mapping's valid bit, but leave the rest of the entry
4105 * unchanged, so that a lockless, concurrent pmap_kextract() can still
4106 * lookup the physical address.
4108 pmap_clear_bits(pte, ATTR_DESCR_VALID);
4111 * When promoting, the L{1,2}_TABLE entry that is being replaced might
4112 * be cached, so we invalidate intermediate entries as well as final
4115 pmap_s1_invalidate_range(pmap, va, va + size, false);
4117 /* Create the new mapping */
4118 pmap_store(pte, newpte);
4124 #if VM_NRESERVLEVEL > 0
4126 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
4127 * replace the many pv entries for the 4KB page mappings by a single pv entry
4128 * for the 2MB page mapping.
4131 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4132 struct rwlock **lockp)
4134 struct md_page *pvh;
4136 vm_offset_t va_last;
4139 KASSERT((pa & L2_OFFSET) == 0,
4140 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
4141 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4144 * Transfer the first page's pv entry for this mapping to the 2mpage's
4145 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
4146 * a transfer avoids the possibility that get_pv_entry() calls
4147 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
4148 * mappings that is being promoted.
4150 m = PHYS_TO_VM_PAGE(pa);
4151 va = va & ~L2_OFFSET;
4152 pv = pmap_pvh_remove(&m->md, pmap, va);
4153 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
4154 pvh = page_to_pvh(m);
4155 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4157 /* Free the remaining NPTEPG - 1 pv entries. */
4158 va_last = va + L2_SIZE - PAGE_SIZE;
4162 pmap_pvh_free(&m->md, pmap, va);
4163 } while (va < va_last);
4167 * Tries to promote the 512, contiguous 4KB page mappings that are within a
4168 * single level 2 table entry to a single 2MB page mapping. For promotion
4169 * to occur, two conditions must be met: (1) the 4KB page mappings must map
4170 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
4171 * identical characteristics.
4174 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va, vm_page_t mpte,
4175 struct rwlock **lockp)
4177 pt_entry_t all_l3e_AF, *firstl3, *l3, newl2, oldl3, pa;
4179 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4182 * Currently, this function only supports promotion on stage 1 pmaps
4183 * because it tests stage 1 specific fields and performs a break-
4184 * before-make sequence that is incorrect for stage 2 pmaps.
4186 if (pmap->pm_stage != PM_STAGE1 || !pmap_ps_enabled(pmap))
4190 * Examine the first L3E in the specified PTP. Abort if this L3E is
4191 * ineligible for promotion...
4193 firstl3 = (pt_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(pmap_load(l2)));
4194 newl2 = pmap_load(firstl3);
4195 if ((newl2 & ATTR_SW_NO_PROMOTE) != 0)
4197 /* ... is not the first physical page within an L2 block */
4198 if ((PTE_TO_PHYS(newl2) & L2_OFFSET) != 0 ||
4199 ((newl2 & ATTR_DESCR_MASK) != L3_PAGE)) { /* ... or is invalid */
4200 atomic_add_long(&pmap_l2_p_failures, 1);
4201 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
4202 " in pmap %p", va, pmap);
4207 * Both here and in the below "for" loop, to allow for repromotion
4208 * after MADV_FREE, conditionally write protect a clean L3E before
4209 * possibly aborting the promotion due to other L3E attributes. Why?
4210 * Suppose that MADV_FREE is applied to a part of a superpage, the
4211 * address range [S, E). pmap_advise() will demote the superpage
4212 * mapping, destroy the 4KB page mapping at the end of [S, E), and
4213 * set AP_RO and clear AF in the L3Es for the rest of [S, E). Later,
4214 * imagine that the memory in [S, E) is recycled, but the last 4KB
4215 * page in [S, E) is not the last to be rewritten, or simply accessed.
4216 * In other words, there is still a 4KB page in [S, E), call it P,
4217 * that is writeable but AP_RO is set and AF is clear in P's L3E.
4218 * Unless we write protect P before aborting the promotion, if and
4219 * when P is finally rewritten, there won't be a page fault to trigger
4223 if ((newl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
4224 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
4226 * When the mapping is clean, i.e., ATTR_S1_AP_RO is set,
4227 * ATTR_SW_DBM can be cleared without a TLB invalidation.
4229 if (!atomic_fcmpset_64(firstl3, &newl2, newl2 & ~ATTR_SW_DBM))
4231 newl2 &= ~ATTR_SW_DBM;
4232 CTR2(KTR_PMAP, "pmap_promote_l2: protect for va %#lx"
4233 " in pmap %p", va & ~L2_OFFSET, pmap);
4237 * Examine each of the other L3Es in the specified PTP. Abort if this
4238 * L3E maps an unexpected 4KB physical page or does not have identical
4239 * characteristics to the first L3E. If ATTR_AF is not set in every
4240 * PTE, then request that the PTP be refilled on demotion.
4242 all_l3e_AF = newl2 & ATTR_AF;
4243 pa = (PTE_TO_PHYS(newl2) | (newl2 & ATTR_DESCR_MASK))
4244 + L2_SIZE - PAGE_SIZE;
4245 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
4246 oldl3 = pmap_load(l3);
4247 if ((PTE_TO_PHYS(oldl3) | (oldl3 & ATTR_DESCR_MASK)) != pa) {
4248 atomic_add_long(&pmap_l2_p_failures, 1);
4249 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
4250 " in pmap %p", va, pmap);
4254 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
4255 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
4257 * When the mapping is clean, i.e., ATTR_S1_AP_RO is
4258 * set, ATTR_SW_DBM can be cleared without a TLB
4261 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
4264 oldl3 &= ~ATTR_SW_DBM;
4266 if ((oldl3 & (ATTR_MASK & ~ATTR_AF)) != (newl2 & (ATTR_MASK &
4268 atomic_add_long(&pmap_l2_p_failures, 1);
4269 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
4270 " in pmap %p", va, pmap);
4273 all_l3e_AF &= oldl3;
4278 * Unless all PTEs have ATTR_AF set, clear it from the superpage
4279 * mapping, so that promotions triggered by speculative mappings,
4280 * such as pmap_enter_quick(), don't automatically mark the
4281 * underlying pages as referenced.
4283 newl2 &= ~ATTR_AF | all_l3e_AF;
4286 * Save the page table page in its current state until the L2
4287 * mapping the superpage is demoted by pmap_demote_l2() or
4288 * destroyed by pmap_remove_l3().
4291 mpte = PHYS_TO_VM_PAGE(PTE_TO_PHYS(pmap_load(l2)));
4292 KASSERT(mpte >= vm_page_array &&
4293 mpte < &vm_page_array[vm_page_array_size],
4294 ("pmap_promote_l2: page table page is out of range"));
4295 KASSERT(mpte->pindex == pmap_l2_pindex(va),
4296 ("pmap_promote_l2: page table page's pindex is wrong"));
4297 if (pmap_insert_pt_page(pmap, mpte, true, all_l3e_AF != 0)) {
4298 atomic_add_long(&pmap_l2_p_failures, 1);
4300 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
4305 if ((newl2 & ATTR_SW_MANAGED) != 0)
4306 pmap_pv_promote_l2(pmap, va, PTE_TO_PHYS(newl2), lockp);
4308 newl2 &= ~ATTR_DESCR_MASK;
4311 pmap_update_entry(pmap, l2, newl2, va & ~L2_OFFSET, L2_SIZE);
4313 atomic_add_long(&pmap_l2_promotions, 1);
4314 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
4318 #endif /* VM_NRESERVLEVEL > 0 */
4321 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags,
4324 pd_entry_t *l0p, *l1p, *l2p, origpte;
4327 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4328 KASSERT(psind > 0 && psind < MAXPAGESIZES,
4329 ("psind %d unexpected", psind));
4330 KASSERT((PTE_TO_PHYS(newpte) & (pagesizes[psind] - 1)) == 0,
4331 ("unaligned phys address %#lx newpte %#lx psind %d",
4332 PTE_TO_PHYS(newpte), newpte, psind));
4336 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
4338 l0p = pmap_l0(pmap, va);
4339 if ((pmap_load(l0p) & ATTR_DESCR_VALID) == 0) {
4340 mp = _pmap_alloc_l3(pmap, pmap_l0_pindex(va), NULL);
4342 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
4343 return (KERN_RESOURCE_SHORTAGE);
4349 l1p = pmap_l0_to_l1(l0p, va);
4350 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va));
4351 origpte = pmap_load(l1p);
4353 l1p = pmap_l0_to_l1(l0p, va);
4354 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va));
4355 origpte = pmap_load(l1p);
4356 if ((origpte & ATTR_DESCR_VALID) == 0) {
4357 mp = PHYS_TO_VM_PAGE(
4358 PTE_TO_PHYS(pmap_load(l0p)));
4362 KASSERT((PTE_TO_PHYS(origpte) == PTE_TO_PHYS(newpte) &&
4363 (origpte & ATTR_DESCR_MASK) == L1_BLOCK) ||
4364 (origpte & ATTR_DESCR_VALID) == 0,
4365 ("va %#lx changing 1G phys page l1 %#lx newpte %#lx",
4366 va, origpte, newpte));
4367 pmap_store(l1p, newpte);
4368 } else /* (psind == 1) */ {
4369 l2p = pmap_l2(pmap, va);
4371 mp = _pmap_alloc_l3(pmap, pmap_l1_pindex(va), NULL);
4373 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
4374 return (KERN_RESOURCE_SHORTAGE);
4380 l2p = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
4381 l2p = &l2p[pmap_l2_index(va)];
4382 origpte = pmap_load(l2p);
4384 l1p = pmap_l1(pmap, va);
4385 origpte = pmap_load(l2p);
4386 if ((origpte & ATTR_DESCR_VALID) == 0) {
4387 mp = PHYS_TO_VM_PAGE(
4388 PTE_TO_PHYS(pmap_load(l1p)));
4392 KASSERT((origpte & ATTR_DESCR_VALID) == 0 ||
4393 ((origpte & ATTR_DESCR_MASK) == L2_BLOCK &&
4394 PTE_TO_PHYS(origpte) == PTE_TO_PHYS(newpte)),
4395 ("va %#lx changing 2M phys page l2 %#lx newpte %#lx",
4396 va, origpte, newpte));
4397 pmap_store(l2p, newpte);
4401 if ((origpte & ATTR_DESCR_VALID) == 0)
4402 pmap_resident_count_inc(pmap, pagesizes[psind] / PAGE_SIZE);
4403 if ((newpte & ATTR_SW_WIRED) != 0 && (origpte & ATTR_SW_WIRED) == 0)
4404 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE;
4405 else if ((newpte & ATTR_SW_WIRED) == 0 &&
4406 (origpte & ATTR_SW_WIRED) != 0)
4407 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE;
4409 return (KERN_SUCCESS);
4413 * Insert the given physical page (p) at
4414 * the specified virtual address (v) in the
4415 * target physical map with the protection requested.
4417 * If specified, the page will be wired down, meaning
4418 * that the related pte can not be reclaimed.
4420 * NB: This is the only routine which MAY NOT lazy-evaluate
4421 * or lose information. That is, this routine must actually
4422 * insert this page into the given map NOW.
4425 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4426 u_int flags, int8_t psind)
4428 struct rwlock *lock;
4430 pt_entry_t new_l3, orig_l3;
4431 pt_entry_t *l2, *l3;
4438 KASSERT(ADDR_IS_CANONICAL(va),
4439 ("%s: Address not in canonical form: %lx", __func__, va));
4441 va = trunc_page(va);
4442 if ((m->oflags & VPO_UNMANAGED) == 0)
4443 VM_PAGE_OBJECT_BUSY_ASSERT(m);
4444 pa = VM_PAGE_TO_PHYS(m);
4445 new_l3 = (pt_entry_t)(PHYS_TO_PTE(pa) | ATTR_DEFAULT | L3_PAGE);
4446 new_l3 |= pmap_pte_memattr(pmap, m->md.pv_memattr);
4447 new_l3 |= pmap_pte_prot(pmap, prot);
4448 if ((flags & PMAP_ENTER_WIRED) != 0)
4449 new_l3 |= ATTR_SW_WIRED;
4450 if (pmap->pm_stage == PM_STAGE1) {
4451 if (!ADDR_IS_KERNEL(va))
4452 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4454 new_l3 |= ATTR_S1_UXN;
4455 if (pmap != kernel_pmap)
4456 new_l3 |= ATTR_S1_nG;
4459 * Clear the access flag on executable mappings, this will be
4460 * set later when the page is accessed. The fault handler is
4461 * required to invalidate the I-cache.
4463 * TODO: Switch to the valid flag to allow hardware management
4464 * of the access flag. Much of the pmap code assumes the
4465 * valid flag is set and fails to destroy the old page tables
4466 * correctly if it is clear.
4468 if (prot & VM_PROT_EXECUTE)
4471 if ((m->oflags & VPO_UNMANAGED) == 0) {
4472 new_l3 |= ATTR_SW_MANAGED;
4473 if ((prot & VM_PROT_WRITE) != 0) {
4474 new_l3 |= ATTR_SW_DBM;
4475 if ((flags & VM_PROT_WRITE) == 0) {
4476 if (pmap->pm_stage == PM_STAGE1)
4477 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
4480 ~ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
4485 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
4489 /* Wait until we lock the pmap to protect the bti rangeset */
4490 new_l3 |= pmap_pte_bti(pmap, va);
4492 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) {
4493 KASSERT((m->oflags & VPO_UNMANAGED) != 0,
4494 ("managed largepage va %#lx flags %#x", va, flags));
4497 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
4499 } else /* (psind == 1) */
4501 rv = pmap_enter_largepage(pmap, va, new_l3, flags, psind);
4505 /* Assert the required virtual and physical alignment. */
4506 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
4507 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
4508 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
4515 * In the case that a page table page is not
4516 * resident, we are creating it here.
4519 pde = pmap_pde(pmap, va, &lvl);
4520 if (pde != NULL && lvl == 2) {
4521 l3 = pmap_l2_to_l3(pde, va);
4522 if (!ADDR_IS_KERNEL(va) && mpte == NULL) {
4523 mpte = PHYS_TO_VM_PAGE(PTE_TO_PHYS(pmap_load(pde)));
4527 } else if (pde != NULL && lvl == 1) {
4528 l2 = pmap_l1_to_l2(pde, va);
4529 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
4530 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
4531 l3 = &l3[pmap_l3_index(va)];
4532 if (!ADDR_IS_KERNEL(va)) {
4533 mpte = PHYS_TO_VM_PAGE(
4534 PTE_TO_PHYS(pmap_load(l2)));
4539 /* We need to allocate an L3 table. */
4541 if (!ADDR_IS_KERNEL(va)) {
4542 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
4545 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
4546 * to handle the possibility that a superpage mapping for "va"
4547 * was created while we slept.
4549 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
4550 nosleep ? NULL : &lock);
4551 if (mpte == NULL && nosleep) {
4552 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
4553 rv = KERN_RESOURCE_SHORTAGE;
4558 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
4561 orig_l3 = pmap_load(l3);
4562 opa = PTE_TO_PHYS(orig_l3);
4566 * Is the specified virtual address already mapped?
4568 if (pmap_l3_valid(orig_l3)) {
4570 * Wiring change, just update stats. We don't worry about
4571 * wiring PT pages as they remain resident as long as there
4572 * are valid mappings in them. Hence, if a user page is wired,
4573 * the PT page will be also.
4575 if ((flags & PMAP_ENTER_WIRED) != 0 &&
4576 (orig_l3 & ATTR_SW_WIRED) == 0)
4577 pmap->pm_stats.wired_count++;
4578 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
4579 (orig_l3 & ATTR_SW_WIRED) != 0)
4580 pmap->pm_stats.wired_count--;
4583 * Remove the extra PT page reference.
4587 KASSERT(mpte->ref_count > 0,
4588 ("pmap_enter: missing reference to page table page,"
4593 * Has the physical page changed?
4597 * No, might be a protection or wiring change.
4599 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
4600 (new_l3 & ATTR_SW_DBM) != 0)
4601 vm_page_aflag_set(m, PGA_WRITEABLE);
4606 * The physical page has changed. Temporarily invalidate
4609 orig_l3 = pmap_load_clear(l3);
4610 KASSERT(PTE_TO_PHYS(orig_l3) == opa,
4611 ("pmap_enter: unexpected pa update for %#lx", va));
4612 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
4613 om = PHYS_TO_VM_PAGE(opa);
4616 * The pmap lock is sufficient to synchronize with
4617 * concurrent calls to pmap_page_test_mappings() and
4618 * pmap_ts_referenced().
4620 if (pmap_pte_dirty(pmap, orig_l3))
4622 if ((orig_l3 & ATTR_AF) != 0) {
4623 pmap_invalidate_page(pmap, va, true);
4624 vm_page_aflag_set(om, PGA_REFERENCED);
4626 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, om);
4627 pv = pmap_pvh_remove(&om->md, pmap, va);
4628 if ((m->oflags & VPO_UNMANAGED) != 0)
4629 free_pv_entry(pmap, pv);
4630 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
4631 TAILQ_EMPTY(&om->md.pv_list) &&
4632 ((om->flags & PG_FICTITIOUS) != 0 ||
4633 TAILQ_EMPTY(&page_to_pvh(om)->pv_list)))
4634 vm_page_aflag_clear(om, PGA_WRITEABLE);
4636 KASSERT((orig_l3 & ATTR_AF) != 0,
4637 ("pmap_enter: unmanaged mapping lacks ATTR_AF"));
4638 pmap_invalidate_page(pmap, va, true);
4643 * Increment the counters.
4645 if ((new_l3 & ATTR_SW_WIRED) != 0)
4646 pmap->pm_stats.wired_count++;
4647 pmap_resident_count_inc(pmap, 1);
4650 * Enter on the PV list if part of our managed memory.
4652 if ((m->oflags & VPO_UNMANAGED) == 0) {
4654 pv = get_pv_entry(pmap, &lock);
4657 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4658 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4660 if ((new_l3 & ATTR_SW_DBM) != 0)
4661 vm_page_aflag_set(m, PGA_WRITEABLE);
4665 if (pmap->pm_stage == PM_STAGE1) {
4667 * Sync icache if exec permission and attribute
4668 * VM_MEMATTR_WRITE_BACK is set. Do it now, before the mapping
4669 * is stored and made valid for hardware table walk. If done
4670 * later, then other can access this page before caches are
4671 * properly synced. Don't do it for kernel memory which is
4672 * mapped with exec permission even if the memory isn't going
4673 * to hold executable code. The only time when icache sync is
4674 * needed is after kernel module is loaded and the relocation
4675 * info is processed. And it's done in elf_cpu_load_file().
4677 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4678 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
4679 (opa != pa || (orig_l3 & ATTR_S1_XN))) {
4680 PMAP_ASSERT_STAGE1(pmap);
4681 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4684 cpu_dcache_wb_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4688 * Update the L3 entry
4690 if (pmap_l3_valid(orig_l3)) {
4691 KASSERT(opa == pa, ("pmap_enter: invalid update"));
4692 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
4693 /* same PA, different attributes */
4694 orig_l3 = pmap_load_store(l3, new_l3);
4695 pmap_invalidate_page(pmap, va, true);
4696 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
4697 pmap_pte_dirty(pmap, orig_l3))
4702 * This can happens if multiple threads simultaneously
4703 * access not yet mapped page. This bad for performance
4704 * since this can cause full demotion-NOP-promotion
4706 * Another possible reasons are:
4707 * - VM and pmap memory layout are diverged
4708 * - tlb flush is missing somewhere and CPU doesn't see
4711 CTR4(KTR_PMAP, "%s: already mapped page - "
4712 "pmap %p va 0x%#lx pte 0x%lx",
4713 __func__, pmap, va, new_l3);
4717 pmap_store(l3, new_l3);
4721 #if VM_NRESERVLEVEL > 0
4723 * If both the page table page and the reservation are fully
4724 * populated, then attempt promotion.
4726 if ((mpte == NULL || mpte->ref_count == NL3PG) &&
4727 (m->flags & PG_FICTITIOUS) == 0 &&
4728 vm_reserv_level_iffullpop(m) == 0)
4729 (void)pmap_promote_l2(pmap, pde, va, mpte, &lock);
4741 * Tries to create a read- and/or execute-only 2MB page mapping. Returns
4742 * KERN_SUCCESS if the mapping was created. Otherwise, returns an error
4743 * value. See pmap_enter_l2() for the possible error values when "no sleep",
4744 * "no replace", and "no reclaim" are specified.
4747 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4748 struct rwlock **lockp)
4752 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4753 PMAP_ASSERT_STAGE1(pmap);
4754 KASSERT(ADDR_IS_CANONICAL(va),
4755 ("%s: Address not in canonical form: %lx", __func__, va));
4757 new_l2 = (pd_entry_t)(PHYS_TO_PTE(VM_PAGE_TO_PHYS(m)) | ATTR_DEFAULT |
4758 ATTR_S1_IDX(m->md.pv_memattr) | ATTR_S1_AP(ATTR_S1_AP_RO) |
4760 new_l2 |= pmap_pte_bti(pmap, va);
4761 if ((m->oflags & VPO_UNMANAGED) == 0) {
4762 new_l2 |= ATTR_SW_MANAGED;
4765 if ((prot & VM_PROT_EXECUTE) == 0 ||
4766 m->md.pv_memattr == VM_MEMATTR_DEVICE)
4767 new_l2 |= ATTR_S1_XN;
4768 if (!ADDR_IS_KERNEL(va))
4769 new_l2 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4771 new_l2 |= ATTR_S1_UXN;
4772 if (pmap != kernel_pmap)
4773 new_l2 |= ATTR_S1_nG;
4774 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
4775 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, m, lockp));
4779 * Returns true if every page table entry in the specified page table is
4783 pmap_every_pte_zero(vm_paddr_t pa)
4785 pt_entry_t *pt_end, *pte;
4787 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
4788 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
4789 for (pt_end = pte + Ln_ENTRIES; pte < pt_end; pte++) {
4797 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
4798 * the mapping was created, and one of KERN_FAILURE, KERN_NO_SPACE, or
4799 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if
4800 * PMAP_ENTER_NOREPLACE was specified and a 4KB page mapping already exists
4801 * within the 2MB virtual address range starting at the specified virtual
4802 * address. Returns KERN_NO_SPACE if PMAP_ENTER_NOREPLACE was specified and a
4803 * 2MB page mapping already exists at the specified virtual address. Returns
4804 * KERN_RESOURCE_SHORTAGE if either (1) PMAP_ENTER_NOSLEEP was specified and a
4805 * page table page allocation failed or (2) PMAP_ENTER_NORECLAIM was specified
4806 * and a PV entry allocation failed.
4809 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
4810 vm_page_t m, struct rwlock **lockp)
4812 struct spglist free;
4813 pd_entry_t *l2, old_l2;
4817 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4818 KASSERT(ADDR_IS_CANONICAL(va),
4819 ("%s: Address not in canonical form: %lx", __func__, va));
4821 if ((l2 = pmap_alloc_l2(pmap, va, &l2pg, (flags &
4822 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
4823 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
4825 return (KERN_RESOURCE_SHORTAGE);
4829 * If there are existing mappings, either abort or remove them.
4831 if ((old_l2 = pmap_load(l2)) != 0) {
4832 KASSERT(l2pg == NULL || l2pg->ref_count > 1,
4833 ("pmap_enter_l2: l2pg's ref count is too low"));
4834 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
4835 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK) {
4839 "pmap_enter_l2: no space for va %#lx"
4840 " in pmap %p", va, pmap);
4841 return (KERN_NO_SPACE);
4842 } else if (!ADDR_IS_KERNEL(va) ||
4843 !pmap_every_pte_zero(PTE_TO_PHYS(old_l2))) {
4847 "pmap_enter_l2: failure for va %#lx"
4848 " in pmap %p", va, pmap);
4849 return (KERN_FAILURE);
4853 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
4854 (void)pmap_remove_l2(pmap, l2, va,
4855 pmap_load(pmap_l1(pmap, va)), &free, lockp);
4857 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
4859 if (!ADDR_IS_KERNEL(va)) {
4860 vm_page_free_pages_toq(&free, true);
4861 KASSERT(pmap_load(l2) == 0,
4862 ("pmap_enter_l2: non-zero L2 entry %p", l2));
4864 KASSERT(SLIST_EMPTY(&free),
4865 ("pmap_enter_l2: freed kernel page table page"));
4868 * Both pmap_remove_l2() and pmap_remove_l3_range()
4869 * will leave the kernel page table page zero filled.
4870 * Nonetheless, the TLB could have an intermediate
4871 * entry for the kernel page table page, so request
4872 * an invalidation at all levels after clearing
4873 * the L2_TABLE entry.
4875 mt = PHYS_TO_VM_PAGE(PTE_TO_PHYS(pmap_load(l2)));
4876 if (pmap_insert_pt_page(pmap, mt, false, false))
4877 panic("pmap_enter_l2: trie insert failed");
4879 pmap_s1_invalidate_page(pmap, va, false);
4884 * Allocate leaf ptpage for wired userspace pages.
4887 if ((new_l2 & ATTR_SW_WIRED) != 0 && pmap != kernel_pmap) {
4888 uwptpg = vm_page_alloc_noobj(VM_ALLOC_WIRED);
4889 if (uwptpg == NULL) {
4890 return (KERN_RESOURCE_SHORTAGE);
4892 uwptpg->pindex = pmap_l2_pindex(va);
4893 if (pmap_insert_pt_page(pmap, uwptpg, true, false)) {
4894 vm_page_unwire_noq(uwptpg);
4895 vm_page_free(uwptpg);
4896 return (KERN_RESOURCE_SHORTAGE);
4898 pmap_resident_count_inc(pmap, 1);
4899 uwptpg->ref_count = NL3PG;
4901 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
4903 * Abort this mapping if its PV entry could not be created.
4905 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
4907 pmap_abort_ptp(pmap, va, l2pg);
4908 if (uwptpg != NULL) {
4909 mt = pmap_remove_pt_page(pmap, va);
4910 KASSERT(mt == uwptpg,
4911 ("removed pt page %p, expected %p", mt,
4913 pmap_resident_count_dec(pmap, 1);
4914 uwptpg->ref_count = 1;
4915 vm_page_unwire_noq(uwptpg);
4916 vm_page_free(uwptpg);
4919 "pmap_enter_l2: failure for va %#lx in pmap %p",
4921 return (KERN_RESOURCE_SHORTAGE);
4923 if ((new_l2 & ATTR_SW_DBM) != 0)
4924 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4925 vm_page_aflag_set(mt, PGA_WRITEABLE);
4929 * Increment counters.
4931 if ((new_l2 & ATTR_SW_WIRED) != 0)
4932 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
4933 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
4936 * Conditionally sync the icache. See pmap_enter() for details.
4938 if ((new_l2 & ATTR_S1_XN) == 0 && (PTE_TO_PHYS(new_l2) !=
4939 PTE_TO_PHYS(old_l2) || (old_l2 & ATTR_S1_XN) != 0) &&
4940 pmap != kernel_pmap && m->md.pv_memattr == VM_MEMATTR_WRITE_BACK) {
4941 cpu_icache_sync_range(PHYS_TO_DMAP(PTE_TO_PHYS(new_l2)),
4946 * Map the superpage.
4948 pmap_store(l2, new_l2);
4951 atomic_add_long(&pmap_l2_mappings, 1);
4952 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
4955 return (KERN_SUCCESS);
4959 * Maps a sequence of resident pages belonging to the same object.
4960 * The sequence begins with the given page m_start. This page is
4961 * mapped at the given virtual address start. Each subsequent page is
4962 * mapped at a virtual address that is offset from start by the same
4963 * amount as the page is offset from m_start within the object. The
4964 * last page in the sequence is the page with the largest offset from
4965 * m_start that can be mapped at a virtual address less than the given
4966 * virtual address end. Not every virtual page between start and end
4967 * is mapped; only those for which a resident page exists with the
4968 * corresponding offset from m_start are mapped.
4971 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4972 vm_page_t m_start, vm_prot_t prot)
4974 struct rwlock *lock;
4977 vm_pindex_t diff, psize;
4980 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4982 psize = atop(end - start);
4987 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4988 va = start + ptoa(diff);
4989 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
4990 m->psind == 1 && pmap_ps_enabled(pmap) &&
4991 ((rv = pmap_enter_2mpage(pmap, va, m, prot, &lock)) ==
4992 KERN_SUCCESS || rv == KERN_NO_SPACE))
4993 m = &m[L2_SIZE / PAGE_SIZE - 1];
4995 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
4997 m = TAILQ_NEXT(m, listq);
5005 * this code makes some *MAJOR* assumptions:
5006 * 1. Current pmap & pmap exists.
5009 * 4. No page table pages.
5010 * but is *MUCH* faster than pmap_enter...
5014 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
5016 struct rwlock *lock;
5020 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
5027 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
5028 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
5031 pt_entry_t *l1, *l2, *l3, l3_val;
5035 KASSERT(!VA_IS_CLEANMAP(va) ||
5036 (m->oflags & VPO_UNMANAGED) != 0,
5037 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
5038 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5039 PMAP_ASSERT_STAGE1(pmap);
5040 KASSERT(ADDR_IS_CANONICAL(va),
5041 ("%s: Address not in canonical form: %lx", __func__, va));
5044 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
5046 * In the case that a page table page is not
5047 * resident, we are creating it here.
5049 if (!ADDR_IS_KERNEL(va)) {
5050 vm_pindex_t l2pindex;
5053 * Calculate pagetable page index
5055 l2pindex = pmap_l2_pindex(va);
5056 if (mpte && (mpte->pindex == l2pindex)) {
5060 * If the page table page is mapped, we just increment
5061 * the hold count, and activate it. Otherwise, we
5062 * attempt to allocate a page table page, passing NULL
5063 * instead of the PV list lock pointer because we don't
5064 * intend to sleep. If this attempt fails, we don't
5065 * retry. Instead, we give up.
5067 l1 = pmap_l1(pmap, va);
5068 if (l1 != NULL && pmap_load(l1) != 0) {
5069 if ((pmap_load(l1) & ATTR_DESCR_MASK) ==
5072 l2 = pmap_l1_to_l2(l1, va);
5073 if (pmap_load(l2) != 0) {
5074 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
5077 mpte = PHYS_TO_VM_PAGE(
5078 PTE_TO_PHYS(pmap_load(l2)));
5081 mpte = _pmap_alloc_l3(pmap, l2pindex,
5087 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
5092 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
5093 l3 = &l3[pmap_l3_index(va)];
5096 pde = pmap_pde(kernel_pmap, va, &lvl);
5097 KASSERT(pde != NULL,
5098 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
5101 ("pmap_enter_quick_locked: Invalid level %d", lvl));
5102 l3 = pmap_l2_to_l3(pde, va);
5106 * Abort if a mapping already exists.
5108 if (pmap_load(l3) != 0) {
5115 * Enter on the PV list if part of our managed memory.
5117 if ((m->oflags & VPO_UNMANAGED) == 0 &&
5118 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
5120 pmap_abort_ptp(pmap, va, mpte);
5125 * Increment counters
5127 pmap_resident_count_inc(pmap, 1);
5129 pa = VM_PAGE_TO_PHYS(m);
5130 l3_val = PHYS_TO_PTE(pa) | ATTR_DEFAULT | ATTR_S1_IDX(m->md.pv_memattr) |
5131 ATTR_S1_AP(ATTR_S1_AP_RO) | L3_PAGE;
5132 l3_val |= pmap_pte_bti(pmap, va);
5133 if ((prot & VM_PROT_EXECUTE) == 0 ||
5134 m->md.pv_memattr == VM_MEMATTR_DEVICE)
5135 l3_val |= ATTR_S1_XN;
5136 if (!ADDR_IS_KERNEL(va))
5137 l3_val |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
5139 l3_val |= ATTR_S1_UXN;
5140 if (pmap != kernel_pmap)
5141 l3_val |= ATTR_S1_nG;
5144 * Now validate mapping with RO protection
5146 if ((m->oflags & VPO_UNMANAGED) == 0) {
5147 l3_val |= ATTR_SW_MANAGED;
5151 /* Sync icache before the mapping is stored to PTE */
5152 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
5153 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
5154 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
5156 pmap_store(l3, l3_val);
5159 #if VM_NRESERVLEVEL > 0
5161 * If both the PTP and the reservation are fully populated, then
5162 * attempt promotion.
5164 if ((mpte == NULL || mpte->ref_count == NL3PG) &&
5165 (m->flags & PG_FICTITIOUS) == 0 &&
5166 vm_reserv_level_iffullpop(m) == 0) {
5168 l2 = pmap_pde(pmap, va, &lvl);
5171 * If promotion succeeds, then the next call to this function
5172 * should not be given the unmapped PTP as a hint.
5174 if (pmap_promote_l2(pmap, l2, va, mpte, lockp))
5183 * This code maps large physical mmap regions into the
5184 * processor address space. Note that some shortcuts
5185 * are taken, but the code works.
5188 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
5189 vm_pindex_t pindex, vm_size_t size)
5192 VM_OBJECT_ASSERT_WLOCKED(object);
5193 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
5194 ("pmap_object_init_pt: non-device object"));
5198 * Clear the wired attribute from the mappings for the specified range of
5199 * addresses in the given pmap. Every valid mapping within that range
5200 * must have the wired attribute set. In contrast, invalid mappings
5201 * cannot have the wired attribute set, so they are ignored.
5203 * The wired attribute of the page table entry is not a hardware feature,
5204 * so there is no need to invalidate any TLB entries.
5207 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5209 vm_offset_t va_next;
5210 pd_entry_t *l0, *l1, *l2;
5214 for (; sva < eva; sva = va_next) {
5215 l0 = pmap_l0(pmap, sva);
5216 if (pmap_load(l0) == 0) {
5217 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
5223 l1 = pmap_l0_to_l1(l0, sva);
5224 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
5227 if (pmap_load(l1) == 0)
5230 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
5231 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
5232 KASSERT(va_next <= eva,
5233 ("partial update of non-transparent 1G page "
5234 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
5235 pmap_load(l1), sva, eva, va_next));
5236 MPASS(pmap != kernel_pmap);
5237 MPASS((pmap_load(l1) & (ATTR_SW_MANAGED |
5238 ATTR_SW_WIRED)) == ATTR_SW_WIRED);
5239 pmap_clear_bits(l1, ATTR_SW_WIRED);
5240 pmap->pm_stats.wired_count -= L1_SIZE / PAGE_SIZE;
5244 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
5248 l2 = pmap_l1_to_l2(l1, sva);
5249 if (pmap_load(l2) == 0)
5252 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
5253 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
5254 panic("pmap_unwire: l2 %#jx is missing "
5255 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
5258 * Are we unwiring the entire large page? If not,
5259 * demote the mapping and fall through.
5261 if (sva + L2_SIZE == va_next && eva >= va_next) {
5262 pmap_clear_bits(l2, ATTR_SW_WIRED);
5263 pmap->pm_stats.wired_count -= L2_SIZE /
5266 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
5267 panic("pmap_unwire: demotion failed");
5269 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
5270 ("pmap_unwire: Invalid l2 entry after demotion"));
5274 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
5276 if (pmap_load(l3) == 0)
5278 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
5279 panic("pmap_unwire: l3 %#jx is missing "
5280 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
5283 * ATTR_SW_WIRED must be cleared atomically. Although
5284 * the pmap lock synchronizes access to ATTR_SW_WIRED,
5285 * the System MMU may write to the entry concurrently.
5287 pmap_clear_bits(l3, ATTR_SW_WIRED);
5288 pmap->pm_stats.wired_count--;
5295 * Copy the range specified by src_addr/len
5296 * from the source map to the range dst_addr/len
5297 * in the destination map.
5299 * This routine is only advisory and need not do anything.
5301 * Because the executable mappings created by this routine are copied,
5302 * it should not have to flush the instruction cache.
5305 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
5306 vm_offset_t src_addr)
5308 struct rwlock *lock;
5309 pd_entry_t *l0, *l1, *l2, srcptepaddr;
5310 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
5311 vm_offset_t addr, end_addr, va_next;
5312 vm_page_t dst_m, dstmpte, srcmpte;
5314 PMAP_ASSERT_STAGE1(dst_pmap);
5315 PMAP_ASSERT_STAGE1(src_pmap);
5317 if (dst_addr != src_addr)
5319 end_addr = src_addr + len;
5321 if (dst_pmap < src_pmap) {
5322 PMAP_LOCK(dst_pmap);
5323 PMAP_LOCK(src_pmap);
5325 PMAP_LOCK(src_pmap);
5326 PMAP_LOCK(dst_pmap);
5328 for (addr = src_addr; addr < end_addr; addr = va_next) {
5329 l0 = pmap_l0(src_pmap, addr);
5330 if (pmap_load(l0) == 0) {
5331 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
5337 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
5340 l1 = pmap_l0_to_l1(l0, addr);
5341 if (pmap_load(l1) == 0)
5343 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
5344 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
5345 KASSERT(va_next <= end_addr,
5346 ("partial update of non-transparent 1G page "
5347 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx",
5348 pmap_load(l1), addr, end_addr, va_next));
5349 srcptepaddr = pmap_load(l1);
5350 l1 = pmap_l1(dst_pmap, addr);
5352 if (_pmap_alloc_l3(dst_pmap,
5353 pmap_l0_pindex(addr), NULL) == NULL)
5355 l1 = pmap_l1(dst_pmap, addr);
5357 l0 = pmap_l0(dst_pmap, addr);
5358 dst_m = PHYS_TO_VM_PAGE(
5359 PTE_TO_PHYS(pmap_load(l0)));
5362 KASSERT(pmap_load(l1) == 0,
5363 ("1G mapping present in dst pmap "
5364 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx",
5365 pmap_load(l1), addr, end_addr, va_next));
5366 pmap_store(l1, srcptepaddr & ~ATTR_SW_WIRED);
5367 pmap_resident_count_inc(dst_pmap, L1_SIZE / PAGE_SIZE);
5371 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
5374 l2 = pmap_l1_to_l2(l1, addr);
5375 srcptepaddr = pmap_load(l2);
5376 if (srcptepaddr == 0)
5378 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
5380 * We can only virtual copy whole superpages.
5382 if ((addr & L2_OFFSET) != 0 ||
5383 addr + L2_SIZE > end_addr)
5385 l2 = pmap_alloc_l2(dst_pmap, addr, &dst_m, NULL);
5388 if (pmap_load(l2) == 0 &&
5389 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
5390 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
5391 PMAP_ENTER_NORECLAIM, &lock))) {
5393 * We leave the dirty bit unchanged because
5394 * managed read/write superpage mappings are
5395 * required to be dirty. However, managed
5396 * superpage mappings are not required to
5397 * have their accessed bit set, so we clear
5398 * it because we don't know if this mapping
5401 srcptepaddr &= ~ATTR_SW_WIRED;
5402 if ((srcptepaddr & ATTR_SW_MANAGED) != 0)
5403 srcptepaddr &= ~ATTR_AF;
5404 pmap_store(l2, srcptepaddr);
5405 pmap_resident_count_inc(dst_pmap, L2_SIZE /
5407 atomic_add_long(&pmap_l2_mappings, 1);
5409 pmap_abort_ptp(dst_pmap, addr, dst_m);
5412 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
5413 ("pmap_copy: invalid L2 entry"));
5414 srcmpte = PHYS_TO_VM_PAGE(PTE_TO_PHYS(srcptepaddr));
5415 KASSERT(srcmpte->ref_count > 0,
5416 ("pmap_copy: source page table page is unused"));
5417 if (va_next > end_addr)
5419 src_pte = (pt_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(srcptepaddr));
5420 src_pte = &src_pte[pmap_l3_index(addr)];
5422 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
5423 ptetemp = pmap_load(src_pte);
5426 * We only virtual copy managed pages.
5428 if ((ptetemp & ATTR_SW_MANAGED) == 0)
5431 if (dstmpte != NULL) {
5432 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
5433 ("dstmpte pindex/addr mismatch"));
5434 dstmpte->ref_count++;
5435 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
5438 dst_pte = (pt_entry_t *)
5439 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
5440 dst_pte = &dst_pte[pmap_l3_index(addr)];
5441 if (pmap_load(dst_pte) == 0 &&
5442 pmap_try_insert_pv_entry(dst_pmap, addr,
5443 PHYS_TO_VM_PAGE(PTE_TO_PHYS(ptetemp)), &lock)) {
5445 * Clear the wired, modified, and accessed
5446 * (referenced) bits during the copy.
5448 mask = ATTR_AF | ATTR_SW_WIRED;
5450 if ((ptetemp & ATTR_SW_DBM) != 0)
5451 nbits |= ATTR_S1_AP_RW_BIT;
5452 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
5453 pmap_resident_count_inc(dst_pmap, 1);
5455 pmap_abort_ptp(dst_pmap, addr, dstmpte);
5458 /* Have we copied all of the valid mappings? */
5459 if (dstmpte->ref_count >= srcmpte->ref_count)
5465 * XXX This barrier may not be needed because the destination pmap is
5472 PMAP_UNLOCK(src_pmap);
5473 PMAP_UNLOCK(dst_pmap);
5477 * pmap_zero_page zeros the specified hardware page by mapping
5478 * the page into KVM and using bzero to clear its contents.
5481 pmap_zero_page(vm_page_t m)
5483 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5485 pagezero((void *)va);
5489 * pmap_zero_page_area zeros the specified hardware page by mapping
5490 * the page into KVM and using bzero to clear its contents.
5492 * off and size may not cover an area beyond a single hardware page.
5495 pmap_zero_page_area(vm_page_t m, int off, int size)
5497 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5499 if (off == 0 && size == PAGE_SIZE)
5500 pagezero((void *)va);
5502 bzero((char *)va + off, size);
5506 * pmap_copy_page copies the specified (machine independent)
5507 * page by mapping the page into virtual memory and using
5508 * bcopy to copy the page, one machine dependent page at a
5512 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
5514 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
5515 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
5517 pagecopy((void *)src, (void *)dst);
5520 int unmapped_buf_allowed = 1;
5523 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5524 vm_offset_t b_offset, int xfersize)
5528 vm_paddr_t p_a, p_b;
5529 vm_offset_t a_pg_offset, b_pg_offset;
5532 while (xfersize > 0) {
5533 a_pg_offset = a_offset & PAGE_MASK;
5534 m_a = ma[a_offset >> PAGE_SHIFT];
5535 p_a = m_a->phys_addr;
5536 b_pg_offset = b_offset & PAGE_MASK;
5537 m_b = mb[b_offset >> PAGE_SHIFT];
5538 p_b = m_b->phys_addr;
5539 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5540 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5541 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
5542 panic("!DMAP a %lx", p_a);
5544 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
5546 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
5547 panic("!DMAP b %lx", p_b);
5549 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
5551 bcopy(a_cp, b_cp, cnt);
5559 pmap_quick_enter_page(vm_page_t m)
5562 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
5566 pmap_quick_remove_page(vm_offset_t addr)
5571 * Returns true if the pmap's pv is one of the first
5572 * 16 pvs linked to from this page. This count may
5573 * be changed upwards or downwards in the future; it
5574 * is only necessary that true be returned for a small
5575 * subset of pmaps for proper page aging.
5578 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5580 struct md_page *pvh;
5581 struct rwlock *lock;
5586 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5587 ("pmap_page_exists_quick: page %p is not managed", m));
5589 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5591 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5592 if (PV_PMAP(pv) == pmap) {
5600 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5601 pvh = page_to_pvh(m);
5602 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5603 if (PV_PMAP(pv) == pmap) {
5617 * pmap_page_wired_mappings:
5619 * Return the number of managed mappings to the given physical page
5623 pmap_page_wired_mappings(vm_page_t m)
5625 struct rwlock *lock;
5626 struct md_page *pvh;
5630 int count, md_gen, pvh_gen;
5632 if ((m->oflags & VPO_UNMANAGED) != 0)
5634 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5638 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5640 if (!PMAP_TRYLOCK(pmap)) {
5641 md_gen = m->md.pv_gen;
5645 if (md_gen != m->md.pv_gen) {
5650 pte = pmap_pte_exists(pmap, pv->pv_va, 3, __func__);
5651 if ((pmap_load(pte) & ATTR_SW_WIRED) != 0)
5655 if ((m->flags & PG_FICTITIOUS) == 0) {
5656 pvh = page_to_pvh(m);
5657 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5659 if (!PMAP_TRYLOCK(pmap)) {
5660 md_gen = m->md.pv_gen;
5661 pvh_gen = pvh->pv_gen;
5665 if (md_gen != m->md.pv_gen ||
5666 pvh_gen != pvh->pv_gen) {
5671 pte = pmap_pte_exists(pmap, pv->pv_va, 2, __func__);
5672 if ((pmap_load(pte) & ATTR_SW_WIRED) != 0)
5682 * Returns true if the given page is mapped individually or as part of
5683 * a 2mpage. Otherwise, returns false.
5686 pmap_page_is_mapped(vm_page_t m)
5688 struct rwlock *lock;
5691 if ((m->oflags & VPO_UNMANAGED) != 0)
5693 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5695 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5696 ((m->flags & PG_FICTITIOUS) == 0 &&
5697 !TAILQ_EMPTY(&page_to_pvh(m)->pv_list));
5703 * Destroy all managed, non-wired mappings in the given user-space
5704 * pmap. This pmap cannot be active on any processor besides the
5707 * This function cannot be applied to the kernel pmap. Moreover, it
5708 * is not intended for general use. It is only to be used during
5709 * process termination. Consequently, it can be implemented in ways
5710 * that make it faster than pmap_remove(). First, it can more quickly
5711 * destroy mappings by iterating over the pmap's collection of PV
5712 * entries, rather than searching the page table. Second, it doesn't
5713 * have to test and clear the page table entries atomically, because
5714 * no processor is currently accessing the user address space. In
5715 * particular, a page table entry's dirty bit won't change state once
5716 * this function starts.
5719 pmap_remove_pages(pmap_t pmap)
5722 pt_entry_t *pte, tpte;
5723 struct spglist free;
5724 struct pv_chunklist free_chunks[PMAP_MEMDOM];
5725 vm_page_t m, ml3, mt;
5727 struct md_page *pvh;
5728 struct pv_chunk *pc, *npc;
5729 struct rwlock *lock;
5731 uint64_t inuse, bitmask;
5732 int allfree, field, i, idx, lvl;
5738 for (i = 0; i < PMAP_MEMDOM; i++)
5739 TAILQ_INIT(&free_chunks[i]);
5742 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5745 for (field = 0; field < _NPCM; field++) {
5746 inuse = ~pc->pc_map[field] & pc_freemask[field];
5747 while (inuse != 0) {
5748 bit = ffsl(inuse) - 1;
5749 bitmask = 1UL << bit;
5750 idx = field * 64 + bit;
5751 pv = &pc->pc_pventry[idx];
5754 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5755 KASSERT(pde != NULL,
5756 ("Attempting to remove an unmapped page"));
5760 pte = pmap_l1_to_l2(pde, pv->pv_va);
5761 tpte = pmap_load(pte);
5762 KASSERT((tpte & ATTR_DESCR_MASK) ==
5764 ("Attempting to remove an invalid "
5765 "block: %lx", tpte));
5768 pte = pmap_l2_to_l3(pde, pv->pv_va);
5769 tpte = pmap_load(pte);
5770 KASSERT((tpte & ATTR_DESCR_MASK) ==
5772 ("Attempting to remove an invalid "
5773 "page: %lx", tpte));
5777 "Invalid page directory level: %d",
5782 * We cannot remove wired pages from a process' mapping at this time
5784 if (tpte & ATTR_SW_WIRED) {
5790 pc->pc_map[field] |= bitmask;
5793 * Because this pmap is not active on other
5794 * processors, the dirty bit cannot have
5795 * changed state since we last loaded pte.
5799 pa = PTE_TO_PHYS(tpte);
5801 m = PHYS_TO_VM_PAGE(pa);
5802 KASSERT(m->phys_addr == pa,
5803 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
5804 m, (uintmax_t)m->phys_addr,
5807 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
5808 m < &vm_page_array[vm_page_array_size],
5809 ("pmap_remove_pages: bad pte %#jx",
5813 * Update the vm_page_t clean/reference bits.
5815 if (pmap_pte_dirty(pmap, tpte)) {
5818 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
5827 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
5831 pmap_resident_count_dec(pmap,
5832 L2_SIZE / PAGE_SIZE);
5833 pvh = page_to_pvh(m);
5834 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
5836 if (TAILQ_EMPTY(&pvh->pv_list)) {
5837 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
5838 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
5839 TAILQ_EMPTY(&mt->md.pv_list))
5840 vm_page_aflag_clear(mt, PGA_WRITEABLE);
5842 ml3 = pmap_remove_pt_page(pmap,
5845 KASSERT(vm_page_any_valid(ml3),
5846 ("pmap_remove_pages: l3 page not promoted"));
5847 pmap_resident_count_dec(pmap,1);
5848 KASSERT(ml3->ref_count == NL3PG,
5849 ("pmap_remove_pages: l3 page ref count error"));
5851 pmap_add_delayed_free_list(ml3,
5856 pmap_resident_count_dec(pmap, 1);
5857 TAILQ_REMOVE(&m->md.pv_list, pv,
5860 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
5861 TAILQ_EMPTY(&m->md.pv_list) &&
5862 (m->flags & PG_FICTITIOUS) == 0) {
5863 pvh = page_to_pvh(m);
5864 if (TAILQ_EMPTY(&pvh->pv_list))
5865 vm_page_aflag_clear(m,
5870 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
5875 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
5876 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
5877 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
5879 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5880 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc,
5886 pmap_invalidate_all(pmap);
5887 free_pv_chunk_batch(free_chunks);
5889 vm_page_free_pages_toq(&free, true);
5893 * This is used to check if a page has been accessed or modified.
5896 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
5898 struct rwlock *lock;
5900 struct md_page *pvh;
5901 pt_entry_t *pte, mask, value;
5903 int md_gen, pvh_gen;
5907 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5910 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5912 PMAP_ASSERT_STAGE1(pmap);
5913 if (!PMAP_TRYLOCK(pmap)) {
5914 md_gen = m->md.pv_gen;
5918 if (md_gen != m->md.pv_gen) {
5923 pte = pmap_pte_exists(pmap, pv->pv_va, 3, __func__);
5927 mask |= ATTR_S1_AP_RW_BIT;
5928 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
5931 mask |= ATTR_AF | ATTR_DESCR_MASK;
5932 value |= ATTR_AF | L3_PAGE;
5934 rv = (pmap_load(pte) & mask) == value;
5939 if ((m->flags & PG_FICTITIOUS) == 0) {
5940 pvh = page_to_pvh(m);
5941 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5943 PMAP_ASSERT_STAGE1(pmap);
5944 if (!PMAP_TRYLOCK(pmap)) {
5945 md_gen = m->md.pv_gen;
5946 pvh_gen = pvh->pv_gen;
5950 if (md_gen != m->md.pv_gen ||
5951 pvh_gen != pvh->pv_gen) {
5956 pte = pmap_pte_exists(pmap, pv->pv_va, 2, __func__);
5960 mask |= ATTR_S1_AP_RW_BIT;
5961 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
5964 mask |= ATTR_AF | ATTR_DESCR_MASK;
5965 value |= ATTR_AF | L2_BLOCK;
5967 rv = (pmap_load(pte) & mask) == value;
5981 * Return whether or not the specified physical page was modified
5982 * in any physical maps.
5985 pmap_is_modified(vm_page_t m)
5988 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5989 ("pmap_is_modified: page %p is not managed", m));
5992 * If the page is not busied then this check is racy.
5994 if (!pmap_page_is_write_mapped(m))
5996 return (pmap_page_test_mappings(m, FALSE, TRUE));
6000 * pmap_is_prefaultable:
6002 * Return whether or not the specified virtual address is eligible
6006 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
6014 * Return TRUE if and only if the L3 entry for the specified virtual
6015 * address is allocated but invalid.
6019 pde = pmap_pde(pmap, addr, &lvl);
6020 if (pde != NULL && lvl == 2) {
6021 pte = pmap_l2_to_l3(pde, addr);
6022 rv = pmap_load(pte) == 0;
6029 * pmap_is_referenced:
6031 * Return whether or not the specified physical page was referenced
6032 * in any physical maps.
6035 pmap_is_referenced(vm_page_t m)
6038 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6039 ("pmap_is_referenced: page %p is not managed", m));
6040 return (pmap_page_test_mappings(m, TRUE, FALSE));
6044 * Clear the write and modified bits in each of the given page's mappings.
6047 pmap_remove_write(vm_page_t m)
6049 struct md_page *pvh;
6051 struct rwlock *lock;
6052 pv_entry_t next_pv, pv;
6053 pt_entry_t oldpte, *pte, set, clear, mask, val;
6055 int md_gen, pvh_gen;
6057 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6058 ("pmap_remove_write: page %p is not managed", m));
6059 vm_page_assert_busied(m);
6061 if (!pmap_page_is_write_mapped(m))
6063 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6064 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
6067 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6069 PMAP_ASSERT_STAGE1(pmap);
6070 if (!PMAP_TRYLOCK(pmap)) {
6071 pvh_gen = pvh->pv_gen;
6075 if (pvh_gen != pvh->pv_gen) {
6081 pte = pmap_pte_exists(pmap, va, 2, __func__);
6082 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
6083 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
6084 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6085 ("inconsistent pv lock %p %p for page %p",
6086 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6089 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6091 if (!PMAP_TRYLOCK(pmap)) {
6092 pvh_gen = pvh->pv_gen;
6093 md_gen = m->md.pv_gen;
6097 if (pvh_gen != pvh->pv_gen ||
6098 md_gen != m->md.pv_gen) {
6103 pte = pmap_pte_exists(pmap, pv->pv_va, 3, __func__);
6104 oldpte = pmap_load(pte);
6105 if ((oldpte & ATTR_SW_DBM) != 0) {
6106 if (pmap->pm_stage == PM_STAGE1) {
6107 set = ATTR_S1_AP_RW_BIT;
6109 mask = ATTR_S1_AP_RW_BIT;
6110 val = ATTR_S1_AP(ATTR_S1_AP_RW);
6113 clear = ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
6114 mask = ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
6115 val = ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
6117 clear |= ATTR_SW_DBM;
6118 while (!atomic_fcmpset_64(pte, &oldpte,
6119 (oldpte | set) & ~clear))
6122 if ((oldpte & mask) == val)
6124 pmap_invalidate_page(pmap, pv->pv_va, true);
6129 vm_page_aflag_clear(m, PGA_WRITEABLE);
6133 * pmap_ts_referenced:
6135 * Return a count of reference bits for a page, clearing those bits.
6136 * It is not necessary for every reference bit to be cleared, but it
6137 * is necessary that 0 only be returned when there are truly no
6138 * reference bits set.
6140 * As an optimization, update the page's dirty field if a modified bit is
6141 * found while counting reference bits. This opportunistic update can be
6142 * performed at low cost and can eliminate the need for some future calls
6143 * to pmap_is_modified(). However, since this function stops after
6144 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
6145 * dirty pages. Those dirty pages will only be detected by a future call
6146 * to pmap_is_modified().
6149 pmap_ts_referenced(vm_page_t m)
6151 struct md_page *pvh;
6154 struct rwlock *lock;
6155 pt_entry_t *pte, tpte;
6158 int cleared, md_gen, not_cleared, pvh_gen;
6159 struct spglist free;
6161 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6162 ("pmap_ts_referenced: page %p is not managed", m));
6165 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
6166 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6170 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
6171 goto small_mappings;
6177 if (!PMAP_TRYLOCK(pmap)) {
6178 pvh_gen = pvh->pv_gen;
6182 if (pvh_gen != pvh->pv_gen) {
6188 pte = pmap_pte_exists(pmap, va, 2, __func__);
6189 tpte = pmap_load(pte);
6190 if (pmap_pte_dirty(pmap, tpte)) {
6192 * Although "tpte" is mapping a 2MB page, because
6193 * this function is called at a 4KB page granularity,
6194 * we only update the 4KB page under test.
6198 if ((tpte & ATTR_AF) != 0) {
6199 pa = VM_PAGE_TO_PHYS(m);
6202 * Since this reference bit is shared by 512 4KB pages,
6203 * it should not be cleared every time it is tested.
6204 * Apply a simple "hash" function on the physical page
6205 * number, the virtual superpage number, and the pmap
6206 * address to select one 4KB page out of the 512 on
6207 * which testing the reference bit will result in
6208 * clearing that reference bit. This function is
6209 * designed to avoid the selection of the same 4KB page
6210 * for every 2MB page mapping.
6212 * On demotion, a mapping that hasn't been referenced
6213 * is simply destroyed. To avoid the possibility of a
6214 * subsequent page fault on a demoted wired mapping,
6215 * always leave its reference bit set. Moreover,
6216 * since the superpage is wired, the current state of
6217 * its reference bit won't affect page replacement.
6219 if ((((pa >> PAGE_SHIFT) ^ (va >> L2_SHIFT) ^
6220 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
6221 (tpte & ATTR_SW_WIRED) == 0) {
6222 pmap_clear_bits(pte, ATTR_AF);
6223 pmap_invalidate_page(pmap, va, true);
6229 /* Rotate the PV list if it has more than one entry. */
6230 if (TAILQ_NEXT(pv, pv_next) != NULL) {
6231 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6232 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
6235 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
6237 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
6239 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
6246 if (!PMAP_TRYLOCK(pmap)) {
6247 pvh_gen = pvh->pv_gen;
6248 md_gen = m->md.pv_gen;
6252 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6257 pte = pmap_pte_exists(pmap, pv->pv_va, 3, __func__);
6258 tpte = pmap_load(pte);
6259 if (pmap_pte_dirty(pmap, tpte))
6261 if ((tpte & ATTR_AF) != 0) {
6262 if ((tpte & ATTR_SW_WIRED) == 0) {
6263 pmap_clear_bits(pte, ATTR_AF);
6264 pmap_invalidate_page(pmap, pv->pv_va, true);
6270 /* Rotate the PV list if it has more than one entry. */
6271 if (TAILQ_NEXT(pv, pv_next) != NULL) {
6272 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6273 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6276 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
6277 not_cleared < PMAP_TS_REFERENCED_MAX);
6280 vm_page_free_pages_toq(&free, true);
6281 return (cleared + not_cleared);
6285 * Apply the given advice to the specified range of addresses within the
6286 * given pmap. Depending on the advice, clear the referenced and/or
6287 * modified flags in each mapping and set the mapped page's dirty field.
6290 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
6292 struct rwlock *lock;
6293 vm_offset_t va, va_next;
6295 pd_entry_t *l0, *l1, *l2, oldl2;
6296 pt_entry_t *l3, oldl3;
6298 PMAP_ASSERT_STAGE1(pmap);
6300 if (advice != MADV_DONTNEED && advice != MADV_FREE)
6304 for (; sva < eva; sva = va_next) {
6305 l0 = pmap_l0(pmap, sva);
6306 if (pmap_load(l0) == 0) {
6307 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
6313 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
6316 l1 = pmap_l0_to_l1(l0, sva);
6317 if (pmap_load(l1) == 0)
6319 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
6320 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
6324 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
6327 l2 = pmap_l1_to_l2(l1, sva);
6328 oldl2 = pmap_load(l2);
6331 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
6332 if ((oldl2 & ATTR_SW_MANAGED) == 0)
6335 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
6340 * The 2MB page mapping was destroyed.
6346 * Unless the page mappings are wired, remove the
6347 * mapping to a single page so that a subsequent
6348 * access may repromote. Choosing the last page
6349 * within the address range [sva, min(va_next, eva))
6350 * generally results in more repromotions. Since the
6351 * underlying page table page is fully populated, this
6352 * removal never frees a page table page.
6354 if ((oldl2 & ATTR_SW_WIRED) == 0) {
6360 ("pmap_advise: no address gap"));
6361 l3 = pmap_l2_to_l3(l2, va);
6362 KASSERT(pmap_load(l3) != 0,
6363 ("pmap_advise: invalid PTE"));
6364 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
6370 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
6371 ("pmap_advise: invalid L2 entry after demotion"));
6375 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
6377 oldl3 = pmap_load(l3);
6378 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
6379 (ATTR_SW_MANAGED | L3_PAGE))
6381 else if (pmap_pte_dirty(pmap, oldl3)) {
6382 if (advice == MADV_DONTNEED) {
6384 * Future calls to pmap_is_modified()
6385 * can be avoided by making the page
6388 m = PHYS_TO_VM_PAGE(PTE_TO_PHYS(oldl3));
6391 while (!atomic_fcmpset_long(l3, &oldl3,
6392 (oldl3 & ~ATTR_AF) |
6393 ATTR_S1_AP(ATTR_S1_AP_RO)))
6395 } else if ((oldl3 & ATTR_AF) != 0)
6396 pmap_clear_bits(l3, ATTR_AF);
6403 if (va != va_next) {
6404 pmap_s1_invalidate_range(pmap, va, sva, true);
6409 pmap_s1_invalidate_range(pmap, va, sva, true);
6415 * Clear the modify bits on the specified physical page.
6418 pmap_clear_modify(vm_page_t m)
6420 struct md_page *pvh;
6421 struct rwlock *lock;
6423 pv_entry_t next_pv, pv;
6424 pd_entry_t *l2, oldl2;
6425 pt_entry_t *l3, oldl3;
6427 int md_gen, pvh_gen;
6429 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6430 ("pmap_clear_modify: page %p is not managed", m));
6431 vm_page_assert_busied(m);
6433 if (!pmap_page_is_write_mapped(m))
6435 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
6436 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6439 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6441 PMAP_ASSERT_STAGE1(pmap);
6442 if (!PMAP_TRYLOCK(pmap)) {
6443 pvh_gen = pvh->pv_gen;
6447 if (pvh_gen != pvh->pv_gen) {
6453 l2 = pmap_l2(pmap, va);
6454 oldl2 = pmap_load(l2);
6455 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */
6456 if ((oldl2 & ATTR_SW_DBM) != 0 &&
6457 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
6458 (oldl2 & ATTR_SW_WIRED) == 0) {
6460 * Write protect the mapping to a single page so that
6461 * a subsequent write access may repromote.
6463 va += VM_PAGE_TO_PHYS(m) - PTE_TO_PHYS(oldl2);
6464 l3 = pmap_l2_to_l3(l2, va);
6465 oldl3 = pmap_load(l3);
6466 while (!atomic_fcmpset_long(l3, &oldl3,
6467 (oldl3 & ~ATTR_SW_DBM) | ATTR_S1_AP(ATTR_S1_AP_RO)))
6470 pmap_s1_invalidate_page(pmap, va, true);
6474 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6476 PMAP_ASSERT_STAGE1(pmap);
6477 if (!PMAP_TRYLOCK(pmap)) {
6478 md_gen = m->md.pv_gen;
6479 pvh_gen = pvh->pv_gen;
6483 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6488 l2 = pmap_l2(pmap, pv->pv_va);
6489 l3 = pmap_l2_to_l3(l2, pv->pv_va);
6490 oldl3 = pmap_load(l3);
6491 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM){
6492 pmap_set_bits(l3, ATTR_S1_AP(ATTR_S1_AP_RO));
6493 pmap_s1_invalidate_page(pmap, pv->pv_va, true);
6501 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6503 struct pmap_preinit_mapping *ppim;
6504 vm_offset_t va, offset;
6505 pd_entry_t old_l2e, *pde;
6507 int i, lvl, l2_blocks, free_l2_count, start_idx;
6509 if (!vm_initialized) {
6511 * No L3 ptables so map entire L2 blocks where start VA is:
6512 * preinit_map_va + start_idx * L2_SIZE
6513 * There may be duplicate mappings (multiple VA -> same PA) but
6514 * ARM64 dcache is always PIPT so that's acceptable.
6519 /* Calculate how many L2 blocks are needed for the mapping */
6520 l2_blocks = (roundup2(pa + size, L2_SIZE) -
6521 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
6523 offset = pa & L2_OFFSET;
6525 if (preinit_map_va == 0)
6528 /* Map 2MiB L2 blocks from reserved VA space */
6532 /* Find enough free contiguous VA space */
6533 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6534 ppim = pmap_preinit_mapping + i;
6535 if (free_l2_count > 0 && ppim->pa != 0) {
6536 /* Not enough space here */
6542 if (ppim->pa == 0) {
6544 if (start_idx == -1)
6547 if (free_l2_count == l2_blocks)
6551 if (free_l2_count != l2_blocks)
6552 panic("%s: too many preinit mappings", __func__);
6554 va = preinit_map_va + (start_idx * L2_SIZE);
6555 for (i = start_idx; i < start_idx + l2_blocks; i++) {
6556 /* Mark entries as allocated */
6557 ppim = pmap_preinit_mapping + i;
6559 ppim->va = va + offset;
6564 pa = rounddown2(pa, L2_SIZE);
6566 for (i = 0; i < l2_blocks; i++) {
6567 pde = pmap_pde(kernel_pmap, va, &lvl);
6568 KASSERT(pde != NULL,
6569 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
6572 ("pmap_mapbios: Invalid level %d", lvl));
6574 /* Insert L2_BLOCK */
6575 l2 = pmap_l1_to_l2(pde, va);
6576 old_l2e |= pmap_load_store(l2,
6577 PHYS_TO_PTE(pa) | ATTR_DEFAULT | ATTR_S1_XN |
6578 ATTR_KERN_GP | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
6584 if ((old_l2e & ATTR_DESCR_VALID) != 0)
6585 pmap_s1_invalidate_all(kernel_pmap);
6588 * Because the old entries were invalid and the new
6589 * mappings are not executable, an isb is not required.
6594 va = preinit_map_va + (start_idx * L2_SIZE);
6597 /* kva_alloc may be used to map the pages */
6598 offset = pa & PAGE_MASK;
6599 size = round_page(offset + size);
6601 va = kva_alloc(size);
6603 panic("%s: Couldn't allocate KVA", __func__);
6605 pde = pmap_pde(kernel_pmap, va, &lvl);
6606 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
6608 /* L3 table is linked */
6609 va = trunc_page(va);
6610 pa = trunc_page(pa);
6611 pmap_kenter(va, size, pa, memory_mapping_mode(pa));
6614 return ((void *)(va + offset));
6618 pmap_unmapbios(void *p, vm_size_t size)
6620 struct pmap_preinit_mapping *ppim;
6621 vm_offset_t offset, va, va_trunc;
6624 int i, lvl, l2_blocks, block;
6627 va = (vm_offset_t)p;
6629 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
6630 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
6632 /* Remove preinit mapping */
6633 preinit_map = false;
6635 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6636 ppim = pmap_preinit_mapping + i;
6637 if (ppim->va == va) {
6638 KASSERT(ppim->size == size,
6639 ("pmap_unmapbios: size mismatch"));
6644 offset = block * L2_SIZE;
6645 va_trunc = rounddown2(va, L2_SIZE) + offset;
6647 /* Remove L2_BLOCK */
6648 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
6649 KASSERT(pde != NULL,
6650 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
6652 l2 = pmap_l1_to_l2(pde, va_trunc);
6655 if (block == (l2_blocks - 1))
6661 pmap_s1_invalidate_all(kernel_pmap);
6665 /* Unmap the pages reserved with kva_alloc. */
6666 if (vm_initialized) {
6667 offset = va & PAGE_MASK;
6668 size = round_page(offset + size);
6669 va = trunc_page(va);
6671 /* Unmap and invalidate the pages */
6672 pmap_kremove_device(va, size);
6679 * Sets the memory attribute for the specified page.
6682 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
6685 m->md.pv_memattr = ma;
6688 * If "m" is a normal page, update its direct mapping. This update
6689 * can be relied upon to perform any cache operations that are
6690 * required for data coherence.
6692 if ((m->flags & PG_FICTITIOUS) == 0 &&
6693 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
6694 m->md.pv_memattr) != 0)
6695 panic("memory attribute change on the direct map failed");
6699 * Changes the specified virtual address range's memory type to that given by
6700 * the parameter "mode". The specified virtual address range must be
6701 * completely contained within either the direct map or the kernel map. If
6702 * the virtual address range is contained within the kernel map, then the
6703 * memory type for each of the corresponding ranges of the direct map is also
6704 * changed. (The corresponding ranges of the direct map are those ranges that
6705 * map the same physical pages as the specified virtual address range.) These
6706 * changes to the direct map are necessary because Intel describes the
6707 * behavior of their processors as "undefined" if two or more mappings to the
6708 * same physical page have different memory types.
6710 * Returns zero if the change completed successfully, and either EINVAL or
6711 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
6712 * of the virtual address range was not mapped, and ENOMEM is returned if
6713 * there was insufficient memory available to complete the change. In the
6714 * latter case, the memory type may have been changed on some part of the
6715 * virtual address range or the direct map.
6718 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
6722 PMAP_LOCK(kernel_pmap);
6723 error = pmap_change_props_locked(va, size, PROT_NONE, mode, false);
6724 PMAP_UNLOCK(kernel_pmap);
6729 * Changes the specified virtual address range's protections to those
6730 * specified by "prot". Like pmap_change_attr(), protections for aliases
6731 * in the direct map are updated as well. Protections on aliasing mappings may
6732 * be a subset of the requested protections; for example, mappings in the direct
6733 * map are never executable.
6736 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
6740 /* Only supported within the kernel map. */
6741 if (va < VM_MIN_KERNEL_ADDRESS)
6744 PMAP_LOCK(kernel_pmap);
6745 error = pmap_change_props_locked(va, size, prot, -1, false);
6746 PMAP_UNLOCK(kernel_pmap);
6751 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
6752 int mode, bool skip_unmapped)
6754 vm_offset_t base, offset, tmpva;
6757 pt_entry_t pte, *ptep, *newpte;
6758 pt_entry_t bits, mask;
6761 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
6762 base = trunc_page(va);
6763 offset = va & PAGE_MASK;
6764 size = round_page(offset + size);
6766 if (!VIRT_IN_DMAP(base) &&
6767 !(base >= VM_MIN_KERNEL_ADDRESS && base < VM_MAX_KERNEL_ADDRESS))
6773 bits = ATTR_S1_IDX(mode);
6774 mask = ATTR_S1_IDX_MASK;
6775 if (mode == VM_MEMATTR_DEVICE) {
6780 if (prot != VM_PROT_NONE) {
6781 /* Don't mark the DMAP as executable. It never is on arm64. */
6782 if (VIRT_IN_DMAP(base)) {
6783 prot &= ~VM_PROT_EXECUTE;
6785 * XXX Mark the DMAP as writable for now. We rely
6786 * on this in ddb & dtrace to insert breakpoint
6789 prot |= VM_PROT_WRITE;
6792 if ((prot & VM_PROT_WRITE) == 0) {
6793 bits |= ATTR_S1_AP(ATTR_S1_AP_RO);
6795 if ((prot & VM_PROT_EXECUTE) == 0) {
6796 bits |= ATTR_S1_PXN;
6798 bits |= ATTR_S1_UXN;
6799 mask |= ATTR_S1_AP_MASK | ATTR_S1_XN;
6802 for (tmpva = base; tmpva < base + size; ) {
6803 ptep = pmap_pte(kernel_pmap, tmpva, &lvl);
6804 if (ptep == NULL && !skip_unmapped) {
6806 } else if ((ptep == NULL && skip_unmapped) ||
6807 (pmap_load(ptep) & mask) == bits) {
6809 * We already have the correct attribute or there
6810 * is no memory mapped at this address and we are
6811 * skipping unmapped memory.
6815 panic("Invalid DMAP table level: %d\n", lvl);
6817 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
6820 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
6827 /* We can't demote/promote this entry */
6828 MPASS((pmap_load(ptep) & ATTR_SW_NO_PROMOTE) == 0);
6831 * Split the entry to an level 3 table, then
6832 * set the new attribute.
6836 panic("Invalid DMAP table level: %d\n", lvl);
6838 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
6839 if ((tmpva & L1_OFFSET) == 0 &&
6840 (base + size - tmpva) >= L1_SIZE) {
6844 newpte = pmap_demote_l1(kernel_pmap, ptep,
6845 tmpva & ~L1_OFFSET);
6848 ptep = pmap_l1_to_l2(ptep, tmpva);
6851 if ((tmpva & L2_OFFSET) == 0 &&
6852 (base + size - tmpva) >= L2_SIZE) {
6856 newpte = pmap_demote_l2(kernel_pmap, ptep,
6860 ptep = pmap_l2_to_l3(ptep, tmpva);
6863 pte_size = PAGE_SIZE;
6867 /* Update the entry */
6868 pte = pmap_load(ptep);
6872 pmap_update_entry(kernel_pmap, ptep, pte, tmpva,
6875 pa = PTE_TO_PHYS(pte);
6876 if (!VIRT_IN_DMAP(tmpva) && PHYS_IN_DMAP(pa)) {
6878 * Keep the DMAP memory in sync.
6880 rv = pmap_change_props_locked(
6881 PHYS_TO_DMAP(pa), pte_size,
6888 * If moving to a non-cacheable entry flush
6891 if (mode == VM_MEMATTR_UNCACHEABLE)
6892 cpu_dcache_wbinv_range(tmpva, pte_size);
6901 * Create an L2 table to map all addresses within an L1 mapping.
6904 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
6906 pt_entry_t *l2, newl2, oldl1;
6908 vm_paddr_t l2phys, phys;
6912 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6913 oldl1 = pmap_load(l1);
6914 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
6915 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
6916 ("pmap_demote_l1: Demoting a non-block entry"));
6917 KASSERT((va & L1_OFFSET) == 0,
6918 ("pmap_demote_l1: Invalid virtual address %#lx", va));
6919 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
6920 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
6921 KASSERT((oldl1 & ATTR_SW_NO_PROMOTE) == 0,
6922 ("pmap_demote_l1: Demoting entry with no-demote flag set"));
6925 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
6926 tmpl1 = kva_alloc(PAGE_SIZE);
6931 if ((ml2 = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED)) ==
6933 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
6934 " in pmap %p", va, pmap);
6939 l2phys = VM_PAGE_TO_PHYS(ml2);
6940 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
6942 /* Address the range points at */
6943 phys = PTE_TO_PHYS(oldl1);
6944 /* The attributed from the old l1 table to be copied */
6945 newl2 = oldl1 & ATTR_MASK;
6947 /* Create the new entries */
6948 for (i = 0; i < Ln_ENTRIES; i++) {
6949 l2[i] = newl2 | phys;
6952 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
6953 ("Invalid l2 page (%lx != %lx)", l2[0],
6954 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
6957 pmap_kenter(tmpl1, PAGE_SIZE,
6958 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET,
6959 VM_MEMATTR_WRITE_BACK);
6960 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
6963 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
6967 pmap_kremove(tmpl1);
6968 kva_free(tmpl1, PAGE_SIZE);
6975 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
6979 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
6986 pmap_demote_l2_check(pt_entry_t *firstl3p __unused, pt_entry_t newl3e __unused)
6990 pt_entry_t *xl3p, *yl3p;
6992 for (xl3p = firstl3p; xl3p < firstl3p + Ln_ENTRIES;
6993 xl3p++, newl3e += PAGE_SIZE) {
6994 if (PTE_TO_PHYS(pmap_load(xl3p)) != PTE_TO_PHYS(newl3e)) {
6995 printf("pmap_demote_l2: xl3e %zd and newl3e map "
6996 "different pages: found %#lx, expected %#lx\n",
6997 xl3p - firstl3p, pmap_load(xl3p), newl3e);
6998 printf("page table dump\n");
6999 for (yl3p = firstl3p; yl3p < firstl3p + Ln_ENTRIES;
7001 printf("%zd %#lx\n", yl3p - firstl3p,
7008 KASSERT(PTE_TO_PHYS(pmap_load(firstl3p)) == PTE_TO_PHYS(newl3e),
7009 ("pmap_demote_l2: firstl3 and newl3e map different physical"
7016 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
7017 struct rwlock **lockp)
7019 struct spglist free;
7022 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
7024 vm_page_free_pages_toq(&free, true);
7028 * Create an L3 table to map all addresses within an L2 mapping.
7031 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
7032 struct rwlock **lockp)
7034 pt_entry_t *l3, newl3, oldl2;
7039 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7040 PMAP_ASSERT_STAGE1(pmap);
7041 KASSERT(ADDR_IS_CANONICAL(va),
7042 ("%s: Address not in canonical form: %lx", __func__, va));
7045 oldl2 = pmap_load(l2);
7046 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
7047 ("pmap_demote_l2: Demoting a non-block entry"));
7048 KASSERT((oldl2 & ATTR_SW_NO_PROMOTE) == 0,
7049 ("pmap_demote_l2: Demoting entry with no-demote flag set"));
7053 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
7054 tmpl2 = kva_alloc(PAGE_SIZE);
7060 * Invalidate the 2MB page mapping and return "failure" if the
7061 * mapping was never accessed.
7063 if ((oldl2 & ATTR_AF) == 0) {
7064 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
7065 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
7066 pmap_demote_l2_abort(pmap, va, l2, lockp);
7067 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
7072 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
7073 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
7074 ("pmap_demote_l2: page table page for a wired mapping"
7078 * If the page table page is missing and the mapping
7079 * is for a kernel address, the mapping must belong to
7080 * either the direct map or the early kernel memory.
7081 * Page table pages are preallocated for every other
7082 * part of the kernel address space, so the direct map
7083 * region and early kernel memory are the only parts of the
7084 * kernel address space that must be handled here.
7086 KASSERT(!ADDR_IS_KERNEL(va) || VIRT_IN_DMAP(va) ||
7087 (va >= VM_MIN_KERNEL_ADDRESS && va < kernel_vm_end),
7088 ("pmap_demote_l2: No saved mpte for va %#lx", va));
7091 * If the 2MB page mapping belongs to the direct map
7092 * region of the kernel's address space, then the page
7093 * allocation request specifies the highest possible
7094 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
7095 * priority is normal.
7097 ml3 = vm_page_alloc_noobj(
7098 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : 0) |
7102 * If the allocation of the new page table page fails,
7103 * invalidate the 2MB page mapping and return "failure".
7106 pmap_demote_l2_abort(pmap, va, l2, lockp);
7107 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
7108 " in pmap %p", va, pmap);
7111 ml3->pindex = pmap_l2_pindex(va);
7113 if (!ADDR_IS_KERNEL(va)) {
7114 ml3->ref_count = NL3PG;
7115 pmap_resident_count_inc(pmap, 1);
7118 l3phys = VM_PAGE_TO_PHYS(ml3);
7119 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
7120 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
7121 KASSERT((oldl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) !=
7122 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM),
7123 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
7126 * If the PTP is not leftover from an earlier promotion or it does not
7127 * have ATTR_AF set in every L3E, then fill it. The new L3Es will all
7130 * When pmap_update_entry() clears the old L2 mapping, it (indirectly)
7131 * performs a dsb(). That dsb() ensures that the stores for filling
7132 * "l3" are visible before "l3" is added to the page table.
7134 if (!vm_page_all_valid(ml3))
7135 pmap_fill_l3(l3, newl3);
7137 pmap_demote_l2_check(l3, newl3);
7140 * If the mapping has changed attributes, update the L3Es.
7142 if ((pmap_load(l3) & (ATTR_MASK & ~ATTR_AF)) != (newl3 & (ATTR_MASK &
7144 pmap_fill_l3(l3, newl3);
7147 * Map the temporary page so we don't lose access to the l2 table.
7150 pmap_kenter(tmpl2, PAGE_SIZE,
7151 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET,
7152 VM_MEMATTR_WRITE_BACK);
7153 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
7157 * The spare PV entries must be reserved prior to demoting the
7158 * mapping, that is, prior to changing the PDE. Otherwise, the state
7159 * of the L2 and the PV lists will be inconsistent, which can result
7160 * in reclaim_pv_chunk() attempting to remove a PV entry from the
7161 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
7162 * PV entry for the 2MB page mapping that is being demoted.
7164 if ((oldl2 & ATTR_SW_MANAGED) != 0)
7165 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
7168 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
7169 * the 2MB page mapping.
7171 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
7174 * Demote the PV entry.
7176 if ((oldl2 & ATTR_SW_MANAGED) != 0)
7177 pmap_pv_demote_l2(pmap, va, PTE_TO_PHYS(oldl2), lockp);
7179 atomic_add_long(&pmap_l2_demotions, 1);
7180 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
7181 " in pmap %p %lx", va, pmap, l3[0]);
7185 pmap_kremove(tmpl2);
7186 kva_free(tmpl2, PAGE_SIZE);
7194 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
7196 struct rwlock *lock;
7200 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
7207 * Perform the pmap work for mincore(2). If the page is not both referenced and
7208 * modified by this pmap, returns its physical address so that the caller can
7209 * find other mappings.
7212 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
7214 pt_entry_t *pte, tpte;
7215 vm_paddr_t mask, pa;
7219 PMAP_ASSERT_STAGE1(pmap);
7221 pte = pmap_pte(pmap, addr, &lvl);
7223 tpte = pmap_load(pte);
7236 panic("pmap_mincore: invalid level %d", lvl);
7239 managed = (tpte & ATTR_SW_MANAGED) != 0;
7240 val = MINCORE_INCORE;
7242 val |= MINCORE_PSIND(3 - lvl);
7243 if ((managed && pmap_pte_dirty(pmap, tpte)) || (!managed &&
7244 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW)))
7245 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
7246 if ((tpte & ATTR_AF) == ATTR_AF)
7247 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
7249 pa = PTE_TO_PHYS(tpte) | (addr & mask);
7255 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
7256 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
7264 * Garbage collect every ASID that is neither active on a processor nor
7268 pmap_reset_asid_set(pmap_t pmap)
7271 int asid, cpuid, epoch;
7272 struct asid_set *set;
7273 enum pmap_stage stage;
7275 set = pmap->pm_asid_set;
7276 stage = pmap->pm_stage;
7278 set = pmap->pm_asid_set;
7279 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
7280 mtx_assert(&set->asid_set_mutex, MA_OWNED);
7283 * Ensure that the store to asid_epoch is globally visible before the
7284 * loads from pc_curpmap are performed.
7286 epoch = set->asid_epoch + 1;
7287 if (epoch == INT_MAX)
7289 set->asid_epoch = epoch;
7291 if (stage == PM_STAGE1) {
7292 __asm __volatile("tlbi vmalle1is");
7294 KASSERT(pmap_clean_stage2_tlbi != NULL,
7295 ("%s: Unset stage 2 tlb invalidation callback\n",
7297 pmap_clean_stage2_tlbi();
7300 bit_nclear(set->asid_set, ASID_FIRST_AVAILABLE,
7301 set->asid_set_size - 1);
7302 CPU_FOREACH(cpuid) {
7303 if (cpuid == curcpu)
7305 if (stage == PM_STAGE1) {
7306 curpmap = pcpu_find(cpuid)->pc_curpmap;
7307 PMAP_ASSERT_STAGE1(pmap);
7309 curpmap = pcpu_find(cpuid)->pc_curvmpmap;
7310 if (curpmap == NULL)
7312 PMAP_ASSERT_STAGE2(pmap);
7314 KASSERT(curpmap->pm_asid_set == set, ("Incorrect set"));
7315 asid = COOKIE_TO_ASID(curpmap->pm_cookie);
7318 bit_set(set->asid_set, asid);
7319 curpmap->pm_cookie = COOKIE_FROM(asid, epoch);
7324 * Allocate a new ASID for the specified pmap.
7327 pmap_alloc_asid(pmap_t pmap)
7329 struct asid_set *set;
7332 set = pmap->pm_asid_set;
7333 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
7335 mtx_lock_spin(&set->asid_set_mutex);
7338 * While this processor was waiting to acquire the asid set mutex,
7339 * pmap_reset_asid_set() running on another processor might have
7340 * updated this pmap's cookie to the current epoch. In which case, we
7341 * don't need to allocate a new ASID.
7343 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch)
7346 bit_ffc_at(set->asid_set, set->asid_next, set->asid_set_size,
7348 if (new_asid == -1) {
7349 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
7350 set->asid_next, &new_asid);
7351 if (new_asid == -1) {
7352 pmap_reset_asid_set(pmap);
7353 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
7354 set->asid_set_size, &new_asid);
7355 KASSERT(new_asid != -1, ("ASID allocation failure"));
7358 bit_set(set->asid_set, new_asid);
7359 set->asid_next = new_asid + 1;
7360 pmap->pm_cookie = COOKIE_FROM(new_asid, set->asid_epoch);
7362 mtx_unlock_spin(&set->asid_set_mutex);
7365 static uint64_t __read_mostly ttbr_flags;
7368 * Compute the value that should be stored in ttbr0 to activate the specified
7369 * pmap. This value may change from time to time.
7372 pmap_to_ttbr0(pmap_t pmap)
7376 ttbr = pmap->pm_ttbr;
7377 ttbr |= ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
7384 pmap_set_cnp(void *arg)
7386 uint64_t ttbr0, ttbr1;
7389 cpuid = *(u_int *)arg;
7390 if (cpuid == curcpu) {
7392 * Set the flags while all CPUs are handling the
7393 * smp_rendezvous so will not call pmap_to_ttbr0. Any calls
7394 * to pmap_to_ttbr0 after this will have the CnP flag set.
7395 * The dsb after invalidating the TLB will act as a barrier
7396 * to ensure all CPUs can observe this change.
7398 ttbr_flags |= TTBR_CnP;
7401 ttbr0 = READ_SPECIALREG(ttbr0_el1);
7404 ttbr1 = READ_SPECIALREG(ttbr1_el1);
7407 /* Update ttbr{0,1}_el1 with the CnP flag */
7408 WRITE_SPECIALREG(ttbr0_el1, ttbr0);
7409 WRITE_SPECIALREG(ttbr1_el1, ttbr1);
7411 __asm __volatile("tlbi vmalle1is");
7417 * Defer enabling CnP until we have read the ID registers to know if it's
7418 * supported on all CPUs.
7421 pmap_init_cnp(void *dummy __unused)
7426 if (!get_kernel_reg(ID_AA64MMFR2_EL1, ®))
7429 if (ID_AA64MMFR2_CnP_VAL(reg) != ID_AA64MMFR2_CnP_NONE) {
7431 printf("Enabling CnP\n");
7433 smp_rendezvous(NULL, pmap_set_cnp, NULL, &cpuid);
7437 SYSINIT(pmap_init_cnp, SI_SUB_SMP, SI_ORDER_ANY, pmap_init_cnp, NULL);
7440 pmap_activate_int(pmap_t pmap)
7442 struct asid_set *set;
7445 KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap"));
7446 KASSERT(pmap != kernel_pmap, ("kernel pmap activation"));
7448 if ((pmap->pm_stage == PM_STAGE1 && pmap == PCPU_GET(curpmap)) ||
7449 (pmap->pm_stage == PM_STAGE2 && pmap == PCPU_GET(curvmpmap))) {
7451 * Handle the possibility that the old thread was preempted
7452 * after an "ic" or "tlbi" instruction but before it performed
7453 * a "dsb" instruction. If the old thread migrates to a new
7454 * processor, its completion of a "dsb" instruction on that
7455 * new processor does not guarantee that the "ic" or "tlbi"
7456 * instructions performed on the old processor have completed.
7462 set = pmap->pm_asid_set;
7463 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
7466 * Ensure that the store to curpmap is globally visible before the
7467 * load from asid_epoch is performed.
7469 if (pmap->pm_stage == PM_STAGE1)
7470 PCPU_SET(curpmap, pmap);
7472 PCPU_SET(curvmpmap, pmap);
7474 epoch = COOKIE_TO_EPOCH(pmap->pm_cookie);
7475 if (epoch >= 0 && epoch != set->asid_epoch)
7476 pmap_alloc_asid(pmap);
7478 if (pmap->pm_stage == PM_STAGE1) {
7479 set_ttbr0(pmap_to_ttbr0(pmap));
7480 if (PCPU_GET(bcast_tlbi_workaround) != 0)
7481 invalidate_local_icache();
7487 pmap_activate_vm(pmap_t pmap)
7490 PMAP_ASSERT_STAGE2(pmap);
7492 (void)pmap_activate_int(pmap);
7496 pmap_activate(struct thread *td)
7500 pmap = vmspace_pmap(td->td_proc->p_vmspace);
7501 PMAP_ASSERT_STAGE1(pmap);
7503 (void)pmap_activate_int(pmap);
7508 * Activate the thread we are switching to.
7509 * To simplify the assembly in cpu_throw return the new threads pcb.
7512 pmap_switch(struct thread *new)
7514 pcpu_bp_harden bp_harden;
7517 /* Store the new curthread */
7518 PCPU_SET(curthread, new);
7520 /* And the new pcb */
7522 PCPU_SET(curpcb, pcb);
7525 * TODO: We may need to flush the cache here if switching
7526 * to a user process.
7529 if (pmap_activate_int(vmspace_pmap(new->td_proc->p_vmspace))) {
7531 * Stop userspace from training the branch predictor against
7532 * other processes. This will call into a CPU specific
7533 * function that clears the branch predictor state.
7535 bp_harden = PCPU_GET(bp_harden);
7536 if (bp_harden != NULL)
7544 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
7547 PMAP_ASSERT_STAGE1(pmap);
7548 KASSERT(ADDR_IS_CANONICAL(va),
7549 ("%s: Address not in canonical form: %lx", __func__, va));
7551 if (ADDR_IS_KERNEL(va)) {
7552 cpu_icache_sync_range(va, sz);
7557 /* Find the length of data in this page to flush */
7558 offset = va & PAGE_MASK;
7559 len = imin(PAGE_SIZE - offset, sz);
7562 /* Extract the physical address & find it in the DMAP */
7563 pa = pmap_extract(pmap, va);
7565 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
7567 /* Move to the next page */
7570 /* Set the length for the next iteration */
7571 len = imin(PAGE_SIZE, sz);
7577 pmap_stage2_fault(pmap_t pmap, uint64_t esr, uint64_t far)
7580 pt_entry_t *ptep, pte;
7583 PMAP_ASSERT_STAGE2(pmap);
7586 /* Data and insn aborts use same encoding for FSC field. */
7587 dfsc = esr & ISS_DATA_DFSC_MASK;
7589 case ISS_DATA_DFSC_TF_L0:
7590 case ISS_DATA_DFSC_TF_L1:
7591 case ISS_DATA_DFSC_TF_L2:
7592 case ISS_DATA_DFSC_TF_L3:
7594 pdep = pmap_pde(pmap, far, &lvl);
7595 if (pdep == NULL || lvl != (dfsc - ISS_DATA_DFSC_TF_L1)) {
7602 ptep = pmap_l0_to_l1(pdep, far);
7605 ptep = pmap_l1_to_l2(pdep, far);
7608 ptep = pmap_l2_to_l3(pdep, far);
7611 panic("%s: Invalid pde level %d", __func__,lvl);
7615 case ISS_DATA_DFSC_AFF_L1:
7616 case ISS_DATA_DFSC_AFF_L2:
7617 case ISS_DATA_DFSC_AFF_L3:
7619 ptep = pmap_pte(pmap, far, &lvl);
7621 if (ptep != NULL && (pte = pmap_load(ptep)) != 0) {
7623 pmap_invalidate_vpipt_icache();
7626 * If accessing an executable page invalidate
7627 * the I-cache so it will be valid when we
7628 * continue execution in the guest. The D-cache
7629 * is assumed to already be clean to the Point
7632 if ((pte & ATTR_S2_XN_MASK) !=
7633 ATTR_S2_XN(ATTR_S2_XN_NONE)) {
7634 invalidate_icache();
7637 pmap_set_bits(ptep, ATTR_AF | ATTR_DESCR_VALID);
7648 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
7650 pt_entry_t pte, *ptep;
7657 ec = ESR_ELx_EXCEPTION(esr);
7659 case EXCP_INSN_ABORT_L:
7660 case EXCP_INSN_ABORT:
7661 case EXCP_DATA_ABORT_L:
7662 case EXCP_DATA_ABORT:
7668 if (pmap->pm_stage == PM_STAGE2)
7669 return (pmap_stage2_fault(pmap, esr, far));
7671 /* Data and insn aborts use same encoding for FSC field. */
7672 switch (esr & ISS_DATA_DFSC_MASK) {
7673 case ISS_DATA_DFSC_AFF_L1:
7674 case ISS_DATA_DFSC_AFF_L2:
7675 case ISS_DATA_DFSC_AFF_L3:
7677 ptep = pmap_pte(pmap, far, &lvl);
7679 pmap_set_bits(ptep, ATTR_AF);
7682 * XXXMJ as an optimization we could mark the entry
7683 * dirty if this is a write fault.
7688 case ISS_DATA_DFSC_PF_L1:
7689 case ISS_DATA_DFSC_PF_L2:
7690 case ISS_DATA_DFSC_PF_L3:
7691 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
7692 (esr & ISS_DATA_WnR) == 0)
7695 ptep = pmap_pte(pmap, far, &lvl);
7697 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
7698 if ((pte & ATTR_S1_AP_RW_BIT) ==
7699 ATTR_S1_AP(ATTR_S1_AP_RO)) {
7700 pmap_clear_bits(ptep, ATTR_S1_AP_RW_BIT);
7701 pmap_s1_invalidate_page(pmap, far, true);
7707 case ISS_DATA_DFSC_TF_L0:
7708 case ISS_DATA_DFSC_TF_L1:
7709 case ISS_DATA_DFSC_TF_L2:
7710 case ISS_DATA_DFSC_TF_L3:
7712 * Retry the translation. A break-before-make sequence can
7713 * produce a transient fault.
7715 if (pmap == kernel_pmap) {
7717 * The translation fault may have occurred within a
7718 * critical section. Therefore, we must check the
7719 * address without acquiring the kernel pmap's lock.
7721 if (pmap_klookup(far, NULL))
7725 /* Ask the MMU to check the address. */
7726 intr = intr_disable();
7727 par = arm64_address_translate_s1e0r(far);
7732 * If the translation was successful, then we can
7733 * return success to the trap handler.
7735 if (PAR_SUCCESS(par))
7745 * Increase the starting virtual address of the given mapping if a
7746 * different alignment might result in more superpage mappings.
7749 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
7750 vm_offset_t *addr, vm_size_t size)
7752 vm_offset_t superpage_offset;
7756 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
7757 offset += ptoa(object->pg_color);
7758 superpage_offset = offset & L2_OFFSET;
7759 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
7760 (*addr & L2_OFFSET) == superpage_offset)
7762 if ((*addr & L2_OFFSET) < superpage_offset)
7763 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
7765 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
7769 * Get the kernel virtual address of a set of physical pages. If there are
7770 * physical addresses not covered by the DMAP perform a transient mapping
7771 * that will be removed when calling pmap_unmap_io_transient.
7773 * \param page The pages the caller wishes to obtain the virtual
7774 * address on the kernel memory map.
7775 * \param vaddr On return contains the kernel virtual memory address
7776 * of the pages passed in the page parameter.
7777 * \param count Number of pages passed in.
7778 * \param can_fault true if the thread using the mapped pages can take
7779 * page faults, false otherwise.
7781 * \returns true if the caller must call pmap_unmap_io_transient when
7782 * finished or false otherwise.
7786 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7791 int error __diagused, i;
7794 * Allocate any KVA space that we need, this is done in a separate
7795 * loop to prevent calling vmem_alloc while pinned.
7797 needs_mapping = false;
7798 for (i = 0; i < count; i++) {
7799 paddr = VM_PAGE_TO_PHYS(page[i]);
7800 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
7801 error = vmem_alloc(kernel_arena, PAGE_SIZE,
7802 M_BESTFIT | M_WAITOK, &vaddr[i]);
7803 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
7804 needs_mapping = true;
7806 vaddr[i] = PHYS_TO_DMAP(paddr);
7810 /* Exit early if everything is covered by the DMAP */
7816 for (i = 0; i < count; i++) {
7817 paddr = VM_PAGE_TO_PHYS(page[i]);
7818 if (!PHYS_IN_DMAP(paddr)) {
7820 "pmap_map_io_transient: TODO: Map out of DMAP data");
7824 return (needs_mapping);
7828 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7836 for (i = 0; i < count; i++) {
7837 paddr = VM_PAGE_TO_PHYS(page[i]);
7838 if (!PHYS_IN_DMAP(paddr)) {
7839 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
7845 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
7848 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);
7852 pmap_pte_bti(pmap_t pmap, vm_offset_t va __diagused)
7854 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7855 MPASS(ADDR_IS_CANONICAL(va));
7857 if (pmap->pm_stage != PM_STAGE1)
7859 if (pmap == kernel_pmap)
7860 return (ATTR_KERN_GP);
7865 static vm_paddr_t pmap_san_early_kernstart;
7866 static pd_entry_t *pmap_san_early_l2;
7868 void __nosanitizeaddress
7869 pmap_san_bootstrap(struct arm64_bootparams *abp)
7872 pmap_san_early_kernstart = pmap_early_vtophys(KERNBASE);
7873 kasan_init_early(abp->kern_stack, KSTACK_PAGES * PAGE_SIZE);
7876 #define SAN_BOOTSTRAP_L2_SIZE (1 * L2_SIZE)
7877 #define SAN_BOOTSTRAP_SIZE (2 * PAGE_SIZE)
7878 static vm_offset_t __nosanitizeaddress
7879 pmap_san_enter_bootstrap_alloc_l2(void)
7881 static uint8_t bootstrap_data[SAN_BOOTSTRAP_L2_SIZE] __aligned(L2_SIZE);
7882 static size_t offset = 0;
7885 if (offset + L2_SIZE > sizeof(bootstrap_data)) {
7886 panic("%s: out of memory for the bootstrap shadow map L2 entries",
7890 addr = (uintptr_t)&bootstrap_data[offset];
7896 * SAN L1 + L2 pages, maybe L3 entries later?
7898 static vm_offset_t __nosanitizeaddress
7899 pmap_san_enter_bootstrap_alloc_pages(int npages)
7901 static uint8_t bootstrap_data[SAN_BOOTSTRAP_SIZE] __aligned(PAGE_SIZE);
7902 static size_t offset = 0;
7905 if (offset + (npages * PAGE_SIZE) > sizeof(bootstrap_data)) {
7906 panic("%s: out of memory for the bootstrap shadow map",
7910 addr = (uintptr_t)&bootstrap_data[offset];
7911 offset += (npages * PAGE_SIZE);
7915 static void __nosanitizeaddress
7916 pmap_san_enter_bootstrap(void)
7918 vm_offset_t freemempos;
7921 freemempos = pmap_san_enter_bootstrap_alloc_pages(2);
7922 bs_state.freemempos = freemempos;
7923 bs_state.va = KASAN_MIN_ADDRESS;
7924 pmap_bootstrap_l1_table(&bs_state);
7925 pmap_san_early_l2 = bs_state.l2;
7929 pmap_san_enter_alloc_l3(void)
7933 m = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED |
7936 panic("%s: no memory to grow shadow map", __func__);
7941 pmap_san_enter_alloc_l2(void)
7943 return (vm_page_alloc_noobj_contig(VM_ALLOC_WIRED | VM_ALLOC_ZERO,
7944 Ln_ENTRIES, 0, ~0ul, L2_SIZE, 0, VM_MEMATTR_DEFAULT));
7947 void __nosanitizeaddress
7948 pmap_san_enter(vm_offset_t va)
7950 pd_entry_t *l1, *l2;
7954 if (virtual_avail == 0) {
7959 /* Temporary shadow map prior to pmap_bootstrap(). */
7960 first = pmap_san_early_l2 == NULL;
7962 pmap_san_enter_bootstrap();
7964 l2 = pmap_san_early_l2;
7965 slot = pmap_l2_index(va);
7967 if ((pmap_load(&l2[slot]) & ATTR_DESCR_VALID) == 0) {
7969 block = pmap_san_enter_bootstrap_alloc_l2();
7970 pmap_store(&l2[slot],
7971 PHYS_TO_PTE(pmap_early_vtophys(block)) |
7972 PMAP_SAN_PTE_BITS | L2_BLOCK);
7979 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
7980 l1 = pmap_l1(kernel_pmap, va);
7982 if ((pmap_load(l1) & ATTR_DESCR_VALID) == 0) {
7983 m = pmap_san_enter_alloc_l3();
7984 pmap_store(l1, PHYS_TO_PTE(VM_PAGE_TO_PHYS(m)) | L1_TABLE);
7986 l2 = pmap_l1_to_l2(l1, va);
7987 if ((pmap_load(l2) & ATTR_DESCR_VALID) == 0) {
7988 m = pmap_san_enter_alloc_l2();
7990 pmap_store(l2, PHYS_TO_PTE(VM_PAGE_TO_PHYS(m)) |
7991 PMAP_SAN_PTE_BITS | L2_BLOCK);
7993 m = pmap_san_enter_alloc_l3();
7994 pmap_store(l2, PHYS_TO_PTE(VM_PAGE_TO_PHYS(m)) |
7999 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK)
8001 l3 = pmap_l2_to_l3(l2, va);
8002 if ((pmap_load(l3) & ATTR_DESCR_VALID) != 0)
8004 m = pmap_san_enter_alloc_l3();
8005 pmap_store(l3, PHYS_TO_PTE(VM_PAGE_TO_PHYS(m)) |
8006 PMAP_SAN_PTE_BITS | L3_PAGE);
8012 * Track a range of the kernel's virtual address space that is contiguous
8013 * in various mapping attributes.
8015 struct pmap_kernel_map_range {
8025 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
8031 if (eva <= range->sva)
8034 index = range->attrs & ATTR_S1_IDX_MASK;
8036 case ATTR_S1_IDX(VM_MEMATTR_DEVICE_NP):
8039 case ATTR_S1_IDX(VM_MEMATTR_DEVICE):
8042 case ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE):
8045 case ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK):
8048 case ATTR_S1_IDX(VM_MEMATTR_WRITE_THROUGH):
8053 "%s: unknown memory type %x for range 0x%016lx-0x%016lx\n",
8054 __func__, index, range->sva, eva);
8059 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c%c %6s %d %d %d %d\n",
8061 (range->attrs & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP_RW ? 'w' : '-',
8062 (range->attrs & ATTR_S1_PXN) != 0 ? '-' : 'x',
8063 (range->attrs & ATTR_S1_UXN) != 0 ? '-' : 'X',
8064 (range->attrs & ATTR_S1_AP(ATTR_S1_AP_USER)) != 0 ? 'u' : 's',
8065 (range->attrs & ATTR_S1_GP) != 0 ? 'g' : '-',
8066 mode, range->l1blocks, range->l2blocks, range->l3contig,
8069 /* Reset to sentinel value. */
8070 range->sva = 0xfffffffffffffffful;
8074 * Determine whether the attributes specified by a page table entry match those
8075 * being tracked by the current range.
8078 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
8081 return (range->attrs == attrs);
8085 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
8089 memset(range, 0, sizeof(*range));
8091 range->attrs = attrs;
8094 /* Get the block/page attributes that correspond to the table attributes */
8096 sysctl_kmaps_table_attrs(pd_entry_t table)
8101 if ((table & TATTR_UXN_TABLE) != 0)
8102 attrs |= ATTR_S1_UXN;
8103 if ((table & TATTR_PXN_TABLE) != 0)
8104 attrs |= ATTR_S1_PXN;
8105 if ((table & TATTR_AP_TABLE_RO) != 0)
8106 attrs |= ATTR_S1_AP(ATTR_S1_AP_RO);
8111 /* Read the block/page attributes we care about */
8113 sysctl_kmaps_block_attrs(pt_entry_t block)
8115 return (block & (ATTR_S1_AP_MASK | ATTR_S1_XN | ATTR_S1_IDX_MASK |
8120 * Given a leaf PTE, derive the mapping's attributes. If they do not match
8121 * those of the current run, dump the address range and its attributes, and
8125 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
8126 vm_offset_t va, pd_entry_t l0e, pd_entry_t l1e, pd_entry_t l2e,
8131 attrs = sysctl_kmaps_table_attrs(l0e);
8133 if ((l1e & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
8134 attrs |= sysctl_kmaps_block_attrs(l1e);
8137 attrs |= sysctl_kmaps_table_attrs(l1e);
8139 if ((l2e & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
8140 attrs |= sysctl_kmaps_block_attrs(l2e);
8143 attrs |= sysctl_kmaps_table_attrs(l2e);
8144 attrs |= sysctl_kmaps_block_attrs(l3e);
8147 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
8148 sysctl_kmaps_dump(sb, range, va);
8149 sysctl_kmaps_reinit(range, va, attrs);
8154 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
8156 struct pmap_kernel_map_range range;
8157 struct sbuf sbuf, *sb;
8158 pd_entry_t l0e, *l1, l1e, *l2, l2e;
8159 pt_entry_t *l3, l3e;
8162 int error, i, j, k, l;
8164 error = sysctl_wire_old_buffer(req, 0);
8168 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
8170 /* Sentinel value. */
8171 range.sva = 0xfffffffffffffffful;
8174 * Iterate over the kernel page tables without holding the kernel pmap
8175 * lock. Kernel page table pages are never freed, so at worst we will
8176 * observe inconsistencies in the output.
8178 for (sva = 0xffff000000000000ul, i = pmap_l0_index(sva); i < Ln_ENTRIES;
8180 if (i == pmap_l0_index(DMAP_MIN_ADDRESS))
8181 sbuf_printf(sb, "\nDirect map:\n");
8182 else if (i == pmap_l0_index(VM_MIN_KERNEL_ADDRESS))
8183 sbuf_printf(sb, "\nKernel map:\n");
8185 else if (i == pmap_l0_index(KASAN_MIN_ADDRESS))
8186 sbuf_printf(sb, "\nKASAN shadow map:\n");
8189 l0e = kernel_pmap->pm_l0[i];
8190 if ((l0e & ATTR_DESCR_VALID) == 0) {
8191 sysctl_kmaps_dump(sb, &range, sva);
8195 pa = PTE_TO_PHYS(l0e);
8196 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa);
8198 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
8200 if ((l1e & ATTR_DESCR_VALID) == 0) {
8201 sysctl_kmaps_dump(sb, &range, sva);
8205 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
8206 PMAP_ASSERT_L1_BLOCKS_SUPPORTED;
8207 sysctl_kmaps_check(sb, &range, sva, l0e, l1e,
8213 pa = PTE_TO_PHYS(l1e);
8214 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa);
8216 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
8218 if ((l2e & ATTR_DESCR_VALID) == 0) {
8219 sysctl_kmaps_dump(sb, &range, sva);
8223 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK) {
8224 sysctl_kmaps_check(sb, &range, sva,
8230 pa = PTE_TO_PHYS(l2e);
8231 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
8233 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
8234 l++, sva += L3_SIZE) {
8236 if ((l3e & ATTR_DESCR_VALID) == 0) {
8237 sysctl_kmaps_dump(sb, &range,
8241 sysctl_kmaps_check(sb, &range, sva,
8242 l0e, l1e, l2e, l3e);
8243 if ((l3e & ATTR_CONTIGUOUS) != 0)
8244 range.l3contig += l % 16 == 0 ?
8253 error = sbuf_finish(sb);
8257 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
8258 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP,
8259 NULL, 0, sysctl_kmaps, "A",
8260 "Dump kernel address layout");