2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/msgbuf.h>
120 #include <sys/mutex.h>
121 #include <sys/proc.h>
122 #include <sys/rwlock.h>
124 #include <sys/vmem.h>
125 #include <sys/vmmeter.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/_unrhdr.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/vm_pager.h>
140 #include <vm/vm_phys.h>
141 #include <vm/vm_radix.h>
142 #include <vm/vm_reserv.h>
145 #include <machine/machdep.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
149 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
150 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
151 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
152 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
154 #define NUL0E L0_ENTRIES
155 #define NUL1E (NUL0E * NL1PG)
156 #define NUL2E (NUL1E * NL2PG)
158 #if !defined(DIAGNOSTIC)
159 #ifdef __GNUC_GNU_INLINE__
160 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
162 #define PMAP_INLINE extern inline
169 * These are configured by the mair_el1 register. This is set up in locore.S
171 #define DEVICE_MEMORY 0
172 #define UNCACHED_MEMORY 1
173 #define CACHED_MEMORY 2
177 #define PV_STAT(x) do { x ; } while (0)
179 #define PV_STAT(x) do { } while (0)
182 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
183 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
185 #define NPV_LIST_LOCKS MAXCPU
187 #define PHYS_TO_PV_LIST_LOCK(pa) \
188 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
190 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
191 struct rwlock **_lockp = (lockp); \
192 struct rwlock *_new_lock; \
194 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
195 if (_new_lock != *_lockp) { \
196 if (*_lockp != NULL) \
197 rw_wunlock(*_lockp); \
198 *_lockp = _new_lock; \
203 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
204 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
206 #define RELEASE_PV_LIST_LOCK(lockp) do { \
207 struct rwlock **_lockp = (lockp); \
209 if (*_lockp != NULL) { \
210 rw_wunlock(*_lockp); \
215 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
216 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
218 struct pmap kernel_pmap_store;
220 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
221 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
222 vm_offset_t kernel_vm_end = 0;
225 * Data for the pv entry allocation mechanism.
226 * Updates to pv_invl_gen are protected by the pv_list_locks[]
227 * elements, but reads are not.
229 static struct md_page *pv_table;
230 static struct md_page pv_dummy;
232 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
233 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
234 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
236 /* This code assumes all L1 DMAP entries will be used */
237 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
238 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
240 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
241 extern pt_entry_t pagetable_dmap[];
243 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
245 static int superpages_enabled = 1;
246 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
247 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
248 "Are large page mappings enabled?");
251 * Data for the pv entry allocation mechanism
253 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
254 static struct mtx pv_chunks_mutex;
255 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
257 static void free_pv_chunk(struct pv_chunk *pc);
258 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
259 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
260 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
261 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
262 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
265 static int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode);
266 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
267 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
268 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
269 vm_offset_t va, struct rwlock **lockp);
270 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
271 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
272 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
273 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
274 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
275 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
276 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
277 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
278 vm_page_t m, struct rwlock **lockp);
280 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
281 struct rwlock **lockp);
283 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
284 struct spglist *free);
285 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
286 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
289 * These load the old table data and store the new value.
290 * They need to be atomic as the System MMU may write to the table at
291 * the same time as the CPU.
293 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
294 #define pmap_set(table, mask) atomic_set_64(table, mask)
295 #define pmap_load_clear(table) atomic_swap_64(table, 0)
296 #define pmap_load(table) (*table)
298 /********************/
299 /* Inline functions */
300 /********************/
303 pagecopy(void *s, void *d)
306 memcpy(d, s, PAGE_SIZE);
309 static __inline pd_entry_t *
310 pmap_l0(pmap_t pmap, vm_offset_t va)
313 return (&pmap->pm_l0[pmap_l0_index(va)]);
316 static __inline pd_entry_t *
317 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
321 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
322 return (&l1[pmap_l1_index(va)]);
325 static __inline pd_entry_t *
326 pmap_l1(pmap_t pmap, vm_offset_t va)
330 l0 = pmap_l0(pmap, va);
331 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
334 return (pmap_l0_to_l1(l0, va));
337 static __inline pd_entry_t *
338 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
342 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
343 return (&l2[pmap_l2_index(va)]);
346 static __inline pd_entry_t *
347 pmap_l2(pmap_t pmap, vm_offset_t va)
351 l1 = pmap_l1(pmap, va);
352 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
355 return (pmap_l1_to_l2(l1, va));
358 static __inline pt_entry_t *
359 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
363 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
364 return (&l3[pmap_l3_index(va)]);
368 * Returns the lowest valid pde for a given virtual address.
369 * The next level may or may not point to a valid page or block.
371 static __inline pd_entry_t *
372 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
374 pd_entry_t *l0, *l1, *l2, desc;
376 l0 = pmap_l0(pmap, va);
377 desc = pmap_load(l0) & ATTR_DESCR_MASK;
378 if (desc != L0_TABLE) {
383 l1 = pmap_l0_to_l1(l0, va);
384 desc = pmap_load(l1) & ATTR_DESCR_MASK;
385 if (desc != L1_TABLE) {
390 l2 = pmap_l1_to_l2(l1, va);
391 desc = pmap_load(l2) & ATTR_DESCR_MASK;
392 if (desc != L2_TABLE) {
402 * Returns the lowest valid pte block or table entry for a given virtual
403 * address. If there are no valid entries return NULL and set the level to
404 * the first invalid level.
406 static __inline pt_entry_t *
407 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
409 pd_entry_t *l1, *l2, desc;
412 l1 = pmap_l1(pmap, va);
417 desc = pmap_load(l1) & ATTR_DESCR_MASK;
418 if (desc == L1_BLOCK) {
423 if (desc != L1_TABLE) {
428 l2 = pmap_l1_to_l2(l1, va);
429 desc = pmap_load(l2) & ATTR_DESCR_MASK;
430 if (desc == L2_BLOCK) {
435 if (desc != L2_TABLE) {
441 l3 = pmap_l2_to_l3(l2, va);
442 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
449 pmap_superpages_enabled(void)
452 return (superpages_enabled != 0);
456 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
457 pd_entry_t **l2, pt_entry_t **l3)
459 pd_entry_t *l0p, *l1p, *l2p;
461 if (pmap->pm_l0 == NULL)
464 l0p = pmap_l0(pmap, va);
467 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
470 l1p = pmap_l0_to_l1(l0p, va);
473 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
479 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
482 l2p = pmap_l1_to_l2(l1p, va);
485 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
490 *l3 = pmap_l2_to_l3(l2p, va);
496 pmap_l3_valid(pt_entry_t l3)
499 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
503 CTASSERT(L1_BLOCK == L2_BLOCK);
506 * Checks if the page is dirty. We currently lack proper tracking of this on
507 * arm64 so for now assume is a page mapped as rw was accessed it is.
510 pmap_page_dirty(pt_entry_t pte)
513 return ((pte & (ATTR_AF | ATTR_AP_RW_BIT)) ==
514 (ATTR_AF | ATTR_AP(ATTR_AP_RW)));
518 pmap_resident_count_inc(pmap_t pmap, int count)
521 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
522 pmap->pm_stats.resident_count += count;
526 pmap_resident_count_dec(pmap_t pmap, int count)
529 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
530 KASSERT(pmap->pm_stats.resident_count >= count,
531 ("pmap %p resident count underflow %ld %d", pmap,
532 pmap->pm_stats.resident_count, count));
533 pmap->pm_stats.resident_count -= count;
537 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
543 l1 = (pd_entry_t *)l1pt;
544 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
546 /* Check locore has used a table L1 map */
547 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
548 ("Invalid bootstrap L1 table"));
549 /* Find the address of the L2 table */
550 l2 = (pt_entry_t *)init_pt_va;
551 *l2_slot = pmap_l2_index(va);
557 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
559 u_int l1_slot, l2_slot;
562 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
564 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
568 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa, vm_paddr_t max_pa)
574 pa = dmap_phys_base = min_pa & ~L1_OFFSET;
575 va = DMAP_MIN_ADDRESS;
576 for (; va < DMAP_MAX_ADDRESS && pa < max_pa;
577 pa += L1_SIZE, va += L1_SIZE, l1_slot++) {
578 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
580 pmap_load_store(&pagetable_dmap[l1_slot],
581 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
582 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
585 /* Set the upper limit of the DMAP region */
593 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
600 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
602 l1 = (pd_entry_t *)l1pt;
603 l1_slot = pmap_l1_index(va);
606 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
607 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
609 pa = pmap_early_vtophys(l1pt, l2pt);
610 pmap_load_store(&l1[l1_slot],
611 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
615 /* Clean the L2 page table */
616 memset((void *)l2_start, 0, l2pt - l2_start);
622 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
629 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
631 l2 = pmap_l2(kernel_pmap, va);
632 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
633 l2_slot = pmap_l2_index(va);
636 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
637 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
639 pa = pmap_early_vtophys(l1pt, l3pt);
640 pmap_load_store(&l2[l2_slot],
641 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
645 /* Clean the L2 page table */
646 memset((void *)l3_start, 0, l3pt - l3_start);
652 * Bootstrap the system enough to run with virtual memory.
655 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
658 u_int l1_slot, l2_slot, avail_slot, map_slot, used_map_slot;
661 vm_offset_t va, freemempos;
662 vm_offset_t dpcpu, msgbufpv;
663 vm_paddr_t pa, max_pa, min_pa;
666 kern_delta = KERNBASE - kernstart;
669 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
670 printf("%lx\n", l1pt);
671 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
673 /* Set this early so we can use the pagetable walking functions */
674 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
675 PMAP_LOCK_INIT(kernel_pmap);
677 /* Assume the address we were loaded to is a valid physical address */
678 min_pa = max_pa = KERNBASE - kern_delta;
681 * Find the minimum physical address. physmap is sorted,
682 * but may contain empty ranges.
684 for (i = 0; i < (physmap_idx * 2); i += 2) {
685 if (physmap[i] == physmap[i + 1])
687 if (physmap[i] <= min_pa)
689 if (physmap[i + 1] > max_pa)
690 max_pa = physmap[i + 1];
693 /* Create a direct map region early so we can use it for pa -> va */
694 pmap_bootstrap_dmap(l1pt, min_pa, max_pa);
697 pa = KERNBASE - kern_delta;
700 * Start to initialise phys_avail by copying from physmap
701 * up to the physical address KERNBASE points at.
703 map_slot = avail_slot = 0;
704 for (; map_slot < (physmap_idx * 2) &&
705 avail_slot < (PHYS_AVAIL_SIZE - 2); map_slot += 2) {
706 if (physmap[map_slot] == physmap[map_slot + 1])
709 if (physmap[map_slot] <= pa &&
710 physmap[map_slot + 1] > pa)
713 phys_avail[avail_slot] = physmap[map_slot];
714 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
715 physmem += (phys_avail[avail_slot + 1] -
716 phys_avail[avail_slot]) >> PAGE_SHIFT;
720 /* Add the memory before the kernel */
721 if (physmap[avail_slot] < pa && avail_slot < (PHYS_AVAIL_SIZE - 2)) {
722 phys_avail[avail_slot] = physmap[map_slot];
723 phys_avail[avail_slot + 1] = pa;
724 physmem += (phys_avail[avail_slot + 1] -
725 phys_avail[avail_slot]) >> PAGE_SHIFT;
728 used_map_slot = map_slot;
731 * Read the page table to find out what is already mapped.
732 * This assumes we have mapped a block of memory from KERNBASE
733 * using a single L1 entry.
735 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
737 /* Sanity check the index, KERNBASE should be the first VA */
738 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
740 /* Find how many pages we have mapped */
741 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
742 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
745 /* Check locore used L2 blocks */
746 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
747 ("Invalid bootstrap L2 table"));
748 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
749 ("Incorrect PA in L2 table"));
755 va = roundup2(va, L1_SIZE);
757 freemempos = KERNBASE + kernlen;
758 freemempos = roundup2(freemempos, PAGE_SIZE);
759 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
760 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
761 /* And the l3 tables for the early devmap */
762 freemempos = pmap_bootstrap_l3(l1pt,
763 VM_MAX_KERNEL_ADDRESS - L2_SIZE, freemempos);
767 #define alloc_pages(var, np) \
768 (var) = freemempos; \
769 freemempos += (np * PAGE_SIZE); \
770 memset((char *)(var), 0, ((np) * PAGE_SIZE));
772 /* Allocate dynamic per-cpu area. */
773 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
774 dpcpu_init((void *)dpcpu, 0);
776 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
777 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
778 msgbufp = (void *)msgbufpv;
780 virtual_avail = roundup2(freemempos, L1_SIZE);
781 virtual_end = VM_MAX_KERNEL_ADDRESS - L2_SIZE;
782 kernel_vm_end = virtual_avail;
784 pa = pmap_early_vtophys(l1pt, freemempos);
786 /* Finish initialising physmap */
787 map_slot = used_map_slot;
788 for (; avail_slot < (PHYS_AVAIL_SIZE - 2) &&
789 map_slot < (physmap_idx * 2); map_slot += 2) {
790 if (physmap[map_slot] == physmap[map_slot + 1])
793 /* Have we used the current range? */
794 if (physmap[map_slot + 1] <= pa)
797 /* Do we need to split the entry? */
798 if (physmap[map_slot] < pa) {
799 phys_avail[avail_slot] = pa;
800 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
802 phys_avail[avail_slot] = physmap[map_slot];
803 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
805 physmem += (phys_avail[avail_slot + 1] -
806 phys_avail[avail_slot]) >> PAGE_SHIFT;
810 phys_avail[avail_slot] = 0;
811 phys_avail[avail_slot + 1] = 0;
814 * Maxmem isn't the "maximum memory", it's one larger than the
815 * highest page of the physical address space. It should be
816 * called something like "Maxphyspage".
818 Maxmem = atop(phys_avail[avail_slot - 1]);
824 * Initialize a vm_page's machine-dependent fields.
827 pmap_page_init(vm_page_t m)
830 TAILQ_INIT(&m->md.pv_list);
831 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
835 * Initialize the pmap module.
836 * Called by vm_init, to initialize any structures that the pmap
837 * system needs to map virtual memory.
846 * Are large page mappings enabled?
848 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
851 * Initialize the pv chunk list mutex.
853 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
856 * Initialize the pool of pv list locks.
858 for (i = 0; i < NPV_LIST_LOCKS; i++)
859 rw_init(&pv_list_locks[i], "pmap pv list");
862 * Calculate the size of the pv head table for superpages.
864 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
867 * Allocate memory for the pv head table for superpages.
869 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
871 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
873 for (i = 0; i < pv_npg; i++)
874 TAILQ_INIT(&pv_table[i].pv_list);
875 TAILQ_INIT(&pv_dummy.pv_list);
878 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
879 "2MB page mapping counters");
881 static u_long pmap_l2_demotions;
882 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
883 &pmap_l2_demotions, 0, "2MB page demotions");
885 static u_long pmap_l2_p_failures;
886 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
887 &pmap_l2_p_failures, 0, "2MB page promotion failures");
889 static u_long pmap_l2_promotions;
890 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
891 &pmap_l2_promotions, 0, "2MB page promotions");
894 * Invalidate a single TLB entry.
897 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
903 "tlbi vaae1is, %0 \n"
906 : : "r"(va >> PAGE_SHIFT));
911 pmap_invalidate_range_nopin(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
916 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
918 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
926 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
930 pmap_invalidate_range_nopin(pmap, sva, eva);
935 pmap_invalidate_all(pmap_t pmap)
948 * Routine: pmap_extract
950 * Extract the physical page address associated
951 * with the given map/virtual_address pair.
954 pmap_extract(pmap_t pmap, vm_offset_t va)
956 pt_entry_t *pte, tpte;
963 * Find the block or page map for this virtual address. pmap_pte
964 * will return either a valid block/page entry, or NULL.
966 pte = pmap_pte(pmap, va, &lvl);
968 tpte = pmap_load(pte);
969 pa = tpte & ~ATTR_MASK;
972 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
973 ("pmap_extract: Invalid L1 pte found: %lx",
974 tpte & ATTR_DESCR_MASK));
975 pa |= (va & L1_OFFSET);
978 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
979 ("pmap_extract: Invalid L2 pte found: %lx",
980 tpte & ATTR_DESCR_MASK));
981 pa |= (va & L2_OFFSET);
984 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
985 ("pmap_extract: Invalid L3 pte found: %lx",
986 tpte & ATTR_DESCR_MASK));
987 pa |= (va & L3_OFFSET);
996 * Routine: pmap_extract_and_hold
998 * Atomically extract and hold the physical page
999 * with the given pmap and virtual address pair
1000 * if that mapping permits the given protection.
1003 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1005 pt_entry_t *pte, tpte;
1015 pte = pmap_pte(pmap, va, &lvl);
1017 tpte = pmap_load(pte);
1019 KASSERT(lvl > 0 && lvl <= 3,
1020 ("pmap_extract_and_hold: Invalid level %d", lvl));
1021 CTASSERT(L1_BLOCK == L2_BLOCK);
1022 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1023 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1024 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1025 tpte & ATTR_DESCR_MASK));
1026 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1027 ((prot & VM_PROT_WRITE) == 0)) {
1030 off = va & L1_OFFSET;
1033 off = va & L2_OFFSET;
1039 if (vm_page_pa_tryrelock(pmap,
1040 (tpte & ~ATTR_MASK) | off, &pa))
1042 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1052 pmap_kextract(vm_offset_t va)
1054 pt_entry_t *pte, tpte;
1058 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1059 pa = DMAP_TO_PHYS(va);
1062 pte = pmap_pte(kernel_pmap, va, &lvl);
1064 tpte = pmap_load(pte);
1065 pa = tpte & ~ATTR_MASK;
1068 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1069 ("pmap_kextract: Invalid L1 pte found: %lx",
1070 tpte & ATTR_DESCR_MASK));
1071 pa |= (va & L1_OFFSET);
1074 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1075 ("pmap_kextract: Invalid L2 pte found: %lx",
1076 tpte & ATTR_DESCR_MASK));
1077 pa |= (va & L2_OFFSET);
1080 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1081 ("pmap_kextract: Invalid L3 pte found: %lx",
1082 tpte & ATTR_DESCR_MASK));
1083 pa |= (va & L3_OFFSET);
1091 /***************************************************
1092 * Low level mapping routines.....
1093 ***************************************************/
1096 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1099 pt_entry_t *pte, attr;
1103 KASSERT((pa & L3_OFFSET) == 0,
1104 ("pmap_kenter: Invalid physical address"));
1105 KASSERT((sva & L3_OFFSET) == 0,
1106 ("pmap_kenter: Invalid virtual address"));
1107 KASSERT((size & PAGE_MASK) == 0,
1108 ("pmap_kenter: Mapping is not page-sized"));
1110 attr = ATTR_DEFAULT | ATTR_IDX(mode) | L3_PAGE;
1111 if (mode == DEVICE_MEMORY)
1116 pde = pmap_pde(kernel_pmap, va, &lvl);
1117 KASSERT(pde != NULL,
1118 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1119 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1121 pte = pmap_l2_to_l3(pde, va);
1122 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1128 pmap_invalidate_range(kernel_pmap, sva, va);
1132 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1135 pmap_kenter(sva, size, pa, DEVICE_MEMORY);
1139 * Remove a page from the kernel pagetables.
1142 pmap_kremove(vm_offset_t va)
1147 pte = pmap_pte(kernel_pmap, va, &lvl);
1148 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1149 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1151 pmap_load_clear(pte);
1152 pmap_invalidate_page(kernel_pmap, va);
1156 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1162 KASSERT((sva & L3_OFFSET) == 0,
1163 ("pmap_kremove_device: Invalid virtual address"));
1164 KASSERT((size & PAGE_MASK) == 0,
1165 ("pmap_kremove_device: Mapping is not page-sized"));
1169 pte = pmap_pte(kernel_pmap, va, &lvl);
1170 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1172 ("Invalid device pagetable level: %d != 3", lvl));
1173 pmap_load_clear(pte);
1178 pmap_invalidate_range(kernel_pmap, sva, va);
1182 * Used to map a range of physical addresses into kernel
1183 * virtual address space.
1185 * The value passed in '*virt' is a suggested virtual address for
1186 * the mapping. Architectures which can support a direct-mapped
1187 * physical to virtual region can return the appropriate address
1188 * within that region, leaving '*virt' unchanged. Other
1189 * architectures should map the pages starting at '*virt' and
1190 * update '*virt' with the first usable address after the mapped
1194 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1196 return PHYS_TO_DMAP(start);
1201 * Add a list of wired pages to the kva
1202 * this routine is only used for temporary
1203 * kernel mappings that do not need to have
1204 * page modification or references recorded.
1205 * Note that old mappings are simply written
1206 * over. The page *must* be wired.
1207 * Note: SMP coherent. Uses a ranged shootdown IPI.
1210 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1213 pt_entry_t *pte, pa;
1219 for (i = 0; i < count; i++) {
1220 pde = pmap_pde(kernel_pmap, va, &lvl);
1221 KASSERT(pde != NULL,
1222 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1224 ("pmap_qenter: Invalid level %d", lvl));
1227 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1228 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1229 if (m->md.pv_memattr == DEVICE_MEMORY)
1231 pte = pmap_l2_to_l3(pde, va);
1232 pmap_load_store(pte, pa);
1236 pmap_invalidate_range(kernel_pmap, sva, va);
1240 * This routine tears out page mappings from the
1241 * kernel -- it is meant only for temporary mappings.
1244 pmap_qremove(vm_offset_t sva, int count)
1250 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1253 while (count-- > 0) {
1254 pte = pmap_pte(kernel_pmap, va, &lvl);
1256 ("Invalid device pagetable level: %d != 3", lvl));
1258 pmap_load_clear(pte);
1263 pmap_invalidate_range(kernel_pmap, sva, va);
1266 /***************************************************
1267 * Page table page management routines.....
1268 ***************************************************/
1269 static __inline void
1270 pmap_free_zero_pages(struct spglist *free)
1274 while ((m = SLIST_FIRST(free)) != NULL) {
1275 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1276 /* Preserve the page's PG_ZERO setting. */
1277 vm_page_free_toq(m);
1282 * Schedule the specified unused page table page to be freed. Specifically,
1283 * add the page to the specified list of pages that will be released to the
1284 * physical memory manager after the TLB has been updated.
1286 static __inline void
1287 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1288 boolean_t set_PG_ZERO)
1292 m->flags |= PG_ZERO;
1294 m->flags &= ~PG_ZERO;
1295 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1299 * Decrements a page table page's wire count, which is used to record the
1300 * number of valid page table entries within the page. If the wire count
1301 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1302 * page table page was unmapped and FALSE otherwise.
1304 static inline boolean_t
1305 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1309 if (m->wire_count == 0) {
1310 _pmap_unwire_l3(pmap, va, m, free);
1317 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1320 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1322 * unmap the page table page
1324 if (m->pindex >= (NUL2E + NUL1E)) {
1328 l0 = pmap_l0(pmap, va);
1329 pmap_load_clear(l0);
1330 } else if (m->pindex >= NUL2E) {
1334 l1 = pmap_l1(pmap, va);
1335 pmap_load_clear(l1);
1340 l2 = pmap_l2(pmap, va);
1341 pmap_load_clear(l2);
1343 pmap_resident_count_dec(pmap, 1);
1344 if (m->pindex < NUL2E) {
1345 /* We just released an l3, unhold the matching l2 */
1346 pd_entry_t *l1, tl1;
1349 l1 = pmap_l1(pmap, va);
1350 tl1 = pmap_load(l1);
1351 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1352 pmap_unwire_l3(pmap, va, l2pg, free);
1353 } else if (m->pindex < (NUL2E + NUL1E)) {
1354 /* We just released an l2, unhold the matching l1 */
1355 pd_entry_t *l0, tl0;
1358 l0 = pmap_l0(pmap, va);
1359 tl0 = pmap_load(l0);
1360 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1361 pmap_unwire_l3(pmap, va, l1pg, free);
1363 pmap_invalidate_page(pmap, va);
1366 * This is a release store so that the ordinary store unmapping
1367 * the page table page is globally performed before TLB shoot-
1370 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
1373 * Put page on a list so that it is released after
1374 * *ALL* TLB shootdown is done
1376 pmap_add_delayed_free_list(m, free, TRUE);
1380 * After removing a page table entry, this routine is used to
1381 * conditionally free the page, and manage the hold/wire counts.
1384 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1385 struct spglist *free)
1389 if (va >= VM_MAXUSER_ADDRESS)
1391 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1392 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1393 return (pmap_unwire_l3(pmap, va, mpte, free));
1397 pmap_pinit0(pmap_t pmap)
1400 PMAP_LOCK_INIT(pmap);
1401 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1402 pmap->pm_l0 = kernel_pmap->pm_l0;
1403 pmap->pm_root.rt_root = 0;
1407 pmap_pinit(pmap_t pmap)
1413 * allocate the l0 page
1415 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1416 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1419 l0phys = VM_PAGE_TO_PHYS(l0pt);
1420 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1422 if ((l0pt->flags & PG_ZERO) == 0)
1423 pagezero(pmap->pm_l0);
1425 pmap->pm_root.rt_root = 0;
1426 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1432 * This routine is called if the desired page table page does not exist.
1434 * If page table page allocation fails, this routine may sleep before
1435 * returning NULL. It sleeps only if a lock pointer was given.
1437 * Note: If a page allocation fails at page table level two or three,
1438 * one or two pages may be held during the wait, only to be released
1439 * afterwards. This conservative approach is easily argued to avoid
1443 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1445 vm_page_t m, l1pg, l2pg;
1447 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1450 * Allocate a page table page.
1452 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1453 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1454 if (lockp != NULL) {
1455 RELEASE_PV_LIST_LOCK(lockp);
1462 * Indicate the need to retry. While waiting, the page table
1463 * page may have been allocated.
1467 if ((m->flags & PG_ZERO) == 0)
1471 * Map the pagetable page into the process address space, if
1472 * it isn't already there.
1475 if (ptepindex >= (NUL2E + NUL1E)) {
1477 vm_pindex_t l0index;
1479 l0index = ptepindex - (NUL2E + NUL1E);
1480 l0 = &pmap->pm_l0[l0index];
1481 pmap_load_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1482 } else if (ptepindex >= NUL2E) {
1483 vm_pindex_t l0index, l1index;
1484 pd_entry_t *l0, *l1;
1487 l1index = ptepindex - NUL2E;
1488 l0index = l1index >> L0_ENTRIES_SHIFT;
1490 l0 = &pmap->pm_l0[l0index];
1491 tl0 = pmap_load(l0);
1493 /* recurse for allocating page dir */
1494 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1497 /* XXX: release mem barrier? */
1498 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1499 vm_page_free_zero(m);
1503 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1507 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1508 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1509 pmap_load_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1511 vm_pindex_t l0index, l1index;
1512 pd_entry_t *l0, *l1, *l2;
1513 pd_entry_t tl0, tl1;
1515 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1516 l0index = l1index >> L0_ENTRIES_SHIFT;
1518 l0 = &pmap->pm_l0[l0index];
1519 tl0 = pmap_load(l0);
1521 /* recurse for allocating page dir */
1522 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1525 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1526 vm_page_free_zero(m);
1529 tl0 = pmap_load(l0);
1530 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1531 l1 = &l1[l1index & Ln_ADDR_MASK];
1533 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1534 l1 = &l1[l1index & Ln_ADDR_MASK];
1535 tl1 = pmap_load(l1);
1537 /* recurse for allocating page dir */
1538 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1541 /* XXX: release mem barrier? */
1542 atomic_subtract_int(
1543 &vm_cnt.v_wire_count, 1);
1544 vm_page_free_zero(m);
1548 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1553 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1554 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1555 pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1558 pmap_resident_count_inc(pmap, 1);
1564 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1566 vm_pindex_t ptepindex;
1567 pd_entry_t *pde, tpde;
1575 * Calculate pagetable page index
1577 ptepindex = pmap_l2_pindex(va);
1580 * Get the page directory entry
1582 pde = pmap_pde(pmap, va, &lvl);
1585 * If the page table page is mapped, we just increment the hold count,
1586 * and activate it. If we get a level 2 pde it will point to a level 3
1594 pte = pmap_l0_to_l1(pde, va);
1595 KASSERT(pmap_load(pte) == 0,
1596 ("pmap_alloc_l3: TODO: l0 superpages"));
1601 pte = pmap_l1_to_l2(pde, va);
1602 KASSERT(pmap_load(pte) == 0,
1603 ("pmap_alloc_l3: TODO: l1 superpages"));
1607 tpde = pmap_load(pde);
1609 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1615 panic("pmap_alloc_l3: Invalid level %d", lvl);
1619 * Here if the pte page isn't mapped, or if it has been deallocated.
1621 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1622 if (m == NULL && lockp != NULL)
1629 /***************************************************
1630 * Pmap allocation/deallocation routines.
1631 ***************************************************/
1634 * Release any resources held by the given physical map.
1635 * Called when a pmap initialized by pmap_pinit is being released.
1636 * Should only be called if the map contains no valid mappings.
1639 pmap_release(pmap_t pmap)
1643 KASSERT(pmap->pm_stats.resident_count == 0,
1644 ("pmap_release: pmap resident count %ld != 0",
1645 pmap->pm_stats.resident_count));
1646 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1647 ("pmap_release: pmap has reserved page table page(s)"));
1649 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1652 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1653 vm_page_free_zero(m);
1657 kvm_size(SYSCTL_HANDLER_ARGS)
1659 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1661 return sysctl_handle_long(oidp, &ksize, 0, req);
1663 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1664 0, 0, kvm_size, "LU", "Size of KVM");
1667 kvm_free(SYSCTL_HANDLER_ARGS)
1669 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1671 return sysctl_handle_long(oidp, &kfree, 0, req);
1673 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1674 0, 0, kvm_free, "LU", "Amount of KVM free");
1677 * grow the number of kernel page table entries, if needed
1680 pmap_growkernel(vm_offset_t addr)
1684 pd_entry_t *l0, *l1, *l2;
1686 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1688 addr = roundup2(addr, L2_SIZE);
1689 if (addr - 1 >= kernel_map->max_offset)
1690 addr = kernel_map->max_offset;
1691 while (kernel_vm_end < addr) {
1692 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1693 KASSERT(pmap_load(l0) != 0,
1694 ("pmap_growkernel: No level 0 kernel entry"));
1696 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1697 if (pmap_load(l1) == 0) {
1698 /* We need a new PDP entry */
1699 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1700 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1701 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1703 panic("pmap_growkernel: no memory to grow kernel");
1704 if ((nkpg->flags & PG_ZERO) == 0)
1705 pmap_zero_page(nkpg);
1706 paddr = VM_PAGE_TO_PHYS(nkpg);
1707 pmap_load_store(l1, paddr | L1_TABLE);
1708 continue; /* try again */
1710 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1711 if ((pmap_load(l2) & ATTR_AF) != 0) {
1712 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1713 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1714 kernel_vm_end = kernel_map->max_offset;
1720 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1721 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1724 panic("pmap_growkernel: no memory to grow kernel");
1725 if ((nkpg->flags & PG_ZERO) == 0)
1726 pmap_zero_page(nkpg);
1727 paddr = VM_PAGE_TO_PHYS(nkpg);
1728 pmap_load_store(l2, paddr | L2_TABLE);
1729 pmap_invalidate_page(kernel_pmap, kernel_vm_end);
1731 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1732 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1733 kernel_vm_end = kernel_map->max_offset;
1740 /***************************************************
1741 * page management routines.
1742 ***************************************************/
1744 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1745 CTASSERT(_NPCM == 3);
1746 CTASSERT(_NPCPV == 168);
1748 static __inline struct pv_chunk *
1749 pv_to_chunk(pv_entry_t pv)
1752 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1755 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1757 #define PC_FREE0 0xfffffffffffffffful
1758 #define PC_FREE1 0xfffffffffffffffful
1759 #define PC_FREE2 0x000000fffffffffful
1761 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1765 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1767 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1768 "Current number of pv entry chunks");
1769 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1770 "Current number of pv entry chunks allocated");
1771 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1772 "Current number of pv entry chunks frees");
1773 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1774 "Number of times tried to get a chunk page but failed.");
1776 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1777 static int pv_entry_spare;
1779 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1780 "Current number of pv entry frees");
1781 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1782 "Current number of pv entry allocs");
1783 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1784 "Current number of pv entries");
1785 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1786 "Current number of spare pv entries");
1791 * We are in a serious low memory condition. Resort to
1792 * drastic measures to free some pages so we can allocate
1793 * another pv entry chunk.
1795 * Returns NULL if PV entries were reclaimed from the specified pmap.
1797 * We do not, however, unmap 2mpages because subsequent accesses will
1798 * allocate per-page pv entries until repromotion occurs, thereby
1799 * exacerbating the shortage of free pv entries.
1802 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1804 struct pch new_tail;
1805 struct pv_chunk *pc;
1806 struct md_page *pvh;
1809 pt_entry_t *pte, tpte;
1813 struct spglist free;
1815 int bit, field, freed, lvl;
1817 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1818 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
1822 TAILQ_INIT(&new_tail);
1823 mtx_lock(&pv_chunks_mutex);
1824 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) {
1825 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1826 mtx_unlock(&pv_chunks_mutex);
1827 if (pmap != pc->pc_pmap) {
1828 if (pmap != NULL && pmap != locked_pmap)
1831 /* Avoid deadlock and lock recursion. */
1832 if (pmap > locked_pmap) {
1833 RELEASE_PV_LIST_LOCK(lockp);
1835 } else if (pmap != locked_pmap &&
1836 !PMAP_TRYLOCK(pmap)) {
1838 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1839 mtx_lock(&pv_chunks_mutex);
1845 * Destroy every non-wired, 4 KB page mapping in the chunk.
1848 for (field = 0; field < _NPCM; field++) {
1849 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1850 inuse != 0; inuse &= ~(1UL << bit)) {
1851 bit = ffsl(inuse) - 1;
1852 pv = &pc->pc_pventry[field * 64 + bit];
1854 pde = pmap_pde(pmap, va, &lvl);
1857 pte = pmap_l2_to_l3(pde, va);
1858 tpte = pmap_load(pte);
1859 if ((tpte & ATTR_SW_WIRED) != 0)
1861 tpte = pmap_load_clear(pte);
1862 pmap_invalidate_page(pmap, va);
1863 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
1864 if (pmap_page_dirty(tpte))
1866 if ((tpte & ATTR_AF) != 0)
1867 vm_page_aflag_set(m, PGA_REFERENCED);
1868 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1869 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
1871 if (TAILQ_EMPTY(&m->md.pv_list) &&
1872 (m->flags & PG_FICTITIOUS) == 0) {
1873 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
1874 if (TAILQ_EMPTY(&pvh->pv_list)) {
1875 vm_page_aflag_clear(m,
1879 pc->pc_map[field] |= 1UL << bit;
1880 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
1885 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1886 mtx_lock(&pv_chunks_mutex);
1889 /* Every freed mapping is for a 4 KB page. */
1890 pmap_resident_count_dec(pmap, freed);
1891 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
1892 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
1893 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
1894 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1895 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
1896 pc->pc_map[2] == PC_FREE2) {
1897 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1898 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1899 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1900 /* Entire chunk is free; return it. */
1901 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1902 dump_drop_page(m_pc->phys_addr);
1903 mtx_lock(&pv_chunks_mutex);
1906 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1907 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1908 mtx_lock(&pv_chunks_mutex);
1909 /* One freed pv entry in locked_pmap is sufficient. */
1910 if (pmap == locked_pmap)
1913 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
1914 mtx_unlock(&pv_chunks_mutex);
1915 if (pmap != NULL && pmap != locked_pmap)
1917 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
1918 m_pc = SLIST_FIRST(&free);
1919 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
1920 /* Recycle a freed page table page. */
1921 m_pc->wire_count = 1;
1922 atomic_add_int(&vm_cnt.v_wire_count, 1);
1924 pmap_free_zero_pages(&free);
1929 * free the pv_entry back to the free list
1932 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1934 struct pv_chunk *pc;
1935 int idx, field, bit;
1937 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1938 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
1939 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
1940 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
1941 pc = pv_to_chunk(pv);
1942 idx = pv - &pc->pc_pventry[0];
1945 pc->pc_map[field] |= 1ul << bit;
1946 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
1947 pc->pc_map[2] != PC_FREE2) {
1948 /* 98% of the time, pc is already at the head of the list. */
1949 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
1950 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1951 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1955 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1960 free_pv_chunk(struct pv_chunk *pc)
1964 mtx_lock(&pv_chunks_mutex);
1965 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1966 mtx_unlock(&pv_chunks_mutex);
1967 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1968 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1969 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1970 /* entire chunk is free, return it */
1971 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1972 dump_drop_page(m->phys_addr);
1973 vm_page_unwire(m, PQ_NONE);
1978 * Returns a new PV entry, allocating a new PV chunk from the system when
1979 * needed. If this PV chunk allocation fails and a PV list lock pointer was
1980 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
1983 * The given PV list lock may be released.
1986 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
1990 struct pv_chunk *pc;
1993 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1994 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
1996 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1998 for (field = 0; field < _NPCM; field++) {
1999 if (pc->pc_map[field]) {
2000 bit = ffsl(pc->pc_map[field]) - 1;
2004 if (field < _NPCM) {
2005 pv = &pc->pc_pventry[field * 64 + bit];
2006 pc->pc_map[field] &= ~(1ul << bit);
2007 /* If this was the last item, move it to tail */
2008 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2009 pc->pc_map[2] == 0) {
2010 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2011 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2014 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2015 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2019 /* No free items, allocate another chunk */
2020 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2023 if (lockp == NULL) {
2024 PV_STAT(pc_chunk_tryfail++);
2027 m = reclaim_pv_chunk(pmap, lockp);
2031 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2032 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2033 dump_add_page(m->phys_addr);
2034 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2036 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2037 pc->pc_map[1] = PC_FREE1;
2038 pc->pc_map[2] = PC_FREE2;
2039 mtx_lock(&pv_chunks_mutex);
2040 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2041 mtx_unlock(&pv_chunks_mutex);
2042 pv = &pc->pc_pventry[0];
2043 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2044 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2045 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2050 * Ensure that the number of spare PV entries in the specified pmap meets or
2051 * exceeds the given count, "needed".
2053 * The given PV list lock may be released.
2056 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2058 struct pch new_tail;
2059 struct pv_chunk *pc;
2063 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2064 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2067 * Newly allocated PV chunks must be stored in a private list until
2068 * the required number of PV chunks have been allocated. Otherwise,
2069 * reclaim_pv_chunk() could recycle one of these chunks. In
2070 * contrast, these chunks must be added to the pmap upon allocation.
2072 TAILQ_INIT(&new_tail);
2075 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2076 bit_count((bitstr_t *)pc->pc_map, 0,
2077 sizeof(pc->pc_map) * NBBY, &free);
2081 if (avail >= needed)
2084 for (; avail < needed; avail += _NPCPV) {
2085 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2088 m = reclaim_pv_chunk(pmap, lockp);
2092 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2093 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2094 dump_add_page(m->phys_addr);
2095 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2097 pc->pc_map[0] = PC_FREE0;
2098 pc->pc_map[1] = PC_FREE1;
2099 pc->pc_map[2] = PC_FREE2;
2100 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2101 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2102 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2104 if (!TAILQ_EMPTY(&new_tail)) {
2105 mtx_lock(&pv_chunks_mutex);
2106 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2107 mtx_unlock(&pv_chunks_mutex);
2112 * First find and then remove the pv entry for the specified pmap and virtual
2113 * address from the specified pv list. Returns the pv entry if found and NULL
2114 * otherwise. This operation can be performed on pv lists for either 4KB or
2115 * 2MB page mappings.
2117 static __inline pv_entry_t
2118 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2122 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2123 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2124 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2133 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2134 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2135 * entries for each of the 4KB page mappings.
2138 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2139 struct rwlock **lockp)
2141 struct md_page *pvh;
2142 struct pv_chunk *pc;
2144 vm_offset_t va_last;
2148 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2149 KASSERT((pa & L2_OFFSET) == 0,
2150 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2151 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2154 * Transfer the 2mpage's pv entry for this mapping to the first
2155 * page's pv list. Once this transfer begins, the pv list lock
2156 * must not be released until the last pv entry is reinstantiated.
2158 pvh = pa_to_pvh(pa);
2159 va = va & ~L2_OFFSET;
2160 pv = pmap_pvh_remove(pvh, pmap, va);
2161 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2162 m = PHYS_TO_VM_PAGE(pa);
2163 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2165 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2166 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2167 va_last = va + L2_SIZE - PAGE_SIZE;
2169 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2170 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2171 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2172 for (field = 0; field < _NPCM; field++) {
2173 while (pc->pc_map[field]) {
2174 bit = ffsl(pc->pc_map[field]) - 1;
2175 pc->pc_map[field] &= ~(1ul << bit);
2176 pv = &pc->pc_pventry[field * 64 + bit];
2180 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2181 ("pmap_pv_demote_l2: page %p is not managed", m));
2182 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2188 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2189 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2192 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2193 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2194 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2196 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2197 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2201 * First find and then destroy the pv entry for the specified pmap and virtual
2202 * address. This operation can be performed on pv lists for either 4KB or 2MB
2206 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2210 pv = pmap_pvh_remove(pvh, pmap, va);
2211 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2212 free_pv_entry(pmap, pv);
2216 * Conditionally create the PV entry for a 4KB page mapping if the required
2217 * memory can be allocated without resorting to reclamation.
2220 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2221 struct rwlock **lockp)
2225 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2226 /* Pass NULL instead of the lock pointer to disable reclamation. */
2227 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2229 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2230 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2238 * pmap_remove_l2: do the things to unmap a level 2 superpage in a process
2241 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2242 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2244 struct md_page *pvh;
2246 vm_offset_t eva, va;
2249 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2250 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2251 old_l2 = pmap_load_clear(l2);
2252 pmap_invalidate_range(pmap, sva, sva + L2_SIZE);
2253 if (old_l2 & ATTR_SW_WIRED)
2254 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2255 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2256 if (old_l2 & ATTR_SW_MANAGED) {
2257 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2258 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2259 pmap_pvh_free(pvh, pmap, sva);
2260 eva = sva + L2_SIZE;
2261 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2262 va < eva; va += PAGE_SIZE, m++) {
2263 if (pmap_page_dirty(old_l2))
2265 if (old_l2 & ATTR_AF)
2266 vm_page_aflag_set(m, PGA_REFERENCED);
2267 if (TAILQ_EMPTY(&m->md.pv_list) &&
2268 TAILQ_EMPTY(&pvh->pv_list))
2269 vm_page_aflag_clear(m, PGA_WRITEABLE);
2272 KASSERT(pmap != kernel_pmap,
2273 ("Attempting to remove an l2 kernel page"));
2274 ml3 = pmap_remove_pt_page(pmap, sva);
2276 pmap_resident_count_dec(pmap, 1);
2277 KASSERT(ml3->wire_count == NL3PG,
2278 ("pmap_remove_pages: l3 page wire count error"));
2279 ml3->wire_count = 0;
2280 pmap_add_delayed_free_list(ml3, free, FALSE);
2281 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2283 return (pmap_unuse_pt(pmap, sva, l1e, free));
2287 * pmap_remove_l3: do the things to unmap a page in a process
2290 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2291 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2293 struct md_page *pvh;
2297 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2298 old_l3 = pmap_load_clear(l3);
2299 pmap_invalidate_page(pmap, va);
2300 if (old_l3 & ATTR_SW_WIRED)
2301 pmap->pm_stats.wired_count -= 1;
2302 pmap_resident_count_dec(pmap, 1);
2303 if (old_l3 & ATTR_SW_MANAGED) {
2304 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2305 if (pmap_page_dirty(old_l3))
2307 if (old_l3 & ATTR_AF)
2308 vm_page_aflag_set(m, PGA_REFERENCED);
2309 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2310 pmap_pvh_free(&m->md, pmap, va);
2311 if (TAILQ_EMPTY(&m->md.pv_list) &&
2312 (m->flags & PG_FICTITIOUS) == 0) {
2313 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2314 if (TAILQ_EMPTY(&pvh->pv_list))
2315 vm_page_aflag_clear(m, PGA_WRITEABLE);
2318 return (pmap_unuse_pt(pmap, va, l2e, free));
2322 * Remove the given range of addresses from the specified map.
2324 * It is assumed that the start and end are properly
2325 * rounded to the page size.
2328 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2330 struct rwlock *lock;
2331 vm_offset_t va, va_next;
2332 pd_entry_t *l0, *l1, *l2;
2333 pt_entry_t l3_paddr, *l3;
2334 struct spglist free;
2337 * Perform an unsynchronized read. This is, however, safe.
2339 if (pmap->pm_stats.resident_count == 0)
2347 for (; sva < eva; sva = va_next) {
2349 if (pmap->pm_stats.resident_count == 0)
2352 l0 = pmap_l0(pmap, sva);
2353 if (pmap_load(l0) == 0) {
2354 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2360 l1 = pmap_l0_to_l1(l0, sva);
2361 if (pmap_load(l1) == 0) {
2362 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2369 * Calculate index for next page table.
2371 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2375 l2 = pmap_l1_to_l2(l1, sva);
2379 l3_paddr = pmap_load(l2);
2381 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2382 if (sva + L2_SIZE == va_next && eva >= va_next) {
2383 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2386 } else if (pmap_demote_l2_locked(pmap, l2,
2387 sva &~L2_OFFSET, &lock) == NULL)
2389 l3_paddr = pmap_load(l2);
2393 * Weed out invalid mappings.
2395 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2399 * Limit our scan to either the end of the va represented
2400 * by the current page table page, or to the end of the
2401 * range being removed.
2407 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2410 panic("l3 == NULL");
2411 if (pmap_load(l3) == 0) {
2412 if (va != va_next) {
2413 pmap_invalidate_range(pmap, va, sva);
2420 if (pmap_remove_l3(pmap, l3, sva, l3_paddr, &free,
2427 pmap_invalidate_range(pmap, va, sva);
2432 pmap_free_zero_pages(&free);
2436 * Routine: pmap_remove_all
2438 * Removes this physical page from
2439 * all physical maps in which it resides.
2440 * Reflects back modify bits to the pager.
2443 * Original versions of this routine were very
2444 * inefficient because they iteratively called
2445 * pmap_remove (slow...)
2449 pmap_remove_all(vm_page_t m)
2451 struct md_page *pvh;
2454 struct rwlock *lock;
2455 pd_entry_t *pde, tpde;
2456 pt_entry_t *pte, tpte;
2458 struct spglist free;
2459 int lvl, pvh_gen, md_gen;
2461 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2462 ("pmap_remove_all: page %p is not managed", m));
2464 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2465 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2466 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2469 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2471 if (!PMAP_TRYLOCK(pmap)) {
2472 pvh_gen = pvh->pv_gen;
2476 if (pvh_gen != pvh->pv_gen) {
2483 pte = pmap_pte(pmap, va, &lvl);
2484 KASSERT(pte != NULL,
2485 ("pmap_remove_all: no page table entry found"));
2487 ("pmap_remove_all: invalid pte level %d", lvl));
2489 pmap_demote_l2_locked(pmap, pte, va, &lock);
2492 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2494 if (!PMAP_TRYLOCK(pmap)) {
2495 pvh_gen = pvh->pv_gen;
2496 md_gen = m->md.pv_gen;
2500 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2506 pmap_resident_count_dec(pmap, 1);
2508 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2509 KASSERT(pde != NULL,
2510 ("pmap_remove_all: no page directory entry found"));
2512 ("pmap_remove_all: invalid pde level %d", lvl));
2513 tpde = pmap_load(pde);
2515 pte = pmap_l2_to_l3(pde, pv->pv_va);
2516 tpte = pmap_load(pte);
2517 pmap_load_clear(pte);
2518 pmap_invalidate_page(pmap, pv->pv_va);
2519 if (tpte & ATTR_SW_WIRED)
2520 pmap->pm_stats.wired_count--;
2521 if ((tpte & ATTR_AF) != 0)
2522 vm_page_aflag_set(m, PGA_REFERENCED);
2525 * Update the vm_page_t clean and reference bits.
2527 if (pmap_page_dirty(tpte))
2529 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2530 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2532 free_pv_entry(pmap, pv);
2535 vm_page_aflag_clear(m, PGA_WRITEABLE);
2537 pmap_free_zero_pages(&free);
2541 * Set the physical protection on the
2542 * specified range of this map as requested.
2545 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2547 vm_offset_t va, va_next;
2548 pd_entry_t *l0, *l1, *l2;
2549 pt_entry_t *l3p, l3, nbits;
2551 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
2552 if (prot == VM_PROT_NONE) {
2553 pmap_remove(pmap, sva, eva);
2557 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
2558 (VM_PROT_WRITE | VM_PROT_EXECUTE))
2562 for (; sva < eva; sva = va_next) {
2564 l0 = pmap_l0(pmap, sva);
2565 if (pmap_load(l0) == 0) {
2566 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2572 l1 = pmap_l0_to_l1(l0, sva);
2573 if (pmap_load(l1) == 0) {
2574 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2580 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2584 l2 = pmap_l1_to_l2(l1, sva);
2585 if (pmap_load(l2) == 0)
2588 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
2589 l3p = pmap_demote_l2(pmap, l2, sva);
2593 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
2594 ("pmap_protect: Invalid L2 entry after demotion"));
2600 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2602 l3 = pmap_load(l3p);
2603 if (!pmap_l3_valid(l3))
2607 if ((prot & VM_PROT_WRITE) == 0) {
2608 if ((l3 & ATTR_SW_MANAGED) &&
2609 pmap_page_dirty(l3)) {
2610 vm_page_dirty(PHYS_TO_VM_PAGE(l3 &
2613 nbits |= ATTR_AP(ATTR_AP_RO);
2615 if ((prot & VM_PROT_EXECUTE) == 0)
2618 pmap_set(l3p, nbits);
2619 /* XXX: Use pmap_invalidate_range */
2620 pmap_invalidate_page(pmap, sva);
2627 * Inserts the specified page table page into the specified pmap's collection
2628 * of idle page table pages. Each of a pmap's page table pages is responsible
2629 * for mapping a distinct range of virtual addresses. The pmap's collection is
2630 * ordered by this virtual address range.
2633 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2636 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2637 return (vm_radix_insert(&pmap->pm_root, mpte));
2641 * Removes the page table page mapping the specified virtual address from the
2642 * specified pmap's collection of idle page table pages, and returns it.
2643 * Otherwise, returns NULL if there is no page table page corresponding to the
2644 * specified virtual address.
2646 static __inline vm_page_t
2647 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2650 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2651 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
2655 * Performs a break-before-make update of a pmap entry. This is needed when
2656 * either promoting or demoting pages to ensure the TLB doesn't get into an
2657 * inconsistent state.
2660 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
2661 vm_offset_t va, vm_size_t size)
2665 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2668 * Ensure we don't get switched out with the page table in an
2669 * inconsistent state. We also need to ensure no interrupts fire
2670 * as they may make use of an address we are about to invalidate.
2672 intr = intr_disable();
2675 /* Clear the old mapping */
2676 pmap_load_clear(pte);
2677 pmap_invalidate_range_nopin(pmap, va, va + size);
2679 /* Create the new mapping */
2680 pmap_load_store(pte, newpte);
2686 #if VM_NRESERVLEVEL > 0
2688 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
2689 * replace the many pv entries for the 4KB page mappings by a single pv entry
2690 * for the 2MB page mapping.
2693 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2694 struct rwlock **lockp)
2696 struct md_page *pvh;
2698 vm_offset_t va_last;
2701 KASSERT((pa & L2_OFFSET) == 0,
2702 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
2703 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2706 * Transfer the first page's pv entry for this mapping to the 2mpage's
2707 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
2708 * a transfer avoids the possibility that get_pv_entry() calls
2709 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
2710 * mappings that is being promoted.
2712 m = PHYS_TO_VM_PAGE(pa);
2713 va = va & ~L2_OFFSET;
2714 pv = pmap_pvh_remove(&m->md, pmap, va);
2715 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
2716 pvh = pa_to_pvh(pa);
2717 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2719 /* Free the remaining NPTEPG - 1 pv entries. */
2720 va_last = va + L2_SIZE - PAGE_SIZE;
2724 pmap_pvh_free(&m->md, pmap, va);
2725 } while (va < va_last);
2729 * Tries to promote the 512, contiguous 4KB page mappings that are within a
2730 * single level 2 table entry to a single 2MB page mapping. For promotion
2731 * to occur, two conditions must be met: (1) the 4KB page mappings must map
2732 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
2733 * identical characteristics.
2736 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
2737 struct rwlock **lockp)
2739 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
2743 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2745 sva = va & ~L2_OFFSET;
2746 firstl3 = pmap_l2_to_l3(l2, sva);
2747 newl2 = pmap_load(firstl3);
2749 /* Check the alingment is valid */
2750 if (((newl2 & ~ATTR_MASK) & L2_OFFSET) != 0) {
2751 atomic_add_long(&pmap_l2_p_failures, 1);
2752 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2753 " in pmap %p", va, pmap);
2757 pa = newl2 + L2_SIZE - PAGE_SIZE;
2758 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
2759 oldl3 = pmap_load(l3);
2761 atomic_add_long(&pmap_l2_p_failures, 1);
2762 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2763 " in pmap %p", va, pmap);
2770 * Save the page table page in its current state until the L2
2771 * mapping the superpage is demoted by pmap_demote_l2() or
2772 * destroyed by pmap_remove_l3().
2774 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
2775 KASSERT(mpte >= vm_page_array &&
2776 mpte < &vm_page_array[vm_page_array_size],
2777 ("pmap_promote_l2: page table page is out of range"));
2778 KASSERT(mpte->pindex == pmap_l2_pindex(va),
2779 ("pmap_promote_l2: page table page's pindex is wrong"));
2780 if (pmap_insert_pt_page(pmap, mpte)) {
2781 atomic_add_long(&pmap_l2_p_failures, 1);
2783 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
2788 if ((newl2 & ATTR_SW_MANAGED) != 0)
2789 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
2791 newl2 &= ~ATTR_DESCR_MASK;
2794 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
2796 atomic_add_long(&pmap_l2_promotions, 1);
2797 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
2800 #endif /* VM_NRESERVLEVEL > 0 */
2803 * Insert the given physical page (p) at
2804 * the specified virtual address (v) in the
2805 * target physical map with the protection requested.
2807 * If specified, the page will be wired down, meaning
2808 * that the related pte can not be reclaimed.
2810 * NB: This is the only routine which MAY NOT lazy-evaluate
2811 * or lose information. That is, this routine must actually
2812 * insert this page into the given map NOW.
2815 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2816 u_int flags, int8_t psind __unused)
2818 struct rwlock *lock;
2820 pt_entry_t new_l3, orig_l3;
2821 pt_entry_t *l2, *l3;
2823 vm_paddr_t opa, pa, l1_pa, l2_pa, l3_pa;
2824 vm_page_t mpte, om, l1_m, l2_m, l3_m;
2828 va = trunc_page(va);
2829 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2830 VM_OBJECT_ASSERT_LOCKED(m->object);
2831 pa = VM_PAGE_TO_PHYS(m);
2832 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
2834 if ((prot & VM_PROT_WRITE) == 0)
2835 new_l3 |= ATTR_AP(ATTR_AP_RO);
2836 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
2838 if ((flags & PMAP_ENTER_WIRED) != 0)
2839 new_l3 |= ATTR_SW_WIRED;
2840 if (va < VM_MAXUSER_ADDRESS)
2841 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
2843 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
2850 pde = pmap_pde(pmap, va, &lvl);
2851 if (pde != NULL && lvl == 1) {
2852 l2 = pmap_l1_to_l2(pde, va);
2853 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
2854 (l3 = pmap_demote_l2_locked(pmap, l2, va & ~L2_OFFSET,
2856 l3 = &l3[pmap_l3_index(va)];
2857 if (va < VM_MAXUSER_ADDRESS) {
2858 mpte = PHYS_TO_VM_PAGE(
2859 pmap_load(l2) & ~ATTR_MASK);
2866 if (va < VM_MAXUSER_ADDRESS) {
2867 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
2868 mpte = pmap_alloc_l3(pmap, va, nosleep ? NULL : &lock);
2869 if (mpte == NULL && nosleep) {
2870 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
2874 return (KERN_RESOURCE_SHORTAGE);
2876 pde = pmap_pde(pmap, va, &lvl);
2877 KASSERT(pde != NULL,
2878 ("pmap_enter: Invalid page entry, va: 0x%lx", va));
2880 ("pmap_enter: Invalid level %d", lvl));
2882 l3 = pmap_l2_to_l3(pde, va);
2885 * If we get a level 2 pde it must point to a level 3 entry
2886 * otherwise we will need to create the intermediate tables
2892 /* Get the l0 pde to update */
2893 pde = pmap_l0(pmap, va);
2894 KASSERT(pde != NULL, ("..."));
2896 l1_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2897 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2900 panic("pmap_enter: l1 pte_m == NULL");
2901 if ((l1_m->flags & PG_ZERO) == 0)
2902 pmap_zero_page(l1_m);
2904 l1_pa = VM_PAGE_TO_PHYS(l1_m);
2905 pmap_load_store(pde, l1_pa | L0_TABLE);
2908 /* Get the l1 pde to update */
2909 pde = pmap_l1_to_l2(pde, va);
2910 KASSERT(pde != NULL, ("..."));
2912 l2_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2913 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2916 panic("pmap_enter: l2 pte_m == NULL");
2917 if ((l2_m->flags & PG_ZERO) == 0)
2918 pmap_zero_page(l2_m);
2920 l2_pa = VM_PAGE_TO_PHYS(l2_m);
2921 pmap_load_store(pde, l2_pa | L1_TABLE);
2924 /* Get the l2 pde to update */
2925 pde = pmap_l1_to_l2(pde, va);
2927 l3_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2928 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2931 panic("pmap_enter: l3 pte_m == NULL");
2932 if ((l3_m->flags & PG_ZERO) == 0)
2933 pmap_zero_page(l3_m);
2935 l3_pa = VM_PAGE_TO_PHYS(l3_m);
2936 pmap_load_store(pde, l3_pa | L2_TABLE);
2940 l3 = pmap_l2_to_l3(pde, va);
2941 pmap_invalidate_page(pmap, va);
2946 orig_l3 = pmap_load(l3);
2947 opa = orig_l3 & ~ATTR_MASK;
2950 * Is the specified virtual address already mapped?
2952 if (pmap_l3_valid(orig_l3)) {
2954 * Wiring change, just update stats. We don't worry about
2955 * wiring PT pages as they remain resident as long as there
2956 * are valid mappings in them. Hence, if a user page is wired,
2957 * the PT page will be also.
2959 if ((flags & PMAP_ENTER_WIRED) != 0 &&
2960 (orig_l3 & ATTR_SW_WIRED) == 0)
2961 pmap->pm_stats.wired_count++;
2962 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
2963 (orig_l3 & ATTR_SW_WIRED) != 0)
2964 pmap->pm_stats.wired_count--;
2967 * Remove the extra PT page reference.
2971 KASSERT(mpte->wire_count > 0,
2972 ("pmap_enter: missing reference to page table page,"
2977 * Has the physical page changed?
2981 * No, might be a protection or wiring change.
2983 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
2984 new_l3 |= ATTR_SW_MANAGED;
2985 if ((new_l3 & ATTR_AP(ATTR_AP_RW)) ==
2986 ATTR_AP(ATTR_AP_RW)) {
2987 vm_page_aflag_set(m, PGA_WRITEABLE);
2994 * Increment the counters.
2996 if ((new_l3 & ATTR_SW_WIRED) != 0)
2997 pmap->pm_stats.wired_count++;
2998 pmap_resident_count_inc(pmap, 1);
3001 * Enter on the PV list if part of our managed memory.
3003 if ((m->oflags & VPO_UNMANAGED) == 0) {
3004 new_l3 |= ATTR_SW_MANAGED;
3005 pv = get_pv_entry(pmap, &lock);
3007 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3008 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3010 if ((new_l3 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3011 vm_page_aflag_set(m, PGA_WRITEABLE);
3015 * Update the L3 entry.
3019 orig_l3 = pmap_load(l3);
3020 opa = orig_l3 & ~ATTR_MASK;
3023 pmap_update_entry(pmap, l3, new_l3, va, PAGE_SIZE);
3024 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3025 om = PHYS_TO_VM_PAGE(opa);
3026 if (pmap_page_dirty(orig_l3))
3028 if ((orig_l3 & ATTR_AF) != 0)
3029 vm_page_aflag_set(om, PGA_REFERENCED);
3030 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3031 pmap_pvh_free(&om->md, pmap, va);
3032 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3033 TAILQ_EMPTY(&om->md.pv_list) &&
3034 ((om->flags & PG_FICTITIOUS) != 0 ||
3035 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3036 vm_page_aflag_clear(om, PGA_WRITEABLE);
3039 pmap_load_store(l3, new_l3);
3040 pmap_invalidate_page(pmap, va);
3041 if (pmap_page_dirty(orig_l3) &&
3042 (orig_l3 & ATTR_SW_MANAGED) != 0)
3046 pmap_load_store(l3, new_l3);
3049 pmap_invalidate_page(pmap, va);
3051 if (pmap != pmap_kernel()) {
3052 if (pmap == &curproc->p_vmspace->vm_pmap &&
3053 (prot & VM_PROT_EXECUTE) != 0)
3054 cpu_icache_sync_range(va, PAGE_SIZE);
3056 #if VM_NRESERVLEVEL > 0
3057 if ((mpte == NULL || mpte->wire_count == NL3PG) &&
3058 pmap_superpages_enabled() &&
3059 (m->flags & PG_FICTITIOUS) == 0 &&
3060 vm_reserv_level_iffullpop(m) == 0) {
3061 pmap_promote_l2(pmap, pde, va, &lock);
3069 return (KERN_SUCCESS);
3073 * Maps a sequence of resident pages belonging to the same object.
3074 * The sequence begins with the given page m_start. This page is
3075 * mapped at the given virtual address start. Each subsequent page is
3076 * mapped at a virtual address that is offset from start by the same
3077 * amount as the page is offset from m_start within the object. The
3078 * last page in the sequence is the page with the largest offset from
3079 * m_start that can be mapped at a virtual address less than the given
3080 * virtual address end. Not every virtual page between start and end
3081 * is mapped; only those for which a resident page exists with the
3082 * corresponding offset from m_start are mapped.
3085 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3086 vm_page_t m_start, vm_prot_t prot)
3088 struct rwlock *lock;
3091 vm_pindex_t diff, psize;
3093 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3095 psize = atop(end - start);
3100 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3101 va = start + ptoa(diff);
3102 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte, &lock);
3103 m = TAILQ_NEXT(m, listq);
3111 * this code makes some *MAJOR* assumptions:
3112 * 1. Current pmap & pmap exists.
3115 * 4. No page table pages.
3116 * but is *MUCH* faster than pmap_enter...
3120 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3122 struct rwlock *lock;
3126 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3133 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3134 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3136 struct spglist free;
3138 pt_entry_t *l2, *l3;
3142 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3143 (m->oflags & VPO_UNMANAGED) != 0,
3144 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3145 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3147 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3149 * In the case that a page table page is not
3150 * resident, we are creating it here.
3152 if (va < VM_MAXUSER_ADDRESS) {
3153 vm_pindex_t l2pindex;
3156 * Calculate pagetable page index
3158 l2pindex = pmap_l2_pindex(va);
3159 if (mpte && (mpte->pindex == l2pindex)) {
3165 pde = pmap_pde(pmap, va, &lvl);
3168 * If the page table page is mapped, we just increment
3169 * the hold count, and activate it. Otherwise, we
3170 * attempt to allocate a page table page. If this
3171 * attempt fails, we don't retry. Instead, we give up.
3174 l2 = pmap_l1_to_l2(pde, va);
3175 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3179 if (lvl == 2 && pmap_load(pde) != 0) {
3181 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3185 * Pass NULL instead of the PV list lock
3186 * pointer, because we don't intend to sleep.
3188 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3193 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3194 l3 = &l3[pmap_l3_index(va)];
3197 pde = pmap_pde(kernel_pmap, va, &lvl);
3198 KASSERT(pde != NULL,
3199 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3202 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3203 l3 = pmap_l2_to_l3(pde, va);
3206 if (pmap_load(l3) != 0) {
3215 * Enter on the PV list if part of our managed memory.
3217 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3218 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3221 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
3222 pmap_invalidate_page(pmap, va);
3223 pmap_free_zero_pages(&free);
3231 * Increment counters
3233 pmap_resident_count_inc(pmap, 1);
3235 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3236 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3237 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3239 else if (va < VM_MAXUSER_ADDRESS)
3243 * Now validate mapping with RO protection
3245 if ((m->oflags & VPO_UNMANAGED) == 0)
3246 pa |= ATTR_SW_MANAGED;
3247 pmap_load_store(l3, pa);
3248 pmap_invalidate_page(pmap, va);
3253 * This code maps large physical mmap regions into the
3254 * processor address space. Note that some shortcuts
3255 * are taken, but the code works.
3258 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3259 vm_pindex_t pindex, vm_size_t size)
3262 VM_OBJECT_ASSERT_WLOCKED(object);
3263 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3264 ("pmap_object_init_pt: non-device object"));
3268 * Clear the wired attribute from the mappings for the specified range of
3269 * addresses in the given pmap. Every valid mapping within that range
3270 * must have the wired attribute set. In contrast, invalid mappings
3271 * cannot have the wired attribute set, so they are ignored.
3273 * The wired attribute of the page table entry is not a hardware feature,
3274 * so there is no need to invalidate any TLB entries.
3277 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3279 vm_offset_t va_next;
3280 pd_entry_t *l0, *l1, *l2;
3284 for (; sva < eva; sva = va_next) {
3285 l0 = pmap_l0(pmap, sva);
3286 if (pmap_load(l0) == 0) {
3287 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3293 l1 = pmap_l0_to_l1(l0, sva);
3294 if (pmap_load(l1) == 0) {
3295 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3301 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3305 l2 = pmap_l1_to_l2(l1, sva);
3306 if (pmap_load(l2) == 0)
3309 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3310 l3 = pmap_demote_l2(pmap, l2, sva);
3314 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3315 ("pmap_unwire: Invalid l2 entry after demotion"));
3319 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3321 if (pmap_load(l3) == 0)
3323 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
3324 panic("pmap_unwire: l3 %#jx is missing "
3325 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
3328 * PG_W must be cleared atomically. Although the pmap
3329 * lock synchronizes access to PG_W, another processor
3330 * could be setting PG_M and/or PG_A concurrently.
3332 atomic_clear_long(l3, ATTR_SW_WIRED);
3333 pmap->pm_stats.wired_count--;
3340 * Copy the range specified by src_addr/len
3341 * from the source map to the range dst_addr/len
3342 * in the destination map.
3344 * This routine is only advisory and need not do anything.
3348 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3349 vm_offset_t src_addr)
3354 * pmap_zero_page zeros the specified hardware page by mapping
3355 * the page into KVM and using bzero to clear its contents.
3358 pmap_zero_page(vm_page_t m)
3360 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3362 pagezero((void *)va);
3366 * pmap_zero_page_area zeros the specified hardware page by mapping
3367 * the page into KVM and using bzero to clear its contents.
3369 * off and size may not cover an area beyond a single hardware page.
3372 pmap_zero_page_area(vm_page_t m, int off, int size)
3374 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3376 if (off == 0 && size == PAGE_SIZE)
3377 pagezero((void *)va);
3379 bzero((char *)va + off, size);
3383 * pmap_copy_page copies the specified (machine independent)
3384 * page by mapping the page into virtual memory and using
3385 * bcopy to copy the page, one machine dependent page at a
3389 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
3391 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
3392 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
3394 pagecopy((void *)src, (void *)dst);
3397 int unmapped_buf_allowed = 1;
3400 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
3401 vm_offset_t b_offset, int xfersize)
3405 vm_paddr_t p_a, p_b;
3406 vm_offset_t a_pg_offset, b_pg_offset;
3409 while (xfersize > 0) {
3410 a_pg_offset = a_offset & PAGE_MASK;
3411 m_a = ma[a_offset >> PAGE_SHIFT];
3412 p_a = m_a->phys_addr;
3413 b_pg_offset = b_offset & PAGE_MASK;
3414 m_b = mb[b_offset >> PAGE_SHIFT];
3415 p_b = m_b->phys_addr;
3416 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
3417 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
3418 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
3419 panic("!DMAP a %lx", p_a);
3421 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
3423 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
3424 panic("!DMAP b %lx", p_b);
3426 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
3428 bcopy(a_cp, b_cp, cnt);
3436 pmap_quick_enter_page(vm_page_t m)
3439 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
3443 pmap_quick_remove_page(vm_offset_t addr)
3448 * Returns true if the pmap's pv is one of the first
3449 * 16 pvs linked to from this page. This count may
3450 * be changed upwards or downwards in the future; it
3451 * is only necessary that true be returned for a small
3452 * subset of pmaps for proper page aging.
3455 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3457 struct md_page *pvh;
3458 struct rwlock *lock;
3463 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3464 ("pmap_page_exists_quick: page %p is not managed", m));
3466 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3468 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3469 if (PV_PMAP(pv) == pmap) {
3477 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
3478 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3479 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3480 if (PV_PMAP(pv) == pmap) {
3494 * pmap_page_wired_mappings:
3496 * Return the number of managed mappings to the given physical page
3500 pmap_page_wired_mappings(vm_page_t m)
3502 struct rwlock *lock;
3503 struct md_page *pvh;
3507 int count, lvl, md_gen, pvh_gen;
3509 if ((m->oflags & VPO_UNMANAGED) != 0)
3511 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3515 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3517 if (!PMAP_TRYLOCK(pmap)) {
3518 md_gen = m->md.pv_gen;
3522 if (md_gen != m->md.pv_gen) {
3527 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3528 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3532 if ((m->flags & PG_FICTITIOUS) == 0) {
3533 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3534 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3536 if (!PMAP_TRYLOCK(pmap)) {
3537 md_gen = m->md.pv_gen;
3538 pvh_gen = pvh->pv_gen;
3542 if (md_gen != m->md.pv_gen ||
3543 pvh_gen != pvh->pv_gen) {
3548 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3550 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3560 * Destroy all managed, non-wired mappings in the given user-space
3561 * pmap. This pmap cannot be active on any processor besides the
3564 * This function cannot be applied to the kernel pmap. Moreover, it
3565 * is not intended for general use. It is only to be used during
3566 * process termination. Consequently, it can be implemented in ways
3567 * that make it faster than pmap_remove(). First, it can more quickly
3568 * destroy mappings by iterating over the pmap's collection of PV
3569 * entries, rather than searching the page table. Second, it doesn't
3570 * have to test and clear the page table entries atomically, because
3571 * no processor is currently accessing the user address space. In
3572 * particular, a page table entry's dirty bit won't change state once
3573 * this function starts.
3576 pmap_remove_pages(pmap_t pmap)
3579 pt_entry_t *pte, tpte;
3580 struct spglist free;
3581 vm_page_t m, ml3, mt;
3583 struct md_page *pvh;
3584 struct pv_chunk *pc, *npc;
3585 struct rwlock *lock;
3587 uint64_t inuse, bitmask;
3588 int allfree, field, freed, idx, lvl;
3595 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
3598 for (field = 0; field < _NPCM; field++) {
3599 inuse = ~pc->pc_map[field] & pc_freemask[field];
3600 while (inuse != 0) {
3601 bit = ffsl(inuse) - 1;
3602 bitmask = 1UL << bit;
3603 idx = field * 64 + bit;
3604 pv = &pc->pc_pventry[idx];
3607 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3608 KASSERT(pde != NULL,
3609 ("Attempting to remove an unmapped page"));
3613 pte = pmap_l1_to_l2(pde, pv->pv_va);
3614 tpte = pmap_load(pte);
3615 KASSERT((tpte & ATTR_DESCR_MASK) ==
3617 ("Attempting to remove an invalid "
3618 "block: %lx", tpte));
3619 tpte = pmap_load(pte);
3622 pte = pmap_l2_to_l3(pde, pv->pv_va);
3623 tpte = pmap_load(pte);
3624 KASSERT((tpte & ATTR_DESCR_MASK) ==
3626 ("Attempting to remove an invalid "
3627 "page: %lx", tpte));
3631 "Invalid page directory level: %d",
3636 * We cannot remove wired pages from a process' mapping at this time
3638 if (tpte & ATTR_SW_WIRED) {
3643 pa = tpte & ~ATTR_MASK;
3645 m = PHYS_TO_VM_PAGE(pa);
3646 KASSERT(m->phys_addr == pa,
3647 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
3648 m, (uintmax_t)m->phys_addr,
3651 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
3652 m < &vm_page_array[vm_page_array_size],
3653 ("pmap_remove_pages: bad pte %#jx",
3656 pmap_load_clear(pte);
3659 * Update the vm_page_t clean/reference bits.
3661 if ((tpte & ATTR_AP_RW_BIT) ==
3662 ATTR_AP(ATTR_AP_RW)) {
3665 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3674 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
3677 pc->pc_map[field] |= bitmask;
3680 pmap_resident_count_dec(pmap,
3681 L2_SIZE / PAGE_SIZE);
3682 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
3683 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
3685 if (TAILQ_EMPTY(&pvh->pv_list)) {
3686 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3687 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
3688 TAILQ_EMPTY(&mt->md.pv_list))
3689 vm_page_aflag_clear(mt, PGA_WRITEABLE);
3691 ml3 = pmap_remove_pt_page(pmap,
3694 pmap_resident_count_dec(pmap,1);
3695 KASSERT(ml3->wire_count == NL3PG,
3696 ("pmap_remove_pages: l3 page wire count error"));
3697 ml3->wire_count = 0;
3698 pmap_add_delayed_free_list(ml3,
3700 atomic_subtract_int(
3701 &vm_cnt.v_wire_count, 1);
3705 pmap_resident_count_dec(pmap, 1);
3706 TAILQ_REMOVE(&m->md.pv_list, pv,
3709 if ((m->aflags & PGA_WRITEABLE) != 0 &&
3710 TAILQ_EMPTY(&m->md.pv_list) &&
3711 (m->flags & PG_FICTITIOUS) == 0) {
3713 VM_PAGE_TO_PHYS(m));
3714 if (TAILQ_EMPTY(&pvh->pv_list))
3715 vm_page_aflag_clear(m,
3720 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
3725 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3726 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3727 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3729 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3733 pmap_invalidate_all(pmap);
3737 pmap_free_zero_pages(&free);
3741 * This is used to check if a page has been accessed or modified. As we
3742 * don't have a bit to see if it has been modified we have to assume it
3743 * has been if the page is read/write.
3746 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
3748 struct rwlock *lock;
3750 struct md_page *pvh;
3751 pt_entry_t *pte, mask, value;
3753 int lvl, md_gen, pvh_gen;
3757 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3760 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3762 if (!PMAP_TRYLOCK(pmap)) {
3763 md_gen = m->md.pv_gen;
3767 if (md_gen != m->md.pv_gen) {
3772 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3774 ("pmap_page_test_mappings: Invalid level %d", lvl));
3778 mask |= ATTR_AP_RW_BIT;
3779 value |= ATTR_AP(ATTR_AP_RW);
3782 mask |= ATTR_AF | ATTR_DESCR_MASK;
3783 value |= ATTR_AF | L3_PAGE;
3785 rv = (pmap_load(pte) & mask) == value;
3790 if ((m->flags & PG_FICTITIOUS) == 0) {
3791 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3792 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3794 if (!PMAP_TRYLOCK(pmap)) {
3795 md_gen = m->md.pv_gen;
3796 pvh_gen = pvh->pv_gen;
3800 if (md_gen != m->md.pv_gen ||
3801 pvh_gen != pvh->pv_gen) {
3806 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3808 ("pmap_page_test_mappings: Invalid level %d", lvl));
3812 mask |= ATTR_AP_RW_BIT;
3813 value |= ATTR_AP(ATTR_AP_RW);
3816 mask |= ATTR_AF | ATTR_DESCR_MASK;
3817 value |= ATTR_AF | L2_BLOCK;
3819 rv = (pmap_load(pte) & mask) == value;
3833 * Return whether or not the specified physical page was modified
3834 * in any physical maps.
3837 pmap_is_modified(vm_page_t m)
3840 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3841 ("pmap_is_modified: page %p is not managed", m));
3844 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3845 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
3846 * is clear, no PTEs can have PG_M set.
3848 VM_OBJECT_ASSERT_WLOCKED(m->object);
3849 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3851 return (pmap_page_test_mappings(m, FALSE, TRUE));
3855 * pmap_is_prefaultable:
3857 * Return whether or not the specified virtual address is eligible
3861 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3869 pte = pmap_pte(pmap, addr, &lvl);
3870 if (pte != NULL && pmap_load(pte) != 0) {
3878 * pmap_is_referenced:
3880 * Return whether or not the specified physical page was referenced
3881 * in any physical maps.
3884 pmap_is_referenced(vm_page_t m)
3887 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3888 ("pmap_is_referenced: page %p is not managed", m));
3889 return (pmap_page_test_mappings(m, TRUE, FALSE));
3893 * Clear the write and modified bits in each of the given page's mappings.
3896 pmap_remove_write(vm_page_t m)
3898 struct md_page *pvh;
3900 struct rwlock *lock;
3901 pv_entry_t next_pv, pv;
3902 pt_entry_t oldpte, *pte;
3904 int lvl, md_gen, pvh_gen;
3906 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3907 ("pmap_remove_write: page %p is not managed", m));
3910 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3911 * set by another thread while the object is locked. Thus,
3912 * if PGA_WRITEABLE is clear, no page table entries need updating.
3914 VM_OBJECT_ASSERT_WLOCKED(m->object);
3915 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3917 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3918 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
3919 pa_to_pvh(VM_PAGE_TO_PHYS(m));
3922 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
3924 if (!PMAP_TRYLOCK(pmap)) {
3925 pvh_gen = pvh->pv_gen;
3929 if (pvh_gen != pvh->pv_gen) {
3936 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3937 if ((pmap_load(pte) & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3938 pmap_demote_l2_locked(pmap, pte, va & ~L2_OFFSET,
3940 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
3941 ("inconsistent pv lock %p %p for page %p",
3942 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
3945 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3947 if (!PMAP_TRYLOCK(pmap)) {
3948 pvh_gen = pvh->pv_gen;
3949 md_gen = m->md.pv_gen;
3953 if (pvh_gen != pvh->pv_gen ||
3954 md_gen != m->md.pv_gen) {
3960 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3962 oldpte = pmap_load(pte);
3963 if ((oldpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) {
3964 if (!atomic_cmpset_long(pte, oldpte,
3965 oldpte | ATTR_AP(ATTR_AP_RO)))
3967 if ((oldpte & ATTR_AF) != 0)
3969 pmap_invalidate_page(pmap, pv->pv_va);
3974 vm_page_aflag_clear(m, PGA_WRITEABLE);
3977 static __inline boolean_t
3978 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
3985 * pmap_ts_referenced:
3987 * Return a count of reference bits for a page, clearing those bits.
3988 * It is not necessary for every reference bit to be cleared, but it
3989 * is necessary that 0 only be returned when there are truly no
3990 * reference bits set.
3992 * As an optimization, update the page's dirty field if a modified bit is
3993 * found while counting reference bits. This opportunistic update can be
3994 * performed at low cost and can eliminate the need for some future calls
3995 * to pmap_is_modified(). However, since this function stops after
3996 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
3997 * dirty pages. Those dirty pages will only be detected by a future call
3998 * to pmap_is_modified().
4001 pmap_ts_referenced(vm_page_t m)
4003 struct md_page *pvh;
4006 struct rwlock *lock;
4007 pd_entry_t *pde, tpde;
4008 pt_entry_t *pte, tpte;
4012 int cleared, md_gen, not_cleared, lvl, pvh_gen;
4013 struct spglist free;
4016 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4017 ("pmap_ts_referenced: page %p is not managed", m));
4020 pa = VM_PAGE_TO_PHYS(m);
4021 lock = PHYS_TO_PV_LIST_LOCK(pa);
4022 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4026 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4027 goto small_mappings;
4033 if (!PMAP_TRYLOCK(pmap)) {
4034 pvh_gen = pvh->pv_gen;
4038 if (pvh_gen != pvh->pv_gen) {
4044 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4045 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4047 ("pmap_ts_referenced: invalid pde level %d", lvl));
4048 tpde = pmap_load(pde);
4049 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4050 ("pmap_ts_referenced: found an invalid l1 table"));
4051 pte = pmap_l1_to_l2(pde, pv->pv_va);
4052 tpte = pmap_load(pte);
4053 if (pmap_page_dirty(tpte)) {
4055 * Although "tpte" is mapping a 2MB page, because
4056 * this function is called at a 4KB page granularity,
4057 * we only update the 4KB page under test.
4061 if ((tpte & ATTR_AF) != 0) {
4063 * Since this reference bit is shared by 512 4KB
4064 * pages, it should not be cleared every time it is
4065 * tested. Apply a simple "hash" function on the
4066 * physical page number, the virtual superpage number,
4067 * and the pmap address to select one 4KB page out of
4068 * the 512 on which testing the reference bit will
4069 * result in clearing that reference bit. This
4070 * function is designed to avoid the selection of the
4071 * same 4KB page for every 2MB page mapping.
4073 * On demotion, a mapping that hasn't been referenced
4074 * is simply destroyed. To avoid the possibility of a
4075 * subsequent page fault on a demoted wired mapping,
4076 * always leave its reference bit set. Moreover,
4077 * since the superpage is wired, the current state of
4078 * its reference bit won't affect page replacement.
4080 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4081 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4082 (tpte & ATTR_SW_WIRED) == 0) {
4083 if (safe_to_clear_referenced(pmap, tpte)) {
4085 * TODO: We don't handle the access
4086 * flag at all. We need to be able
4087 * to set it in the exception handler.
4090 "safe_to_clear_referenced\n");
4091 } else if (pmap_demote_l2_locked(pmap, pte,
4092 pv->pv_va, &lock) != NULL) {
4094 va += VM_PAGE_TO_PHYS(m) -
4095 (tpte & ~ATTR_MASK);
4096 l3 = pmap_l2_to_l3(pte, va);
4097 pmap_remove_l3(pmap, l3, va,
4098 pmap_load(pte), NULL, &lock);
4104 * The superpage mapping was removed
4105 * entirely and therefore 'pv' is no
4113 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4114 ("inconsistent pv lock %p %p for page %p",
4115 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4120 /* Rotate the PV list if it has more than one entry. */
4121 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4122 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4123 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4126 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4128 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4130 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4137 if (!PMAP_TRYLOCK(pmap)) {
4138 pvh_gen = pvh->pv_gen;
4139 md_gen = m->md.pv_gen;
4143 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4148 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4149 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4151 ("pmap_ts_referenced: invalid pde level %d", lvl));
4152 tpde = pmap_load(pde);
4153 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4154 ("pmap_ts_referenced: found an invalid l2 table"));
4155 pte = pmap_l2_to_l3(pde, pv->pv_va);
4156 tpte = pmap_load(pte);
4157 if (pmap_page_dirty(tpte))
4159 if ((tpte & ATTR_AF) != 0) {
4160 if (safe_to_clear_referenced(pmap, tpte)) {
4162 * TODO: We don't handle the access flag
4163 * at all. We need to be able to set it in
4164 * the exception handler.
4166 panic("ARM64TODO: safe_to_clear_referenced\n");
4167 } else if ((tpte & ATTR_SW_WIRED) == 0) {
4169 * Wired pages cannot be paged out so
4170 * doing accessed bit emulation for
4171 * them is wasted effort. We do the
4172 * hard work for unwired pages only.
4174 pmap_remove_l3(pmap, pte, pv->pv_va, tpde,
4176 pmap_invalidate_page(pmap, pv->pv_va);
4181 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4182 ("inconsistent pv lock %p %p for page %p",
4183 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4188 /* Rotate the PV list if it has more than one entry. */
4189 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4190 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4191 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4194 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4195 not_cleared < PMAP_TS_REFERENCED_MAX);
4198 pmap_free_zero_pages(&free);
4199 return (cleared + not_cleared);
4203 * Apply the given advice to the specified range of addresses within the
4204 * given pmap. Depending on the advice, clear the referenced and/or
4205 * modified flags in each mapping and set the mapped page's dirty field.
4208 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4213 * Clear the modify bits on the specified physical page.
4216 pmap_clear_modify(vm_page_t m)
4219 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4220 ("pmap_clear_modify: page %p is not managed", m));
4221 VM_OBJECT_ASSERT_WLOCKED(m->object);
4222 KASSERT(!vm_page_xbusied(m),
4223 ("pmap_clear_modify: page %p is exclusive busied", m));
4226 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4227 * If the object containing the page is locked and the page is not
4228 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4230 if ((m->aflags & PGA_WRITEABLE) == 0)
4233 /* ARM64TODO: We lack support for tracking if a page is modified */
4237 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4240 return ((void *)PHYS_TO_DMAP(pa));
4244 pmap_unmapbios(vm_paddr_t pa, vm_size_t size)
4249 * Sets the memory attribute for the specified page.
4252 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4255 m->md.pv_memattr = ma;
4258 * If "m" is a normal page, update its direct mapping. This update
4259 * can be relied upon to perform any cache operations that are
4260 * required for data coherence.
4262 if ((m->flags & PG_FICTITIOUS) == 0 &&
4263 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
4264 m->md.pv_memattr) != 0)
4265 panic("memory attribute change on the direct map failed");
4269 * Changes the specified virtual address range's memory type to that given by
4270 * the parameter "mode". The specified virtual address range must be
4271 * completely contained within either the direct map or the kernel map. If
4272 * the virtual address range is contained within the kernel map, then the
4273 * memory type for each of the corresponding ranges of the direct map is also
4274 * changed. (The corresponding ranges of the direct map are those ranges that
4275 * map the same physical pages as the specified virtual address range.) These
4276 * changes to the direct map are necessary because Intel describes the
4277 * behavior of their processors as "undefined" if two or more mappings to the
4278 * same physical page have different memory types.
4280 * Returns zero if the change completed successfully, and either EINVAL or
4281 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
4282 * of the virtual address range was not mapped, and ENOMEM is returned if
4283 * there was insufficient memory available to complete the change. In the
4284 * latter case, the memory type may have been changed on some part of the
4285 * virtual address range or the direct map.
4288 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
4292 PMAP_LOCK(kernel_pmap);
4293 error = pmap_change_attr_locked(va, size, mode);
4294 PMAP_UNLOCK(kernel_pmap);
4299 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
4301 vm_offset_t base, offset, tmpva;
4302 pt_entry_t l3, *pte, *newpte;
4305 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
4306 base = trunc_page(va);
4307 offset = va & PAGE_MASK;
4308 size = round_page(offset + size);
4310 if (!VIRT_IN_DMAP(base))
4313 for (tmpva = base; tmpva < base + size; ) {
4314 pte = pmap_pte(kernel_pmap, va, &lvl);
4318 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
4320 * We already have the correct attribute,
4321 * ignore this entry.
4325 panic("Invalid DMAP table level: %d\n", lvl);
4327 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
4330 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
4338 * Split the entry to an level 3 table, then
4339 * set the new attribute.
4343 panic("Invalid DMAP table level: %d\n", lvl);
4345 newpte = pmap_demote_l1(kernel_pmap, pte,
4346 tmpva & ~L1_OFFSET);
4349 pte = pmap_l1_to_l2(pte, tmpva);
4351 newpte = pmap_demote_l2(kernel_pmap, pte,
4352 tmpva & ~L2_OFFSET);
4355 pte = pmap_l2_to_l3(pte, tmpva);
4357 /* Update the entry */
4358 l3 = pmap_load(pte);
4359 l3 &= ~ATTR_IDX_MASK;
4360 l3 |= ATTR_IDX(mode);
4361 if (mode == DEVICE_MEMORY)
4364 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
4368 * If moving to a non-cacheable entry flush
4371 if (mode == VM_MEMATTR_UNCACHEABLE)
4372 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
4384 * Create an L2 table to map all addresses within an L1 mapping.
4387 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
4389 pt_entry_t *l2, newl2, oldl1;
4391 vm_paddr_t l2phys, phys;
4395 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4396 oldl1 = pmap_load(l1);
4397 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
4398 ("pmap_demote_l1: Demoting a non-block entry"));
4399 KASSERT((va & L1_OFFSET) == 0,
4400 ("pmap_demote_l1: Invalid virtual address %#lx", va));
4401 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
4402 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
4405 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
4406 tmpl1 = kva_alloc(PAGE_SIZE);
4411 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
4412 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
4413 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
4414 " in pmap %p", va, pmap);
4418 l2phys = VM_PAGE_TO_PHYS(ml2);
4419 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
4421 /* Address the range points at */
4422 phys = oldl1 & ~ATTR_MASK;
4423 /* The attributed from the old l1 table to be copied */
4424 newl2 = oldl1 & ATTR_MASK;
4426 /* Create the new entries */
4427 for (i = 0; i < Ln_ENTRIES; i++) {
4428 l2[i] = newl2 | phys;
4431 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
4432 ("Invalid l2 page (%lx != %lx)", l2[0],
4433 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
4436 pmap_kenter(tmpl1, PAGE_SIZE,
4437 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY);
4438 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
4441 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
4444 pmap_kremove(tmpl1);
4445 kva_free(tmpl1, PAGE_SIZE);
4452 * Create an L3 table to map all addresses within an L2 mapping.
4455 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
4456 struct rwlock **lockp)
4458 pt_entry_t *l3, newl3, oldl2;
4460 vm_paddr_t l3phys, phys;
4464 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4466 oldl2 = pmap_load(l2);
4467 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
4468 ("pmap_demote_l2: Demoting a non-block entry"));
4469 KASSERT((va & L2_OFFSET) == 0,
4470 ("pmap_demote_l2: Invalid virtual address %#lx", va));
4473 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
4474 tmpl2 = kva_alloc(PAGE_SIZE);
4479 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
4480 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
4481 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4482 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
4484 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
4485 " in pmap %p", va, pmap);
4488 if (va < VM_MAXUSER_ADDRESS)
4489 pmap_resident_count_inc(pmap, 1);
4492 l3phys = VM_PAGE_TO_PHYS(ml3);
4493 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
4495 /* Address the range points at */
4496 phys = oldl2 & ~ATTR_MASK;
4497 /* The attributed from the old l2 table to be copied */
4498 newl3 = (oldl2 & (ATTR_MASK & ~ATTR_DESCR_MASK)) | L3_PAGE;
4501 * If the page table page is new, initialize it.
4503 if (ml3->wire_count == 1) {
4504 for (i = 0; i < Ln_ENTRIES; i++) {
4505 l3[i] = newl3 | phys;
4509 KASSERT(l3[0] == ((oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE),
4510 ("Invalid l3 page (%lx != %lx)", l3[0],
4511 (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE));
4514 * Map the temporary page so we don't lose access to the l2 table.
4517 pmap_kenter(tmpl2, PAGE_SIZE,
4518 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY);
4519 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
4523 * The spare PV entries must be reserved prior to demoting the
4524 * mapping, that is, prior to changing the PDE. Otherwise, the state
4525 * of the L2 and the PV lists will be inconsistent, which can result
4526 * in reclaim_pv_chunk() attempting to remove a PV entry from the
4527 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
4528 * PV entry for the 2MB page mapping that is being demoted.
4530 if ((oldl2 & ATTR_SW_MANAGED) != 0)
4531 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
4533 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
4536 * Demote the PV entry.
4538 if ((oldl2 & ATTR_SW_MANAGED) != 0)
4539 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
4541 atomic_add_long(&pmap_l2_demotions, 1);
4542 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
4543 " in pmap %p %lx", va, pmap, l3[0]);
4547 pmap_kremove(tmpl2);
4548 kva_free(tmpl2, PAGE_SIZE);
4556 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
4558 struct rwlock *lock;
4562 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
4569 * perform the pmap work for mincore
4572 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
4574 pd_entry_t *l1p, l1;
4575 pd_entry_t *l2p, l2;
4576 pt_entry_t *l3p, l3;
4587 l1p = pmap_l1(pmap, addr);
4588 if (l1p == NULL) /* No l1 */
4591 l1 = pmap_load(l1p);
4592 if ((l1 & ATTR_DESCR_MASK) == L1_INVAL)
4595 if ((l1 & ATTR_DESCR_MASK) == L1_BLOCK) {
4596 pa = (l1 & ~ATTR_MASK) | (addr & L1_OFFSET);
4597 managed = (l1 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4598 val = MINCORE_SUPER | MINCORE_INCORE;
4599 if (pmap_page_dirty(l1))
4600 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4601 if ((l1 & ATTR_AF) == ATTR_AF)
4602 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4606 l2p = pmap_l1_to_l2(l1p, addr);
4607 if (l2p == NULL) /* No l2 */
4610 l2 = pmap_load(l2p);
4611 if ((l2 & ATTR_DESCR_MASK) == L2_INVAL)
4614 if ((l2 & ATTR_DESCR_MASK) == L2_BLOCK) {
4615 pa = (l2 & ~ATTR_MASK) | (addr & L2_OFFSET);
4616 managed = (l2 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4617 val = MINCORE_SUPER | MINCORE_INCORE;
4618 if (pmap_page_dirty(l2))
4619 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4620 if ((l2 & ATTR_AF) == ATTR_AF)
4621 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4625 l3p = pmap_l2_to_l3(l2p, addr);
4626 if (l3p == NULL) /* No l3 */
4629 l3 = pmap_load(l2p);
4630 if ((l3 & ATTR_DESCR_MASK) == L3_INVAL)
4633 if ((l3 & ATTR_DESCR_MASK) == L3_PAGE) {
4634 pa = (l3 & ~ATTR_MASK) | (addr & L3_OFFSET);
4635 managed = (l3 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4636 val = MINCORE_INCORE;
4637 if (pmap_page_dirty(l3))
4638 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4639 if ((l3 & ATTR_AF) == ATTR_AF)
4640 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4644 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
4645 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
4646 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
4647 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
4650 PA_UNLOCK_COND(*locked_pa);
4657 pmap_activate(struct thread *td)
4662 pmap = vmspace_pmap(td->td_proc->p_vmspace);
4663 td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0);
4664 __asm __volatile("msr ttbr0_el1, %0" : :
4665 "r"(td->td_proc->p_md.md_l0addr));
4666 pmap_invalidate_all(pmap);
4671 pmap_switch(struct thread *old, struct thread *new)
4673 pcpu_bp_harden bp_harden;
4676 /* Store the new curthread */
4677 PCPU_SET(curthread, new);
4679 /* And the new pcb */
4681 PCPU_SET(curpcb, pcb);
4684 * TODO: We may need to flush the cache here if switching
4685 * to a user process.
4689 old->td_proc->p_md.md_l0addr != new->td_proc->p_md.md_l0addr) {
4691 /* Switch to the new pmap */
4692 "msr ttbr0_el1, %0 \n"
4695 /* Invalidate the TLB */
4700 : : "r"(new->td_proc->p_md.md_l0addr));
4703 * Stop userspace from training the branch predictor against
4704 * other processes. This will call into a CPU specific
4705 * function that clears the branch predictor state.
4707 bp_harden = PCPU_GET(bp_harden);
4708 if (bp_harden != NULL)
4716 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
4719 if (va >= VM_MIN_KERNEL_ADDRESS) {
4720 cpu_icache_sync_range(va, sz);
4725 /* Find the length of data in this page to flush */
4726 offset = va & PAGE_MASK;
4727 len = imin(PAGE_SIZE - offset, sz);
4730 /* Extract the physical address & find it in the DMAP */
4731 pa = pmap_extract(pmap, va);
4733 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
4735 /* Move to the next page */
4738 /* Set the length for the next iteration */
4739 len = imin(PAGE_SIZE, sz);
4745 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
4751 switch (ESR_ELx_EXCEPTION(esr)) {
4752 case EXCP_DATA_ABORT_L:
4753 case EXCP_DATA_ABORT:
4756 return (KERN_FAILURE);
4761 switch (esr & ISS_DATA_DFSC_MASK) {
4762 case ISS_DATA_DFSC_TF_L0:
4763 case ISS_DATA_DFSC_TF_L1:
4764 case ISS_DATA_DFSC_TF_L2:
4765 case ISS_DATA_DFSC_TF_L3:
4766 /* Ask the MMU to check the address */
4767 if (pmap == kernel_pmap)
4768 par = arm64_address_translate_s1e1r(far);
4770 par = arm64_address_translate_s1e0r(far);
4773 * If the translation was successful the address was invalid
4774 * due to a break-before-make sequence. We can unlock and
4775 * return success to the trap handler.
4777 if (PAR_SUCCESS(par)) {
4779 return (KERN_SUCCESS);
4788 return (KERN_FAILURE);
4792 * Increase the starting virtual address of the given mapping if a
4793 * different alignment might result in more superpage mappings.
4796 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4797 vm_offset_t *addr, vm_size_t size)
4799 vm_offset_t superpage_offset;
4803 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
4804 offset += ptoa(object->pg_color);
4805 superpage_offset = offset & L2_OFFSET;
4806 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
4807 (*addr & L2_OFFSET) == superpage_offset)
4809 if ((*addr & L2_OFFSET) < superpage_offset)
4810 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
4812 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
4816 * Get the kernel virtual address of a set of physical pages. If there are
4817 * physical addresses not covered by the DMAP perform a transient mapping
4818 * that will be removed when calling pmap_unmap_io_transient.
4820 * \param page The pages the caller wishes to obtain the virtual
4821 * address on the kernel memory map.
4822 * \param vaddr On return contains the kernel virtual memory address
4823 * of the pages passed in the page parameter.
4824 * \param count Number of pages passed in.
4825 * \param can_fault TRUE if the thread using the mapped pages can take
4826 * page faults, FALSE otherwise.
4828 * \returns TRUE if the caller must call pmap_unmap_io_transient when
4829 * finished or FALSE otherwise.
4833 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
4834 boolean_t can_fault)
4837 boolean_t needs_mapping;
4841 * Allocate any KVA space that we need, this is done in a separate
4842 * loop to prevent calling vmem_alloc while pinned.
4844 needs_mapping = FALSE;
4845 for (i = 0; i < count; i++) {
4846 paddr = VM_PAGE_TO_PHYS(page[i]);
4847 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
4848 error = vmem_alloc(kernel_arena, PAGE_SIZE,
4849 M_BESTFIT | M_WAITOK, &vaddr[i]);
4850 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
4851 needs_mapping = TRUE;
4853 vaddr[i] = PHYS_TO_DMAP(paddr);
4857 /* Exit early if everything is covered by the DMAP */
4863 for (i = 0; i < count; i++) {
4864 paddr = VM_PAGE_TO_PHYS(page[i]);
4865 if (!PHYS_IN_DMAP(paddr)) {
4867 "pmap_map_io_transient: TODO: Map out of DMAP data");
4871 return (needs_mapping);
4875 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
4876 boolean_t can_fault)
4883 for (i = 0; i < count; i++) {
4884 paddr = VM_PAGE_TO_PHYS(page[i]);
4885 if (!PHYS_IN_DMAP(paddr)) {
4886 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");