2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/msgbuf.h>
120 #include <sys/mutex.h>
121 #include <sys/proc.h>
122 #include <sys/rwlock.h>
124 #include <sys/vmem.h>
125 #include <sys/vmmeter.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/_unrhdr.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/vm_pager.h>
140 #include <vm/vm_phys.h>
141 #include <vm/vm_radix.h>
142 #include <vm/vm_reserv.h>
145 #include <machine/machdep.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
149 #include <arm/include/physmem.h>
151 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
152 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
153 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
154 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
156 #define NUL0E L0_ENTRIES
157 #define NUL1E (NUL0E * NL1PG)
158 #define NUL2E (NUL1E * NL2PG)
160 #if !defined(DIAGNOSTIC)
161 #ifdef __GNUC_GNU_INLINE__
162 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
164 #define PMAP_INLINE extern inline
171 * These are configured by the mair_el1 register. This is set up in locore.S
173 #define DEVICE_MEMORY 0
174 #define UNCACHED_MEMORY 1
175 #define CACHED_MEMORY 2
179 #define PV_STAT(x) do { x ; } while (0)
181 #define PV_STAT(x) do { } while (0)
184 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
185 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
187 #define NPV_LIST_LOCKS MAXCPU
189 #define PHYS_TO_PV_LIST_LOCK(pa) \
190 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
192 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
193 struct rwlock **_lockp = (lockp); \
194 struct rwlock *_new_lock; \
196 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
197 if (_new_lock != *_lockp) { \
198 if (*_lockp != NULL) \
199 rw_wunlock(*_lockp); \
200 *_lockp = _new_lock; \
205 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
206 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
208 #define RELEASE_PV_LIST_LOCK(lockp) do { \
209 struct rwlock **_lockp = (lockp); \
211 if (*_lockp != NULL) { \
212 rw_wunlock(*_lockp); \
217 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
218 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
220 struct pmap kernel_pmap_store;
222 /* Used for mapping ACPI memory before VM is initialized */
223 #define PMAP_PREINIT_MAPPING_COUNT 32
224 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
225 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
226 static int vm_initialized = 0; /* No need to use pre-init maps when set */
229 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
230 * Always map entire L2 block for simplicity.
231 * VA of L2 block = preinit_map_va + i * L2_SIZE
233 static struct pmap_preinit_mapping {
237 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
239 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
240 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
241 vm_offset_t kernel_vm_end = 0;
244 * Data for the pv entry allocation mechanism.
245 * Updates to pv_invl_gen are protected by the pv_list_locks[]
246 * elements, but reads are not.
248 static struct md_page *pv_table;
249 static struct md_page pv_dummy;
251 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
252 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
253 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
255 /* This code assumes all L1 DMAP entries will be used */
256 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
257 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
259 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
260 extern pt_entry_t pagetable_dmap[];
262 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
263 static vm_paddr_t physmap[PHYSMAP_SIZE];
264 static u_int physmap_idx;
266 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
268 static int superpages_enabled = 1;
269 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
270 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
271 "Are large page mappings enabled?");
274 * Data for the pv entry allocation mechanism
276 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
277 static struct mtx pv_chunks_mutex;
278 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
281 * Internal flags for pmap_enter()'s helper functions.
283 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
284 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
286 static void free_pv_chunk(struct pv_chunk *pc);
287 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
288 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
289 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
290 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
291 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
294 static int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode);
295 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
296 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
297 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
298 vm_offset_t va, struct rwlock **lockp);
299 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
300 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
301 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
302 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
303 u_int flags, vm_page_t m, struct rwlock **lockp);
304 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
305 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
306 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
307 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
308 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
309 vm_page_t m, struct rwlock **lockp);
311 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
312 struct rwlock **lockp);
314 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
315 struct spglist *free);
316 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
317 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
320 * These load the old table data and store the new value.
321 * They need to be atomic as the System MMU may write to the table at
322 * the same time as the CPU.
324 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
325 #define pmap_set(table, mask) atomic_set_64(table, mask)
326 #define pmap_load_clear(table) atomic_swap_64(table, 0)
327 #define pmap_load(table) (*table)
329 /********************/
330 /* Inline functions */
331 /********************/
334 pagecopy(void *s, void *d)
337 memcpy(d, s, PAGE_SIZE);
340 static __inline pd_entry_t *
341 pmap_l0(pmap_t pmap, vm_offset_t va)
344 return (&pmap->pm_l0[pmap_l0_index(va)]);
347 static __inline pd_entry_t *
348 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
352 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
353 return (&l1[pmap_l1_index(va)]);
356 static __inline pd_entry_t *
357 pmap_l1(pmap_t pmap, vm_offset_t va)
361 l0 = pmap_l0(pmap, va);
362 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
365 return (pmap_l0_to_l1(l0, va));
368 static __inline pd_entry_t *
369 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
373 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
374 return (&l2[pmap_l2_index(va)]);
377 static __inline pd_entry_t *
378 pmap_l2(pmap_t pmap, vm_offset_t va)
382 l1 = pmap_l1(pmap, va);
383 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
386 return (pmap_l1_to_l2(l1, va));
389 static __inline pt_entry_t *
390 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
394 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
395 return (&l3[pmap_l3_index(va)]);
399 * Returns the lowest valid pde for a given virtual address.
400 * The next level may or may not point to a valid page or block.
402 static __inline pd_entry_t *
403 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
405 pd_entry_t *l0, *l1, *l2, desc;
407 l0 = pmap_l0(pmap, va);
408 desc = pmap_load(l0) & ATTR_DESCR_MASK;
409 if (desc != L0_TABLE) {
414 l1 = pmap_l0_to_l1(l0, va);
415 desc = pmap_load(l1) & ATTR_DESCR_MASK;
416 if (desc != L1_TABLE) {
421 l2 = pmap_l1_to_l2(l1, va);
422 desc = pmap_load(l2) & ATTR_DESCR_MASK;
423 if (desc != L2_TABLE) {
433 * Returns the lowest valid pte block or table entry for a given virtual
434 * address. If there are no valid entries return NULL and set the level to
435 * the first invalid level.
437 static __inline pt_entry_t *
438 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
440 pd_entry_t *l1, *l2, desc;
443 l1 = pmap_l1(pmap, va);
448 desc = pmap_load(l1) & ATTR_DESCR_MASK;
449 if (desc == L1_BLOCK) {
454 if (desc != L1_TABLE) {
459 l2 = pmap_l1_to_l2(l1, va);
460 desc = pmap_load(l2) & ATTR_DESCR_MASK;
461 if (desc == L2_BLOCK) {
466 if (desc != L2_TABLE) {
472 l3 = pmap_l2_to_l3(l2, va);
473 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
480 pmap_ps_enabled(pmap_t pmap __unused)
483 return (superpages_enabled != 0);
487 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
488 pd_entry_t **l2, pt_entry_t **l3)
490 pd_entry_t *l0p, *l1p, *l2p;
492 if (pmap->pm_l0 == NULL)
495 l0p = pmap_l0(pmap, va);
498 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
501 l1p = pmap_l0_to_l1(l0p, va);
504 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
510 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
513 l2p = pmap_l1_to_l2(l1p, va);
516 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
521 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
524 *l3 = pmap_l2_to_l3(l2p, va);
530 pmap_l3_valid(pt_entry_t l3)
533 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
537 CTASSERT(L1_BLOCK == L2_BLOCK);
540 * Checks if the page is dirty. We currently lack proper tracking of this on
541 * arm64 so for now assume is a page mapped as rw was accessed it is.
544 pmap_page_dirty(pt_entry_t pte)
547 return ((pte & (ATTR_AF | ATTR_AP_RW_BIT)) ==
548 (ATTR_AF | ATTR_AP(ATTR_AP_RW)));
552 pmap_resident_count_inc(pmap_t pmap, int count)
555 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
556 pmap->pm_stats.resident_count += count;
560 pmap_resident_count_dec(pmap_t pmap, int count)
563 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
564 KASSERT(pmap->pm_stats.resident_count >= count,
565 ("pmap %p resident count underflow %ld %d", pmap,
566 pmap->pm_stats.resident_count, count));
567 pmap->pm_stats.resident_count -= count;
571 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
577 l1 = (pd_entry_t *)l1pt;
578 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
580 /* Check locore has used a table L1 map */
581 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
582 ("Invalid bootstrap L1 table"));
583 /* Find the address of the L2 table */
584 l2 = (pt_entry_t *)init_pt_va;
585 *l2_slot = pmap_l2_index(va);
591 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
593 u_int l1_slot, l2_slot;
596 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
598 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
602 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
603 vm_offset_t freemempos)
607 vm_paddr_t l2_pa, pa;
608 u_int l1_slot, l2_slot, prev_l1_slot;
611 dmap_phys_base = min_pa & ~L1_OFFSET;
617 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
618 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
620 for (i = 0; i < (physmap_idx * 2); i += 2) {
621 pa = physmap[i] & ~L2_OFFSET;
622 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
624 /* Create L2 mappings at the start of the region */
625 if ((pa & L1_OFFSET) != 0) {
626 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
627 if (l1_slot != prev_l1_slot) {
628 prev_l1_slot = l1_slot;
629 l2 = (pt_entry_t *)freemempos;
630 l2_pa = pmap_early_vtophys(kern_l1,
632 freemempos += PAGE_SIZE;
634 pmap_load_store(&pagetable_dmap[l1_slot],
635 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
637 memset(l2, 0, PAGE_SIZE);
640 ("pmap_bootstrap_dmap: NULL l2 map"));
641 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
642 pa += L2_SIZE, va += L2_SIZE) {
644 * We are on a boundary, stop to
645 * create a level 1 block
647 if ((pa & L1_OFFSET) == 0)
650 l2_slot = pmap_l2_index(va);
651 KASSERT(l2_slot != 0, ("..."));
652 pmap_load_store(&l2[l2_slot],
653 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
654 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
656 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
660 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
661 (physmap[i + 1] - pa) >= L1_SIZE;
662 pa += L1_SIZE, va += L1_SIZE) {
663 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
664 pmap_load_store(&pagetable_dmap[l1_slot],
665 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
666 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
669 /* Create L2 mappings at the end of the region */
670 if (pa < physmap[i + 1]) {
671 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
672 if (l1_slot != prev_l1_slot) {
673 prev_l1_slot = l1_slot;
674 l2 = (pt_entry_t *)freemempos;
675 l2_pa = pmap_early_vtophys(kern_l1,
677 freemempos += PAGE_SIZE;
679 pmap_load_store(&pagetable_dmap[l1_slot],
680 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
682 memset(l2, 0, PAGE_SIZE);
685 ("pmap_bootstrap_dmap: NULL l2 map"));
686 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
687 pa += L2_SIZE, va += L2_SIZE) {
688 l2_slot = pmap_l2_index(va);
689 pmap_load_store(&l2[l2_slot],
690 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
691 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
695 if (pa > dmap_phys_max) {
707 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
714 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
716 l1 = (pd_entry_t *)l1pt;
717 l1_slot = pmap_l1_index(va);
720 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
721 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
723 pa = pmap_early_vtophys(l1pt, l2pt);
724 pmap_load_store(&l1[l1_slot],
725 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
729 /* Clean the L2 page table */
730 memset((void *)l2_start, 0, l2pt - l2_start);
736 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
743 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
745 l2 = pmap_l2(kernel_pmap, va);
746 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
747 l2_slot = pmap_l2_index(va);
750 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
751 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
753 pa = pmap_early_vtophys(l1pt, l3pt);
754 pmap_load_store(&l2[l2_slot],
755 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
759 /* Clean the L2 page table */
760 memset((void *)l3_start, 0, l3pt - l3_start);
766 * Bootstrap the system enough to run with virtual memory.
769 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
772 u_int l1_slot, l2_slot;
775 vm_offset_t va, freemempos;
776 vm_offset_t dpcpu, msgbufpv;
777 vm_paddr_t start_pa, pa, min_pa;
780 kern_delta = KERNBASE - kernstart;
782 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
783 printf("%lx\n", l1pt);
784 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
786 /* Set this early so we can use the pagetable walking functions */
787 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
788 PMAP_LOCK_INIT(kernel_pmap);
790 /* Assume the address we were loaded to is a valid physical address */
791 min_pa = KERNBASE - kern_delta;
793 physmap_idx = arm_physmem_avail(physmap, nitems(physmap));
797 * Find the minimum physical address. physmap is sorted,
798 * but may contain empty ranges.
800 for (i = 0; i < (physmap_idx * 2); i += 2) {
801 if (physmap[i] == physmap[i + 1])
803 if (physmap[i] <= min_pa)
807 freemempos = KERNBASE + kernlen;
808 freemempos = roundup2(freemempos, PAGE_SIZE);
810 /* Create a direct map region early so we can use it for pa -> va */
811 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
814 start_pa = pa = KERNBASE - kern_delta;
817 * Read the page table to find out what is already mapped.
818 * This assumes we have mapped a block of memory from KERNBASE
819 * using a single L1 entry.
821 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
823 /* Sanity check the index, KERNBASE should be the first VA */
824 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
826 /* Find how many pages we have mapped */
827 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
828 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
831 /* Check locore used L2 blocks */
832 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
833 ("Invalid bootstrap L2 table"));
834 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
835 ("Incorrect PA in L2 table"));
841 va = roundup2(va, L1_SIZE);
843 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
844 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
845 /* And the l3 tables for the early devmap */
846 freemempos = pmap_bootstrap_l3(l1pt,
847 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
851 #define alloc_pages(var, np) \
852 (var) = freemempos; \
853 freemempos += (np * PAGE_SIZE); \
854 memset((char *)(var), 0, ((np) * PAGE_SIZE));
856 /* Allocate dynamic per-cpu area. */
857 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
858 dpcpu_init((void *)dpcpu, 0);
860 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
861 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
862 msgbufp = (void *)msgbufpv;
864 /* Reserve some VA space for early BIOS/ACPI mapping */
865 preinit_map_va = roundup2(freemempos, L2_SIZE);
867 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
868 virtual_avail = roundup2(virtual_avail, L1_SIZE);
869 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
870 kernel_vm_end = virtual_avail;
872 pa = pmap_early_vtophys(l1pt, freemempos);
874 arm_physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
880 * Initialize a vm_page's machine-dependent fields.
883 pmap_page_init(vm_page_t m)
886 TAILQ_INIT(&m->md.pv_list);
887 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
891 * Initialize the pmap module.
892 * Called by vm_init, to initialize any structures that the pmap
893 * system needs to map virtual memory.
902 * Are large page mappings enabled?
904 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
905 if (superpages_enabled) {
906 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
907 ("pmap_init: can't assign to pagesizes[1]"));
908 pagesizes[1] = L2_SIZE;
912 * Initialize the pv chunk list mutex.
914 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
917 * Initialize the pool of pv list locks.
919 for (i = 0; i < NPV_LIST_LOCKS; i++)
920 rw_init(&pv_list_locks[i], "pmap pv list");
923 * Calculate the size of the pv head table for superpages.
925 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
928 * Allocate memory for the pv head table for superpages.
930 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
932 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
934 for (i = 0; i < pv_npg; i++)
935 TAILQ_INIT(&pv_table[i].pv_list);
936 TAILQ_INIT(&pv_dummy.pv_list);
941 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
942 "2MB page mapping counters");
944 static u_long pmap_l2_demotions;
945 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
946 &pmap_l2_demotions, 0, "2MB page demotions");
948 static u_long pmap_l2_mappings;
949 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
950 &pmap_l2_mappings, 0, "2MB page mappings");
952 static u_long pmap_l2_p_failures;
953 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
954 &pmap_l2_p_failures, 0, "2MB page promotion failures");
956 static u_long pmap_l2_promotions;
957 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
958 &pmap_l2_promotions, 0, "2MB page promotions");
961 * Invalidate a single TLB entry.
964 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
970 "tlbi vaae1is, %0 \n"
973 : : "r"(va >> PAGE_SHIFT));
978 pmap_invalidate_range_nopin(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
983 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
985 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
993 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
997 pmap_invalidate_range_nopin(pmap, sva, eva);
1001 static __inline void
1002 pmap_invalidate_all(pmap_t pmap)
1015 * Routine: pmap_extract
1017 * Extract the physical page address associated
1018 * with the given map/virtual_address pair.
1021 pmap_extract(pmap_t pmap, vm_offset_t va)
1023 pt_entry_t *pte, tpte;
1030 * Find the block or page map for this virtual address. pmap_pte
1031 * will return either a valid block/page entry, or NULL.
1033 pte = pmap_pte(pmap, va, &lvl);
1035 tpte = pmap_load(pte);
1036 pa = tpte & ~ATTR_MASK;
1039 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1040 ("pmap_extract: Invalid L1 pte found: %lx",
1041 tpte & ATTR_DESCR_MASK));
1042 pa |= (va & L1_OFFSET);
1045 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1046 ("pmap_extract: Invalid L2 pte found: %lx",
1047 tpte & ATTR_DESCR_MASK));
1048 pa |= (va & L2_OFFSET);
1051 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1052 ("pmap_extract: Invalid L3 pte found: %lx",
1053 tpte & ATTR_DESCR_MASK));
1054 pa |= (va & L3_OFFSET);
1063 * Routine: pmap_extract_and_hold
1065 * Atomically extract and hold the physical page
1066 * with the given pmap and virtual address pair
1067 * if that mapping permits the given protection.
1070 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1072 pt_entry_t *pte, tpte;
1082 pte = pmap_pte(pmap, va, &lvl);
1084 tpte = pmap_load(pte);
1086 KASSERT(lvl > 0 && lvl <= 3,
1087 ("pmap_extract_and_hold: Invalid level %d", lvl));
1088 CTASSERT(L1_BLOCK == L2_BLOCK);
1089 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1090 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1091 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1092 tpte & ATTR_DESCR_MASK));
1093 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1094 ((prot & VM_PROT_WRITE) == 0)) {
1097 off = va & L1_OFFSET;
1100 off = va & L2_OFFSET;
1106 if (vm_page_pa_tryrelock(pmap,
1107 (tpte & ~ATTR_MASK) | off, &pa))
1109 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1119 pmap_kextract(vm_offset_t va)
1121 pt_entry_t *pte, tpte;
1125 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1126 pa = DMAP_TO_PHYS(va);
1129 pte = pmap_pte(kernel_pmap, va, &lvl);
1131 tpte = pmap_load(pte);
1132 pa = tpte & ~ATTR_MASK;
1135 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1136 ("pmap_kextract: Invalid L1 pte found: %lx",
1137 tpte & ATTR_DESCR_MASK));
1138 pa |= (va & L1_OFFSET);
1141 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1142 ("pmap_kextract: Invalid L2 pte found: %lx",
1143 tpte & ATTR_DESCR_MASK));
1144 pa |= (va & L2_OFFSET);
1147 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1148 ("pmap_kextract: Invalid L3 pte found: %lx",
1149 tpte & ATTR_DESCR_MASK));
1150 pa |= (va & L3_OFFSET);
1158 /***************************************************
1159 * Low level mapping routines.....
1160 ***************************************************/
1163 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1166 pt_entry_t *pte, attr;
1170 KASSERT((pa & L3_OFFSET) == 0,
1171 ("pmap_kenter: Invalid physical address"));
1172 KASSERT((sva & L3_OFFSET) == 0,
1173 ("pmap_kenter: Invalid virtual address"));
1174 KASSERT((size & PAGE_MASK) == 0,
1175 ("pmap_kenter: Mapping is not page-sized"));
1177 attr = ATTR_DEFAULT | ATTR_IDX(mode) | L3_PAGE;
1178 if (mode == DEVICE_MEMORY)
1183 pde = pmap_pde(kernel_pmap, va, &lvl);
1184 KASSERT(pde != NULL,
1185 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1186 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1188 pte = pmap_l2_to_l3(pde, va);
1189 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1195 pmap_invalidate_range(kernel_pmap, sva, va);
1199 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1202 pmap_kenter(sva, size, pa, DEVICE_MEMORY);
1206 * Remove a page from the kernel pagetables.
1209 pmap_kremove(vm_offset_t va)
1214 pte = pmap_pte(kernel_pmap, va, &lvl);
1215 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1216 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1218 pmap_load_clear(pte);
1219 pmap_invalidate_page(kernel_pmap, va);
1223 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1229 KASSERT((sva & L3_OFFSET) == 0,
1230 ("pmap_kremove_device: Invalid virtual address"));
1231 KASSERT((size & PAGE_MASK) == 0,
1232 ("pmap_kremove_device: Mapping is not page-sized"));
1236 pte = pmap_pte(kernel_pmap, va, &lvl);
1237 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1239 ("Invalid device pagetable level: %d != 3", lvl));
1240 pmap_load_clear(pte);
1245 pmap_invalidate_range(kernel_pmap, sva, va);
1249 * Used to map a range of physical addresses into kernel
1250 * virtual address space.
1252 * The value passed in '*virt' is a suggested virtual address for
1253 * the mapping. Architectures which can support a direct-mapped
1254 * physical to virtual region can return the appropriate address
1255 * within that region, leaving '*virt' unchanged. Other
1256 * architectures should map the pages starting at '*virt' and
1257 * update '*virt' with the first usable address after the mapped
1261 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1263 return PHYS_TO_DMAP(start);
1268 * Add a list of wired pages to the kva
1269 * this routine is only used for temporary
1270 * kernel mappings that do not need to have
1271 * page modification or references recorded.
1272 * Note that old mappings are simply written
1273 * over. The page *must* be wired.
1274 * Note: SMP coherent. Uses a ranged shootdown IPI.
1277 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1280 pt_entry_t *pte, pa;
1286 for (i = 0; i < count; i++) {
1287 pde = pmap_pde(kernel_pmap, va, &lvl);
1288 KASSERT(pde != NULL,
1289 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1291 ("pmap_qenter: Invalid level %d", lvl));
1294 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1295 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1296 if (m->md.pv_memattr == DEVICE_MEMORY)
1298 pte = pmap_l2_to_l3(pde, va);
1299 pmap_load_store(pte, pa);
1303 pmap_invalidate_range(kernel_pmap, sva, va);
1307 * This routine tears out page mappings from the
1308 * kernel -- it is meant only for temporary mappings.
1311 pmap_qremove(vm_offset_t sva, int count)
1317 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1320 while (count-- > 0) {
1321 pte = pmap_pte(kernel_pmap, va, &lvl);
1323 ("Invalid device pagetable level: %d != 3", lvl));
1325 pmap_load_clear(pte);
1330 pmap_invalidate_range(kernel_pmap, sva, va);
1333 /***************************************************
1334 * Page table page management routines.....
1335 ***************************************************/
1337 * Schedule the specified unused page table page to be freed. Specifically,
1338 * add the page to the specified list of pages that will be released to the
1339 * physical memory manager after the TLB has been updated.
1341 static __inline void
1342 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1343 boolean_t set_PG_ZERO)
1347 m->flags |= PG_ZERO;
1349 m->flags &= ~PG_ZERO;
1350 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1354 * Decrements a page table page's wire count, which is used to record the
1355 * number of valid page table entries within the page. If the wire count
1356 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1357 * page table page was unmapped and FALSE otherwise.
1359 static inline boolean_t
1360 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1364 if (m->wire_count == 0) {
1365 _pmap_unwire_l3(pmap, va, m, free);
1372 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1375 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1377 * unmap the page table page
1379 if (m->pindex >= (NUL2E + NUL1E)) {
1383 l0 = pmap_l0(pmap, va);
1384 pmap_load_clear(l0);
1385 } else if (m->pindex >= NUL2E) {
1389 l1 = pmap_l1(pmap, va);
1390 pmap_load_clear(l1);
1395 l2 = pmap_l2(pmap, va);
1396 pmap_load_clear(l2);
1398 pmap_resident_count_dec(pmap, 1);
1399 if (m->pindex < NUL2E) {
1400 /* We just released an l3, unhold the matching l2 */
1401 pd_entry_t *l1, tl1;
1404 l1 = pmap_l1(pmap, va);
1405 tl1 = pmap_load(l1);
1406 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1407 pmap_unwire_l3(pmap, va, l2pg, free);
1408 } else if (m->pindex < (NUL2E + NUL1E)) {
1409 /* We just released an l2, unhold the matching l1 */
1410 pd_entry_t *l0, tl0;
1413 l0 = pmap_l0(pmap, va);
1414 tl0 = pmap_load(l0);
1415 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1416 pmap_unwire_l3(pmap, va, l1pg, free);
1418 pmap_invalidate_page(pmap, va);
1423 * Put page on a list so that it is released after
1424 * *ALL* TLB shootdown is done
1426 pmap_add_delayed_free_list(m, free, TRUE);
1430 * After removing a page table entry, this routine is used to
1431 * conditionally free the page, and manage the hold/wire counts.
1434 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1435 struct spglist *free)
1439 if (va >= VM_MAXUSER_ADDRESS)
1441 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1442 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1443 return (pmap_unwire_l3(pmap, va, mpte, free));
1447 pmap_pinit0(pmap_t pmap)
1450 PMAP_LOCK_INIT(pmap);
1451 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1452 pmap->pm_l0 = kernel_pmap->pm_l0;
1453 pmap->pm_root.rt_root = 0;
1457 pmap_pinit(pmap_t pmap)
1463 * allocate the l0 page
1465 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1466 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1469 l0phys = VM_PAGE_TO_PHYS(l0pt);
1470 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1472 if ((l0pt->flags & PG_ZERO) == 0)
1473 pagezero(pmap->pm_l0);
1475 pmap->pm_root.rt_root = 0;
1476 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1482 * This routine is called if the desired page table page does not exist.
1484 * If page table page allocation fails, this routine may sleep before
1485 * returning NULL. It sleeps only if a lock pointer was given.
1487 * Note: If a page allocation fails at page table level two or three,
1488 * one or two pages may be held during the wait, only to be released
1489 * afterwards. This conservative approach is easily argued to avoid
1493 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1495 vm_page_t m, l1pg, l2pg;
1497 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1500 * Allocate a page table page.
1502 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1503 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1504 if (lockp != NULL) {
1505 RELEASE_PV_LIST_LOCK(lockp);
1512 * Indicate the need to retry. While waiting, the page table
1513 * page may have been allocated.
1517 if ((m->flags & PG_ZERO) == 0)
1521 * Map the pagetable page into the process address space, if
1522 * it isn't already there.
1525 if (ptepindex >= (NUL2E + NUL1E)) {
1527 vm_pindex_t l0index;
1529 l0index = ptepindex - (NUL2E + NUL1E);
1530 l0 = &pmap->pm_l0[l0index];
1531 pmap_load_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1532 } else if (ptepindex >= NUL2E) {
1533 vm_pindex_t l0index, l1index;
1534 pd_entry_t *l0, *l1;
1537 l1index = ptepindex - NUL2E;
1538 l0index = l1index >> L0_ENTRIES_SHIFT;
1540 l0 = &pmap->pm_l0[l0index];
1541 tl0 = pmap_load(l0);
1543 /* recurse for allocating page dir */
1544 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1546 vm_page_unwire_noq(m);
1547 vm_page_free_zero(m);
1551 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1555 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1556 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1557 pmap_load_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1559 vm_pindex_t l0index, l1index;
1560 pd_entry_t *l0, *l1, *l2;
1561 pd_entry_t tl0, tl1;
1563 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1564 l0index = l1index >> L0_ENTRIES_SHIFT;
1566 l0 = &pmap->pm_l0[l0index];
1567 tl0 = pmap_load(l0);
1569 /* recurse for allocating page dir */
1570 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1572 vm_page_unwire_noq(m);
1573 vm_page_free_zero(m);
1576 tl0 = pmap_load(l0);
1577 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1578 l1 = &l1[l1index & Ln_ADDR_MASK];
1580 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1581 l1 = &l1[l1index & Ln_ADDR_MASK];
1582 tl1 = pmap_load(l1);
1584 /* recurse for allocating page dir */
1585 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1587 vm_page_unwire_noq(m);
1588 vm_page_free_zero(m);
1592 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1597 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1598 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1599 pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1602 pmap_resident_count_inc(pmap, 1);
1608 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1612 vm_pindex_t l2pindex;
1615 l1 = pmap_l1(pmap, va);
1616 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1617 /* Add a reference to the L2 page. */
1618 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1621 /* Allocate a L2 page. */
1622 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1623 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1624 if (l2pg == NULL && lockp != NULL)
1631 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1633 vm_pindex_t ptepindex;
1634 pd_entry_t *pde, tpde;
1642 * Calculate pagetable page index
1644 ptepindex = pmap_l2_pindex(va);
1647 * Get the page directory entry
1649 pde = pmap_pde(pmap, va, &lvl);
1652 * If the page table page is mapped, we just increment the hold count,
1653 * and activate it. If we get a level 2 pde it will point to a level 3
1661 pte = pmap_l0_to_l1(pde, va);
1662 KASSERT(pmap_load(pte) == 0,
1663 ("pmap_alloc_l3: TODO: l0 superpages"));
1668 pte = pmap_l1_to_l2(pde, va);
1669 KASSERT(pmap_load(pte) == 0,
1670 ("pmap_alloc_l3: TODO: l1 superpages"));
1674 tpde = pmap_load(pde);
1676 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1682 panic("pmap_alloc_l3: Invalid level %d", lvl);
1686 * Here if the pte page isn't mapped, or if it has been deallocated.
1688 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1689 if (m == NULL && lockp != NULL)
1695 /***************************************************
1696 * Pmap allocation/deallocation routines.
1697 ***************************************************/
1700 * Release any resources held by the given physical map.
1701 * Called when a pmap initialized by pmap_pinit is being released.
1702 * Should only be called if the map contains no valid mappings.
1705 pmap_release(pmap_t pmap)
1709 KASSERT(pmap->pm_stats.resident_count == 0,
1710 ("pmap_release: pmap resident count %ld != 0",
1711 pmap->pm_stats.resident_count));
1712 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1713 ("pmap_release: pmap has reserved page table page(s)"));
1715 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1717 vm_page_unwire_noq(m);
1718 vm_page_free_zero(m);
1722 kvm_size(SYSCTL_HANDLER_ARGS)
1724 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1726 return sysctl_handle_long(oidp, &ksize, 0, req);
1728 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1729 0, 0, kvm_size, "LU", "Size of KVM");
1732 kvm_free(SYSCTL_HANDLER_ARGS)
1734 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1736 return sysctl_handle_long(oidp, &kfree, 0, req);
1738 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1739 0, 0, kvm_free, "LU", "Amount of KVM free");
1742 * grow the number of kernel page table entries, if needed
1745 pmap_growkernel(vm_offset_t addr)
1749 pd_entry_t *l0, *l1, *l2;
1751 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1753 addr = roundup2(addr, L2_SIZE);
1754 if (addr - 1 >= kernel_map->max_offset)
1755 addr = kernel_map->max_offset;
1756 while (kernel_vm_end < addr) {
1757 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1758 KASSERT(pmap_load(l0) != 0,
1759 ("pmap_growkernel: No level 0 kernel entry"));
1761 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1762 if (pmap_load(l1) == 0) {
1763 /* We need a new PDP entry */
1764 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1765 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1766 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1768 panic("pmap_growkernel: no memory to grow kernel");
1769 if ((nkpg->flags & PG_ZERO) == 0)
1770 pmap_zero_page(nkpg);
1771 paddr = VM_PAGE_TO_PHYS(nkpg);
1772 pmap_load_store(l1, paddr | L1_TABLE);
1773 continue; /* try again */
1775 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1776 if ((pmap_load(l2) & ATTR_AF) != 0) {
1777 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1778 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1779 kernel_vm_end = kernel_map->max_offset;
1785 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1786 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1789 panic("pmap_growkernel: no memory to grow kernel");
1790 if ((nkpg->flags & PG_ZERO) == 0)
1791 pmap_zero_page(nkpg);
1792 paddr = VM_PAGE_TO_PHYS(nkpg);
1793 pmap_load_store(l2, paddr | L2_TABLE);
1794 pmap_invalidate_page(kernel_pmap, kernel_vm_end);
1796 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1797 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1798 kernel_vm_end = kernel_map->max_offset;
1805 /***************************************************
1806 * page management routines.
1807 ***************************************************/
1809 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1810 CTASSERT(_NPCM == 3);
1811 CTASSERT(_NPCPV == 168);
1813 static __inline struct pv_chunk *
1814 pv_to_chunk(pv_entry_t pv)
1817 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1820 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1822 #define PC_FREE0 0xfffffffffffffffful
1823 #define PC_FREE1 0xfffffffffffffffful
1824 #define PC_FREE2 0x000000fffffffffful
1826 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1830 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1832 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1833 "Current number of pv entry chunks");
1834 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1835 "Current number of pv entry chunks allocated");
1836 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1837 "Current number of pv entry chunks frees");
1838 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1839 "Number of times tried to get a chunk page but failed.");
1841 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1842 static int pv_entry_spare;
1844 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1845 "Current number of pv entry frees");
1846 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1847 "Current number of pv entry allocs");
1848 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1849 "Current number of pv entries");
1850 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1851 "Current number of spare pv entries");
1856 * We are in a serious low memory condition. Resort to
1857 * drastic measures to free some pages so we can allocate
1858 * another pv entry chunk.
1860 * Returns NULL if PV entries were reclaimed from the specified pmap.
1862 * We do not, however, unmap 2mpages because subsequent accesses will
1863 * allocate per-page pv entries until repromotion occurs, thereby
1864 * exacerbating the shortage of free pv entries.
1867 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1869 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
1870 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
1871 struct md_page *pvh;
1873 pmap_t next_pmap, pmap;
1874 pt_entry_t *pte, tpte;
1878 struct spglist free;
1880 int bit, field, freed, lvl;
1881 static int active_reclaims = 0;
1883 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1884 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
1889 bzero(&pc_marker_b, sizeof(pc_marker_b));
1890 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
1891 pc_marker = (struct pv_chunk *)&pc_marker_b;
1892 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
1894 mtx_lock(&pv_chunks_mutex);
1896 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
1897 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
1898 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
1899 SLIST_EMPTY(&free)) {
1900 next_pmap = pc->pc_pmap;
1901 if (next_pmap == NULL) {
1903 * The next chunk is a marker. However, it is
1904 * not our marker, so active_reclaims must be
1905 * > 1. Consequently, the next_chunk code
1906 * will not rotate the pv_chunks list.
1910 mtx_unlock(&pv_chunks_mutex);
1913 * A pv_chunk can only be removed from the pc_lru list
1914 * when both pv_chunks_mutex is owned and the
1915 * corresponding pmap is locked.
1917 if (pmap != next_pmap) {
1918 if (pmap != NULL && pmap != locked_pmap)
1921 /* Avoid deadlock and lock recursion. */
1922 if (pmap > locked_pmap) {
1923 RELEASE_PV_LIST_LOCK(lockp);
1925 mtx_lock(&pv_chunks_mutex);
1927 } else if (pmap != locked_pmap) {
1928 if (PMAP_TRYLOCK(pmap)) {
1929 mtx_lock(&pv_chunks_mutex);
1932 pmap = NULL; /* pmap is not locked */
1933 mtx_lock(&pv_chunks_mutex);
1934 pc = TAILQ_NEXT(pc_marker, pc_lru);
1936 pc->pc_pmap != next_pmap)
1944 * Destroy every non-wired, 4 KB page mapping in the chunk.
1947 for (field = 0; field < _NPCM; field++) {
1948 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1949 inuse != 0; inuse &= ~(1UL << bit)) {
1950 bit = ffsl(inuse) - 1;
1951 pv = &pc->pc_pventry[field * 64 + bit];
1953 pde = pmap_pde(pmap, va, &lvl);
1956 pte = pmap_l2_to_l3(pde, va);
1957 tpte = pmap_load(pte);
1958 if ((tpte & ATTR_SW_WIRED) != 0)
1960 tpte = pmap_load_clear(pte);
1961 pmap_invalidate_page(pmap, va);
1962 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
1963 if (pmap_page_dirty(tpte))
1965 if ((tpte & ATTR_AF) != 0)
1966 vm_page_aflag_set(m, PGA_REFERENCED);
1967 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1968 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
1970 if (TAILQ_EMPTY(&m->md.pv_list) &&
1971 (m->flags & PG_FICTITIOUS) == 0) {
1972 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
1973 if (TAILQ_EMPTY(&pvh->pv_list)) {
1974 vm_page_aflag_clear(m,
1978 pc->pc_map[field] |= 1UL << bit;
1979 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
1984 mtx_lock(&pv_chunks_mutex);
1987 /* Every freed mapping is for a 4 KB page. */
1988 pmap_resident_count_dec(pmap, freed);
1989 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
1990 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
1991 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
1992 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1993 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
1994 pc->pc_map[2] == PC_FREE2) {
1995 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1996 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1997 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1998 /* Entire chunk is free; return it. */
1999 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2000 dump_drop_page(m_pc->phys_addr);
2001 mtx_lock(&pv_chunks_mutex);
2002 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2005 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2006 mtx_lock(&pv_chunks_mutex);
2007 /* One freed pv entry in locked_pmap is sufficient. */
2008 if (pmap == locked_pmap)
2012 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2013 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2014 if (active_reclaims == 1 && pmap != NULL) {
2016 * Rotate the pv chunks list so that we do not
2017 * scan the same pv chunks that could not be
2018 * freed (because they contained a wired
2019 * and/or superpage mapping) on every
2020 * invocation of reclaim_pv_chunk().
2022 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2023 MPASS(pc->pc_pmap != NULL);
2024 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2025 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2029 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2030 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2032 mtx_unlock(&pv_chunks_mutex);
2033 if (pmap != NULL && pmap != locked_pmap)
2035 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2036 m_pc = SLIST_FIRST(&free);
2037 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2038 /* Recycle a freed page table page. */
2039 m_pc->wire_count = 1;
2042 vm_page_free_pages_toq(&free, false);
2047 * free the pv_entry back to the free list
2050 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2052 struct pv_chunk *pc;
2053 int idx, field, bit;
2055 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2056 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2057 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2058 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2059 pc = pv_to_chunk(pv);
2060 idx = pv - &pc->pc_pventry[0];
2063 pc->pc_map[field] |= 1ul << bit;
2064 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2065 pc->pc_map[2] != PC_FREE2) {
2066 /* 98% of the time, pc is already at the head of the list. */
2067 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2068 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2069 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2073 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2078 free_pv_chunk(struct pv_chunk *pc)
2082 mtx_lock(&pv_chunks_mutex);
2083 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2084 mtx_unlock(&pv_chunks_mutex);
2085 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2086 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2087 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2088 /* entire chunk is free, return it */
2089 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2090 dump_drop_page(m->phys_addr);
2091 vm_page_unwire_noq(m);
2096 * Returns a new PV entry, allocating a new PV chunk from the system when
2097 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2098 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2101 * The given PV list lock may be released.
2104 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2108 struct pv_chunk *pc;
2111 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2112 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2114 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2116 for (field = 0; field < _NPCM; field++) {
2117 if (pc->pc_map[field]) {
2118 bit = ffsl(pc->pc_map[field]) - 1;
2122 if (field < _NPCM) {
2123 pv = &pc->pc_pventry[field * 64 + bit];
2124 pc->pc_map[field] &= ~(1ul << bit);
2125 /* If this was the last item, move it to tail */
2126 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2127 pc->pc_map[2] == 0) {
2128 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2129 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2132 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2133 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2137 /* No free items, allocate another chunk */
2138 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2141 if (lockp == NULL) {
2142 PV_STAT(pc_chunk_tryfail++);
2145 m = reclaim_pv_chunk(pmap, lockp);
2149 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2150 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2151 dump_add_page(m->phys_addr);
2152 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2154 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2155 pc->pc_map[1] = PC_FREE1;
2156 pc->pc_map[2] = PC_FREE2;
2157 mtx_lock(&pv_chunks_mutex);
2158 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2159 mtx_unlock(&pv_chunks_mutex);
2160 pv = &pc->pc_pventry[0];
2161 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2162 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2163 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2168 * Ensure that the number of spare PV entries in the specified pmap meets or
2169 * exceeds the given count, "needed".
2171 * The given PV list lock may be released.
2174 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2176 struct pch new_tail;
2177 struct pv_chunk *pc;
2182 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2183 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2186 * Newly allocated PV chunks must be stored in a private list until
2187 * the required number of PV chunks have been allocated. Otherwise,
2188 * reclaim_pv_chunk() could recycle one of these chunks. In
2189 * contrast, these chunks must be added to the pmap upon allocation.
2191 TAILQ_INIT(&new_tail);
2194 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2195 bit_count((bitstr_t *)pc->pc_map, 0,
2196 sizeof(pc->pc_map) * NBBY, &free);
2200 if (avail >= needed)
2203 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2204 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2207 m = reclaim_pv_chunk(pmap, lockp);
2212 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2213 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2214 dump_add_page(m->phys_addr);
2215 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2217 pc->pc_map[0] = PC_FREE0;
2218 pc->pc_map[1] = PC_FREE1;
2219 pc->pc_map[2] = PC_FREE2;
2220 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2221 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2222 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2225 * The reclaim might have freed a chunk from the current pmap.
2226 * If that chunk contained available entries, we need to
2227 * re-count the number of available entries.
2232 if (!TAILQ_EMPTY(&new_tail)) {
2233 mtx_lock(&pv_chunks_mutex);
2234 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2235 mtx_unlock(&pv_chunks_mutex);
2240 * First find and then remove the pv entry for the specified pmap and virtual
2241 * address from the specified pv list. Returns the pv entry if found and NULL
2242 * otherwise. This operation can be performed on pv lists for either 4KB or
2243 * 2MB page mappings.
2245 static __inline pv_entry_t
2246 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2250 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2251 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2252 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2261 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2262 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2263 * entries for each of the 4KB page mappings.
2266 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2267 struct rwlock **lockp)
2269 struct md_page *pvh;
2270 struct pv_chunk *pc;
2272 vm_offset_t va_last;
2276 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2277 KASSERT((pa & L2_OFFSET) == 0,
2278 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2279 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2282 * Transfer the 2mpage's pv entry for this mapping to the first
2283 * page's pv list. Once this transfer begins, the pv list lock
2284 * must not be released until the last pv entry is reinstantiated.
2286 pvh = pa_to_pvh(pa);
2287 va = va & ~L2_OFFSET;
2288 pv = pmap_pvh_remove(pvh, pmap, va);
2289 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2290 m = PHYS_TO_VM_PAGE(pa);
2291 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2293 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2294 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2295 va_last = va + L2_SIZE - PAGE_SIZE;
2297 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2298 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2299 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2300 for (field = 0; field < _NPCM; field++) {
2301 while (pc->pc_map[field]) {
2302 bit = ffsl(pc->pc_map[field]) - 1;
2303 pc->pc_map[field] &= ~(1ul << bit);
2304 pv = &pc->pc_pventry[field * 64 + bit];
2308 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2309 ("pmap_pv_demote_l2: page %p is not managed", m));
2310 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2316 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2317 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2320 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2321 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2322 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2324 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2325 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2329 * First find and then destroy the pv entry for the specified pmap and virtual
2330 * address. This operation can be performed on pv lists for either 4KB or 2MB
2334 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2338 pv = pmap_pvh_remove(pvh, pmap, va);
2339 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2340 free_pv_entry(pmap, pv);
2344 * Conditionally create the PV entry for a 4KB page mapping if the required
2345 * memory can be allocated without resorting to reclamation.
2348 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2349 struct rwlock **lockp)
2353 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2354 /* Pass NULL instead of the lock pointer to disable reclamation. */
2355 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2357 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2358 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2366 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2367 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2368 * false if the PV entry cannot be allocated without resorting to reclamation.
2371 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2372 struct rwlock **lockp)
2374 struct md_page *pvh;
2378 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2379 /* Pass NULL instead of the lock pointer to disable reclamation. */
2380 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2381 NULL : lockp)) == NULL)
2384 pa = l2e & ~ATTR_MASK;
2385 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2386 pvh = pa_to_pvh(pa);
2387 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2393 * pmap_remove_l2: do the things to unmap a level 2 superpage in a process
2396 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2397 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2399 struct md_page *pvh;
2401 vm_offset_t eva, va;
2404 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2405 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2406 old_l2 = pmap_load_clear(l2);
2407 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2408 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2409 pmap_invalidate_range(pmap, sva, sva + L2_SIZE);
2410 if (old_l2 & ATTR_SW_WIRED)
2411 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2412 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2413 if (old_l2 & ATTR_SW_MANAGED) {
2414 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2415 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2416 pmap_pvh_free(pvh, pmap, sva);
2417 eva = sva + L2_SIZE;
2418 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2419 va < eva; va += PAGE_SIZE, m++) {
2420 if (pmap_page_dirty(old_l2))
2422 if (old_l2 & ATTR_AF)
2423 vm_page_aflag_set(m, PGA_REFERENCED);
2424 if (TAILQ_EMPTY(&m->md.pv_list) &&
2425 TAILQ_EMPTY(&pvh->pv_list))
2426 vm_page_aflag_clear(m, PGA_WRITEABLE);
2429 KASSERT(pmap != kernel_pmap,
2430 ("Attempting to remove an l2 kernel page"));
2431 ml3 = pmap_remove_pt_page(pmap, sva);
2433 pmap_resident_count_dec(pmap, 1);
2434 KASSERT(ml3->wire_count == NL3PG,
2435 ("pmap_remove_l2: l3 page wire count error"));
2436 ml3->wire_count = 1;
2437 vm_page_unwire_noq(ml3);
2438 pmap_add_delayed_free_list(ml3, free, FALSE);
2440 return (pmap_unuse_pt(pmap, sva, l1e, free));
2444 * pmap_remove_l3: do the things to unmap a page in a process
2447 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2448 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2450 struct md_page *pvh;
2454 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2455 old_l3 = pmap_load_clear(l3);
2456 pmap_invalidate_page(pmap, va);
2457 if (old_l3 & ATTR_SW_WIRED)
2458 pmap->pm_stats.wired_count -= 1;
2459 pmap_resident_count_dec(pmap, 1);
2460 if (old_l3 & ATTR_SW_MANAGED) {
2461 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2462 if (pmap_page_dirty(old_l3))
2464 if (old_l3 & ATTR_AF)
2465 vm_page_aflag_set(m, PGA_REFERENCED);
2466 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2467 pmap_pvh_free(&m->md, pmap, va);
2468 if (TAILQ_EMPTY(&m->md.pv_list) &&
2469 (m->flags & PG_FICTITIOUS) == 0) {
2470 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2471 if (TAILQ_EMPTY(&pvh->pv_list))
2472 vm_page_aflag_clear(m, PGA_WRITEABLE);
2475 return (pmap_unuse_pt(pmap, va, l2e, free));
2479 * Remove the given range of addresses from the specified map.
2481 * It is assumed that the start and end are properly
2482 * rounded to the page size.
2485 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2487 struct rwlock *lock;
2488 vm_offset_t va, va_next;
2489 pd_entry_t *l0, *l1, *l2;
2490 pt_entry_t l3_paddr, *l3;
2491 struct spglist free;
2494 * Perform an unsynchronized read. This is, however, safe.
2496 if (pmap->pm_stats.resident_count == 0)
2504 for (; sva < eva; sva = va_next) {
2506 if (pmap->pm_stats.resident_count == 0)
2509 l0 = pmap_l0(pmap, sva);
2510 if (pmap_load(l0) == 0) {
2511 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2517 l1 = pmap_l0_to_l1(l0, sva);
2518 if (pmap_load(l1) == 0) {
2519 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2526 * Calculate index for next page table.
2528 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2532 l2 = pmap_l1_to_l2(l1, sva);
2536 l3_paddr = pmap_load(l2);
2538 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2539 if (sva + L2_SIZE == va_next && eva >= va_next) {
2540 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2543 } else if (pmap_demote_l2_locked(pmap, l2,
2544 sva &~L2_OFFSET, &lock) == NULL)
2546 l3_paddr = pmap_load(l2);
2550 * Weed out invalid mappings.
2552 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2556 * Limit our scan to either the end of the va represented
2557 * by the current page table page, or to the end of the
2558 * range being removed.
2564 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2567 panic("l3 == NULL");
2568 if (pmap_load(l3) == 0) {
2569 if (va != va_next) {
2570 pmap_invalidate_range(pmap, va, sva);
2577 if (pmap_remove_l3(pmap, l3, sva, l3_paddr, &free,
2584 pmap_invalidate_range(pmap, va, sva);
2589 vm_page_free_pages_toq(&free, false);
2593 * Routine: pmap_remove_all
2595 * Removes this physical page from
2596 * all physical maps in which it resides.
2597 * Reflects back modify bits to the pager.
2600 * Original versions of this routine were very
2601 * inefficient because they iteratively called
2602 * pmap_remove (slow...)
2606 pmap_remove_all(vm_page_t m)
2608 struct md_page *pvh;
2611 struct rwlock *lock;
2612 pd_entry_t *pde, tpde;
2613 pt_entry_t *pte, tpte;
2615 struct spglist free;
2616 int lvl, pvh_gen, md_gen;
2618 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2619 ("pmap_remove_all: page %p is not managed", m));
2621 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2622 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2623 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2626 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2628 if (!PMAP_TRYLOCK(pmap)) {
2629 pvh_gen = pvh->pv_gen;
2633 if (pvh_gen != pvh->pv_gen) {
2640 pte = pmap_pte(pmap, va, &lvl);
2641 KASSERT(pte != NULL,
2642 ("pmap_remove_all: no page table entry found"));
2644 ("pmap_remove_all: invalid pte level %d", lvl));
2646 pmap_demote_l2_locked(pmap, pte, va, &lock);
2649 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2651 if (!PMAP_TRYLOCK(pmap)) {
2652 pvh_gen = pvh->pv_gen;
2653 md_gen = m->md.pv_gen;
2657 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2663 pmap_resident_count_dec(pmap, 1);
2665 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2666 KASSERT(pde != NULL,
2667 ("pmap_remove_all: no page directory entry found"));
2669 ("pmap_remove_all: invalid pde level %d", lvl));
2670 tpde = pmap_load(pde);
2672 pte = pmap_l2_to_l3(pde, pv->pv_va);
2673 tpte = pmap_load(pte);
2674 pmap_load_clear(pte);
2675 pmap_invalidate_page(pmap, pv->pv_va);
2676 if (tpte & ATTR_SW_WIRED)
2677 pmap->pm_stats.wired_count--;
2678 if ((tpte & ATTR_AF) != 0)
2679 vm_page_aflag_set(m, PGA_REFERENCED);
2682 * Update the vm_page_t clean and reference bits.
2684 if (pmap_page_dirty(tpte))
2686 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2687 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2689 free_pv_entry(pmap, pv);
2692 vm_page_aflag_clear(m, PGA_WRITEABLE);
2694 vm_page_free_pages_toq(&free, false);
2698 * Set the physical protection on the
2699 * specified range of this map as requested.
2702 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2704 vm_offset_t va, va_next;
2705 pd_entry_t *l0, *l1, *l2;
2706 pt_entry_t *l3p, l3, nbits;
2708 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
2709 if (prot == VM_PROT_NONE) {
2710 pmap_remove(pmap, sva, eva);
2714 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
2715 (VM_PROT_WRITE | VM_PROT_EXECUTE))
2719 for (; sva < eva; sva = va_next) {
2721 l0 = pmap_l0(pmap, sva);
2722 if (pmap_load(l0) == 0) {
2723 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2729 l1 = pmap_l0_to_l1(l0, sva);
2730 if (pmap_load(l1) == 0) {
2731 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2737 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2741 l2 = pmap_l1_to_l2(l1, sva);
2742 if (pmap_load(l2) == 0)
2745 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
2746 l3p = pmap_demote_l2(pmap, l2, sva);
2750 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
2751 ("pmap_protect: Invalid L2 entry after demotion"));
2757 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2759 l3 = pmap_load(l3p);
2760 if (!pmap_l3_valid(l3))
2764 if ((prot & VM_PROT_WRITE) == 0) {
2765 if ((l3 & ATTR_SW_MANAGED) &&
2766 pmap_page_dirty(l3)) {
2767 vm_page_dirty(PHYS_TO_VM_PAGE(l3 &
2770 nbits |= ATTR_AP(ATTR_AP_RO);
2772 if ((prot & VM_PROT_EXECUTE) == 0)
2775 pmap_set(l3p, nbits);
2776 /* XXX: Use pmap_invalidate_range */
2777 pmap_invalidate_page(pmap, sva);
2784 * Inserts the specified page table page into the specified pmap's collection
2785 * of idle page table pages. Each of a pmap's page table pages is responsible
2786 * for mapping a distinct range of virtual addresses. The pmap's collection is
2787 * ordered by this virtual address range.
2790 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2793 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2794 return (vm_radix_insert(&pmap->pm_root, mpte));
2798 * Removes the page table page mapping the specified virtual address from the
2799 * specified pmap's collection of idle page table pages, and returns it.
2800 * Otherwise, returns NULL if there is no page table page corresponding to the
2801 * specified virtual address.
2803 static __inline vm_page_t
2804 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2807 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2808 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
2812 * Performs a break-before-make update of a pmap entry. This is needed when
2813 * either promoting or demoting pages to ensure the TLB doesn't get into an
2814 * inconsistent state.
2817 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
2818 vm_offset_t va, vm_size_t size)
2822 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2825 * Ensure we don't get switched out with the page table in an
2826 * inconsistent state. We also need to ensure no interrupts fire
2827 * as they may make use of an address we are about to invalidate.
2829 intr = intr_disable();
2832 /* Clear the old mapping */
2833 pmap_load_clear(pte);
2834 pmap_invalidate_range_nopin(pmap, va, va + size);
2836 /* Create the new mapping */
2837 pmap_load_store(pte, newpte);
2843 #if VM_NRESERVLEVEL > 0
2845 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
2846 * replace the many pv entries for the 4KB page mappings by a single pv entry
2847 * for the 2MB page mapping.
2850 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2851 struct rwlock **lockp)
2853 struct md_page *pvh;
2855 vm_offset_t va_last;
2858 KASSERT((pa & L2_OFFSET) == 0,
2859 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
2860 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2863 * Transfer the first page's pv entry for this mapping to the 2mpage's
2864 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
2865 * a transfer avoids the possibility that get_pv_entry() calls
2866 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
2867 * mappings that is being promoted.
2869 m = PHYS_TO_VM_PAGE(pa);
2870 va = va & ~L2_OFFSET;
2871 pv = pmap_pvh_remove(&m->md, pmap, va);
2872 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
2873 pvh = pa_to_pvh(pa);
2874 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2876 /* Free the remaining NPTEPG - 1 pv entries. */
2877 va_last = va + L2_SIZE - PAGE_SIZE;
2881 pmap_pvh_free(&m->md, pmap, va);
2882 } while (va < va_last);
2886 * Tries to promote the 512, contiguous 4KB page mappings that are within a
2887 * single level 2 table entry to a single 2MB page mapping. For promotion
2888 * to occur, two conditions must be met: (1) the 4KB page mappings must map
2889 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
2890 * identical characteristics.
2893 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
2894 struct rwlock **lockp)
2896 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
2900 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2902 sva = va & ~L2_OFFSET;
2903 firstl3 = pmap_l2_to_l3(l2, sva);
2904 newl2 = pmap_load(firstl3);
2906 /* Check the alingment is valid */
2907 if (((newl2 & ~ATTR_MASK) & L2_OFFSET) != 0) {
2908 atomic_add_long(&pmap_l2_p_failures, 1);
2909 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2910 " in pmap %p", va, pmap);
2914 pa = newl2 + L2_SIZE - PAGE_SIZE;
2915 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
2916 oldl3 = pmap_load(l3);
2918 atomic_add_long(&pmap_l2_p_failures, 1);
2919 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2920 " in pmap %p", va, pmap);
2927 * Save the page table page in its current state until the L2
2928 * mapping the superpage is demoted by pmap_demote_l2() or
2929 * destroyed by pmap_remove_l3().
2931 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
2932 KASSERT(mpte >= vm_page_array &&
2933 mpte < &vm_page_array[vm_page_array_size],
2934 ("pmap_promote_l2: page table page is out of range"));
2935 KASSERT(mpte->pindex == pmap_l2_pindex(va),
2936 ("pmap_promote_l2: page table page's pindex is wrong"));
2937 if (pmap_insert_pt_page(pmap, mpte)) {
2938 atomic_add_long(&pmap_l2_p_failures, 1);
2940 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
2945 if ((newl2 & ATTR_SW_MANAGED) != 0)
2946 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
2948 newl2 &= ~ATTR_DESCR_MASK;
2951 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
2953 atomic_add_long(&pmap_l2_promotions, 1);
2954 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
2957 #endif /* VM_NRESERVLEVEL > 0 */
2960 * Insert the given physical page (p) at
2961 * the specified virtual address (v) in the
2962 * target physical map with the protection requested.
2964 * If specified, the page will be wired down, meaning
2965 * that the related pte can not be reclaimed.
2967 * NB: This is the only routine which MAY NOT lazy-evaluate
2968 * or lose information. That is, this routine must actually
2969 * insert this page into the given map NOW.
2972 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2973 u_int flags, int8_t psind)
2975 struct rwlock *lock;
2977 pt_entry_t new_l3, orig_l3;
2978 pt_entry_t *l2, *l3;
2980 vm_paddr_t opa, pa, l1_pa, l2_pa, l3_pa;
2981 vm_page_t mpte, om, l1_m, l2_m, l3_m;
2985 va = trunc_page(va);
2986 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2987 VM_OBJECT_ASSERT_LOCKED(m->object);
2988 pa = VM_PAGE_TO_PHYS(m);
2989 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
2991 if ((prot & VM_PROT_WRITE) == 0)
2992 new_l3 |= ATTR_AP(ATTR_AP_RO);
2993 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
2995 if ((flags & PMAP_ENTER_WIRED) != 0)
2996 new_l3 |= ATTR_SW_WIRED;
2997 if (va < VM_MAXUSER_ADDRESS)
2998 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
2999 if ((m->oflags & VPO_UNMANAGED) == 0)
3000 new_l3 |= ATTR_SW_MANAGED;
3002 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3008 /* Assert the required virtual and physical alignment. */
3009 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3010 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3011 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3016 pde = pmap_pde(pmap, va, &lvl);
3017 if (pde != NULL && lvl == 1) {
3018 l2 = pmap_l1_to_l2(pde, va);
3019 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3020 (l3 = pmap_demote_l2_locked(pmap, l2, va & ~L2_OFFSET,
3022 l3 = &l3[pmap_l3_index(va)];
3023 if (va < VM_MAXUSER_ADDRESS) {
3024 mpte = PHYS_TO_VM_PAGE(
3025 pmap_load(l2) & ~ATTR_MASK);
3032 if (va < VM_MAXUSER_ADDRESS) {
3033 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
3034 mpte = pmap_alloc_l3(pmap, va, nosleep ? NULL : &lock);
3035 if (mpte == NULL && nosleep) {
3036 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3040 return (KERN_RESOURCE_SHORTAGE);
3042 pde = pmap_pde(pmap, va, &lvl);
3043 KASSERT(pde != NULL,
3044 ("pmap_enter: Invalid page entry, va: 0x%lx", va));
3046 ("pmap_enter: Invalid level %d", lvl));
3049 * If we get a level 2 pde it must point to a level 3 entry
3050 * otherwise we will need to create the intermediate tables
3056 /* Get the l0 pde to update */
3057 pde = pmap_l0(pmap, va);
3058 KASSERT(pde != NULL, ("..."));
3060 l1_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3061 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3064 panic("pmap_enter: l1 pte_m == NULL");
3065 if ((l1_m->flags & PG_ZERO) == 0)
3066 pmap_zero_page(l1_m);
3068 l1_pa = VM_PAGE_TO_PHYS(l1_m);
3069 pmap_load_store(pde, l1_pa | L0_TABLE);
3072 /* Get the l1 pde to update */
3073 pde = pmap_l1_to_l2(pde, va);
3074 KASSERT(pde != NULL, ("..."));
3076 l2_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3077 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3080 panic("pmap_enter: l2 pte_m == NULL");
3081 if ((l2_m->flags & PG_ZERO) == 0)
3082 pmap_zero_page(l2_m);
3084 l2_pa = VM_PAGE_TO_PHYS(l2_m);
3085 pmap_load_store(pde, l2_pa | L1_TABLE);
3088 /* Get the l2 pde to update */
3089 pde = pmap_l1_to_l2(pde, va);
3090 KASSERT(pde != NULL, ("..."));
3092 l3_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3093 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3096 panic("pmap_enter: l3 pte_m == NULL");
3097 if ((l3_m->flags & PG_ZERO) == 0)
3098 pmap_zero_page(l3_m);
3100 l3_pa = VM_PAGE_TO_PHYS(l3_m);
3101 pmap_load_store(pde, l3_pa | L2_TABLE);
3106 l3 = pmap_l2_to_l3(pde, va);
3109 orig_l3 = pmap_load(l3);
3110 opa = orig_l3 & ~ATTR_MASK;
3114 * Is the specified virtual address already mapped?
3116 if (pmap_l3_valid(orig_l3)) {
3118 * Wiring change, just update stats. We don't worry about
3119 * wiring PT pages as they remain resident as long as there
3120 * are valid mappings in them. Hence, if a user page is wired,
3121 * the PT page will be also.
3123 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3124 (orig_l3 & ATTR_SW_WIRED) == 0)
3125 pmap->pm_stats.wired_count++;
3126 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3127 (orig_l3 & ATTR_SW_WIRED) != 0)
3128 pmap->pm_stats.wired_count--;
3131 * Remove the extra PT page reference.
3135 KASSERT(mpte->wire_count > 0,
3136 ("pmap_enter: missing reference to page table page,"
3141 * Has the physical page changed?
3145 * No, might be a protection or wiring change.
3147 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3148 if ((new_l3 & ATTR_AP(ATTR_AP_RW)) ==
3149 ATTR_AP(ATTR_AP_RW)) {
3150 vm_page_aflag_set(m, PGA_WRITEABLE);
3157 * The physical page has changed.
3159 (void)pmap_load_clear(l3);
3160 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
3161 ("pmap_enter: unexpected pa update for %#lx", va));
3162 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3163 om = PHYS_TO_VM_PAGE(opa);
3166 * The pmap lock is sufficient to synchronize with
3167 * concurrent calls to pmap_page_test_mappings() and
3168 * pmap_ts_referenced().
3170 if (pmap_page_dirty(orig_l3))
3172 if ((orig_l3 & ATTR_AF) != 0)
3173 vm_page_aflag_set(om, PGA_REFERENCED);
3174 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3175 pv = pmap_pvh_remove(&om->md, pmap, va);
3176 if ((m->oflags & VPO_UNMANAGED) != 0)
3177 free_pv_entry(pmap, pv);
3178 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3179 TAILQ_EMPTY(&om->md.pv_list) &&
3180 ((om->flags & PG_FICTITIOUS) != 0 ||
3181 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3182 vm_page_aflag_clear(om, PGA_WRITEABLE);
3184 pmap_invalidate_page(pmap, va);
3188 * Increment the counters.
3190 if ((new_l3 & ATTR_SW_WIRED) != 0)
3191 pmap->pm_stats.wired_count++;
3192 pmap_resident_count_inc(pmap, 1);
3195 * Enter on the PV list if part of our managed memory.
3197 if ((m->oflags & VPO_UNMANAGED) == 0) {
3199 pv = get_pv_entry(pmap, &lock);
3202 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3203 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3205 if ((new_l3 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3206 vm_page_aflag_set(m, PGA_WRITEABLE);
3211 * Sync icache if exec permission and attribute VM_MEMATTR_WRITE_BACK
3212 * is set. Do it now, before the mapping is stored and made
3213 * valid for hardware table walk. If done later, then other can
3214 * access this page before caches are properly synced.
3215 * Don't do it for kernel memory which is mapped with exec
3216 * permission even if the memory isn't going to hold executable
3217 * code. The only time when icache sync is needed is after
3218 * kernel module is loaded and the relocation info is processed.
3219 * And it's done in elf_cpu_load_file().
3221 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3222 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3223 (opa != pa || (orig_l3 & ATTR_XN)))
3224 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3227 * Update the L3 entry
3229 if (pmap_l3_valid(orig_l3)) {
3230 KASSERT(opa == pa, ("pmap_enter: invalid update"));
3231 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3232 /* same PA, different attributes */
3233 pmap_load_store(l3, new_l3);
3234 pmap_invalidate_page(pmap, va);
3235 if (pmap_page_dirty(orig_l3) &&
3236 (orig_l3 & ATTR_SW_MANAGED) != 0)
3241 * This can happens if multiple threads simultaneously
3242 * access not yet mapped page. This bad for performance
3243 * since this can cause full demotion-NOP-promotion
3245 * Another possible reasons are:
3246 * - VM and pmap memory layout are diverged
3247 * - tlb flush is missing somewhere and CPU doesn't see
3250 CTR4(KTR_PMAP, "%s: already mapped page - "
3251 "pmap %p va 0x%#lx pte 0x%lx",
3252 __func__, pmap, va, new_l3);
3256 pmap_load_store(l3, new_l3);
3259 #if VM_NRESERVLEVEL > 0
3260 if (pmap != pmap_kernel() &&
3261 (mpte == NULL || mpte->wire_count == NL3PG) &&
3262 pmap_ps_enabled(pmap) &&
3263 (m->flags & PG_FICTITIOUS) == 0 &&
3264 vm_reserv_level_iffullpop(m) == 0) {
3265 pmap_promote_l2(pmap, pde, va, &lock);
3278 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
3279 * if successful. Returns false if (1) a page table page cannot be allocated
3280 * without sleeping, (2) a mapping already exists at the specified virtual
3281 * address, or (3) a PV entry cannot be allocated without reclaiming another
3285 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3286 struct rwlock **lockp)
3290 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3292 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
3293 ATTR_IDX(m->md.pv_memattr) | ATTR_AP(ATTR_AP_RO) | L2_BLOCK);
3294 if ((m->oflags & VPO_UNMANAGED) == 0)
3295 new_l2 |= ATTR_SW_MANAGED;
3296 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3298 if (va < VM_MAXUSER_ADDRESS)
3299 new_l2 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3300 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
3301 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
3306 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
3307 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
3308 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
3309 * a mapping already exists at the specified virtual address. Returns
3310 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
3311 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
3312 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3314 * The parameter "m" is only used when creating a managed, writeable mapping.
3317 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
3318 vm_page_t m, struct rwlock **lockp)
3320 struct spglist free;
3321 pd_entry_t *l2, *l3, old_l2;
3325 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3327 if ((l2pg = pmap_alloc_l2(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
3328 NULL : lockp)) == NULL) {
3329 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
3331 return (KERN_RESOURCE_SHORTAGE);
3334 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
3335 l2 = &l2[pmap_l2_index(va)];
3336 if ((old_l2 = pmap_load(l2)) != 0) {
3337 KASSERT(l2pg->wire_count > 1,
3338 ("pmap_enter_l2: l2pg's wire count is too low"));
3339 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3342 "pmap_enter_l2: failure for va %#lx in pmap %p",
3344 return (KERN_FAILURE);
3347 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
3348 (void)pmap_remove_l2(pmap, l2, va,
3349 pmap_load(pmap_l1(pmap, va)), &free, lockp);
3351 for (sva = va; sva < va + L2_SIZE; sva += PAGE_SIZE) {
3352 l3 = pmap_l2_to_l3(l2, sva);
3353 if (pmap_l3_valid(pmap_load(l3)) &&
3354 pmap_remove_l3(pmap, l3, sva, old_l2, &free,
3358 vm_page_free_pages_toq(&free, true);
3359 if (va >= VM_MAXUSER_ADDRESS) {
3360 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3361 if (pmap_insert_pt_page(pmap, mt)) {
3363 * XXX Currently, this can't happen bacuse
3364 * we do not perform pmap_enter(psind == 1)
3365 * on the kernel pmap.
3367 panic("pmap_enter_l2: trie insert failed");
3370 KASSERT(pmap_load(l2) == 0,
3371 ("pmap_enter_l2: non-zero L2 entry %p", l2));
3374 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
3376 * Abort this mapping if its PV entry could not be created.
3378 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
3380 if (pmap_unwire_l3(pmap, va, l2pg, &free)) {
3382 * Although "va" is not mapped, paging-structure
3383 * caches could nonetheless have entries that
3384 * refer to the freed page table pages.
3385 * Invalidate those entries.
3387 pmap_invalidate_page(pmap, va);
3388 vm_page_free_pages_toq(&free, true);
3391 "pmap_enter_l2: failure for va %#lx in pmap %p",
3393 return (KERN_RESOURCE_SHORTAGE);
3395 if ((new_l2 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3396 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3397 vm_page_aflag_set(mt, PGA_WRITEABLE);
3401 * Increment counters.
3403 if ((new_l2 & ATTR_SW_WIRED) != 0)
3404 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
3405 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
3408 * Map the superpage.
3410 (void)pmap_load_store(l2, new_l2);
3412 atomic_add_long(&pmap_l2_mappings, 1);
3413 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
3416 return (KERN_SUCCESS);
3420 * Maps a sequence of resident pages belonging to the same object.
3421 * The sequence begins with the given page m_start. This page is
3422 * mapped at the given virtual address start. Each subsequent page is
3423 * mapped at a virtual address that is offset from start by the same
3424 * amount as the page is offset from m_start within the object. The
3425 * last page in the sequence is the page with the largest offset from
3426 * m_start that can be mapped at a virtual address less than the given
3427 * virtual address end. Not every virtual page between start and end
3428 * is mapped; only those for which a resident page exists with the
3429 * corresponding offset from m_start are mapped.
3432 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3433 vm_page_t m_start, vm_prot_t prot)
3435 struct rwlock *lock;
3438 vm_pindex_t diff, psize;
3440 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3442 psize = atop(end - start);
3447 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3448 va = start + ptoa(diff);
3449 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
3450 m->psind == 1 && pmap_ps_enabled(pmap) &&
3451 pmap_enter_2mpage(pmap, va, m, prot, &lock))
3452 m = &m[L2_SIZE / PAGE_SIZE - 1];
3454 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
3456 m = TAILQ_NEXT(m, listq);
3464 * this code makes some *MAJOR* assumptions:
3465 * 1. Current pmap & pmap exists.
3468 * 4. No page table pages.
3469 * but is *MUCH* faster than pmap_enter...
3473 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3475 struct rwlock *lock;
3479 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3486 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3487 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3489 struct spglist free;
3491 pt_entry_t *l2, *l3, l3_val;
3495 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3496 (m->oflags & VPO_UNMANAGED) != 0,
3497 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3498 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3500 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3502 * In the case that a page table page is not
3503 * resident, we are creating it here.
3505 if (va < VM_MAXUSER_ADDRESS) {
3506 vm_pindex_t l2pindex;
3509 * Calculate pagetable page index
3511 l2pindex = pmap_l2_pindex(va);
3512 if (mpte && (mpte->pindex == l2pindex)) {
3518 pde = pmap_pde(pmap, va, &lvl);
3521 * If the page table page is mapped, we just increment
3522 * the hold count, and activate it. Otherwise, we
3523 * attempt to allocate a page table page. If this
3524 * attempt fails, we don't retry. Instead, we give up.
3527 l2 = pmap_l1_to_l2(pde, va);
3528 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3532 if (lvl == 2 && pmap_load(pde) != 0) {
3534 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3538 * Pass NULL instead of the PV list lock
3539 * pointer, because we don't intend to sleep.
3541 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3546 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3547 l3 = &l3[pmap_l3_index(va)];
3550 pde = pmap_pde(kernel_pmap, va, &lvl);
3551 KASSERT(pde != NULL,
3552 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3555 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3556 l3 = pmap_l2_to_l3(pde, va);
3559 if (pmap_load(l3) != 0) {
3568 * Enter on the PV list if part of our managed memory.
3570 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3571 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3574 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
3575 pmap_invalidate_page(pmap, va);
3576 vm_page_free_pages_toq(&free, false);
3584 * Increment counters
3586 pmap_resident_count_inc(pmap, 1);
3588 pa = VM_PAGE_TO_PHYS(m);
3589 l3_val = pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3590 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3591 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3593 else if (va < VM_MAXUSER_ADDRESS)
3597 * Now validate mapping with RO protection
3599 if ((m->oflags & VPO_UNMANAGED) == 0)
3600 l3_val |= ATTR_SW_MANAGED;
3602 /* Sync icache before the mapping is stored to PTE */
3603 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3604 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
3605 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3607 pmap_load_store(l3, l3_val);
3608 pmap_invalidate_page(pmap, va);
3613 * This code maps large physical mmap regions into the
3614 * processor address space. Note that some shortcuts
3615 * are taken, but the code works.
3618 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3619 vm_pindex_t pindex, vm_size_t size)
3622 VM_OBJECT_ASSERT_WLOCKED(object);
3623 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3624 ("pmap_object_init_pt: non-device object"));
3628 * Clear the wired attribute from the mappings for the specified range of
3629 * addresses in the given pmap. Every valid mapping within that range
3630 * must have the wired attribute set. In contrast, invalid mappings
3631 * cannot have the wired attribute set, so they are ignored.
3633 * The wired attribute of the page table entry is not a hardware feature,
3634 * so there is no need to invalidate any TLB entries.
3637 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3639 vm_offset_t va_next;
3640 pd_entry_t *l0, *l1, *l2;
3644 for (; sva < eva; sva = va_next) {
3645 l0 = pmap_l0(pmap, sva);
3646 if (pmap_load(l0) == 0) {
3647 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3653 l1 = pmap_l0_to_l1(l0, sva);
3654 if (pmap_load(l1) == 0) {
3655 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3661 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3665 l2 = pmap_l1_to_l2(l1, sva);
3666 if (pmap_load(l2) == 0)
3669 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3670 l3 = pmap_demote_l2(pmap, l2, sva);
3674 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3675 ("pmap_unwire: Invalid l2 entry after demotion"));
3679 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3681 if (pmap_load(l3) == 0)
3683 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
3684 panic("pmap_unwire: l3 %#jx is missing "
3685 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
3688 * PG_W must be cleared atomically. Although the pmap
3689 * lock synchronizes access to PG_W, another processor
3690 * could be setting PG_M and/or PG_A concurrently.
3692 atomic_clear_long(l3, ATTR_SW_WIRED);
3693 pmap->pm_stats.wired_count--;
3700 * Copy the range specified by src_addr/len
3701 * from the source map to the range dst_addr/len
3702 * in the destination map.
3704 * This routine is only advisory and need not do anything.
3708 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3709 vm_offset_t src_addr)
3714 * pmap_zero_page zeros the specified hardware page by mapping
3715 * the page into KVM and using bzero to clear its contents.
3718 pmap_zero_page(vm_page_t m)
3720 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3722 pagezero((void *)va);
3726 * pmap_zero_page_area zeros the specified hardware page by mapping
3727 * the page into KVM and using bzero to clear its contents.
3729 * off and size may not cover an area beyond a single hardware page.
3732 pmap_zero_page_area(vm_page_t m, int off, int size)
3734 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3736 if (off == 0 && size == PAGE_SIZE)
3737 pagezero((void *)va);
3739 bzero((char *)va + off, size);
3743 * pmap_copy_page copies the specified (machine independent)
3744 * page by mapping the page into virtual memory and using
3745 * bcopy to copy the page, one machine dependent page at a
3749 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
3751 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
3752 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
3754 pagecopy((void *)src, (void *)dst);
3757 int unmapped_buf_allowed = 1;
3760 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
3761 vm_offset_t b_offset, int xfersize)
3765 vm_paddr_t p_a, p_b;
3766 vm_offset_t a_pg_offset, b_pg_offset;
3769 while (xfersize > 0) {
3770 a_pg_offset = a_offset & PAGE_MASK;
3771 m_a = ma[a_offset >> PAGE_SHIFT];
3772 p_a = m_a->phys_addr;
3773 b_pg_offset = b_offset & PAGE_MASK;
3774 m_b = mb[b_offset >> PAGE_SHIFT];
3775 p_b = m_b->phys_addr;
3776 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
3777 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
3778 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
3779 panic("!DMAP a %lx", p_a);
3781 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
3783 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
3784 panic("!DMAP b %lx", p_b);
3786 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
3788 bcopy(a_cp, b_cp, cnt);
3796 pmap_quick_enter_page(vm_page_t m)
3799 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
3803 pmap_quick_remove_page(vm_offset_t addr)
3808 * Returns true if the pmap's pv is one of the first
3809 * 16 pvs linked to from this page. This count may
3810 * be changed upwards or downwards in the future; it
3811 * is only necessary that true be returned for a small
3812 * subset of pmaps for proper page aging.
3815 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3817 struct md_page *pvh;
3818 struct rwlock *lock;
3823 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3824 ("pmap_page_exists_quick: page %p is not managed", m));
3826 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3828 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3829 if (PV_PMAP(pv) == pmap) {
3837 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
3838 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3839 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3840 if (PV_PMAP(pv) == pmap) {
3854 * pmap_page_wired_mappings:
3856 * Return the number of managed mappings to the given physical page
3860 pmap_page_wired_mappings(vm_page_t m)
3862 struct rwlock *lock;
3863 struct md_page *pvh;
3867 int count, lvl, md_gen, pvh_gen;
3869 if ((m->oflags & VPO_UNMANAGED) != 0)
3871 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3875 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3877 if (!PMAP_TRYLOCK(pmap)) {
3878 md_gen = m->md.pv_gen;
3882 if (md_gen != m->md.pv_gen) {
3887 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3888 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3892 if ((m->flags & PG_FICTITIOUS) == 0) {
3893 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3894 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3896 if (!PMAP_TRYLOCK(pmap)) {
3897 md_gen = m->md.pv_gen;
3898 pvh_gen = pvh->pv_gen;
3902 if (md_gen != m->md.pv_gen ||
3903 pvh_gen != pvh->pv_gen) {
3908 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3910 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3920 * Destroy all managed, non-wired mappings in the given user-space
3921 * pmap. This pmap cannot be active on any processor besides the
3924 * This function cannot be applied to the kernel pmap. Moreover, it
3925 * is not intended for general use. It is only to be used during
3926 * process termination. Consequently, it can be implemented in ways
3927 * that make it faster than pmap_remove(). First, it can more quickly
3928 * destroy mappings by iterating over the pmap's collection of PV
3929 * entries, rather than searching the page table. Second, it doesn't
3930 * have to test and clear the page table entries atomically, because
3931 * no processor is currently accessing the user address space. In
3932 * particular, a page table entry's dirty bit won't change state once
3933 * this function starts.
3936 pmap_remove_pages(pmap_t pmap)
3939 pt_entry_t *pte, tpte;
3940 struct spglist free;
3941 vm_page_t m, ml3, mt;
3943 struct md_page *pvh;
3944 struct pv_chunk *pc, *npc;
3945 struct rwlock *lock;
3947 uint64_t inuse, bitmask;
3948 int allfree, field, freed, idx, lvl;
3955 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
3958 for (field = 0; field < _NPCM; field++) {
3959 inuse = ~pc->pc_map[field] & pc_freemask[field];
3960 while (inuse != 0) {
3961 bit = ffsl(inuse) - 1;
3962 bitmask = 1UL << bit;
3963 idx = field * 64 + bit;
3964 pv = &pc->pc_pventry[idx];
3967 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3968 KASSERT(pde != NULL,
3969 ("Attempting to remove an unmapped page"));
3973 pte = pmap_l1_to_l2(pde, pv->pv_va);
3974 tpte = pmap_load(pte);
3975 KASSERT((tpte & ATTR_DESCR_MASK) ==
3977 ("Attempting to remove an invalid "
3978 "block: %lx", tpte));
3979 tpte = pmap_load(pte);
3982 pte = pmap_l2_to_l3(pde, pv->pv_va);
3983 tpte = pmap_load(pte);
3984 KASSERT((tpte & ATTR_DESCR_MASK) ==
3986 ("Attempting to remove an invalid "
3987 "page: %lx", tpte));
3991 "Invalid page directory level: %d",
3996 * We cannot remove wired pages from a process' mapping at this time
3998 if (tpte & ATTR_SW_WIRED) {
4003 pa = tpte & ~ATTR_MASK;
4005 m = PHYS_TO_VM_PAGE(pa);
4006 KASSERT(m->phys_addr == pa,
4007 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4008 m, (uintmax_t)m->phys_addr,
4011 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4012 m < &vm_page_array[vm_page_array_size],
4013 ("pmap_remove_pages: bad pte %#jx",
4016 pmap_load_clear(pte);
4019 * Update the vm_page_t clean/reference bits.
4021 if ((tpte & ATTR_AP_RW_BIT) ==
4022 ATTR_AP(ATTR_AP_RW)) {
4025 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4034 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4037 pc->pc_map[field] |= bitmask;
4040 pmap_resident_count_dec(pmap,
4041 L2_SIZE / PAGE_SIZE);
4042 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
4043 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
4045 if (TAILQ_EMPTY(&pvh->pv_list)) {
4046 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4047 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
4048 TAILQ_EMPTY(&mt->md.pv_list))
4049 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4051 ml3 = pmap_remove_pt_page(pmap,
4054 pmap_resident_count_dec(pmap,1);
4055 KASSERT(ml3->wire_count == NL3PG,
4056 ("pmap_remove_pages: l3 page wire count error"));
4057 ml3->wire_count = 1;
4058 vm_page_unwire_noq(ml3);
4059 pmap_add_delayed_free_list(ml3,
4064 pmap_resident_count_dec(pmap, 1);
4065 TAILQ_REMOVE(&m->md.pv_list, pv,
4068 if ((m->aflags & PGA_WRITEABLE) != 0 &&
4069 TAILQ_EMPTY(&m->md.pv_list) &&
4070 (m->flags & PG_FICTITIOUS) == 0) {
4072 VM_PAGE_TO_PHYS(m));
4073 if (TAILQ_EMPTY(&pvh->pv_list))
4074 vm_page_aflag_clear(m,
4079 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
4084 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4085 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4086 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4088 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4092 pmap_invalidate_all(pmap);
4096 vm_page_free_pages_toq(&free, false);
4100 * This is used to check if a page has been accessed or modified. As we
4101 * don't have a bit to see if it has been modified we have to assume it
4102 * has been if the page is read/write.
4105 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
4107 struct rwlock *lock;
4109 struct md_page *pvh;
4110 pt_entry_t *pte, mask, value;
4112 int lvl, md_gen, pvh_gen;
4116 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4119 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4121 if (!PMAP_TRYLOCK(pmap)) {
4122 md_gen = m->md.pv_gen;
4126 if (md_gen != m->md.pv_gen) {
4131 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4133 ("pmap_page_test_mappings: Invalid level %d", lvl));
4137 mask |= ATTR_AP_RW_BIT;
4138 value |= ATTR_AP(ATTR_AP_RW);
4141 mask |= ATTR_AF | ATTR_DESCR_MASK;
4142 value |= ATTR_AF | L3_PAGE;
4144 rv = (pmap_load(pte) & mask) == value;
4149 if ((m->flags & PG_FICTITIOUS) == 0) {
4150 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4151 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4153 if (!PMAP_TRYLOCK(pmap)) {
4154 md_gen = m->md.pv_gen;
4155 pvh_gen = pvh->pv_gen;
4159 if (md_gen != m->md.pv_gen ||
4160 pvh_gen != pvh->pv_gen) {
4165 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4167 ("pmap_page_test_mappings: Invalid level %d", lvl));
4171 mask |= ATTR_AP_RW_BIT;
4172 value |= ATTR_AP(ATTR_AP_RW);
4175 mask |= ATTR_AF | ATTR_DESCR_MASK;
4176 value |= ATTR_AF | L2_BLOCK;
4178 rv = (pmap_load(pte) & mask) == value;
4192 * Return whether or not the specified physical page was modified
4193 * in any physical maps.
4196 pmap_is_modified(vm_page_t m)
4199 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4200 ("pmap_is_modified: page %p is not managed", m));
4203 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4204 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4205 * is clear, no PTEs can have PG_M set.
4207 VM_OBJECT_ASSERT_WLOCKED(m->object);
4208 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4210 return (pmap_page_test_mappings(m, FALSE, TRUE));
4214 * pmap_is_prefaultable:
4216 * Return whether or not the specified virtual address is eligible
4220 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4228 pte = pmap_pte(pmap, addr, &lvl);
4229 if (pte != NULL && pmap_load(pte) != 0) {
4237 * pmap_is_referenced:
4239 * Return whether or not the specified physical page was referenced
4240 * in any physical maps.
4243 pmap_is_referenced(vm_page_t m)
4246 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4247 ("pmap_is_referenced: page %p is not managed", m));
4248 return (pmap_page_test_mappings(m, TRUE, FALSE));
4252 * Clear the write and modified bits in each of the given page's mappings.
4255 pmap_remove_write(vm_page_t m)
4257 struct md_page *pvh;
4259 struct rwlock *lock;
4260 pv_entry_t next_pv, pv;
4261 pt_entry_t oldpte, *pte;
4263 int lvl, md_gen, pvh_gen;
4265 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4266 ("pmap_remove_write: page %p is not managed", m));
4269 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4270 * set by another thread while the object is locked. Thus,
4271 * if PGA_WRITEABLE is clear, no page table entries need updating.
4273 VM_OBJECT_ASSERT_WLOCKED(m->object);
4274 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4276 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4277 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4278 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4281 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4283 if (!PMAP_TRYLOCK(pmap)) {
4284 pvh_gen = pvh->pv_gen;
4288 if (pvh_gen != pvh->pv_gen) {
4295 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4296 if ((pmap_load(pte) & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
4297 pmap_demote_l2_locked(pmap, pte, va & ~L2_OFFSET,
4299 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4300 ("inconsistent pv lock %p %p for page %p",
4301 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4304 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4306 if (!PMAP_TRYLOCK(pmap)) {
4307 pvh_gen = pvh->pv_gen;
4308 md_gen = m->md.pv_gen;
4312 if (pvh_gen != pvh->pv_gen ||
4313 md_gen != m->md.pv_gen) {
4319 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4321 oldpte = pmap_load(pte);
4322 if ((oldpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) {
4323 if (!atomic_cmpset_long(pte, oldpte,
4324 oldpte | ATTR_AP(ATTR_AP_RO)))
4326 if ((oldpte & ATTR_AF) != 0)
4328 pmap_invalidate_page(pmap, pv->pv_va);
4333 vm_page_aflag_clear(m, PGA_WRITEABLE);
4336 static __inline boolean_t
4337 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
4344 * pmap_ts_referenced:
4346 * Return a count of reference bits for a page, clearing those bits.
4347 * It is not necessary for every reference bit to be cleared, but it
4348 * is necessary that 0 only be returned when there are truly no
4349 * reference bits set.
4351 * As an optimization, update the page's dirty field if a modified bit is
4352 * found while counting reference bits. This opportunistic update can be
4353 * performed at low cost and can eliminate the need for some future calls
4354 * to pmap_is_modified(). However, since this function stops after
4355 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4356 * dirty pages. Those dirty pages will only be detected by a future call
4357 * to pmap_is_modified().
4360 pmap_ts_referenced(vm_page_t m)
4362 struct md_page *pvh;
4365 struct rwlock *lock;
4366 pd_entry_t *pde, tpde;
4367 pt_entry_t *pte, tpte;
4371 int cleared, md_gen, not_cleared, lvl, pvh_gen;
4372 struct spglist free;
4375 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4376 ("pmap_ts_referenced: page %p is not managed", m));
4379 pa = VM_PAGE_TO_PHYS(m);
4380 lock = PHYS_TO_PV_LIST_LOCK(pa);
4381 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4385 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4386 goto small_mappings;
4392 if (!PMAP_TRYLOCK(pmap)) {
4393 pvh_gen = pvh->pv_gen;
4397 if (pvh_gen != pvh->pv_gen) {
4403 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4404 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4406 ("pmap_ts_referenced: invalid pde level %d", lvl));
4407 tpde = pmap_load(pde);
4408 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4409 ("pmap_ts_referenced: found an invalid l1 table"));
4410 pte = pmap_l1_to_l2(pde, pv->pv_va);
4411 tpte = pmap_load(pte);
4412 if (pmap_page_dirty(tpte)) {
4414 * Although "tpte" is mapping a 2MB page, because
4415 * this function is called at a 4KB page granularity,
4416 * we only update the 4KB page under test.
4420 if ((tpte & ATTR_AF) != 0) {
4422 * Since this reference bit is shared by 512 4KB
4423 * pages, it should not be cleared every time it is
4424 * tested. Apply a simple "hash" function on the
4425 * physical page number, the virtual superpage number,
4426 * and the pmap address to select one 4KB page out of
4427 * the 512 on which testing the reference bit will
4428 * result in clearing that reference bit. This
4429 * function is designed to avoid the selection of the
4430 * same 4KB page for every 2MB page mapping.
4432 * On demotion, a mapping that hasn't been referenced
4433 * is simply destroyed. To avoid the possibility of a
4434 * subsequent page fault on a demoted wired mapping,
4435 * always leave its reference bit set. Moreover,
4436 * since the superpage is wired, the current state of
4437 * its reference bit won't affect page replacement.
4439 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4440 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4441 (tpte & ATTR_SW_WIRED) == 0) {
4442 if (safe_to_clear_referenced(pmap, tpte)) {
4444 * TODO: We don't handle the access
4445 * flag at all. We need to be able
4446 * to set it in the exception handler.
4449 "safe_to_clear_referenced\n");
4450 } else if (pmap_demote_l2_locked(pmap, pte,
4451 pv->pv_va, &lock) != NULL) {
4453 va += VM_PAGE_TO_PHYS(m) -
4454 (tpte & ~ATTR_MASK);
4455 l3 = pmap_l2_to_l3(pte, va);
4456 pmap_remove_l3(pmap, l3, va,
4457 pmap_load(pte), NULL, &lock);
4463 * The superpage mapping was removed
4464 * entirely and therefore 'pv' is no
4472 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4473 ("inconsistent pv lock %p %p for page %p",
4474 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4479 /* Rotate the PV list if it has more than one entry. */
4480 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4481 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4482 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4485 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4487 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4489 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4496 if (!PMAP_TRYLOCK(pmap)) {
4497 pvh_gen = pvh->pv_gen;
4498 md_gen = m->md.pv_gen;
4502 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4507 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4508 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4510 ("pmap_ts_referenced: invalid pde level %d", lvl));
4511 tpde = pmap_load(pde);
4512 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4513 ("pmap_ts_referenced: found an invalid l2 table"));
4514 pte = pmap_l2_to_l3(pde, pv->pv_va);
4515 tpte = pmap_load(pte);
4516 if (pmap_page_dirty(tpte))
4518 if ((tpte & ATTR_AF) != 0) {
4519 if (safe_to_clear_referenced(pmap, tpte)) {
4521 * TODO: We don't handle the access flag
4522 * at all. We need to be able to set it in
4523 * the exception handler.
4525 panic("ARM64TODO: safe_to_clear_referenced\n");
4526 } else if ((tpte & ATTR_SW_WIRED) == 0) {
4528 * Wired pages cannot be paged out so
4529 * doing accessed bit emulation for
4530 * them is wasted effort. We do the
4531 * hard work for unwired pages only.
4533 pmap_remove_l3(pmap, pte, pv->pv_va, tpde,
4535 pmap_invalidate_page(pmap, pv->pv_va);
4540 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4541 ("inconsistent pv lock %p %p for page %p",
4542 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4547 /* Rotate the PV list if it has more than one entry. */
4548 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4549 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4550 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4553 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4554 not_cleared < PMAP_TS_REFERENCED_MAX);
4557 vm_page_free_pages_toq(&free, false);
4558 return (cleared + not_cleared);
4562 * Apply the given advice to the specified range of addresses within the
4563 * given pmap. Depending on the advice, clear the referenced and/or
4564 * modified flags in each mapping and set the mapped page's dirty field.
4567 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4572 * Clear the modify bits on the specified physical page.
4575 pmap_clear_modify(vm_page_t m)
4578 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4579 ("pmap_clear_modify: page %p is not managed", m));
4580 VM_OBJECT_ASSERT_WLOCKED(m->object);
4581 KASSERT(!vm_page_xbusied(m),
4582 ("pmap_clear_modify: page %p is exclusive busied", m));
4585 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4586 * If the object containing the page is locked and the page is not
4587 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4589 if ((m->aflags & PGA_WRITEABLE) == 0)
4592 /* ARM64TODO: We lack support for tracking if a page is modified */
4596 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4598 struct pmap_preinit_mapping *ppim;
4599 vm_offset_t va, offset;
4602 int i, lvl, l2_blocks, free_l2_count, start_idx;
4604 if (!vm_initialized) {
4606 * No L3 ptables so map entire L2 blocks where start VA is:
4607 * preinit_map_va + start_idx * L2_SIZE
4608 * There may be duplicate mappings (multiple VA -> same PA) but
4609 * ARM64 dcache is always PIPT so that's acceptable.
4614 /* Calculate how many full L2 blocks are needed for the mapping */
4615 l2_blocks = (roundup2(pa + size, L2_SIZE) - rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
4617 offset = pa & L2_OFFSET;
4619 if (preinit_map_va == 0)
4622 /* Map 2MiB L2 blocks from reserved VA space */
4626 /* Find enough free contiguous VA space */
4627 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
4628 ppim = pmap_preinit_mapping + i;
4629 if (free_l2_count > 0 && ppim->pa != 0) {
4630 /* Not enough space here */
4636 if (ppim->pa == 0) {
4638 if (start_idx == -1)
4641 if (free_l2_count == l2_blocks)
4645 if (free_l2_count != l2_blocks)
4646 panic("%s: too many preinit mappings", __func__);
4648 va = preinit_map_va + (start_idx * L2_SIZE);
4649 for (i = start_idx; i < start_idx + l2_blocks; i++) {
4650 /* Mark entries as allocated */
4651 ppim = pmap_preinit_mapping + i;
4653 ppim->va = va + offset;
4658 pa = rounddown2(pa, L2_SIZE);
4659 for (i = 0; i < l2_blocks; i++) {
4660 pde = pmap_pde(kernel_pmap, va, &lvl);
4661 KASSERT(pde != NULL,
4662 ("pmap_mapbios: Invalid page entry, va: 0x%lx", va));
4663 KASSERT(lvl == 1, ("pmap_mapbios: Invalid level %d", lvl));
4665 /* Insert L2_BLOCK */
4666 l2 = pmap_l1_to_l2(pde, va);
4668 pa | ATTR_DEFAULT | ATTR_XN |
4669 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
4670 pmap_invalidate_range(kernel_pmap, va, va + L2_SIZE);
4676 va = preinit_map_va + (start_idx * L2_SIZE);
4679 /* kva_alloc may be used to map the pages */
4680 offset = pa & PAGE_MASK;
4681 size = round_page(offset + size);
4683 va = kva_alloc(size);
4685 panic("%s: Couldn't allocate KVA", __func__);
4687 pde = pmap_pde(kernel_pmap, va, &lvl);
4688 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
4690 /* L3 table is linked */
4691 va = trunc_page(va);
4692 pa = trunc_page(pa);
4693 pmap_kenter(va, size, pa, CACHED_MEMORY);
4696 return ((void *)(va + offset));
4700 pmap_unmapbios(vm_offset_t va, vm_size_t size)
4702 struct pmap_preinit_mapping *ppim;
4703 vm_offset_t offset, tmpsize, va_trunc;
4706 int i, lvl, l2_blocks, block;
4708 l2_blocks = (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
4709 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
4711 /* Remove preinit mapping */
4713 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
4714 ppim = pmap_preinit_mapping + i;
4715 if (ppim->va == va) {
4716 KASSERT(ppim->size == size, ("pmap_unmapbios: size mismatch"));
4720 offset = block * L2_SIZE;
4721 va_trunc = rounddown2(va, L2_SIZE) + offset;
4723 /* Remove L2_BLOCK */
4724 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
4725 KASSERT(pde != NULL,
4726 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va_trunc));
4727 l2 = pmap_l1_to_l2(pde, va_trunc);
4728 pmap_load_clear(l2);
4729 pmap_invalidate_range(kernel_pmap, va_trunc, va_trunc + L2_SIZE);
4731 if (block == (l2_blocks - 1))
4737 /* Unmap the pages reserved with kva_alloc. */
4738 if (vm_initialized) {
4739 offset = va & PAGE_MASK;
4740 size = round_page(offset + size);
4741 va = trunc_page(va);
4743 pde = pmap_pde(kernel_pmap, va, &lvl);
4744 KASSERT(pde != NULL,
4745 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
4746 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
4748 /* Unmap and invalidate the pages */
4749 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
4750 pmap_kremove(va + tmpsize);
4757 * Sets the memory attribute for the specified page.
4760 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4763 m->md.pv_memattr = ma;
4766 * If "m" is a normal page, update its direct mapping. This update
4767 * can be relied upon to perform any cache operations that are
4768 * required for data coherence.
4770 if ((m->flags & PG_FICTITIOUS) == 0 &&
4771 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
4772 m->md.pv_memattr) != 0)
4773 panic("memory attribute change on the direct map failed");
4777 * Changes the specified virtual address range's memory type to that given by
4778 * the parameter "mode". The specified virtual address range must be
4779 * completely contained within either the direct map or the kernel map. If
4780 * the virtual address range is contained within the kernel map, then the
4781 * memory type for each of the corresponding ranges of the direct map is also
4782 * changed. (The corresponding ranges of the direct map are those ranges that
4783 * map the same physical pages as the specified virtual address range.) These
4784 * changes to the direct map are necessary because Intel describes the
4785 * behavior of their processors as "undefined" if two or more mappings to the
4786 * same physical page have different memory types.
4788 * Returns zero if the change completed successfully, and either EINVAL or
4789 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
4790 * of the virtual address range was not mapped, and ENOMEM is returned if
4791 * there was insufficient memory available to complete the change. In the
4792 * latter case, the memory type may have been changed on some part of the
4793 * virtual address range or the direct map.
4796 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
4800 PMAP_LOCK(kernel_pmap);
4801 error = pmap_change_attr_locked(va, size, mode);
4802 PMAP_UNLOCK(kernel_pmap);
4807 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
4809 vm_offset_t base, offset, tmpva;
4810 pt_entry_t l3, *pte, *newpte;
4813 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
4814 base = trunc_page(va);
4815 offset = va & PAGE_MASK;
4816 size = round_page(offset + size);
4818 if (!VIRT_IN_DMAP(base))
4821 for (tmpva = base; tmpva < base + size; ) {
4822 pte = pmap_pte(kernel_pmap, va, &lvl);
4826 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
4828 * We already have the correct attribute,
4829 * ignore this entry.
4833 panic("Invalid DMAP table level: %d\n", lvl);
4835 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
4838 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
4846 * Split the entry to an level 3 table, then
4847 * set the new attribute.
4851 panic("Invalid DMAP table level: %d\n", lvl);
4853 newpte = pmap_demote_l1(kernel_pmap, pte,
4854 tmpva & ~L1_OFFSET);
4857 pte = pmap_l1_to_l2(pte, tmpva);
4859 newpte = pmap_demote_l2(kernel_pmap, pte,
4860 tmpva & ~L2_OFFSET);
4863 pte = pmap_l2_to_l3(pte, tmpva);
4865 /* Update the entry */
4866 l3 = pmap_load(pte);
4867 l3 &= ~ATTR_IDX_MASK;
4868 l3 |= ATTR_IDX(mode);
4869 if (mode == DEVICE_MEMORY)
4872 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
4876 * If moving to a non-cacheable entry flush
4879 if (mode == VM_MEMATTR_UNCACHEABLE)
4880 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
4892 * Create an L2 table to map all addresses within an L1 mapping.
4895 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
4897 pt_entry_t *l2, newl2, oldl1;
4899 vm_paddr_t l2phys, phys;
4903 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4904 oldl1 = pmap_load(l1);
4905 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
4906 ("pmap_demote_l1: Demoting a non-block entry"));
4907 KASSERT((va & L1_OFFSET) == 0,
4908 ("pmap_demote_l1: Invalid virtual address %#lx", va));
4909 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
4910 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
4913 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
4914 tmpl1 = kva_alloc(PAGE_SIZE);
4919 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
4920 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
4921 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
4922 " in pmap %p", va, pmap);
4926 l2phys = VM_PAGE_TO_PHYS(ml2);
4927 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
4929 /* Address the range points at */
4930 phys = oldl1 & ~ATTR_MASK;
4931 /* The attributed from the old l1 table to be copied */
4932 newl2 = oldl1 & ATTR_MASK;
4934 /* Create the new entries */
4935 for (i = 0; i < Ln_ENTRIES; i++) {
4936 l2[i] = newl2 | phys;
4939 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
4940 ("Invalid l2 page (%lx != %lx)", l2[0],
4941 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
4944 pmap_kenter(tmpl1, PAGE_SIZE,
4945 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY);
4946 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
4949 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
4952 pmap_kremove(tmpl1);
4953 kva_free(tmpl1, PAGE_SIZE);
4960 * Create an L3 table to map all addresses within an L2 mapping.
4963 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
4964 struct rwlock **lockp)
4966 pt_entry_t *l3, newl3, oldl2;
4968 vm_paddr_t l3phys, phys;
4972 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4974 oldl2 = pmap_load(l2);
4975 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
4976 ("pmap_demote_l2: Demoting a non-block entry"));
4977 KASSERT((va & L2_OFFSET) == 0,
4978 ("pmap_demote_l2: Invalid virtual address %#lx", va));
4981 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
4982 tmpl2 = kva_alloc(PAGE_SIZE);
4987 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
4988 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
4989 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4990 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
4992 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
4993 " in pmap %p", va, pmap);
4996 if (va < VM_MAXUSER_ADDRESS)
4997 pmap_resident_count_inc(pmap, 1);
5000 l3phys = VM_PAGE_TO_PHYS(ml3);
5001 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
5003 /* Address the range points at */
5004 phys = oldl2 & ~ATTR_MASK;
5005 /* The attributed from the old l2 table to be copied */
5006 newl3 = (oldl2 & (ATTR_MASK & ~ATTR_DESCR_MASK)) | L3_PAGE;
5009 * If the page table page is new, initialize it.
5011 if (ml3->wire_count == 1) {
5012 ml3->wire_count = NL3PG;
5013 for (i = 0; i < Ln_ENTRIES; i++) {
5014 l3[i] = newl3 | phys;
5018 KASSERT(l3[0] == ((oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE),
5019 ("Invalid l3 page (%lx != %lx)", l3[0],
5020 (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE));
5023 * Map the temporary page so we don't lose access to the l2 table.
5026 pmap_kenter(tmpl2, PAGE_SIZE,
5027 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY);
5028 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
5032 * The spare PV entries must be reserved prior to demoting the
5033 * mapping, that is, prior to changing the PDE. Otherwise, the state
5034 * of the L2 and the PV lists will be inconsistent, which can result
5035 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5036 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
5037 * PV entry for the 2MB page mapping that is being demoted.
5039 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5040 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
5042 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
5045 * Demote the PV entry.
5047 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5048 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
5050 atomic_add_long(&pmap_l2_demotions, 1);
5051 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
5052 " in pmap %p %lx", va, pmap, l3[0]);
5056 pmap_kremove(tmpl2);
5057 kva_free(tmpl2, PAGE_SIZE);
5065 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
5067 struct rwlock *lock;
5071 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
5078 * perform the pmap work for mincore
5081 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5083 pd_entry_t *l1p, l1;
5084 pd_entry_t *l2p, l2;
5085 pt_entry_t *l3p, l3;
5096 l1p = pmap_l1(pmap, addr);
5097 if (l1p == NULL) /* No l1 */
5100 l1 = pmap_load(l1p);
5101 if ((l1 & ATTR_DESCR_MASK) == L1_INVAL)
5104 if ((l1 & ATTR_DESCR_MASK) == L1_BLOCK) {
5105 pa = (l1 & ~ATTR_MASK) | (addr & L1_OFFSET);
5106 managed = (l1 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
5107 val = MINCORE_SUPER | MINCORE_INCORE;
5108 if (pmap_page_dirty(l1))
5109 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5110 if ((l1 & ATTR_AF) == ATTR_AF)
5111 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5115 l2p = pmap_l1_to_l2(l1p, addr);
5116 if (l2p == NULL) /* No l2 */
5119 l2 = pmap_load(l2p);
5120 if ((l2 & ATTR_DESCR_MASK) == L2_INVAL)
5123 if ((l2 & ATTR_DESCR_MASK) == L2_BLOCK) {
5124 pa = (l2 & ~ATTR_MASK) | (addr & L2_OFFSET);
5125 managed = (l2 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
5126 val = MINCORE_SUPER | MINCORE_INCORE;
5127 if (pmap_page_dirty(l2))
5128 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5129 if ((l2 & ATTR_AF) == ATTR_AF)
5130 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5134 l3p = pmap_l2_to_l3(l2p, addr);
5135 if (l3p == NULL) /* No l3 */
5138 l3 = pmap_load(l2p);
5139 if ((l3 & ATTR_DESCR_MASK) == L3_INVAL)
5142 if ((l3 & ATTR_DESCR_MASK) == L3_PAGE) {
5143 pa = (l3 & ~ATTR_MASK) | (addr & L3_OFFSET);
5144 managed = (l3 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
5145 val = MINCORE_INCORE;
5146 if (pmap_page_dirty(l3))
5147 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5148 if ((l3 & ATTR_AF) == ATTR_AF)
5149 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5153 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5154 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
5155 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5156 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5159 PA_UNLOCK_COND(*locked_pa);
5166 pmap_activate(struct thread *td)
5171 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5172 td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0);
5173 __asm __volatile("msr ttbr0_el1, %0" : :
5174 "r"(td->td_proc->p_md.md_l0addr));
5175 pmap_invalidate_all(pmap);
5180 pmap_switch(struct thread *old, struct thread *new)
5182 pcpu_bp_harden bp_harden;
5185 /* Store the new curthread */
5186 PCPU_SET(curthread, new);
5188 /* And the new pcb */
5190 PCPU_SET(curpcb, pcb);
5193 * TODO: We may need to flush the cache here if switching
5194 * to a user process.
5198 old->td_proc->p_md.md_l0addr != new->td_proc->p_md.md_l0addr) {
5200 /* Switch to the new pmap */
5201 "msr ttbr0_el1, %0 \n"
5204 /* Invalidate the TLB */
5209 : : "r"(new->td_proc->p_md.md_l0addr));
5212 * Stop userspace from training the branch predictor against
5213 * other processes. This will call into a CPU specific
5214 * function that clears the branch predictor state.
5216 bp_harden = PCPU_GET(bp_harden);
5217 if (bp_harden != NULL)
5225 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
5228 if (va >= VM_MIN_KERNEL_ADDRESS) {
5229 cpu_icache_sync_range(va, sz);
5234 /* Find the length of data in this page to flush */
5235 offset = va & PAGE_MASK;
5236 len = imin(PAGE_SIZE - offset, sz);
5239 /* Extract the physical address & find it in the DMAP */
5240 pa = pmap_extract(pmap, va);
5242 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
5244 /* Move to the next page */
5247 /* Set the length for the next iteration */
5248 len = imin(PAGE_SIZE, sz);
5254 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
5260 switch (ESR_ELx_EXCEPTION(esr)) {
5261 case EXCP_INSN_ABORT_L:
5262 case EXCP_INSN_ABORT:
5263 case EXCP_DATA_ABORT_L:
5264 case EXCP_DATA_ABORT:
5267 return (KERN_FAILURE);
5270 /* Data and insn aborts use same encoding for FCS field. */
5271 switch (esr & ISS_DATA_DFSC_MASK) {
5272 case ISS_DATA_DFSC_TF_L0:
5273 case ISS_DATA_DFSC_TF_L1:
5274 case ISS_DATA_DFSC_TF_L2:
5275 case ISS_DATA_DFSC_TF_L3:
5277 /* Ask the MMU to check the address */
5278 intr = intr_disable();
5279 if (pmap == kernel_pmap)
5280 par = arm64_address_translate_s1e1r(far);
5282 par = arm64_address_translate_s1e0r(far);
5287 * If the translation was successful the address was invalid
5288 * due to a break-before-make sequence. We can unlock and
5289 * return success to the trap handler.
5291 if (PAR_SUCCESS(par))
5292 return (KERN_SUCCESS);
5299 return (KERN_FAILURE);
5303 * Increase the starting virtual address of the given mapping if a
5304 * different alignment might result in more superpage mappings.
5307 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5308 vm_offset_t *addr, vm_size_t size)
5310 vm_offset_t superpage_offset;
5314 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5315 offset += ptoa(object->pg_color);
5316 superpage_offset = offset & L2_OFFSET;
5317 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
5318 (*addr & L2_OFFSET) == superpage_offset)
5320 if ((*addr & L2_OFFSET) < superpage_offset)
5321 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
5323 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
5327 * Get the kernel virtual address of a set of physical pages. If there are
5328 * physical addresses not covered by the DMAP perform a transient mapping
5329 * that will be removed when calling pmap_unmap_io_transient.
5331 * \param page The pages the caller wishes to obtain the virtual
5332 * address on the kernel memory map.
5333 * \param vaddr On return contains the kernel virtual memory address
5334 * of the pages passed in the page parameter.
5335 * \param count Number of pages passed in.
5336 * \param can_fault TRUE if the thread using the mapped pages can take
5337 * page faults, FALSE otherwise.
5339 * \returns TRUE if the caller must call pmap_unmap_io_transient when
5340 * finished or FALSE otherwise.
5344 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
5345 boolean_t can_fault)
5348 boolean_t needs_mapping;
5352 * Allocate any KVA space that we need, this is done in a separate
5353 * loop to prevent calling vmem_alloc while pinned.
5355 needs_mapping = FALSE;
5356 for (i = 0; i < count; i++) {
5357 paddr = VM_PAGE_TO_PHYS(page[i]);
5358 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
5359 error = vmem_alloc(kernel_arena, PAGE_SIZE,
5360 M_BESTFIT | M_WAITOK, &vaddr[i]);
5361 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
5362 needs_mapping = TRUE;
5364 vaddr[i] = PHYS_TO_DMAP(paddr);
5368 /* Exit early if everything is covered by the DMAP */
5374 for (i = 0; i < count; i++) {
5375 paddr = VM_PAGE_TO_PHYS(page[i]);
5376 if (!PHYS_IN_DMAP(paddr)) {
5378 "pmap_map_io_transient: TODO: Map out of DMAP data");
5382 return (needs_mapping);
5386 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
5387 boolean_t can_fault)
5394 for (i = 0; i < count; i++) {
5395 paddr = VM_PAGE_TO_PHYS(page[i]);
5396 if (!PHYS_IN_DMAP(paddr)) {
5397 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");