2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/msgbuf.h>
120 #include <sys/mutex.h>
121 #include <sys/proc.h>
122 #include <sys/rwlock.h>
124 #include <sys/vmem.h>
125 #include <sys/vmmeter.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/_unrhdr.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/vm_pager.h>
140 #include <vm/vm_phys.h>
141 #include <vm/vm_radix.h>
142 #include <vm/vm_reserv.h>
145 #include <machine/machdep.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
149 #include <arm/include/physmem.h>
151 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
152 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
153 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
154 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
156 #define NUL0E L0_ENTRIES
157 #define NUL1E (NUL0E * NL1PG)
158 #define NUL2E (NUL1E * NL2PG)
160 #if !defined(DIAGNOSTIC)
161 #ifdef __GNUC_GNU_INLINE__
162 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
164 #define PMAP_INLINE extern inline
171 * These are configured by the mair_el1 register. This is set up in locore.S
173 #define DEVICE_MEMORY 0
174 #define UNCACHED_MEMORY 1
175 #define CACHED_MEMORY 2
179 #define PV_STAT(x) do { x ; } while (0)
181 #define PV_STAT(x) do { } while (0)
184 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
185 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
187 #define NPV_LIST_LOCKS MAXCPU
189 #define PHYS_TO_PV_LIST_LOCK(pa) \
190 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
192 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
193 struct rwlock **_lockp = (lockp); \
194 struct rwlock *_new_lock; \
196 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
197 if (_new_lock != *_lockp) { \
198 if (*_lockp != NULL) \
199 rw_wunlock(*_lockp); \
200 *_lockp = _new_lock; \
205 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
206 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
208 #define RELEASE_PV_LIST_LOCK(lockp) do { \
209 struct rwlock **_lockp = (lockp); \
211 if (*_lockp != NULL) { \
212 rw_wunlock(*_lockp); \
217 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
218 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
220 struct pmap kernel_pmap_store;
222 /* Used for mapping ACPI memory before VM is initialized */
223 #define PMAP_PREINIT_MAPPING_COUNT 32
224 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
225 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
226 static int vm_initialized = 0; /* No need to use pre-init maps when set */
229 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
230 * Always map entire L2 block for simplicity.
231 * VA of L2 block = preinit_map_va + i * L2_SIZE
233 static struct pmap_preinit_mapping {
237 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
239 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
240 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
241 vm_offset_t kernel_vm_end = 0;
244 * Data for the pv entry allocation mechanism.
246 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
247 static struct mtx pv_chunks_mutex;
248 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
249 static struct md_page *pv_table;
250 static struct md_page pv_dummy;
252 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
253 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
254 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
256 /* This code assumes all L1 DMAP entries will be used */
257 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
258 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
260 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
261 extern pt_entry_t pagetable_dmap[];
263 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
264 static vm_paddr_t physmap[PHYSMAP_SIZE];
265 static u_int physmap_idx;
267 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
269 static int superpages_enabled = 1;
270 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
271 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
272 "Are large page mappings enabled?");
275 * Internal flags for pmap_enter()'s helper functions.
277 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
278 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
280 static void free_pv_chunk(struct pv_chunk *pc);
281 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
282 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
283 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
284 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
285 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
288 static int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode);
289 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
290 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
291 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
292 vm_offset_t va, struct rwlock **lockp);
293 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
294 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
295 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
296 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
297 u_int flags, vm_page_t m, struct rwlock **lockp);
298 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
299 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
300 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
301 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
302 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
303 vm_page_t m, struct rwlock **lockp);
305 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
306 struct rwlock **lockp);
308 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
309 struct spglist *free);
310 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
311 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
314 * These load the old table data and store the new value.
315 * They need to be atomic as the System MMU may write to the table at
316 * the same time as the CPU.
318 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
319 #define pmap_set(table, mask) atomic_set_64(table, mask)
320 #define pmap_load_clear(table) atomic_swap_64(table, 0)
321 #define pmap_load(table) (*table)
323 /********************/
324 /* Inline functions */
325 /********************/
328 pagecopy(void *s, void *d)
331 memcpy(d, s, PAGE_SIZE);
334 static __inline pd_entry_t *
335 pmap_l0(pmap_t pmap, vm_offset_t va)
338 return (&pmap->pm_l0[pmap_l0_index(va)]);
341 static __inline pd_entry_t *
342 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
346 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
347 return (&l1[pmap_l1_index(va)]);
350 static __inline pd_entry_t *
351 pmap_l1(pmap_t pmap, vm_offset_t va)
355 l0 = pmap_l0(pmap, va);
356 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
359 return (pmap_l0_to_l1(l0, va));
362 static __inline pd_entry_t *
363 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
367 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
368 return (&l2[pmap_l2_index(va)]);
371 static __inline pd_entry_t *
372 pmap_l2(pmap_t pmap, vm_offset_t va)
376 l1 = pmap_l1(pmap, va);
377 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
380 return (pmap_l1_to_l2(l1, va));
383 static __inline pt_entry_t *
384 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
388 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
389 return (&l3[pmap_l3_index(va)]);
393 * Returns the lowest valid pde for a given virtual address.
394 * The next level may or may not point to a valid page or block.
396 static __inline pd_entry_t *
397 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
399 pd_entry_t *l0, *l1, *l2, desc;
401 l0 = pmap_l0(pmap, va);
402 desc = pmap_load(l0) & ATTR_DESCR_MASK;
403 if (desc != L0_TABLE) {
408 l1 = pmap_l0_to_l1(l0, va);
409 desc = pmap_load(l1) & ATTR_DESCR_MASK;
410 if (desc != L1_TABLE) {
415 l2 = pmap_l1_to_l2(l1, va);
416 desc = pmap_load(l2) & ATTR_DESCR_MASK;
417 if (desc != L2_TABLE) {
427 * Returns the lowest valid pte block or table entry for a given virtual
428 * address. If there are no valid entries return NULL and set the level to
429 * the first invalid level.
431 static __inline pt_entry_t *
432 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
434 pd_entry_t *l1, *l2, desc;
437 l1 = pmap_l1(pmap, va);
442 desc = pmap_load(l1) & ATTR_DESCR_MASK;
443 if (desc == L1_BLOCK) {
448 if (desc != L1_TABLE) {
453 l2 = pmap_l1_to_l2(l1, va);
454 desc = pmap_load(l2) & ATTR_DESCR_MASK;
455 if (desc == L2_BLOCK) {
460 if (desc != L2_TABLE) {
466 l3 = pmap_l2_to_l3(l2, va);
467 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
474 pmap_ps_enabled(pmap_t pmap __unused)
477 return (superpages_enabled != 0);
481 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
482 pd_entry_t **l2, pt_entry_t **l3)
484 pd_entry_t *l0p, *l1p, *l2p;
486 if (pmap->pm_l0 == NULL)
489 l0p = pmap_l0(pmap, va);
492 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
495 l1p = pmap_l0_to_l1(l0p, va);
498 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
504 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
507 l2p = pmap_l1_to_l2(l1p, va);
510 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
515 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
518 *l3 = pmap_l2_to_l3(l2p, va);
524 pmap_l3_valid(pt_entry_t l3)
527 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
531 CTASSERT(L1_BLOCK == L2_BLOCK);
534 * Checks if the page is dirty. We currently lack proper tracking of this on
535 * arm64 so for now assume is a page mapped as rw was accessed it is.
538 pmap_page_dirty(pt_entry_t pte)
541 return ((pte & (ATTR_AF | ATTR_AP_RW_BIT)) ==
542 (ATTR_AF | ATTR_AP(ATTR_AP_RW)));
546 pmap_resident_count_inc(pmap_t pmap, int count)
549 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
550 pmap->pm_stats.resident_count += count;
554 pmap_resident_count_dec(pmap_t pmap, int count)
557 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
558 KASSERT(pmap->pm_stats.resident_count >= count,
559 ("pmap %p resident count underflow %ld %d", pmap,
560 pmap->pm_stats.resident_count, count));
561 pmap->pm_stats.resident_count -= count;
565 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
571 l1 = (pd_entry_t *)l1pt;
572 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
574 /* Check locore has used a table L1 map */
575 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
576 ("Invalid bootstrap L1 table"));
577 /* Find the address of the L2 table */
578 l2 = (pt_entry_t *)init_pt_va;
579 *l2_slot = pmap_l2_index(va);
585 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
587 u_int l1_slot, l2_slot;
590 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
592 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
596 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
597 vm_offset_t freemempos)
601 vm_paddr_t l2_pa, pa;
602 u_int l1_slot, l2_slot, prev_l1_slot;
605 dmap_phys_base = min_pa & ~L1_OFFSET;
611 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
612 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
614 for (i = 0; i < (physmap_idx * 2); i += 2) {
615 pa = physmap[i] & ~L2_OFFSET;
616 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
618 /* Create L2 mappings at the start of the region */
619 if ((pa & L1_OFFSET) != 0) {
620 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
621 if (l1_slot != prev_l1_slot) {
622 prev_l1_slot = l1_slot;
623 l2 = (pt_entry_t *)freemempos;
624 l2_pa = pmap_early_vtophys(kern_l1,
626 freemempos += PAGE_SIZE;
628 pmap_load_store(&pagetable_dmap[l1_slot],
629 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
631 memset(l2, 0, PAGE_SIZE);
634 ("pmap_bootstrap_dmap: NULL l2 map"));
635 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
636 pa += L2_SIZE, va += L2_SIZE) {
638 * We are on a boundary, stop to
639 * create a level 1 block
641 if ((pa & L1_OFFSET) == 0)
644 l2_slot = pmap_l2_index(va);
645 KASSERT(l2_slot != 0, ("..."));
646 pmap_load_store(&l2[l2_slot],
647 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
648 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
650 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
654 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
655 (physmap[i + 1] - pa) >= L1_SIZE;
656 pa += L1_SIZE, va += L1_SIZE) {
657 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
658 pmap_load_store(&pagetable_dmap[l1_slot],
659 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
660 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
663 /* Create L2 mappings at the end of the region */
664 if (pa < physmap[i + 1]) {
665 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
666 if (l1_slot != prev_l1_slot) {
667 prev_l1_slot = l1_slot;
668 l2 = (pt_entry_t *)freemempos;
669 l2_pa = pmap_early_vtophys(kern_l1,
671 freemempos += PAGE_SIZE;
673 pmap_load_store(&pagetable_dmap[l1_slot],
674 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
676 memset(l2, 0, PAGE_SIZE);
679 ("pmap_bootstrap_dmap: NULL l2 map"));
680 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
681 pa += L2_SIZE, va += L2_SIZE) {
682 l2_slot = pmap_l2_index(va);
683 pmap_load_store(&l2[l2_slot],
684 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
685 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
689 if (pa > dmap_phys_max) {
701 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
708 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
710 l1 = (pd_entry_t *)l1pt;
711 l1_slot = pmap_l1_index(va);
714 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
715 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
717 pa = pmap_early_vtophys(l1pt, l2pt);
718 pmap_load_store(&l1[l1_slot],
719 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
723 /* Clean the L2 page table */
724 memset((void *)l2_start, 0, l2pt - l2_start);
730 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
737 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
739 l2 = pmap_l2(kernel_pmap, va);
740 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
741 l2_slot = pmap_l2_index(va);
744 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
745 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
747 pa = pmap_early_vtophys(l1pt, l3pt);
748 pmap_load_store(&l2[l2_slot],
749 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
753 /* Clean the L2 page table */
754 memset((void *)l3_start, 0, l3pt - l3_start);
760 * Bootstrap the system enough to run with virtual memory.
763 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
766 u_int l1_slot, l2_slot;
769 vm_offset_t va, freemempos;
770 vm_offset_t dpcpu, msgbufpv;
771 vm_paddr_t start_pa, pa, min_pa;
774 kern_delta = KERNBASE - kernstart;
776 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
777 printf("%lx\n", l1pt);
778 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
780 /* Set this early so we can use the pagetable walking functions */
781 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
782 PMAP_LOCK_INIT(kernel_pmap);
784 /* Assume the address we were loaded to is a valid physical address */
785 min_pa = KERNBASE - kern_delta;
787 physmap_idx = arm_physmem_avail(physmap, nitems(physmap));
791 * Find the minimum physical address. physmap is sorted,
792 * but may contain empty ranges.
794 for (i = 0; i < (physmap_idx * 2); i += 2) {
795 if (physmap[i] == physmap[i + 1])
797 if (physmap[i] <= min_pa)
801 freemempos = KERNBASE + kernlen;
802 freemempos = roundup2(freemempos, PAGE_SIZE);
804 /* Create a direct map region early so we can use it for pa -> va */
805 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
808 start_pa = pa = KERNBASE - kern_delta;
811 * Read the page table to find out what is already mapped.
812 * This assumes we have mapped a block of memory from KERNBASE
813 * using a single L1 entry.
815 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
817 /* Sanity check the index, KERNBASE should be the first VA */
818 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
820 /* Find how many pages we have mapped */
821 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
822 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
825 /* Check locore used L2 blocks */
826 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
827 ("Invalid bootstrap L2 table"));
828 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
829 ("Incorrect PA in L2 table"));
835 va = roundup2(va, L1_SIZE);
837 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
838 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
839 /* And the l3 tables for the early devmap */
840 freemempos = pmap_bootstrap_l3(l1pt,
841 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
845 #define alloc_pages(var, np) \
846 (var) = freemempos; \
847 freemempos += (np * PAGE_SIZE); \
848 memset((char *)(var), 0, ((np) * PAGE_SIZE));
850 /* Allocate dynamic per-cpu area. */
851 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
852 dpcpu_init((void *)dpcpu, 0);
854 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
855 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
856 msgbufp = (void *)msgbufpv;
858 /* Reserve some VA space for early BIOS/ACPI mapping */
859 preinit_map_va = roundup2(freemempos, L2_SIZE);
861 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
862 virtual_avail = roundup2(virtual_avail, L1_SIZE);
863 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
864 kernel_vm_end = virtual_avail;
866 pa = pmap_early_vtophys(l1pt, freemempos);
868 arm_physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
874 * Initialize a vm_page's machine-dependent fields.
877 pmap_page_init(vm_page_t m)
880 TAILQ_INIT(&m->md.pv_list);
881 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
885 * Initialize the pmap module.
886 * Called by vm_init, to initialize any structures that the pmap
887 * system needs to map virtual memory.
896 * Are large page mappings enabled?
898 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
899 if (superpages_enabled) {
900 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
901 ("pmap_init: can't assign to pagesizes[1]"));
902 pagesizes[1] = L2_SIZE;
906 * Initialize the pv chunk list mutex.
908 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
911 * Initialize the pool of pv list locks.
913 for (i = 0; i < NPV_LIST_LOCKS; i++)
914 rw_init(&pv_list_locks[i], "pmap pv list");
917 * Calculate the size of the pv head table for superpages.
919 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
922 * Allocate memory for the pv head table for superpages.
924 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
926 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
927 for (i = 0; i < pv_npg; i++)
928 TAILQ_INIT(&pv_table[i].pv_list);
929 TAILQ_INIT(&pv_dummy.pv_list);
934 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
935 "2MB page mapping counters");
937 static u_long pmap_l2_demotions;
938 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
939 &pmap_l2_demotions, 0, "2MB page demotions");
941 static u_long pmap_l2_mappings;
942 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
943 &pmap_l2_mappings, 0, "2MB page mappings");
945 static u_long pmap_l2_p_failures;
946 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
947 &pmap_l2_p_failures, 0, "2MB page promotion failures");
949 static u_long pmap_l2_promotions;
950 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
951 &pmap_l2_promotions, 0, "2MB page promotions");
954 * Invalidate a single TLB entry.
957 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
963 "tlbi vaae1is, %0 \n"
966 : : "r"(va >> PAGE_SHIFT));
971 pmap_invalidate_range_nopin(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
976 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
978 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
986 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
990 pmap_invalidate_range_nopin(pmap, sva, eva);
995 pmap_invalidate_all(pmap_t pmap)
1008 * Routine: pmap_extract
1010 * Extract the physical page address associated
1011 * with the given map/virtual_address pair.
1014 pmap_extract(pmap_t pmap, vm_offset_t va)
1016 pt_entry_t *pte, tpte;
1023 * Find the block or page map for this virtual address. pmap_pte
1024 * will return either a valid block/page entry, or NULL.
1026 pte = pmap_pte(pmap, va, &lvl);
1028 tpte = pmap_load(pte);
1029 pa = tpte & ~ATTR_MASK;
1032 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1033 ("pmap_extract: Invalid L1 pte found: %lx",
1034 tpte & ATTR_DESCR_MASK));
1035 pa |= (va & L1_OFFSET);
1038 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1039 ("pmap_extract: Invalid L2 pte found: %lx",
1040 tpte & ATTR_DESCR_MASK));
1041 pa |= (va & L2_OFFSET);
1044 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1045 ("pmap_extract: Invalid L3 pte found: %lx",
1046 tpte & ATTR_DESCR_MASK));
1047 pa |= (va & L3_OFFSET);
1056 * Routine: pmap_extract_and_hold
1058 * Atomically extract and hold the physical page
1059 * with the given pmap and virtual address pair
1060 * if that mapping permits the given protection.
1063 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1065 pt_entry_t *pte, tpte;
1075 pte = pmap_pte(pmap, va, &lvl);
1077 tpte = pmap_load(pte);
1079 KASSERT(lvl > 0 && lvl <= 3,
1080 ("pmap_extract_and_hold: Invalid level %d", lvl));
1081 CTASSERT(L1_BLOCK == L2_BLOCK);
1082 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1083 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1084 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1085 tpte & ATTR_DESCR_MASK));
1086 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1087 ((prot & VM_PROT_WRITE) == 0)) {
1090 off = va & L1_OFFSET;
1093 off = va & L2_OFFSET;
1099 if (vm_page_pa_tryrelock(pmap,
1100 (tpte & ~ATTR_MASK) | off, &pa))
1102 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1112 pmap_kextract(vm_offset_t va)
1114 pt_entry_t *pte, tpte;
1118 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1119 pa = DMAP_TO_PHYS(va);
1122 pte = pmap_pte(kernel_pmap, va, &lvl);
1124 tpte = pmap_load(pte);
1125 pa = tpte & ~ATTR_MASK;
1128 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1129 ("pmap_kextract: Invalid L1 pte found: %lx",
1130 tpte & ATTR_DESCR_MASK));
1131 pa |= (va & L1_OFFSET);
1134 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1135 ("pmap_kextract: Invalid L2 pte found: %lx",
1136 tpte & ATTR_DESCR_MASK));
1137 pa |= (va & L2_OFFSET);
1140 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1141 ("pmap_kextract: Invalid L3 pte found: %lx",
1142 tpte & ATTR_DESCR_MASK));
1143 pa |= (va & L3_OFFSET);
1151 /***************************************************
1152 * Low level mapping routines.....
1153 ***************************************************/
1156 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1159 pt_entry_t *pte, attr;
1163 KASSERT((pa & L3_OFFSET) == 0,
1164 ("pmap_kenter: Invalid physical address"));
1165 KASSERT((sva & L3_OFFSET) == 0,
1166 ("pmap_kenter: Invalid virtual address"));
1167 KASSERT((size & PAGE_MASK) == 0,
1168 ("pmap_kenter: Mapping is not page-sized"));
1170 attr = ATTR_DEFAULT | ATTR_IDX(mode) | L3_PAGE;
1171 if (mode == DEVICE_MEMORY)
1176 pde = pmap_pde(kernel_pmap, va, &lvl);
1177 KASSERT(pde != NULL,
1178 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1179 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1181 pte = pmap_l2_to_l3(pde, va);
1182 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1188 pmap_invalidate_range(kernel_pmap, sva, va);
1192 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1195 pmap_kenter(sva, size, pa, DEVICE_MEMORY);
1199 * Remove a page from the kernel pagetables.
1202 pmap_kremove(vm_offset_t va)
1207 pte = pmap_pte(kernel_pmap, va, &lvl);
1208 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1209 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1211 pmap_load_clear(pte);
1212 pmap_invalidate_page(kernel_pmap, va);
1216 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1222 KASSERT((sva & L3_OFFSET) == 0,
1223 ("pmap_kremove_device: Invalid virtual address"));
1224 KASSERT((size & PAGE_MASK) == 0,
1225 ("pmap_kremove_device: Mapping is not page-sized"));
1229 pte = pmap_pte(kernel_pmap, va, &lvl);
1230 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1232 ("Invalid device pagetable level: %d != 3", lvl));
1233 pmap_load_clear(pte);
1238 pmap_invalidate_range(kernel_pmap, sva, va);
1242 * Used to map a range of physical addresses into kernel
1243 * virtual address space.
1245 * The value passed in '*virt' is a suggested virtual address for
1246 * the mapping. Architectures which can support a direct-mapped
1247 * physical to virtual region can return the appropriate address
1248 * within that region, leaving '*virt' unchanged. Other
1249 * architectures should map the pages starting at '*virt' and
1250 * update '*virt' with the first usable address after the mapped
1254 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1256 return PHYS_TO_DMAP(start);
1261 * Add a list of wired pages to the kva
1262 * this routine is only used for temporary
1263 * kernel mappings that do not need to have
1264 * page modification or references recorded.
1265 * Note that old mappings are simply written
1266 * over. The page *must* be wired.
1267 * Note: SMP coherent. Uses a ranged shootdown IPI.
1270 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1273 pt_entry_t *pte, pa;
1279 for (i = 0; i < count; i++) {
1280 pde = pmap_pde(kernel_pmap, va, &lvl);
1281 KASSERT(pde != NULL,
1282 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1284 ("pmap_qenter: Invalid level %d", lvl));
1287 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1288 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1289 if (m->md.pv_memattr == DEVICE_MEMORY)
1291 pte = pmap_l2_to_l3(pde, va);
1292 pmap_load_store(pte, pa);
1296 pmap_invalidate_range(kernel_pmap, sva, va);
1300 * This routine tears out page mappings from the
1301 * kernel -- it is meant only for temporary mappings.
1304 pmap_qremove(vm_offset_t sva, int count)
1310 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1313 while (count-- > 0) {
1314 pte = pmap_pte(kernel_pmap, va, &lvl);
1316 ("Invalid device pagetable level: %d != 3", lvl));
1318 pmap_load_clear(pte);
1323 pmap_invalidate_range(kernel_pmap, sva, va);
1326 /***************************************************
1327 * Page table page management routines.....
1328 ***************************************************/
1330 * Schedule the specified unused page table page to be freed. Specifically,
1331 * add the page to the specified list of pages that will be released to the
1332 * physical memory manager after the TLB has been updated.
1334 static __inline void
1335 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1336 boolean_t set_PG_ZERO)
1340 m->flags |= PG_ZERO;
1342 m->flags &= ~PG_ZERO;
1343 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1347 * Decrements a page table page's wire count, which is used to record the
1348 * number of valid page table entries within the page. If the wire count
1349 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1350 * page table page was unmapped and FALSE otherwise.
1352 static inline boolean_t
1353 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1357 if (m->wire_count == 0) {
1358 _pmap_unwire_l3(pmap, va, m, free);
1365 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1368 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1370 * unmap the page table page
1372 if (m->pindex >= (NUL2E + NUL1E)) {
1376 l0 = pmap_l0(pmap, va);
1377 pmap_load_clear(l0);
1378 } else if (m->pindex >= NUL2E) {
1382 l1 = pmap_l1(pmap, va);
1383 pmap_load_clear(l1);
1388 l2 = pmap_l2(pmap, va);
1389 pmap_load_clear(l2);
1391 pmap_resident_count_dec(pmap, 1);
1392 if (m->pindex < NUL2E) {
1393 /* We just released an l3, unhold the matching l2 */
1394 pd_entry_t *l1, tl1;
1397 l1 = pmap_l1(pmap, va);
1398 tl1 = pmap_load(l1);
1399 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1400 pmap_unwire_l3(pmap, va, l2pg, free);
1401 } else if (m->pindex < (NUL2E + NUL1E)) {
1402 /* We just released an l2, unhold the matching l1 */
1403 pd_entry_t *l0, tl0;
1406 l0 = pmap_l0(pmap, va);
1407 tl0 = pmap_load(l0);
1408 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1409 pmap_unwire_l3(pmap, va, l1pg, free);
1411 pmap_invalidate_page(pmap, va);
1416 * Put page on a list so that it is released after
1417 * *ALL* TLB shootdown is done
1419 pmap_add_delayed_free_list(m, free, TRUE);
1423 * After removing a page table entry, this routine is used to
1424 * conditionally free the page, and manage the hold/wire counts.
1427 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1428 struct spglist *free)
1432 if (va >= VM_MAXUSER_ADDRESS)
1434 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1435 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1436 return (pmap_unwire_l3(pmap, va, mpte, free));
1440 pmap_pinit0(pmap_t pmap)
1443 PMAP_LOCK_INIT(pmap);
1444 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1445 pmap->pm_l0 = kernel_pmap->pm_l0;
1446 pmap->pm_root.rt_root = 0;
1450 pmap_pinit(pmap_t pmap)
1456 * allocate the l0 page
1458 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1459 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1462 l0phys = VM_PAGE_TO_PHYS(l0pt);
1463 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1465 if ((l0pt->flags & PG_ZERO) == 0)
1466 pagezero(pmap->pm_l0);
1468 pmap->pm_root.rt_root = 0;
1469 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1475 * This routine is called if the desired page table page does not exist.
1477 * If page table page allocation fails, this routine may sleep before
1478 * returning NULL. It sleeps only if a lock pointer was given.
1480 * Note: If a page allocation fails at page table level two or three,
1481 * one or two pages may be held during the wait, only to be released
1482 * afterwards. This conservative approach is easily argued to avoid
1486 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1488 vm_page_t m, l1pg, l2pg;
1490 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1493 * Allocate a page table page.
1495 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1496 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1497 if (lockp != NULL) {
1498 RELEASE_PV_LIST_LOCK(lockp);
1505 * Indicate the need to retry. While waiting, the page table
1506 * page may have been allocated.
1510 if ((m->flags & PG_ZERO) == 0)
1514 * Map the pagetable page into the process address space, if
1515 * it isn't already there.
1518 if (ptepindex >= (NUL2E + NUL1E)) {
1520 vm_pindex_t l0index;
1522 l0index = ptepindex - (NUL2E + NUL1E);
1523 l0 = &pmap->pm_l0[l0index];
1524 pmap_load_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1525 } else if (ptepindex >= NUL2E) {
1526 vm_pindex_t l0index, l1index;
1527 pd_entry_t *l0, *l1;
1530 l1index = ptepindex - NUL2E;
1531 l0index = l1index >> L0_ENTRIES_SHIFT;
1533 l0 = &pmap->pm_l0[l0index];
1534 tl0 = pmap_load(l0);
1536 /* recurse for allocating page dir */
1537 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1539 vm_page_unwire_noq(m);
1540 vm_page_free_zero(m);
1544 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1548 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1549 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1550 pmap_load_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1552 vm_pindex_t l0index, l1index;
1553 pd_entry_t *l0, *l1, *l2;
1554 pd_entry_t tl0, tl1;
1556 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1557 l0index = l1index >> L0_ENTRIES_SHIFT;
1559 l0 = &pmap->pm_l0[l0index];
1560 tl0 = pmap_load(l0);
1562 /* recurse for allocating page dir */
1563 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1565 vm_page_unwire_noq(m);
1566 vm_page_free_zero(m);
1569 tl0 = pmap_load(l0);
1570 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1571 l1 = &l1[l1index & Ln_ADDR_MASK];
1573 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1574 l1 = &l1[l1index & Ln_ADDR_MASK];
1575 tl1 = pmap_load(l1);
1577 /* recurse for allocating page dir */
1578 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1580 vm_page_unwire_noq(m);
1581 vm_page_free_zero(m);
1585 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1590 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1591 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1592 pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1595 pmap_resident_count_inc(pmap, 1);
1601 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1605 vm_pindex_t l2pindex;
1608 l1 = pmap_l1(pmap, va);
1609 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1610 /* Add a reference to the L2 page. */
1611 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1614 /* Allocate a L2 page. */
1615 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1616 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1617 if (l2pg == NULL && lockp != NULL)
1624 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1626 vm_pindex_t ptepindex;
1627 pd_entry_t *pde, tpde;
1635 * Calculate pagetable page index
1637 ptepindex = pmap_l2_pindex(va);
1640 * Get the page directory entry
1642 pde = pmap_pde(pmap, va, &lvl);
1645 * If the page table page is mapped, we just increment the hold count,
1646 * and activate it. If we get a level 2 pde it will point to a level 3
1654 pte = pmap_l0_to_l1(pde, va);
1655 KASSERT(pmap_load(pte) == 0,
1656 ("pmap_alloc_l3: TODO: l0 superpages"));
1661 pte = pmap_l1_to_l2(pde, va);
1662 KASSERT(pmap_load(pte) == 0,
1663 ("pmap_alloc_l3: TODO: l1 superpages"));
1667 tpde = pmap_load(pde);
1669 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1675 panic("pmap_alloc_l3: Invalid level %d", lvl);
1679 * Here if the pte page isn't mapped, or if it has been deallocated.
1681 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1682 if (m == NULL && lockp != NULL)
1688 /***************************************************
1689 * Pmap allocation/deallocation routines.
1690 ***************************************************/
1693 * Release any resources held by the given physical map.
1694 * Called when a pmap initialized by pmap_pinit is being released.
1695 * Should only be called if the map contains no valid mappings.
1698 pmap_release(pmap_t pmap)
1702 KASSERT(pmap->pm_stats.resident_count == 0,
1703 ("pmap_release: pmap resident count %ld != 0",
1704 pmap->pm_stats.resident_count));
1705 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1706 ("pmap_release: pmap has reserved page table page(s)"));
1708 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1710 vm_page_unwire_noq(m);
1711 vm_page_free_zero(m);
1715 kvm_size(SYSCTL_HANDLER_ARGS)
1717 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1719 return sysctl_handle_long(oidp, &ksize, 0, req);
1721 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1722 0, 0, kvm_size, "LU", "Size of KVM");
1725 kvm_free(SYSCTL_HANDLER_ARGS)
1727 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1729 return sysctl_handle_long(oidp, &kfree, 0, req);
1731 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1732 0, 0, kvm_free, "LU", "Amount of KVM free");
1735 * grow the number of kernel page table entries, if needed
1738 pmap_growkernel(vm_offset_t addr)
1742 pd_entry_t *l0, *l1, *l2;
1744 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1746 addr = roundup2(addr, L2_SIZE);
1747 if (addr - 1 >= vm_map_max(kernel_map))
1748 addr = vm_map_max(kernel_map);
1749 while (kernel_vm_end < addr) {
1750 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1751 KASSERT(pmap_load(l0) != 0,
1752 ("pmap_growkernel: No level 0 kernel entry"));
1754 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1755 if (pmap_load(l1) == 0) {
1756 /* We need a new PDP entry */
1757 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1758 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1759 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1761 panic("pmap_growkernel: no memory to grow kernel");
1762 if ((nkpg->flags & PG_ZERO) == 0)
1763 pmap_zero_page(nkpg);
1764 paddr = VM_PAGE_TO_PHYS(nkpg);
1765 pmap_load_store(l1, paddr | L1_TABLE);
1766 continue; /* try again */
1768 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1769 if ((pmap_load(l2) & ATTR_AF) != 0) {
1770 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1771 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1772 kernel_vm_end = vm_map_max(kernel_map);
1778 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1779 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1782 panic("pmap_growkernel: no memory to grow kernel");
1783 if ((nkpg->flags & PG_ZERO) == 0)
1784 pmap_zero_page(nkpg);
1785 paddr = VM_PAGE_TO_PHYS(nkpg);
1786 pmap_load_store(l2, paddr | L2_TABLE);
1787 pmap_invalidate_page(kernel_pmap, kernel_vm_end);
1789 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1790 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1791 kernel_vm_end = vm_map_max(kernel_map);
1798 /***************************************************
1799 * page management routines.
1800 ***************************************************/
1802 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1803 CTASSERT(_NPCM == 3);
1804 CTASSERT(_NPCPV == 168);
1806 static __inline struct pv_chunk *
1807 pv_to_chunk(pv_entry_t pv)
1810 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1813 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1815 #define PC_FREE0 0xfffffffffffffffful
1816 #define PC_FREE1 0xfffffffffffffffful
1817 #define PC_FREE2 0x000000fffffffffful
1819 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1823 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1825 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1826 "Current number of pv entry chunks");
1827 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1828 "Current number of pv entry chunks allocated");
1829 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1830 "Current number of pv entry chunks frees");
1831 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1832 "Number of times tried to get a chunk page but failed.");
1834 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1835 static int pv_entry_spare;
1837 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1838 "Current number of pv entry frees");
1839 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1840 "Current number of pv entry allocs");
1841 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1842 "Current number of pv entries");
1843 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1844 "Current number of spare pv entries");
1849 * We are in a serious low memory condition. Resort to
1850 * drastic measures to free some pages so we can allocate
1851 * another pv entry chunk.
1853 * Returns NULL if PV entries were reclaimed from the specified pmap.
1855 * We do not, however, unmap 2mpages because subsequent accesses will
1856 * allocate per-page pv entries until repromotion occurs, thereby
1857 * exacerbating the shortage of free pv entries.
1860 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1862 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
1863 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
1864 struct md_page *pvh;
1866 pmap_t next_pmap, pmap;
1867 pt_entry_t *pte, tpte;
1871 struct spglist free;
1873 int bit, field, freed, lvl;
1874 static int active_reclaims = 0;
1876 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1877 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
1882 bzero(&pc_marker_b, sizeof(pc_marker_b));
1883 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
1884 pc_marker = (struct pv_chunk *)&pc_marker_b;
1885 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
1887 mtx_lock(&pv_chunks_mutex);
1889 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
1890 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
1891 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
1892 SLIST_EMPTY(&free)) {
1893 next_pmap = pc->pc_pmap;
1894 if (next_pmap == NULL) {
1896 * The next chunk is a marker. However, it is
1897 * not our marker, so active_reclaims must be
1898 * > 1. Consequently, the next_chunk code
1899 * will not rotate the pv_chunks list.
1903 mtx_unlock(&pv_chunks_mutex);
1906 * A pv_chunk can only be removed from the pc_lru list
1907 * when both pv_chunks_mutex is owned and the
1908 * corresponding pmap is locked.
1910 if (pmap != next_pmap) {
1911 if (pmap != NULL && pmap != locked_pmap)
1914 /* Avoid deadlock and lock recursion. */
1915 if (pmap > locked_pmap) {
1916 RELEASE_PV_LIST_LOCK(lockp);
1918 mtx_lock(&pv_chunks_mutex);
1920 } else if (pmap != locked_pmap) {
1921 if (PMAP_TRYLOCK(pmap)) {
1922 mtx_lock(&pv_chunks_mutex);
1925 pmap = NULL; /* pmap is not locked */
1926 mtx_lock(&pv_chunks_mutex);
1927 pc = TAILQ_NEXT(pc_marker, pc_lru);
1929 pc->pc_pmap != next_pmap)
1937 * Destroy every non-wired, 4 KB page mapping in the chunk.
1940 for (field = 0; field < _NPCM; field++) {
1941 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1942 inuse != 0; inuse &= ~(1UL << bit)) {
1943 bit = ffsl(inuse) - 1;
1944 pv = &pc->pc_pventry[field * 64 + bit];
1946 pde = pmap_pde(pmap, va, &lvl);
1949 pte = pmap_l2_to_l3(pde, va);
1950 tpte = pmap_load(pte);
1951 if ((tpte & ATTR_SW_WIRED) != 0)
1953 tpte = pmap_load_clear(pte);
1954 pmap_invalidate_page(pmap, va);
1955 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
1956 if (pmap_page_dirty(tpte))
1958 if ((tpte & ATTR_AF) != 0)
1959 vm_page_aflag_set(m, PGA_REFERENCED);
1960 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1961 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
1963 if (TAILQ_EMPTY(&m->md.pv_list) &&
1964 (m->flags & PG_FICTITIOUS) == 0) {
1965 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
1966 if (TAILQ_EMPTY(&pvh->pv_list)) {
1967 vm_page_aflag_clear(m,
1971 pc->pc_map[field] |= 1UL << bit;
1972 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
1977 mtx_lock(&pv_chunks_mutex);
1980 /* Every freed mapping is for a 4 KB page. */
1981 pmap_resident_count_dec(pmap, freed);
1982 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
1983 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
1984 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
1985 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1986 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
1987 pc->pc_map[2] == PC_FREE2) {
1988 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1989 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1990 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1991 /* Entire chunk is free; return it. */
1992 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1993 dump_drop_page(m_pc->phys_addr);
1994 mtx_lock(&pv_chunks_mutex);
1995 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1998 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1999 mtx_lock(&pv_chunks_mutex);
2000 /* One freed pv entry in locked_pmap is sufficient. */
2001 if (pmap == locked_pmap)
2005 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2006 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2007 if (active_reclaims == 1 && pmap != NULL) {
2009 * Rotate the pv chunks list so that we do not
2010 * scan the same pv chunks that could not be
2011 * freed (because they contained a wired
2012 * and/or superpage mapping) on every
2013 * invocation of reclaim_pv_chunk().
2015 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2016 MPASS(pc->pc_pmap != NULL);
2017 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2018 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2022 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2023 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2025 mtx_unlock(&pv_chunks_mutex);
2026 if (pmap != NULL && pmap != locked_pmap)
2028 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2029 m_pc = SLIST_FIRST(&free);
2030 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2031 /* Recycle a freed page table page. */
2032 m_pc->wire_count = 1;
2035 vm_page_free_pages_toq(&free, false);
2040 * free the pv_entry back to the free list
2043 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2045 struct pv_chunk *pc;
2046 int idx, field, bit;
2048 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2049 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2050 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2051 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2052 pc = pv_to_chunk(pv);
2053 idx = pv - &pc->pc_pventry[0];
2056 pc->pc_map[field] |= 1ul << bit;
2057 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2058 pc->pc_map[2] != PC_FREE2) {
2059 /* 98% of the time, pc is already at the head of the list. */
2060 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2061 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2062 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2066 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2071 free_pv_chunk(struct pv_chunk *pc)
2075 mtx_lock(&pv_chunks_mutex);
2076 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2077 mtx_unlock(&pv_chunks_mutex);
2078 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2079 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2080 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2081 /* entire chunk is free, return it */
2082 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2083 dump_drop_page(m->phys_addr);
2084 vm_page_unwire_noq(m);
2089 * Returns a new PV entry, allocating a new PV chunk from the system when
2090 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2091 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2094 * The given PV list lock may be released.
2097 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2101 struct pv_chunk *pc;
2104 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2105 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2107 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2109 for (field = 0; field < _NPCM; field++) {
2110 if (pc->pc_map[field]) {
2111 bit = ffsl(pc->pc_map[field]) - 1;
2115 if (field < _NPCM) {
2116 pv = &pc->pc_pventry[field * 64 + bit];
2117 pc->pc_map[field] &= ~(1ul << bit);
2118 /* If this was the last item, move it to tail */
2119 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2120 pc->pc_map[2] == 0) {
2121 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2122 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2125 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2126 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2130 /* No free items, allocate another chunk */
2131 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2134 if (lockp == NULL) {
2135 PV_STAT(pc_chunk_tryfail++);
2138 m = reclaim_pv_chunk(pmap, lockp);
2142 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2143 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2144 dump_add_page(m->phys_addr);
2145 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2147 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2148 pc->pc_map[1] = PC_FREE1;
2149 pc->pc_map[2] = PC_FREE2;
2150 mtx_lock(&pv_chunks_mutex);
2151 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2152 mtx_unlock(&pv_chunks_mutex);
2153 pv = &pc->pc_pventry[0];
2154 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2155 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2156 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2161 * Ensure that the number of spare PV entries in the specified pmap meets or
2162 * exceeds the given count, "needed".
2164 * The given PV list lock may be released.
2167 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2169 struct pch new_tail;
2170 struct pv_chunk *pc;
2175 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2176 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2179 * Newly allocated PV chunks must be stored in a private list until
2180 * the required number of PV chunks have been allocated. Otherwise,
2181 * reclaim_pv_chunk() could recycle one of these chunks. In
2182 * contrast, these chunks must be added to the pmap upon allocation.
2184 TAILQ_INIT(&new_tail);
2187 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2188 bit_count((bitstr_t *)pc->pc_map, 0,
2189 sizeof(pc->pc_map) * NBBY, &free);
2193 if (avail >= needed)
2196 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2197 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2200 m = reclaim_pv_chunk(pmap, lockp);
2205 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2206 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2207 dump_add_page(m->phys_addr);
2208 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2210 pc->pc_map[0] = PC_FREE0;
2211 pc->pc_map[1] = PC_FREE1;
2212 pc->pc_map[2] = PC_FREE2;
2213 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2214 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2215 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2218 * The reclaim might have freed a chunk from the current pmap.
2219 * If that chunk contained available entries, we need to
2220 * re-count the number of available entries.
2225 if (!TAILQ_EMPTY(&new_tail)) {
2226 mtx_lock(&pv_chunks_mutex);
2227 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2228 mtx_unlock(&pv_chunks_mutex);
2233 * First find and then remove the pv entry for the specified pmap and virtual
2234 * address from the specified pv list. Returns the pv entry if found and NULL
2235 * otherwise. This operation can be performed on pv lists for either 4KB or
2236 * 2MB page mappings.
2238 static __inline pv_entry_t
2239 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2243 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2244 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2245 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2254 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2255 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2256 * entries for each of the 4KB page mappings.
2259 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2260 struct rwlock **lockp)
2262 struct md_page *pvh;
2263 struct pv_chunk *pc;
2265 vm_offset_t va_last;
2269 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2270 KASSERT((pa & L2_OFFSET) == 0,
2271 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2272 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2275 * Transfer the 2mpage's pv entry for this mapping to the first
2276 * page's pv list. Once this transfer begins, the pv list lock
2277 * must not be released until the last pv entry is reinstantiated.
2279 pvh = pa_to_pvh(pa);
2280 va = va & ~L2_OFFSET;
2281 pv = pmap_pvh_remove(pvh, pmap, va);
2282 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2283 m = PHYS_TO_VM_PAGE(pa);
2284 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2286 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2287 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2288 va_last = va + L2_SIZE - PAGE_SIZE;
2290 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2291 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2292 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2293 for (field = 0; field < _NPCM; field++) {
2294 while (pc->pc_map[field]) {
2295 bit = ffsl(pc->pc_map[field]) - 1;
2296 pc->pc_map[field] &= ~(1ul << bit);
2297 pv = &pc->pc_pventry[field * 64 + bit];
2301 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2302 ("pmap_pv_demote_l2: page %p is not managed", m));
2303 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2309 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2310 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2313 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2314 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2315 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2317 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2318 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2322 * First find and then destroy the pv entry for the specified pmap and virtual
2323 * address. This operation can be performed on pv lists for either 4KB or 2MB
2327 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2331 pv = pmap_pvh_remove(pvh, pmap, va);
2332 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2333 free_pv_entry(pmap, pv);
2337 * Conditionally create the PV entry for a 4KB page mapping if the required
2338 * memory can be allocated without resorting to reclamation.
2341 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2342 struct rwlock **lockp)
2346 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2347 /* Pass NULL instead of the lock pointer to disable reclamation. */
2348 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2350 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2351 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2359 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2360 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2361 * false if the PV entry cannot be allocated without resorting to reclamation.
2364 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2365 struct rwlock **lockp)
2367 struct md_page *pvh;
2371 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2372 /* Pass NULL instead of the lock pointer to disable reclamation. */
2373 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2374 NULL : lockp)) == NULL)
2377 pa = l2e & ~ATTR_MASK;
2378 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2379 pvh = pa_to_pvh(pa);
2380 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2386 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2388 pt_entry_t newl2, oldl2;
2392 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2393 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2394 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2396 ml3 = pmap_remove_pt_page(pmap, va);
2398 panic("pmap_remove_kernel_l2: Missing pt page");
2400 ml3pa = VM_PAGE_TO_PHYS(ml3);
2401 newl2 = ml3pa | L2_TABLE;
2404 * Initialize the page table page.
2406 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2409 * Demote the mapping. The caller must have already invalidated the
2410 * mapping (i.e., the "break" in break-before-make).
2412 oldl2 = pmap_load_store(l2, newl2);
2413 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
2414 __func__, l2, oldl2));
2418 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
2421 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2422 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2424 struct md_page *pvh;
2426 vm_offset_t eva, va;
2429 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2430 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2431 old_l2 = pmap_load_clear(l2);
2432 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2433 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2434 pmap_invalidate_range(pmap, sva, sva + L2_SIZE);
2435 if (old_l2 & ATTR_SW_WIRED)
2436 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2437 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2438 if (old_l2 & ATTR_SW_MANAGED) {
2439 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2440 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2441 pmap_pvh_free(pvh, pmap, sva);
2442 eva = sva + L2_SIZE;
2443 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2444 va < eva; va += PAGE_SIZE, m++) {
2445 if (pmap_page_dirty(old_l2))
2447 if (old_l2 & ATTR_AF)
2448 vm_page_aflag_set(m, PGA_REFERENCED);
2449 if (TAILQ_EMPTY(&m->md.pv_list) &&
2450 TAILQ_EMPTY(&pvh->pv_list))
2451 vm_page_aflag_clear(m, PGA_WRITEABLE);
2454 if (pmap == kernel_pmap) {
2455 pmap_remove_kernel_l2(pmap, l2, sva);
2457 ml3 = pmap_remove_pt_page(pmap, sva);
2459 pmap_resident_count_dec(pmap, 1);
2460 KASSERT(ml3->wire_count == NL3PG,
2461 ("pmap_remove_l2: l3 page wire count error"));
2462 ml3->wire_count = 1;
2463 vm_page_unwire_noq(ml3);
2464 pmap_add_delayed_free_list(ml3, free, FALSE);
2467 return (pmap_unuse_pt(pmap, sva, l1e, free));
2471 * pmap_remove_l3: do the things to unmap a page in a process
2474 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2475 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2477 struct md_page *pvh;
2481 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2482 old_l3 = pmap_load_clear(l3);
2483 pmap_invalidate_page(pmap, va);
2484 if (old_l3 & ATTR_SW_WIRED)
2485 pmap->pm_stats.wired_count -= 1;
2486 pmap_resident_count_dec(pmap, 1);
2487 if (old_l3 & ATTR_SW_MANAGED) {
2488 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2489 if (pmap_page_dirty(old_l3))
2491 if (old_l3 & ATTR_AF)
2492 vm_page_aflag_set(m, PGA_REFERENCED);
2493 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2494 pmap_pvh_free(&m->md, pmap, va);
2495 if (TAILQ_EMPTY(&m->md.pv_list) &&
2496 (m->flags & PG_FICTITIOUS) == 0) {
2497 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2498 if (TAILQ_EMPTY(&pvh->pv_list))
2499 vm_page_aflag_clear(m, PGA_WRITEABLE);
2502 return (pmap_unuse_pt(pmap, va, l2e, free));
2506 * Remove the given range of addresses from the specified map.
2508 * It is assumed that the start and end are properly
2509 * rounded to the page size.
2512 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2514 struct rwlock *lock;
2515 vm_offset_t va, va_next;
2516 pd_entry_t *l0, *l1, *l2;
2517 pt_entry_t l3_paddr, *l3;
2518 struct spglist free;
2521 * Perform an unsynchronized read. This is, however, safe.
2523 if (pmap->pm_stats.resident_count == 0)
2531 for (; sva < eva; sva = va_next) {
2533 if (pmap->pm_stats.resident_count == 0)
2536 l0 = pmap_l0(pmap, sva);
2537 if (pmap_load(l0) == 0) {
2538 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2544 l1 = pmap_l0_to_l1(l0, sva);
2545 if (pmap_load(l1) == 0) {
2546 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2553 * Calculate index for next page table.
2555 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2559 l2 = pmap_l1_to_l2(l1, sva);
2563 l3_paddr = pmap_load(l2);
2565 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2566 if (sva + L2_SIZE == va_next && eva >= va_next) {
2567 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2570 } else if (pmap_demote_l2_locked(pmap, l2,
2571 sva &~L2_OFFSET, &lock) == NULL)
2573 l3_paddr = pmap_load(l2);
2577 * Weed out invalid mappings.
2579 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2583 * Limit our scan to either the end of the va represented
2584 * by the current page table page, or to the end of the
2585 * range being removed.
2591 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2594 panic("l3 == NULL");
2595 if (pmap_load(l3) == 0) {
2596 if (va != va_next) {
2597 pmap_invalidate_range(pmap, va, sva);
2604 if (pmap_remove_l3(pmap, l3, sva, l3_paddr, &free,
2611 pmap_invalidate_range(pmap, va, sva);
2616 vm_page_free_pages_toq(&free, false);
2620 * Routine: pmap_remove_all
2622 * Removes this physical page from
2623 * all physical maps in which it resides.
2624 * Reflects back modify bits to the pager.
2627 * Original versions of this routine were very
2628 * inefficient because they iteratively called
2629 * pmap_remove (slow...)
2633 pmap_remove_all(vm_page_t m)
2635 struct md_page *pvh;
2638 struct rwlock *lock;
2639 pd_entry_t *pde, tpde;
2640 pt_entry_t *pte, tpte;
2642 struct spglist free;
2643 int lvl, pvh_gen, md_gen;
2645 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2646 ("pmap_remove_all: page %p is not managed", m));
2648 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2649 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2650 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2653 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2655 if (!PMAP_TRYLOCK(pmap)) {
2656 pvh_gen = pvh->pv_gen;
2660 if (pvh_gen != pvh->pv_gen) {
2667 pte = pmap_pte(pmap, va, &lvl);
2668 KASSERT(pte != NULL,
2669 ("pmap_remove_all: no page table entry found"));
2671 ("pmap_remove_all: invalid pte level %d", lvl));
2673 pmap_demote_l2_locked(pmap, pte, va, &lock);
2676 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2678 if (!PMAP_TRYLOCK(pmap)) {
2679 pvh_gen = pvh->pv_gen;
2680 md_gen = m->md.pv_gen;
2684 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2690 pmap_resident_count_dec(pmap, 1);
2692 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2693 KASSERT(pde != NULL,
2694 ("pmap_remove_all: no page directory entry found"));
2696 ("pmap_remove_all: invalid pde level %d", lvl));
2697 tpde = pmap_load(pde);
2699 pte = pmap_l2_to_l3(pde, pv->pv_va);
2700 tpte = pmap_load(pte);
2701 pmap_load_clear(pte);
2702 pmap_invalidate_page(pmap, pv->pv_va);
2703 if (tpte & ATTR_SW_WIRED)
2704 pmap->pm_stats.wired_count--;
2705 if ((tpte & ATTR_AF) != 0)
2706 vm_page_aflag_set(m, PGA_REFERENCED);
2709 * Update the vm_page_t clean and reference bits.
2711 if (pmap_page_dirty(tpte))
2713 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2714 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2716 free_pv_entry(pmap, pv);
2719 vm_page_aflag_clear(m, PGA_WRITEABLE);
2721 vm_page_free_pages_toq(&free, false);
2725 * Set the physical protection on the
2726 * specified range of this map as requested.
2729 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2731 vm_offset_t va, va_next;
2732 pd_entry_t *l0, *l1, *l2;
2733 pt_entry_t *l3p, l3, nbits;
2735 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
2736 if (prot == VM_PROT_NONE) {
2737 pmap_remove(pmap, sva, eva);
2741 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
2742 (VM_PROT_WRITE | VM_PROT_EXECUTE))
2746 for (; sva < eva; sva = va_next) {
2748 l0 = pmap_l0(pmap, sva);
2749 if (pmap_load(l0) == 0) {
2750 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2756 l1 = pmap_l0_to_l1(l0, sva);
2757 if (pmap_load(l1) == 0) {
2758 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2764 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2768 l2 = pmap_l1_to_l2(l1, sva);
2769 if (pmap_load(l2) == 0)
2772 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
2773 l3p = pmap_demote_l2(pmap, l2, sva);
2777 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
2778 ("pmap_protect: Invalid L2 entry after demotion"));
2784 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2786 l3 = pmap_load(l3p);
2787 if (!pmap_l3_valid(l3))
2791 if ((prot & VM_PROT_WRITE) == 0) {
2792 if ((l3 & ATTR_SW_MANAGED) &&
2793 pmap_page_dirty(l3)) {
2794 vm_page_dirty(PHYS_TO_VM_PAGE(l3 &
2797 nbits |= ATTR_AP(ATTR_AP_RO);
2799 if ((prot & VM_PROT_EXECUTE) == 0)
2802 pmap_set(l3p, nbits);
2803 /* XXX: Use pmap_invalidate_range */
2804 pmap_invalidate_page(pmap, sva);
2811 * Inserts the specified page table page into the specified pmap's collection
2812 * of idle page table pages. Each of a pmap's page table pages is responsible
2813 * for mapping a distinct range of virtual addresses. The pmap's collection is
2814 * ordered by this virtual address range.
2817 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2820 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2821 return (vm_radix_insert(&pmap->pm_root, mpte));
2825 * Removes the page table page mapping the specified virtual address from the
2826 * specified pmap's collection of idle page table pages, and returns it.
2827 * Otherwise, returns NULL if there is no page table page corresponding to the
2828 * specified virtual address.
2830 static __inline vm_page_t
2831 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2834 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2835 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
2839 * Performs a break-before-make update of a pmap entry. This is needed when
2840 * either promoting or demoting pages to ensure the TLB doesn't get into an
2841 * inconsistent state.
2844 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
2845 vm_offset_t va, vm_size_t size)
2849 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2852 * Ensure we don't get switched out with the page table in an
2853 * inconsistent state. We also need to ensure no interrupts fire
2854 * as they may make use of an address we are about to invalidate.
2856 intr = intr_disable();
2859 /* Clear the old mapping */
2860 pmap_load_clear(pte);
2861 pmap_invalidate_range_nopin(pmap, va, va + size);
2863 /* Create the new mapping */
2864 pmap_load_store(pte, newpte);
2870 #if VM_NRESERVLEVEL > 0
2872 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
2873 * replace the many pv entries for the 4KB page mappings by a single pv entry
2874 * for the 2MB page mapping.
2877 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2878 struct rwlock **lockp)
2880 struct md_page *pvh;
2882 vm_offset_t va_last;
2885 KASSERT((pa & L2_OFFSET) == 0,
2886 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
2887 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2890 * Transfer the first page's pv entry for this mapping to the 2mpage's
2891 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
2892 * a transfer avoids the possibility that get_pv_entry() calls
2893 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
2894 * mappings that is being promoted.
2896 m = PHYS_TO_VM_PAGE(pa);
2897 va = va & ~L2_OFFSET;
2898 pv = pmap_pvh_remove(&m->md, pmap, va);
2899 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
2900 pvh = pa_to_pvh(pa);
2901 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2903 /* Free the remaining NPTEPG - 1 pv entries. */
2904 va_last = va + L2_SIZE - PAGE_SIZE;
2908 pmap_pvh_free(&m->md, pmap, va);
2909 } while (va < va_last);
2913 * Tries to promote the 512, contiguous 4KB page mappings that are within a
2914 * single level 2 table entry to a single 2MB page mapping. For promotion
2915 * to occur, two conditions must be met: (1) the 4KB page mappings must map
2916 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
2917 * identical characteristics.
2920 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
2921 struct rwlock **lockp)
2923 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
2927 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2929 sva = va & ~L2_OFFSET;
2930 firstl3 = pmap_l2_to_l3(l2, sva);
2931 newl2 = pmap_load(firstl3);
2933 /* Check the alingment is valid */
2934 if (((newl2 & ~ATTR_MASK) & L2_OFFSET) != 0) {
2935 atomic_add_long(&pmap_l2_p_failures, 1);
2936 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2937 " in pmap %p", va, pmap);
2941 pa = newl2 + L2_SIZE - PAGE_SIZE;
2942 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
2943 oldl3 = pmap_load(l3);
2945 atomic_add_long(&pmap_l2_p_failures, 1);
2946 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2947 " in pmap %p", va, pmap);
2954 * Save the page table page in its current state until the L2
2955 * mapping the superpage is demoted by pmap_demote_l2() or
2956 * destroyed by pmap_remove_l3().
2958 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
2959 KASSERT(mpte >= vm_page_array &&
2960 mpte < &vm_page_array[vm_page_array_size],
2961 ("pmap_promote_l2: page table page is out of range"));
2962 KASSERT(mpte->pindex == pmap_l2_pindex(va),
2963 ("pmap_promote_l2: page table page's pindex is wrong"));
2964 if (pmap_insert_pt_page(pmap, mpte)) {
2965 atomic_add_long(&pmap_l2_p_failures, 1);
2967 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
2972 if ((newl2 & ATTR_SW_MANAGED) != 0)
2973 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
2975 newl2 &= ~ATTR_DESCR_MASK;
2978 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
2980 atomic_add_long(&pmap_l2_promotions, 1);
2981 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
2984 #endif /* VM_NRESERVLEVEL > 0 */
2987 * Insert the given physical page (p) at
2988 * the specified virtual address (v) in the
2989 * target physical map with the protection requested.
2991 * If specified, the page will be wired down, meaning
2992 * that the related pte can not be reclaimed.
2994 * NB: This is the only routine which MAY NOT lazy-evaluate
2995 * or lose information. That is, this routine must actually
2996 * insert this page into the given map NOW.
2999 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3000 u_int flags, int8_t psind)
3002 struct rwlock *lock;
3004 pt_entry_t new_l3, orig_l3;
3005 pt_entry_t *l2, *l3;
3007 vm_paddr_t opa, pa, l1_pa, l2_pa, l3_pa;
3008 vm_page_t mpte, om, l1_m, l2_m, l3_m;
3012 va = trunc_page(va);
3013 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3014 VM_OBJECT_ASSERT_LOCKED(m->object);
3015 pa = VM_PAGE_TO_PHYS(m);
3016 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3018 if ((prot & VM_PROT_WRITE) == 0)
3019 new_l3 |= ATTR_AP(ATTR_AP_RO);
3020 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3022 if ((flags & PMAP_ENTER_WIRED) != 0)
3023 new_l3 |= ATTR_SW_WIRED;
3024 if (va < VM_MAXUSER_ADDRESS)
3025 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3026 if ((m->oflags & VPO_UNMANAGED) == 0)
3027 new_l3 |= ATTR_SW_MANAGED;
3029 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3035 /* Assert the required virtual and physical alignment. */
3036 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3037 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3038 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3043 pde = pmap_pde(pmap, va, &lvl);
3044 if (pde != NULL && lvl == 1) {
3045 l2 = pmap_l1_to_l2(pde, va);
3046 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3047 (l3 = pmap_demote_l2_locked(pmap, l2, va & ~L2_OFFSET,
3049 l3 = &l3[pmap_l3_index(va)];
3050 if (va < VM_MAXUSER_ADDRESS) {
3051 mpte = PHYS_TO_VM_PAGE(
3052 pmap_load(l2) & ~ATTR_MASK);
3059 if (va < VM_MAXUSER_ADDRESS) {
3060 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
3061 mpte = pmap_alloc_l3(pmap, va, nosleep ? NULL : &lock);
3062 if (mpte == NULL && nosleep) {
3063 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3067 return (KERN_RESOURCE_SHORTAGE);
3069 pde = pmap_pde(pmap, va, &lvl);
3070 KASSERT(pde != NULL,
3071 ("pmap_enter: Invalid page entry, va: 0x%lx", va));
3073 ("pmap_enter: Invalid level %d", lvl));
3076 * If we get a level 2 pde it must point to a level 3 entry
3077 * otherwise we will need to create the intermediate tables
3083 /* Get the l0 pde to update */
3084 pde = pmap_l0(pmap, va);
3085 KASSERT(pde != NULL, ("..."));
3087 l1_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3088 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3091 panic("pmap_enter: l1 pte_m == NULL");
3092 if ((l1_m->flags & PG_ZERO) == 0)
3093 pmap_zero_page(l1_m);
3095 l1_pa = VM_PAGE_TO_PHYS(l1_m);
3096 pmap_load_store(pde, l1_pa | L0_TABLE);
3099 /* Get the l1 pde to update */
3100 pde = pmap_l1_to_l2(pde, va);
3101 KASSERT(pde != NULL, ("..."));
3103 l2_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3104 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3107 panic("pmap_enter: l2 pte_m == NULL");
3108 if ((l2_m->flags & PG_ZERO) == 0)
3109 pmap_zero_page(l2_m);
3111 l2_pa = VM_PAGE_TO_PHYS(l2_m);
3112 pmap_load_store(pde, l2_pa | L1_TABLE);
3115 /* Get the l2 pde to update */
3116 pde = pmap_l1_to_l2(pde, va);
3117 KASSERT(pde != NULL, ("..."));
3119 l3_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3120 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3123 panic("pmap_enter: l3 pte_m == NULL");
3124 if ((l3_m->flags & PG_ZERO) == 0)
3125 pmap_zero_page(l3_m);
3127 l3_pa = VM_PAGE_TO_PHYS(l3_m);
3128 pmap_load_store(pde, l3_pa | L2_TABLE);
3133 l3 = pmap_l2_to_l3(pde, va);
3136 orig_l3 = pmap_load(l3);
3137 opa = orig_l3 & ~ATTR_MASK;
3141 * Is the specified virtual address already mapped?
3143 if (pmap_l3_valid(orig_l3)) {
3145 * Wiring change, just update stats. We don't worry about
3146 * wiring PT pages as they remain resident as long as there
3147 * are valid mappings in them. Hence, if a user page is wired,
3148 * the PT page will be also.
3150 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3151 (orig_l3 & ATTR_SW_WIRED) == 0)
3152 pmap->pm_stats.wired_count++;
3153 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3154 (orig_l3 & ATTR_SW_WIRED) != 0)
3155 pmap->pm_stats.wired_count--;
3158 * Remove the extra PT page reference.
3162 KASSERT(mpte->wire_count > 0,
3163 ("pmap_enter: missing reference to page table page,"
3168 * Has the physical page changed?
3172 * No, might be a protection or wiring change.
3174 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3175 if ((new_l3 & ATTR_AP(ATTR_AP_RW)) ==
3176 ATTR_AP(ATTR_AP_RW)) {
3177 vm_page_aflag_set(m, PGA_WRITEABLE);
3184 * The physical page has changed.
3186 (void)pmap_load_clear(l3);
3187 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
3188 ("pmap_enter: unexpected pa update for %#lx", va));
3189 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3190 om = PHYS_TO_VM_PAGE(opa);
3193 * The pmap lock is sufficient to synchronize with
3194 * concurrent calls to pmap_page_test_mappings() and
3195 * pmap_ts_referenced().
3197 if (pmap_page_dirty(orig_l3))
3199 if ((orig_l3 & ATTR_AF) != 0)
3200 vm_page_aflag_set(om, PGA_REFERENCED);
3201 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3202 pv = pmap_pvh_remove(&om->md, pmap, va);
3203 if ((m->oflags & VPO_UNMANAGED) != 0)
3204 free_pv_entry(pmap, pv);
3205 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3206 TAILQ_EMPTY(&om->md.pv_list) &&
3207 ((om->flags & PG_FICTITIOUS) != 0 ||
3208 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3209 vm_page_aflag_clear(om, PGA_WRITEABLE);
3211 pmap_invalidate_page(pmap, va);
3215 * Increment the counters.
3217 if ((new_l3 & ATTR_SW_WIRED) != 0)
3218 pmap->pm_stats.wired_count++;
3219 pmap_resident_count_inc(pmap, 1);
3222 * Enter on the PV list if part of our managed memory.
3224 if ((m->oflags & VPO_UNMANAGED) == 0) {
3226 pv = get_pv_entry(pmap, &lock);
3229 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3230 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3232 if ((new_l3 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3233 vm_page_aflag_set(m, PGA_WRITEABLE);
3238 * Sync icache if exec permission and attribute VM_MEMATTR_WRITE_BACK
3239 * is set. Do it now, before the mapping is stored and made
3240 * valid for hardware table walk. If done later, then other can
3241 * access this page before caches are properly synced.
3242 * Don't do it for kernel memory which is mapped with exec
3243 * permission even if the memory isn't going to hold executable
3244 * code. The only time when icache sync is needed is after
3245 * kernel module is loaded and the relocation info is processed.
3246 * And it's done in elf_cpu_load_file().
3248 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3249 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3250 (opa != pa || (orig_l3 & ATTR_XN)))
3251 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3254 * Update the L3 entry
3256 if (pmap_l3_valid(orig_l3)) {
3257 KASSERT(opa == pa, ("pmap_enter: invalid update"));
3258 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3259 /* same PA, different attributes */
3260 pmap_load_store(l3, new_l3);
3261 pmap_invalidate_page(pmap, va);
3262 if (pmap_page_dirty(orig_l3) &&
3263 (orig_l3 & ATTR_SW_MANAGED) != 0)
3268 * This can happens if multiple threads simultaneously
3269 * access not yet mapped page. This bad for performance
3270 * since this can cause full demotion-NOP-promotion
3272 * Another possible reasons are:
3273 * - VM and pmap memory layout are diverged
3274 * - tlb flush is missing somewhere and CPU doesn't see
3277 CTR4(KTR_PMAP, "%s: already mapped page - "
3278 "pmap %p va 0x%#lx pte 0x%lx",
3279 __func__, pmap, va, new_l3);
3283 pmap_load_store(l3, new_l3);
3286 #if VM_NRESERVLEVEL > 0
3287 if (pmap != pmap_kernel() &&
3288 (mpte == NULL || mpte->wire_count == NL3PG) &&
3289 pmap_ps_enabled(pmap) &&
3290 (m->flags & PG_FICTITIOUS) == 0 &&
3291 vm_reserv_level_iffullpop(m) == 0) {
3292 pmap_promote_l2(pmap, pde, va, &lock);
3305 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
3306 * if successful. Returns false if (1) a page table page cannot be allocated
3307 * without sleeping, (2) a mapping already exists at the specified virtual
3308 * address, or (3) a PV entry cannot be allocated without reclaiming another
3312 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3313 struct rwlock **lockp)
3317 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3319 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
3320 ATTR_IDX(m->md.pv_memattr) | ATTR_AP(ATTR_AP_RO) | L2_BLOCK);
3321 if ((m->oflags & VPO_UNMANAGED) == 0)
3322 new_l2 |= ATTR_SW_MANAGED;
3323 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3325 if (va < VM_MAXUSER_ADDRESS)
3326 new_l2 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3327 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
3328 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
3333 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
3334 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
3335 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
3336 * a mapping already exists at the specified virtual address. Returns
3337 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
3338 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
3339 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3341 * The parameter "m" is only used when creating a managed, writeable mapping.
3344 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
3345 vm_page_t m, struct rwlock **lockp)
3347 struct spglist free;
3348 pd_entry_t *l2, *l3, old_l2;
3352 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3354 if ((l2pg = pmap_alloc_l2(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
3355 NULL : lockp)) == NULL) {
3356 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
3358 return (KERN_RESOURCE_SHORTAGE);
3361 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
3362 l2 = &l2[pmap_l2_index(va)];
3363 if ((old_l2 = pmap_load(l2)) != 0) {
3364 KASSERT(l2pg->wire_count > 1,
3365 ("pmap_enter_l2: l2pg's wire count is too low"));
3366 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3369 "pmap_enter_l2: failure for va %#lx in pmap %p",
3371 return (KERN_FAILURE);
3374 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
3375 (void)pmap_remove_l2(pmap, l2, va,
3376 pmap_load(pmap_l1(pmap, va)), &free, lockp);
3378 for (sva = va; sva < va + L2_SIZE; sva += PAGE_SIZE) {
3379 l3 = pmap_l2_to_l3(l2, sva);
3380 if (pmap_l3_valid(pmap_load(l3)) &&
3381 pmap_remove_l3(pmap, l3, sva, old_l2, &free,
3385 vm_page_free_pages_toq(&free, true);
3386 if (va >= VM_MAXUSER_ADDRESS) {
3387 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3388 if (pmap_insert_pt_page(pmap, mt)) {
3390 * XXX Currently, this can't happen bacuse
3391 * we do not perform pmap_enter(psind == 1)
3392 * on the kernel pmap.
3394 panic("pmap_enter_l2: trie insert failed");
3397 KASSERT(pmap_load(l2) == 0,
3398 ("pmap_enter_l2: non-zero L2 entry %p", l2));
3401 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
3403 * Abort this mapping if its PV entry could not be created.
3405 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
3407 if (pmap_unwire_l3(pmap, va, l2pg, &free)) {
3409 * Although "va" is not mapped, paging-structure
3410 * caches could nonetheless have entries that
3411 * refer to the freed page table pages.
3412 * Invalidate those entries.
3414 pmap_invalidate_page(pmap, va);
3415 vm_page_free_pages_toq(&free, true);
3418 "pmap_enter_l2: failure for va %#lx in pmap %p",
3420 return (KERN_RESOURCE_SHORTAGE);
3422 if ((new_l2 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3423 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3424 vm_page_aflag_set(mt, PGA_WRITEABLE);
3428 * Increment counters.
3430 if ((new_l2 & ATTR_SW_WIRED) != 0)
3431 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
3432 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
3435 * Map the superpage.
3437 (void)pmap_load_store(l2, new_l2);
3439 atomic_add_long(&pmap_l2_mappings, 1);
3440 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
3443 return (KERN_SUCCESS);
3447 * Maps a sequence of resident pages belonging to the same object.
3448 * The sequence begins with the given page m_start. This page is
3449 * mapped at the given virtual address start. Each subsequent page is
3450 * mapped at a virtual address that is offset from start by the same
3451 * amount as the page is offset from m_start within the object. The
3452 * last page in the sequence is the page with the largest offset from
3453 * m_start that can be mapped at a virtual address less than the given
3454 * virtual address end. Not every virtual page between start and end
3455 * is mapped; only those for which a resident page exists with the
3456 * corresponding offset from m_start are mapped.
3459 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3460 vm_page_t m_start, vm_prot_t prot)
3462 struct rwlock *lock;
3465 vm_pindex_t diff, psize;
3467 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3469 psize = atop(end - start);
3474 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3475 va = start + ptoa(diff);
3476 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
3477 m->psind == 1 && pmap_ps_enabled(pmap) &&
3478 pmap_enter_2mpage(pmap, va, m, prot, &lock))
3479 m = &m[L2_SIZE / PAGE_SIZE - 1];
3481 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
3483 m = TAILQ_NEXT(m, listq);
3491 * this code makes some *MAJOR* assumptions:
3492 * 1. Current pmap & pmap exists.
3495 * 4. No page table pages.
3496 * but is *MUCH* faster than pmap_enter...
3500 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3502 struct rwlock *lock;
3506 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3513 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3514 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3516 struct spglist free;
3518 pt_entry_t *l2, *l3, l3_val;
3522 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3523 (m->oflags & VPO_UNMANAGED) != 0,
3524 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3525 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3527 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3529 * In the case that a page table page is not
3530 * resident, we are creating it here.
3532 if (va < VM_MAXUSER_ADDRESS) {
3533 vm_pindex_t l2pindex;
3536 * Calculate pagetable page index
3538 l2pindex = pmap_l2_pindex(va);
3539 if (mpte && (mpte->pindex == l2pindex)) {
3545 pde = pmap_pde(pmap, va, &lvl);
3548 * If the page table page is mapped, we just increment
3549 * the hold count, and activate it. Otherwise, we
3550 * attempt to allocate a page table page. If this
3551 * attempt fails, we don't retry. Instead, we give up.
3554 l2 = pmap_l1_to_l2(pde, va);
3555 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3559 if (lvl == 2 && pmap_load(pde) != 0) {
3561 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3565 * Pass NULL instead of the PV list lock
3566 * pointer, because we don't intend to sleep.
3568 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3573 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3574 l3 = &l3[pmap_l3_index(va)];
3577 pde = pmap_pde(kernel_pmap, va, &lvl);
3578 KASSERT(pde != NULL,
3579 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3582 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3583 l3 = pmap_l2_to_l3(pde, va);
3586 if (pmap_load(l3) != 0) {
3595 * Enter on the PV list if part of our managed memory.
3597 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3598 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3601 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
3602 pmap_invalidate_page(pmap, va);
3603 vm_page_free_pages_toq(&free, false);
3611 * Increment counters
3613 pmap_resident_count_inc(pmap, 1);
3615 pa = VM_PAGE_TO_PHYS(m);
3616 l3_val = pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3617 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3618 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3620 else if (va < VM_MAXUSER_ADDRESS)
3624 * Now validate mapping with RO protection
3626 if ((m->oflags & VPO_UNMANAGED) == 0)
3627 l3_val |= ATTR_SW_MANAGED;
3629 /* Sync icache before the mapping is stored to PTE */
3630 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3631 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
3632 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3634 pmap_load_store(l3, l3_val);
3635 pmap_invalidate_page(pmap, va);
3640 * This code maps large physical mmap regions into the
3641 * processor address space. Note that some shortcuts
3642 * are taken, but the code works.
3645 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3646 vm_pindex_t pindex, vm_size_t size)
3649 VM_OBJECT_ASSERT_WLOCKED(object);
3650 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3651 ("pmap_object_init_pt: non-device object"));
3655 * Clear the wired attribute from the mappings for the specified range of
3656 * addresses in the given pmap. Every valid mapping within that range
3657 * must have the wired attribute set. In contrast, invalid mappings
3658 * cannot have the wired attribute set, so they are ignored.
3660 * The wired attribute of the page table entry is not a hardware feature,
3661 * so there is no need to invalidate any TLB entries.
3664 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3666 vm_offset_t va_next;
3667 pd_entry_t *l0, *l1, *l2;
3671 for (; sva < eva; sva = va_next) {
3672 l0 = pmap_l0(pmap, sva);
3673 if (pmap_load(l0) == 0) {
3674 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3680 l1 = pmap_l0_to_l1(l0, sva);
3681 if (pmap_load(l1) == 0) {
3682 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3688 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3692 l2 = pmap_l1_to_l2(l1, sva);
3693 if (pmap_load(l2) == 0)
3696 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3697 l3 = pmap_demote_l2(pmap, l2, sva);
3701 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3702 ("pmap_unwire: Invalid l2 entry after demotion"));
3706 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3708 if (pmap_load(l3) == 0)
3710 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
3711 panic("pmap_unwire: l3 %#jx is missing "
3712 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
3715 * PG_W must be cleared atomically. Although the pmap
3716 * lock synchronizes access to PG_W, another processor
3717 * could be setting PG_M and/or PG_A concurrently.
3719 atomic_clear_long(l3, ATTR_SW_WIRED);
3720 pmap->pm_stats.wired_count--;
3727 * Copy the range specified by src_addr/len
3728 * from the source map to the range dst_addr/len
3729 * in the destination map.
3731 * This routine is only advisory and need not do anything.
3735 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3736 vm_offset_t src_addr)
3741 * pmap_zero_page zeros the specified hardware page by mapping
3742 * the page into KVM and using bzero to clear its contents.
3745 pmap_zero_page(vm_page_t m)
3747 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3749 pagezero((void *)va);
3753 * pmap_zero_page_area zeros the specified hardware page by mapping
3754 * the page into KVM and using bzero to clear its contents.
3756 * off and size may not cover an area beyond a single hardware page.
3759 pmap_zero_page_area(vm_page_t m, int off, int size)
3761 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3763 if (off == 0 && size == PAGE_SIZE)
3764 pagezero((void *)va);
3766 bzero((char *)va + off, size);
3770 * pmap_copy_page copies the specified (machine independent)
3771 * page by mapping the page into virtual memory and using
3772 * bcopy to copy the page, one machine dependent page at a
3776 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
3778 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
3779 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
3781 pagecopy((void *)src, (void *)dst);
3784 int unmapped_buf_allowed = 1;
3787 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
3788 vm_offset_t b_offset, int xfersize)
3792 vm_paddr_t p_a, p_b;
3793 vm_offset_t a_pg_offset, b_pg_offset;
3796 while (xfersize > 0) {
3797 a_pg_offset = a_offset & PAGE_MASK;
3798 m_a = ma[a_offset >> PAGE_SHIFT];
3799 p_a = m_a->phys_addr;
3800 b_pg_offset = b_offset & PAGE_MASK;
3801 m_b = mb[b_offset >> PAGE_SHIFT];
3802 p_b = m_b->phys_addr;
3803 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
3804 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
3805 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
3806 panic("!DMAP a %lx", p_a);
3808 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
3810 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
3811 panic("!DMAP b %lx", p_b);
3813 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
3815 bcopy(a_cp, b_cp, cnt);
3823 pmap_quick_enter_page(vm_page_t m)
3826 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
3830 pmap_quick_remove_page(vm_offset_t addr)
3835 * Returns true if the pmap's pv is one of the first
3836 * 16 pvs linked to from this page. This count may
3837 * be changed upwards or downwards in the future; it
3838 * is only necessary that true be returned for a small
3839 * subset of pmaps for proper page aging.
3842 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3844 struct md_page *pvh;
3845 struct rwlock *lock;
3850 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3851 ("pmap_page_exists_quick: page %p is not managed", m));
3853 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3855 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3856 if (PV_PMAP(pv) == pmap) {
3864 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
3865 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3866 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3867 if (PV_PMAP(pv) == pmap) {
3881 * pmap_page_wired_mappings:
3883 * Return the number of managed mappings to the given physical page
3887 pmap_page_wired_mappings(vm_page_t m)
3889 struct rwlock *lock;
3890 struct md_page *pvh;
3894 int count, lvl, md_gen, pvh_gen;
3896 if ((m->oflags & VPO_UNMANAGED) != 0)
3898 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3902 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3904 if (!PMAP_TRYLOCK(pmap)) {
3905 md_gen = m->md.pv_gen;
3909 if (md_gen != m->md.pv_gen) {
3914 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3915 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3919 if ((m->flags & PG_FICTITIOUS) == 0) {
3920 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3921 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3923 if (!PMAP_TRYLOCK(pmap)) {
3924 md_gen = m->md.pv_gen;
3925 pvh_gen = pvh->pv_gen;
3929 if (md_gen != m->md.pv_gen ||
3930 pvh_gen != pvh->pv_gen) {
3935 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3937 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3947 * Destroy all managed, non-wired mappings in the given user-space
3948 * pmap. This pmap cannot be active on any processor besides the
3951 * This function cannot be applied to the kernel pmap. Moreover, it
3952 * is not intended for general use. It is only to be used during
3953 * process termination. Consequently, it can be implemented in ways
3954 * that make it faster than pmap_remove(). First, it can more quickly
3955 * destroy mappings by iterating over the pmap's collection of PV
3956 * entries, rather than searching the page table. Second, it doesn't
3957 * have to test and clear the page table entries atomically, because
3958 * no processor is currently accessing the user address space. In
3959 * particular, a page table entry's dirty bit won't change state once
3960 * this function starts.
3963 pmap_remove_pages(pmap_t pmap)
3966 pt_entry_t *pte, tpte;
3967 struct spglist free;
3968 vm_page_t m, ml3, mt;
3970 struct md_page *pvh;
3971 struct pv_chunk *pc, *npc;
3972 struct rwlock *lock;
3974 uint64_t inuse, bitmask;
3975 int allfree, field, freed, idx, lvl;
3982 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
3985 for (field = 0; field < _NPCM; field++) {
3986 inuse = ~pc->pc_map[field] & pc_freemask[field];
3987 while (inuse != 0) {
3988 bit = ffsl(inuse) - 1;
3989 bitmask = 1UL << bit;
3990 idx = field * 64 + bit;
3991 pv = &pc->pc_pventry[idx];
3994 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3995 KASSERT(pde != NULL,
3996 ("Attempting to remove an unmapped page"));
4000 pte = pmap_l1_to_l2(pde, pv->pv_va);
4001 tpte = pmap_load(pte);
4002 KASSERT((tpte & ATTR_DESCR_MASK) ==
4004 ("Attempting to remove an invalid "
4005 "block: %lx", tpte));
4006 tpte = pmap_load(pte);
4009 pte = pmap_l2_to_l3(pde, pv->pv_va);
4010 tpte = pmap_load(pte);
4011 KASSERT((tpte & ATTR_DESCR_MASK) ==
4013 ("Attempting to remove an invalid "
4014 "page: %lx", tpte));
4018 "Invalid page directory level: %d",
4023 * We cannot remove wired pages from a process' mapping at this time
4025 if (tpte & ATTR_SW_WIRED) {
4030 pa = tpte & ~ATTR_MASK;
4032 m = PHYS_TO_VM_PAGE(pa);
4033 KASSERT(m->phys_addr == pa,
4034 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4035 m, (uintmax_t)m->phys_addr,
4038 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4039 m < &vm_page_array[vm_page_array_size],
4040 ("pmap_remove_pages: bad pte %#jx",
4043 pmap_load_clear(pte);
4046 * Update the vm_page_t clean/reference bits.
4048 if ((tpte & ATTR_AP_RW_BIT) ==
4049 ATTR_AP(ATTR_AP_RW)) {
4052 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4061 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4064 pc->pc_map[field] |= bitmask;
4067 pmap_resident_count_dec(pmap,
4068 L2_SIZE / PAGE_SIZE);
4069 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
4070 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
4072 if (TAILQ_EMPTY(&pvh->pv_list)) {
4073 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4074 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
4075 TAILQ_EMPTY(&mt->md.pv_list))
4076 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4078 ml3 = pmap_remove_pt_page(pmap,
4081 pmap_resident_count_dec(pmap,1);
4082 KASSERT(ml3->wire_count == NL3PG,
4083 ("pmap_remove_pages: l3 page wire count error"));
4084 ml3->wire_count = 1;
4085 vm_page_unwire_noq(ml3);
4086 pmap_add_delayed_free_list(ml3,
4091 pmap_resident_count_dec(pmap, 1);
4092 TAILQ_REMOVE(&m->md.pv_list, pv,
4095 if ((m->aflags & PGA_WRITEABLE) != 0 &&
4096 TAILQ_EMPTY(&m->md.pv_list) &&
4097 (m->flags & PG_FICTITIOUS) == 0) {
4099 VM_PAGE_TO_PHYS(m));
4100 if (TAILQ_EMPTY(&pvh->pv_list))
4101 vm_page_aflag_clear(m,
4106 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
4111 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4112 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4113 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4115 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4119 pmap_invalidate_all(pmap);
4123 vm_page_free_pages_toq(&free, false);
4127 * This is used to check if a page has been accessed or modified. As we
4128 * don't have a bit to see if it has been modified we have to assume it
4129 * has been if the page is read/write.
4132 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
4134 struct rwlock *lock;
4136 struct md_page *pvh;
4137 pt_entry_t *pte, mask, value;
4139 int lvl, md_gen, pvh_gen;
4143 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4146 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4148 if (!PMAP_TRYLOCK(pmap)) {
4149 md_gen = m->md.pv_gen;
4153 if (md_gen != m->md.pv_gen) {
4158 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4160 ("pmap_page_test_mappings: Invalid level %d", lvl));
4164 mask |= ATTR_AP_RW_BIT;
4165 value |= ATTR_AP(ATTR_AP_RW);
4168 mask |= ATTR_AF | ATTR_DESCR_MASK;
4169 value |= ATTR_AF | L3_PAGE;
4171 rv = (pmap_load(pte) & mask) == value;
4176 if ((m->flags & PG_FICTITIOUS) == 0) {
4177 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4178 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4180 if (!PMAP_TRYLOCK(pmap)) {
4181 md_gen = m->md.pv_gen;
4182 pvh_gen = pvh->pv_gen;
4186 if (md_gen != m->md.pv_gen ||
4187 pvh_gen != pvh->pv_gen) {
4192 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4194 ("pmap_page_test_mappings: Invalid level %d", lvl));
4198 mask |= ATTR_AP_RW_BIT;
4199 value |= ATTR_AP(ATTR_AP_RW);
4202 mask |= ATTR_AF | ATTR_DESCR_MASK;
4203 value |= ATTR_AF | L2_BLOCK;
4205 rv = (pmap_load(pte) & mask) == value;
4219 * Return whether or not the specified physical page was modified
4220 * in any physical maps.
4223 pmap_is_modified(vm_page_t m)
4226 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4227 ("pmap_is_modified: page %p is not managed", m));
4230 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4231 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4232 * is clear, no PTEs can have PG_M set.
4234 VM_OBJECT_ASSERT_WLOCKED(m->object);
4235 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4237 return (pmap_page_test_mappings(m, FALSE, TRUE));
4241 * pmap_is_prefaultable:
4243 * Return whether or not the specified virtual address is eligible
4247 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4255 pte = pmap_pte(pmap, addr, &lvl);
4256 if (pte != NULL && pmap_load(pte) != 0) {
4264 * pmap_is_referenced:
4266 * Return whether or not the specified physical page was referenced
4267 * in any physical maps.
4270 pmap_is_referenced(vm_page_t m)
4273 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4274 ("pmap_is_referenced: page %p is not managed", m));
4275 return (pmap_page_test_mappings(m, TRUE, FALSE));
4279 * Clear the write and modified bits in each of the given page's mappings.
4282 pmap_remove_write(vm_page_t m)
4284 struct md_page *pvh;
4286 struct rwlock *lock;
4287 pv_entry_t next_pv, pv;
4288 pt_entry_t oldpte, *pte;
4290 int lvl, md_gen, pvh_gen;
4292 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4293 ("pmap_remove_write: page %p is not managed", m));
4296 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4297 * set by another thread while the object is locked. Thus,
4298 * if PGA_WRITEABLE is clear, no page table entries need updating.
4300 VM_OBJECT_ASSERT_WLOCKED(m->object);
4301 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4303 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4304 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4305 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4308 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4310 if (!PMAP_TRYLOCK(pmap)) {
4311 pvh_gen = pvh->pv_gen;
4315 if (pvh_gen != pvh->pv_gen) {
4322 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4323 if ((pmap_load(pte) & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
4324 pmap_demote_l2_locked(pmap, pte, va & ~L2_OFFSET,
4326 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4327 ("inconsistent pv lock %p %p for page %p",
4328 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4331 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4333 if (!PMAP_TRYLOCK(pmap)) {
4334 pvh_gen = pvh->pv_gen;
4335 md_gen = m->md.pv_gen;
4339 if (pvh_gen != pvh->pv_gen ||
4340 md_gen != m->md.pv_gen) {
4346 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4348 oldpte = pmap_load(pte);
4349 if ((oldpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) {
4350 if (!atomic_cmpset_long(pte, oldpte,
4351 oldpte | ATTR_AP(ATTR_AP_RO)))
4353 if ((oldpte & ATTR_AF) != 0)
4355 pmap_invalidate_page(pmap, pv->pv_va);
4360 vm_page_aflag_clear(m, PGA_WRITEABLE);
4363 static __inline boolean_t
4364 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
4371 * pmap_ts_referenced:
4373 * Return a count of reference bits for a page, clearing those bits.
4374 * It is not necessary for every reference bit to be cleared, but it
4375 * is necessary that 0 only be returned when there are truly no
4376 * reference bits set.
4378 * As an optimization, update the page's dirty field if a modified bit is
4379 * found while counting reference bits. This opportunistic update can be
4380 * performed at low cost and can eliminate the need for some future calls
4381 * to pmap_is_modified(). However, since this function stops after
4382 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4383 * dirty pages. Those dirty pages will only be detected by a future call
4384 * to pmap_is_modified().
4387 pmap_ts_referenced(vm_page_t m)
4389 struct md_page *pvh;
4392 struct rwlock *lock;
4393 pd_entry_t *pde, tpde;
4394 pt_entry_t *pte, tpte;
4398 int cleared, md_gen, not_cleared, lvl, pvh_gen;
4399 struct spglist free;
4402 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4403 ("pmap_ts_referenced: page %p is not managed", m));
4406 pa = VM_PAGE_TO_PHYS(m);
4407 lock = PHYS_TO_PV_LIST_LOCK(pa);
4408 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4412 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4413 goto small_mappings;
4419 if (!PMAP_TRYLOCK(pmap)) {
4420 pvh_gen = pvh->pv_gen;
4424 if (pvh_gen != pvh->pv_gen) {
4430 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4431 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4433 ("pmap_ts_referenced: invalid pde level %d", lvl));
4434 tpde = pmap_load(pde);
4435 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4436 ("pmap_ts_referenced: found an invalid l1 table"));
4437 pte = pmap_l1_to_l2(pde, pv->pv_va);
4438 tpte = pmap_load(pte);
4439 if (pmap_page_dirty(tpte)) {
4441 * Although "tpte" is mapping a 2MB page, because
4442 * this function is called at a 4KB page granularity,
4443 * we only update the 4KB page under test.
4447 if ((tpte & ATTR_AF) != 0) {
4449 * Since this reference bit is shared by 512 4KB
4450 * pages, it should not be cleared every time it is
4451 * tested. Apply a simple "hash" function on the
4452 * physical page number, the virtual superpage number,
4453 * and the pmap address to select one 4KB page out of
4454 * the 512 on which testing the reference bit will
4455 * result in clearing that reference bit. This
4456 * function is designed to avoid the selection of the
4457 * same 4KB page for every 2MB page mapping.
4459 * On demotion, a mapping that hasn't been referenced
4460 * is simply destroyed. To avoid the possibility of a
4461 * subsequent page fault on a demoted wired mapping,
4462 * always leave its reference bit set. Moreover,
4463 * since the superpage is wired, the current state of
4464 * its reference bit won't affect page replacement.
4466 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4467 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4468 (tpte & ATTR_SW_WIRED) == 0) {
4469 if (safe_to_clear_referenced(pmap, tpte)) {
4471 * TODO: We don't handle the access
4472 * flag at all. We need to be able
4473 * to set it in the exception handler.
4476 "safe_to_clear_referenced\n");
4477 } else if (pmap_demote_l2_locked(pmap, pte,
4478 pv->pv_va, &lock) != NULL) {
4480 va += VM_PAGE_TO_PHYS(m) -
4481 (tpte & ~ATTR_MASK);
4482 l3 = pmap_l2_to_l3(pte, va);
4483 pmap_remove_l3(pmap, l3, va,
4484 pmap_load(pte), NULL, &lock);
4490 * The superpage mapping was removed
4491 * entirely and therefore 'pv' is no
4499 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4500 ("inconsistent pv lock %p %p for page %p",
4501 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4506 /* Rotate the PV list if it has more than one entry. */
4507 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4508 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4509 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4512 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4514 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4516 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4523 if (!PMAP_TRYLOCK(pmap)) {
4524 pvh_gen = pvh->pv_gen;
4525 md_gen = m->md.pv_gen;
4529 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4534 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4535 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4537 ("pmap_ts_referenced: invalid pde level %d", lvl));
4538 tpde = pmap_load(pde);
4539 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4540 ("pmap_ts_referenced: found an invalid l2 table"));
4541 pte = pmap_l2_to_l3(pde, pv->pv_va);
4542 tpte = pmap_load(pte);
4543 if (pmap_page_dirty(tpte))
4545 if ((tpte & ATTR_AF) != 0) {
4546 if (safe_to_clear_referenced(pmap, tpte)) {
4548 * TODO: We don't handle the access flag
4549 * at all. We need to be able to set it in
4550 * the exception handler.
4552 panic("ARM64TODO: safe_to_clear_referenced\n");
4553 } else if ((tpte & ATTR_SW_WIRED) == 0) {
4555 * Wired pages cannot be paged out so
4556 * doing accessed bit emulation for
4557 * them is wasted effort. We do the
4558 * hard work for unwired pages only.
4560 pmap_remove_l3(pmap, pte, pv->pv_va, tpde,
4562 pmap_invalidate_page(pmap, pv->pv_va);
4567 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4568 ("inconsistent pv lock %p %p for page %p",
4569 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4574 /* Rotate the PV list if it has more than one entry. */
4575 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4576 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4577 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4580 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4581 not_cleared < PMAP_TS_REFERENCED_MAX);
4584 vm_page_free_pages_toq(&free, false);
4585 return (cleared + not_cleared);
4589 * Apply the given advice to the specified range of addresses within the
4590 * given pmap. Depending on the advice, clear the referenced and/or
4591 * modified flags in each mapping and set the mapped page's dirty field.
4594 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4599 * Clear the modify bits on the specified physical page.
4602 pmap_clear_modify(vm_page_t m)
4605 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4606 ("pmap_clear_modify: page %p is not managed", m));
4607 VM_OBJECT_ASSERT_WLOCKED(m->object);
4608 KASSERT(!vm_page_xbusied(m),
4609 ("pmap_clear_modify: page %p is exclusive busied", m));
4612 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4613 * If the object containing the page is locked and the page is not
4614 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4616 if ((m->aflags & PGA_WRITEABLE) == 0)
4619 /* ARM64TODO: We lack support for tracking if a page is modified */
4623 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4625 struct pmap_preinit_mapping *ppim;
4626 vm_offset_t va, offset;
4629 int i, lvl, l2_blocks, free_l2_count, start_idx;
4631 if (!vm_initialized) {
4633 * No L3 ptables so map entire L2 blocks where start VA is:
4634 * preinit_map_va + start_idx * L2_SIZE
4635 * There may be duplicate mappings (multiple VA -> same PA) but
4636 * ARM64 dcache is always PIPT so that's acceptable.
4641 /* Calculate how many full L2 blocks are needed for the mapping */
4642 l2_blocks = (roundup2(pa + size, L2_SIZE) - rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
4644 offset = pa & L2_OFFSET;
4646 if (preinit_map_va == 0)
4649 /* Map 2MiB L2 blocks from reserved VA space */
4653 /* Find enough free contiguous VA space */
4654 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
4655 ppim = pmap_preinit_mapping + i;
4656 if (free_l2_count > 0 && ppim->pa != 0) {
4657 /* Not enough space here */
4663 if (ppim->pa == 0) {
4665 if (start_idx == -1)
4668 if (free_l2_count == l2_blocks)
4672 if (free_l2_count != l2_blocks)
4673 panic("%s: too many preinit mappings", __func__);
4675 va = preinit_map_va + (start_idx * L2_SIZE);
4676 for (i = start_idx; i < start_idx + l2_blocks; i++) {
4677 /* Mark entries as allocated */
4678 ppim = pmap_preinit_mapping + i;
4680 ppim->va = va + offset;
4685 pa = rounddown2(pa, L2_SIZE);
4686 for (i = 0; i < l2_blocks; i++) {
4687 pde = pmap_pde(kernel_pmap, va, &lvl);
4688 KASSERT(pde != NULL,
4689 ("pmap_mapbios: Invalid page entry, va: 0x%lx", va));
4690 KASSERT(lvl == 1, ("pmap_mapbios: Invalid level %d", lvl));
4692 /* Insert L2_BLOCK */
4693 l2 = pmap_l1_to_l2(pde, va);
4695 pa | ATTR_DEFAULT | ATTR_XN |
4696 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
4697 pmap_invalidate_range(kernel_pmap, va, va + L2_SIZE);
4703 va = preinit_map_va + (start_idx * L2_SIZE);
4706 /* kva_alloc may be used to map the pages */
4707 offset = pa & PAGE_MASK;
4708 size = round_page(offset + size);
4710 va = kva_alloc(size);
4712 panic("%s: Couldn't allocate KVA", __func__);
4714 pde = pmap_pde(kernel_pmap, va, &lvl);
4715 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
4717 /* L3 table is linked */
4718 va = trunc_page(va);
4719 pa = trunc_page(pa);
4720 pmap_kenter(va, size, pa, CACHED_MEMORY);
4723 return ((void *)(va + offset));
4727 pmap_unmapbios(vm_offset_t va, vm_size_t size)
4729 struct pmap_preinit_mapping *ppim;
4730 vm_offset_t offset, tmpsize, va_trunc;
4733 int i, lvl, l2_blocks, block;
4735 l2_blocks = (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
4736 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
4738 /* Remove preinit mapping */
4740 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
4741 ppim = pmap_preinit_mapping + i;
4742 if (ppim->va == va) {
4743 KASSERT(ppim->size == size, ("pmap_unmapbios: size mismatch"));
4747 offset = block * L2_SIZE;
4748 va_trunc = rounddown2(va, L2_SIZE) + offset;
4750 /* Remove L2_BLOCK */
4751 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
4752 KASSERT(pde != NULL,
4753 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va_trunc));
4754 l2 = pmap_l1_to_l2(pde, va_trunc);
4755 pmap_load_clear(l2);
4756 pmap_invalidate_range(kernel_pmap, va_trunc, va_trunc + L2_SIZE);
4758 if (block == (l2_blocks - 1))
4764 /* Unmap the pages reserved with kva_alloc. */
4765 if (vm_initialized) {
4766 offset = va & PAGE_MASK;
4767 size = round_page(offset + size);
4768 va = trunc_page(va);
4770 pde = pmap_pde(kernel_pmap, va, &lvl);
4771 KASSERT(pde != NULL,
4772 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
4773 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
4775 /* Unmap and invalidate the pages */
4776 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
4777 pmap_kremove(va + tmpsize);
4784 * Sets the memory attribute for the specified page.
4787 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4790 m->md.pv_memattr = ma;
4793 * If "m" is a normal page, update its direct mapping. This update
4794 * can be relied upon to perform any cache operations that are
4795 * required for data coherence.
4797 if ((m->flags & PG_FICTITIOUS) == 0 &&
4798 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
4799 m->md.pv_memattr) != 0)
4800 panic("memory attribute change on the direct map failed");
4804 * Changes the specified virtual address range's memory type to that given by
4805 * the parameter "mode". The specified virtual address range must be
4806 * completely contained within either the direct map or the kernel map. If
4807 * the virtual address range is contained within the kernel map, then the
4808 * memory type for each of the corresponding ranges of the direct map is also
4809 * changed. (The corresponding ranges of the direct map are those ranges that
4810 * map the same physical pages as the specified virtual address range.) These
4811 * changes to the direct map are necessary because Intel describes the
4812 * behavior of their processors as "undefined" if two or more mappings to the
4813 * same physical page have different memory types.
4815 * Returns zero if the change completed successfully, and either EINVAL or
4816 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
4817 * of the virtual address range was not mapped, and ENOMEM is returned if
4818 * there was insufficient memory available to complete the change. In the
4819 * latter case, the memory type may have been changed on some part of the
4820 * virtual address range or the direct map.
4823 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
4827 PMAP_LOCK(kernel_pmap);
4828 error = pmap_change_attr_locked(va, size, mode);
4829 PMAP_UNLOCK(kernel_pmap);
4834 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
4836 vm_offset_t base, offset, tmpva;
4837 pt_entry_t l3, *pte, *newpte;
4840 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
4841 base = trunc_page(va);
4842 offset = va & PAGE_MASK;
4843 size = round_page(offset + size);
4845 if (!VIRT_IN_DMAP(base))
4848 for (tmpva = base; tmpva < base + size; ) {
4849 pte = pmap_pte(kernel_pmap, tmpva, &lvl);
4853 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
4855 * We already have the correct attribute,
4856 * ignore this entry.
4860 panic("Invalid DMAP table level: %d\n", lvl);
4862 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
4865 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
4873 * Split the entry to an level 3 table, then
4874 * set the new attribute.
4878 panic("Invalid DMAP table level: %d\n", lvl);
4880 newpte = pmap_demote_l1(kernel_pmap, pte,
4881 tmpva & ~L1_OFFSET);
4884 pte = pmap_l1_to_l2(pte, tmpva);
4886 newpte = pmap_demote_l2(kernel_pmap, pte,
4887 tmpva & ~L2_OFFSET);
4890 pte = pmap_l2_to_l3(pte, tmpva);
4892 /* Update the entry */
4893 l3 = pmap_load(pte);
4894 l3 &= ~ATTR_IDX_MASK;
4895 l3 |= ATTR_IDX(mode);
4896 if (mode == DEVICE_MEMORY)
4899 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
4903 * If moving to a non-cacheable entry flush
4906 if (mode == VM_MEMATTR_UNCACHEABLE)
4907 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
4919 * Create an L2 table to map all addresses within an L1 mapping.
4922 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
4924 pt_entry_t *l2, newl2, oldl1;
4926 vm_paddr_t l2phys, phys;
4930 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4931 oldl1 = pmap_load(l1);
4932 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
4933 ("pmap_demote_l1: Demoting a non-block entry"));
4934 KASSERT((va & L1_OFFSET) == 0,
4935 ("pmap_demote_l1: Invalid virtual address %#lx", va));
4936 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
4937 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
4940 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
4941 tmpl1 = kva_alloc(PAGE_SIZE);
4946 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
4947 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
4948 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
4949 " in pmap %p", va, pmap);
4953 l2phys = VM_PAGE_TO_PHYS(ml2);
4954 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
4956 /* Address the range points at */
4957 phys = oldl1 & ~ATTR_MASK;
4958 /* The attributed from the old l1 table to be copied */
4959 newl2 = oldl1 & ATTR_MASK;
4961 /* Create the new entries */
4962 for (i = 0; i < Ln_ENTRIES; i++) {
4963 l2[i] = newl2 | phys;
4966 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
4967 ("Invalid l2 page (%lx != %lx)", l2[0],
4968 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
4971 pmap_kenter(tmpl1, PAGE_SIZE,
4972 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY);
4973 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
4976 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
4979 pmap_kremove(tmpl1);
4980 kva_free(tmpl1, PAGE_SIZE);
4987 * Create an L3 table to map all addresses within an L2 mapping.
4990 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
4991 struct rwlock **lockp)
4993 pt_entry_t *l3, newl3, oldl2;
4995 vm_paddr_t l3phys, phys;
4999 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5001 oldl2 = pmap_load(l2);
5002 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
5003 ("pmap_demote_l2: Demoting a non-block entry"));
5004 KASSERT((va & L2_OFFSET) == 0,
5005 ("pmap_demote_l2: Invalid virtual address %#lx", va));
5008 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
5009 tmpl2 = kva_alloc(PAGE_SIZE);
5014 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
5015 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
5016 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5017 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5019 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
5020 " in pmap %p", va, pmap);
5023 if (va < VM_MAXUSER_ADDRESS)
5024 pmap_resident_count_inc(pmap, 1);
5027 l3phys = VM_PAGE_TO_PHYS(ml3);
5028 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
5030 /* Address the range points at */
5031 phys = oldl2 & ~ATTR_MASK;
5032 /* The attributed from the old l2 table to be copied */
5033 newl3 = (oldl2 & (ATTR_MASK & ~ATTR_DESCR_MASK)) | L3_PAGE;
5036 * If the page table page is new, initialize it.
5038 if (ml3->wire_count == 1) {
5039 ml3->wire_count = NL3PG;
5040 for (i = 0; i < Ln_ENTRIES; i++) {
5041 l3[i] = newl3 | phys;
5045 KASSERT(l3[0] == ((oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE),
5046 ("Invalid l3 page (%lx != %lx)", l3[0],
5047 (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE));
5050 * Map the temporary page so we don't lose access to the l2 table.
5053 pmap_kenter(tmpl2, PAGE_SIZE,
5054 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY);
5055 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
5059 * The spare PV entries must be reserved prior to demoting the
5060 * mapping, that is, prior to changing the PDE. Otherwise, the state
5061 * of the L2 and the PV lists will be inconsistent, which can result
5062 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5063 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
5064 * PV entry for the 2MB page mapping that is being demoted.
5066 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5067 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
5069 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
5072 * Demote the PV entry.
5074 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5075 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
5077 atomic_add_long(&pmap_l2_demotions, 1);
5078 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
5079 " in pmap %p %lx", va, pmap, l3[0]);
5083 pmap_kremove(tmpl2);
5084 kva_free(tmpl2, PAGE_SIZE);
5092 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
5094 struct rwlock *lock;
5098 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
5105 * perform the pmap work for mincore
5108 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5110 pt_entry_t *pte, tpte;
5111 vm_paddr_t mask, pa;
5118 pte = pmap_pte(pmap, addr, &lvl);
5120 tpte = pmap_load(pte);
5133 panic("pmap_mincore: invalid level %d", lvl);
5136 val = MINCORE_INCORE;
5138 val |= MINCORE_SUPER;
5139 if (pmap_page_dirty(tpte))
5140 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5141 if ((tpte & ATTR_AF) == ATTR_AF)
5142 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5144 managed = (tpte & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
5145 pa = (tpte & ~ATTR_MASK) | (addr & mask);
5149 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5150 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
5151 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5152 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5155 PA_UNLOCK_COND(*locked_pa);
5162 pmap_activate(struct thread *td)
5167 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5168 td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0);
5169 __asm __volatile("msr ttbr0_el1, %0" : :
5170 "r"(td->td_proc->p_md.md_l0addr));
5171 pmap_invalidate_all(pmap);
5176 pmap_switch(struct thread *old, struct thread *new)
5178 pcpu_bp_harden bp_harden;
5181 /* Store the new curthread */
5182 PCPU_SET(curthread, new);
5184 /* And the new pcb */
5186 PCPU_SET(curpcb, pcb);
5189 * TODO: We may need to flush the cache here if switching
5190 * to a user process.
5194 old->td_proc->p_md.md_l0addr != new->td_proc->p_md.md_l0addr) {
5196 /* Switch to the new pmap */
5197 "msr ttbr0_el1, %0 \n"
5200 /* Invalidate the TLB */
5205 : : "r"(new->td_proc->p_md.md_l0addr));
5208 * Stop userspace from training the branch predictor against
5209 * other processes. This will call into a CPU specific
5210 * function that clears the branch predictor state.
5212 bp_harden = PCPU_GET(bp_harden);
5213 if (bp_harden != NULL)
5221 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
5224 if (va >= VM_MIN_KERNEL_ADDRESS) {
5225 cpu_icache_sync_range(va, sz);
5230 /* Find the length of data in this page to flush */
5231 offset = va & PAGE_MASK;
5232 len = imin(PAGE_SIZE - offset, sz);
5235 /* Extract the physical address & find it in the DMAP */
5236 pa = pmap_extract(pmap, va);
5238 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
5240 /* Move to the next page */
5243 /* Set the length for the next iteration */
5244 len = imin(PAGE_SIZE, sz);
5250 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
5256 switch (ESR_ELx_EXCEPTION(esr)) {
5257 case EXCP_INSN_ABORT_L:
5258 case EXCP_INSN_ABORT:
5259 case EXCP_DATA_ABORT_L:
5260 case EXCP_DATA_ABORT:
5263 return (KERN_FAILURE);
5266 /* Data and insn aborts use same encoding for FCS field. */
5267 switch (esr & ISS_DATA_DFSC_MASK) {
5268 case ISS_DATA_DFSC_TF_L0:
5269 case ISS_DATA_DFSC_TF_L1:
5270 case ISS_DATA_DFSC_TF_L2:
5271 case ISS_DATA_DFSC_TF_L3:
5273 /* Ask the MMU to check the address */
5274 intr = intr_disable();
5275 if (pmap == kernel_pmap)
5276 par = arm64_address_translate_s1e1r(far);
5278 par = arm64_address_translate_s1e0r(far);
5283 * If the translation was successful the address was invalid
5284 * due to a break-before-make sequence. We can unlock and
5285 * return success to the trap handler.
5287 if (PAR_SUCCESS(par))
5288 return (KERN_SUCCESS);
5295 return (KERN_FAILURE);
5299 * Increase the starting virtual address of the given mapping if a
5300 * different alignment might result in more superpage mappings.
5303 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5304 vm_offset_t *addr, vm_size_t size)
5306 vm_offset_t superpage_offset;
5310 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5311 offset += ptoa(object->pg_color);
5312 superpage_offset = offset & L2_OFFSET;
5313 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
5314 (*addr & L2_OFFSET) == superpage_offset)
5316 if ((*addr & L2_OFFSET) < superpage_offset)
5317 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
5319 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
5323 * Get the kernel virtual address of a set of physical pages. If there are
5324 * physical addresses not covered by the DMAP perform a transient mapping
5325 * that will be removed when calling pmap_unmap_io_transient.
5327 * \param page The pages the caller wishes to obtain the virtual
5328 * address on the kernel memory map.
5329 * \param vaddr On return contains the kernel virtual memory address
5330 * of the pages passed in the page parameter.
5331 * \param count Number of pages passed in.
5332 * \param can_fault TRUE if the thread using the mapped pages can take
5333 * page faults, FALSE otherwise.
5335 * \returns TRUE if the caller must call pmap_unmap_io_transient when
5336 * finished or FALSE otherwise.
5340 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
5341 boolean_t can_fault)
5344 boolean_t needs_mapping;
5348 * Allocate any KVA space that we need, this is done in a separate
5349 * loop to prevent calling vmem_alloc while pinned.
5351 needs_mapping = FALSE;
5352 for (i = 0; i < count; i++) {
5353 paddr = VM_PAGE_TO_PHYS(page[i]);
5354 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
5355 error = vmem_alloc(kernel_arena, PAGE_SIZE,
5356 M_BESTFIT | M_WAITOK, &vaddr[i]);
5357 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
5358 needs_mapping = TRUE;
5360 vaddr[i] = PHYS_TO_DMAP(paddr);
5364 /* Exit early if everything is covered by the DMAP */
5370 for (i = 0; i < count; i++) {
5371 paddr = VM_PAGE_TO_PHYS(page[i]);
5372 if (!PHYS_IN_DMAP(paddr)) {
5374 "pmap_map_io_transient: TODO: Map out of DMAP data");
5378 return (needs_mapping);
5382 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
5383 boolean_t can_fault)
5390 for (i = 0; i < count; i++) {
5391 paddr = VM_PAGE_TO_PHYS(page[i]);
5392 if (!PHYS_IN_DMAP(paddr)) {
5393 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
5399 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
5402 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);